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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 10/31] hw/arm/exynos4210: Put a9mpcore device into state struct
Date: Thu, 21 Apr 2022 12:18:25 +0100
Message-Id: <20220421111846.2011565-11-peter.maydell@linaro.org>
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The exynos4210 SoC mostly creates its child devices as if it were
board code. This includes the a9mpcore object. Switch that to a
new-style "embedded in the state struct" creation, because in the
next commit we're going to want to refer to the object again further
down in the exynos4210_realize() function.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220404154658.565020-4-peter.maydell@linaro.org
---
include/hw/arm/exynos4210.h | 2 ++
hw/arm/exynos4210.c | 11 ++++++-----
2 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h
index 3999034053e..215c039b414 100644
--- a/include/hw/arm/exynos4210.h
+++ b/include/hw/arm/exynos4210.h
@@ -26,6 +26,7 @@
=20
#include "hw/or-irq.h"
#include "hw/sysbus.h"
+#include "hw/cpu/a9mpcore.h"
#include "target/arm/cpu-qom.h"
#include "qom/object.h"
=20
@@ -103,6 +104,7 @@ struct Exynos4210State {
I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER];
qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA];
qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS];
+ A9MPPrivState a9mpcore;
};
=20
#define TYPE_EXYNOS4210_SOC "exynos4210"
diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c
index dfc0a4eec25..ef4d646eb91 100644
--- a/hw/arm/exynos4210.c
+++ b/hw/arm/exynos4210.c
@@ -244,17 +244,16 @@ static void exynos4210_realize(DeviceState *socdev, E=
rror **errp)
}
=20
/* Private memory region and Internal GIC */
- dev =3D qdev_new(TYPE_A9MPCORE_PRIV);
- qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS);
- busdev =3D SYS_BUS_DEVICE(dev);
- sysbus_realize_and_unref(busdev, &error_fatal);
+ qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-cpu", EXYNOS4210_NCPUS=
);
+ busdev =3D SYS_BUS_DEVICE(&s->a9mpcore);
+ sysbus_realize(busdev, &error_fatal);
sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR);
for (n =3D 0; n < EXYNOS4210_NCPUS; n++) {
sysbus_connect_irq(busdev, n,
qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]),=
0));
}
for (n =3D 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) {
- s->irqs.int_gic_irq[n] =3D qdev_get_gpio_in(dev, n);
+ s->irqs.int_gic_irq[n] =3D qdev_get_gpio_in(DEVICE(&s->a9mpcore), =
n);
}
=20
/* Cache controller */
@@ -489,6 +488,8 @@ static void exynos4210_init(Object *obj)
g_autofree char *name =3D g_strdup_printf("cpu-irq-orgate%d", i);
object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_=
IRQ);
}
+
+ object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_P=
RIV);
}
=20
static void exynos4210_class_init(ObjectClass *klass, void *data)
--=20
2.25.1