From nobody Tue May 21 06:35:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650540133; cv=none; d=zohomail.com; s=zohoarc; b=WsupnP9YJlYljysqkadROPFmQN/vIoLdqADTCmkbZHscXaYzaucs6AgcGRGA+q/dZNgGkBIiHNYpsmJ8aK1IutSCciG8hwbdAEfXnuQamZchpW4SDJbydqdv4orwWQCjdCUbIzaIe0qrWU5rFv/4+AZPnVPZI1MGz/Dda/JtonY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650540133; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=MEtor4j+P9zV/cCDr31gN48wrx6xOJygpWmwTKMQDwk=; b=MYGzP6aO9QkWriX4uCBdQ/0rVItKH85CFwmfzChFqcLQaOBMCKV6OSuRfmbopje3Yyb8sRDxoiz7t+2WeLJkUi1MmQsR9gyIkmwH8o71s+3wrooDIGt26QPnfWm5g9zxVVweQMbPHGd8nFY4MziWzastsMfF3ZWDHCAw37YucMs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650540133977179.2662203682844; Thu, 21 Apr 2022 04:22:13 -0700 (PDT) Received: from localhost ([::1]:35220 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhUt2-0006OF-LE for importer@patchew.org; Thu, 21 Apr 2022 07:22:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59032) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhUpo-0002g2-L1 for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:18:52 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:41510) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nhUpm-0003Q0-LF for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:18:52 -0400 Received: by mail-wm1-x334.google.com with SMTP id o20-20020a05600c511400b0038ebbbb2ad8so3203081wms.0 for ; Thu, 21 Apr 2022 04:18:49 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e4-20020a5d6d04000000b0020a8bbbb72bsm2597694wrq.97.2022.04.21.04.18.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 04:18:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=MEtor4j+P9zV/cCDr31gN48wrx6xOJygpWmwTKMQDwk=; b=V+xylE735e+Mbe6ZBvaUKQJv1i9wA3UBx+FbQfh7PU5RmY0z79rASvlg79cQovQgAM /KiR0QCpaSceW/w/qrNqXVhYJUrqRnvFTV3GLt17wbNNsOIxqTGWW1x7puYFG2ENJyGr QMCOuS1tLkSFlYg0Ify40oIPh50d1rI0pMR0kgMTV4Wn48ihAhj4nuFNd/27mNflAL2w W2yP4CS+XQzO6ZHBnOFRKRZol44q6B4kTrLmuUTAayWflDAepeJMvyROC3QHG+NzF2br +Qdn+hXoNoJhWUQGqMXN78mTa2sN8bmBJAwwfF1lqVYOqdLchX2itLE5wknzvrgx/ndh VHug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MEtor4j+P9zV/cCDr31gN48wrx6xOJygpWmwTKMQDwk=; b=BBW8jkdm40ObAgviGcwxcDH/Hx+eltzCRdVebNGcenhf8gzGt7svQEf7jlqUspegoV OUoirrvWpwTVV1kZtYVC+NyB01x2ZaP2UXU7iC6baan31NfQAY0oV/xeQ1jf6QhVJIKV RLkK9+N6bRNTK8C2iCrkWhiot8Vvin0qkDiHadyuax7aX0BGxnYbs2XKo6L200H4VEbr jkAwP6eAGKrsVLOMZrF+/c9nn7TcVHqd7Rh+a9AWfj8Lbjw/UStrkj79Uls7gTlMv5xE iYlIrhzhcm6wiKg7c1JyPvE0u+RAv1C7Yf6CgHDvKCaV2dHSRvyAmiAbGpWlls2D2do9 odCA== X-Gm-Message-State: AOAM531hp07AajJePupq//D47sjkB9t0UILWg02NmbyqW16+J9VUYNAd x+FVxER+iaQFbrukV4wIQ07KT//m9yWkQQ== X-Google-Smtp-Source: ABdhPJxjYxx3TBxba0QB1XJhkPG0FH2SMKs1gyPWRrfx+LznTt9UQv+dI4yQcVGpvfgiBIxW3y2RNQ== X-Received: by 2002:a05:600c:1552:b0:38e:c7a4:f056 with SMTP id f18-20020a05600c155200b0038ec7a4f056mr8169781wmg.183.1650539928956; Thu, 21 Apr 2022 04:18:48 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/31] hw/arm/virt: Check for attempt to use TrustZone with KVM or HVF Date: Thu, 21 Apr 2022 12:18:16 +0100 Message-Id: <20220421111846.2011565-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org> References: <20220421111846.2011565-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650540135825100003 Content-Type: text/plain; charset="utf-8" It's not possible to provide the guest with the Security extensions (TrustZone) when using KVM or HVF, because the hardware virtualization extensions don't permit running EL3 guest code. However, we weren't checking for this combination, with the result that QEMU would assert if you tried it: $ qemu-system-aarch64 -enable-kvm -machine virt,secure=3Don -cpu host -disp= lay none Unexpected error in object_property_find_err() at ../../qom/object.c:1304: qemu-system-aarch64: Property 'host-arm-cpu.secure-memory' not found Aborted Check for this combination of options and report an error, in the same way we already do for attempts to give a KVM or HVF guest the Virtualization or MTE extensions. Now we will report: qemu-system-aarch64: mach-virt: KVM does not support providing Security ext= ensions (TrustZone) to the guest CPU Resolves: https://gitlab.com/qemu-project/qemu/-/issues/961 Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220404155301.566542-1-peter.maydell@linaro.org --- hw/arm/virt.c | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 9284f7d28e6..bb6a2484d81 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2048,6 +2048,13 @@ static void machvirt_init(MachineState *machine) exit(1); } =20 + if (vms->secure && (kvm_enabled() || hvf_enabled())) { + error_report("mach-virt: %s does not support providing " + "Security extensions (TrustZone) to the guest CPU", + kvm_enabled() ? "KVM" : "HVF"); + exit(1); + } + if (vms->virt && (kvm_enabled() || hvf_enabled())) { error_report("mach-virt: %s does not support providing " "Virtualization extensions to the guest CPU", --=20 2.25.1 From nobody Tue May 21 06:35:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650540121; cv=none; d=zohomail.com; s=zohoarc; b=Y7yMzmexwcwz/hFOSF+z43DnChgIu0LCanXuks0MNd9A7E+4NqRPnZ4eSPYfcilt4sfdOG+tgH4RV3sRgjUj3ZxJ3KkKj3uWuKiRXekE3hJQ3llltFYEkWgMEUW47/WUCpY8/NlymsPEcV8EpXW29KPR523HahtJ+y93Vj52tcU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650540121; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=TwQCGhEvSSQC/Z2/EccxdurzG1YqSvcBdgIIL6E/lik=; b=SVvZRTVWkFvVJFqZdTZdtnrc0UeMgRuhiVKFoacqbYgfa1/xRieq2h7huDb+TAIOgeurKUHuPlpsI5BFfmfn/vxPIJoCzWMfTuzj/ECe/WlqhMPH7xYxdjd+TYPMPzDR10IGf7NegtVBHDZRC2zwKpYiuT0QL8blzrdX/erlF+o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650540121836658.2324129724502; Thu, 21 Apr 2022 04:22:01 -0700 (PDT) Received: from localhost ([::1]:34298 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhUsq-0005le-JT for importer@patchew.org; Thu, 21 Apr 2022 07:22:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59072) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhUpq-0002js-3F for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:18:54 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:35755) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nhUpn-0003Q8-C1 for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:18:53 -0400 Received: by mail-wr1-x436.google.com with SMTP id k22so6227929wrd.2 for ; Thu, 21 Apr 2022 04:18:50 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e4-20020a5d6d04000000b0020a8bbbb72bsm2597694wrq.97.2022.04.21.04.18.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 04:18:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=TwQCGhEvSSQC/Z2/EccxdurzG1YqSvcBdgIIL6E/lik=; b=GSzUzfymB4RGM71lbqIspMIWR7nnanN6QGW9GjbJWpE265kzng/iPaZLD7K/laDupw 17zEhQDhlM+DAxsAwmizBpxvyZ+kISH0g3jRLcay0+h61CLuD93wctvj7nhZ9nRQ0mGH 2AiOOOUr2MZ3lO670+ycldbnh9Asc175si3kv3d3Nzc1K2qRhrcMjEENtpJJ8Ji8Nf7f md+YXt6fRq4zKjKJ7Eici53DYBJv8rmiWAY3nUAdzBKduFalFsY6TzGYaQWfeeFJlHlj lWAJ3weEQXWQCWAUXUoOe2pc3tICUBnqbQbP1KYPbKhKMawair5mdaYQzqkx2mZO7Smj pf4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TwQCGhEvSSQC/Z2/EccxdurzG1YqSvcBdgIIL6E/lik=; b=hMLplDQYwoBuL4SEu4dKs07RbFXg3IGsYCo1TQ6hDwWdTeweNyK37Opj/lQfGugbUf QdVErsAOUhp4/q/qX6NnlywkJ3/LqhEG9d+b5/0832IZQr+sIRFrQwlkWqxYTPJa0nNw R3MjseSyeFDs9kfzXBJMrdNVZrByhEARu9BvPMhk9WIdI2p39c+m+fqhHz2dD3VVJpIx M0nU2AgJDGy+YAv8nbqEa+37gBStPcKD+7C18RF18Dhj+Giqw8kD/9E+nigck3+7iaAZ 6EhrXiRfFZpwKF3Ph78iE+03hLLaJ+zekwXjJe8KMEuufyPV6pDDRIzeADxgGgkF82Dh Q5Cg== X-Gm-Message-State: AOAM530ekGfqQYIMRp/QE4oKlVHfc632zCicEF9DrTebiWdMkcm1VFXb frsbDQ0qs/o+85hekTf/aeOerZdn8TFX+g== X-Google-Smtp-Source: ABdhPJx+/DNV5Nn6Yzb7gPVeSPQ7y1JG6BZ7FRaW9OfM4BDfVAp4aw77Pj8hQWD2LlLk8BHyBi047Q== X-Received: by 2002:adf:ebd2:0:b0:20a:9c10:ab29 with SMTP id v18-20020adfebd2000000b0020a9c10ab29mr13123277wrn.212.1650539929889; Thu, 21 Apr 2022 04:18:49 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/31] timer: cadence_ttc: Break out header file to allow embedding Date: Thu, 21 Apr 2022 12:18:17 +0100 Message-Id: <20220421111846.2011565-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org> References: <20220421111846.2011565-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650540123652100001 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Break out header file to allow embedding of the the TTC. Signed-off-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Reviewed-by: Luc Michel Reviewed-by: Francisco Iglesias Message-id: 20220331222017.2914409-2-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- include/hw/timer/cadence_ttc.h | 54 ++++++++++++++++++++++++++++++++++ hw/timer/cadence_ttc.c | 32 ++------------------ 2 files changed, 56 insertions(+), 30 deletions(-) create mode 100644 include/hw/timer/cadence_ttc.h diff --git a/include/hw/timer/cadence_ttc.h b/include/hw/timer/cadence_ttc.h new file mode 100644 index 00000000000..e1251383f2a --- /dev/null +++ b/include/hw/timer/cadence_ttc.h @@ -0,0 +1,54 @@ +/* + * Xilinx Zynq cadence TTC model + * + * Copyright (c) 2011 Xilinx Inc. + * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.= com) + * Copyright (c) 2012 PetaLogix Pty Ltd. + * Written By Haibing Ma + * M. Habib + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version + * 2 of the License, or (at your option) any later version. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ +#ifndef HW_TIMER_CADENCE_TTC_H +#define HW_TIMER_CADENCE_TTC_H + +#include "hw/sysbus.h" +#include "qemu/timer.h" + +typedef struct { + QEMUTimer *timer; + int freq; + + uint32_t reg_clock; + uint32_t reg_count; + uint32_t reg_value; + uint16_t reg_interval; + uint16_t reg_match[3]; + uint32_t reg_intr; + uint32_t reg_intr_en; + uint32_t reg_event_ctrl; + uint32_t reg_event; + + uint64_t cpu_time; + unsigned int cpu_time_valid; + + qemu_irq irq; +} CadenceTimerState; + +#define TYPE_CADENCE_TTC "cadence_ttc" +OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC) + +struct CadenceTTCState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + CadenceTimerState timer[3]; +}; + +#endif diff --git a/hw/timer/cadence_ttc.c b/hw/timer/cadence_ttc.c index 64108241ba9..e57a0f5f09f 100644 --- a/hw/timer/cadence_ttc.c +++ b/hw/timer/cadence_ttc.c @@ -24,6 +24,8 @@ #include "qemu/timer.h" #include "qom/object.h" =20 +#include "hw/timer/cadence_ttc.h" + #ifdef CADENCE_TTC_ERR_DEBUG #define DB_PRINT(...) do { \ fprintf(stderr, ": %s: ", __func__); \ @@ -49,36 +51,6 @@ #define CLOCK_CTRL_PS_EN 0x00000001 #define CLOCK_CTRL_PS_V 0x0000001e =20 -typedef struct { - QEMUTimer *timer; - int freq; - - uint32_t reg_clock; - uint32_t reg_count; - uint32_t reg_value; - uint16_t reg_interval; - uint16_t reg_match[3]; - uint32_t reg_intr; - uint32_t reg_intr_en; - uint32_t reg_event_ctrl; - uint32_t reg_event; - - uint64_t cpu_time; - unsigned int cpu_time_valid; - - qemu_irq irq; -} CadenceTimerState; - -#define TYPE_CADENCE_TTC "cadence_ttc" -OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC) - -struct CadenceTTCState { - SysBusDevice parent_obj; - - MemoryRegion iomem; - CadenceTimerState timer[3]; -}; - static void cadence_timer_update(CadenceTimerState *s) { qemu_set_irq(s->irq, !!(s->reg_intr & s->reg_intr_en)); --=20 2.25.1 From nobody Tue May 21 06:35:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650540338; cv=none; d=zohomail.com; s=zohoarc; b=nZdEa+bZ48Ay0nA+yZqoV+X7jOeH6S1gVnE0d2yybx26c5iIMJYWsm+0P+jI5q9yq4Tlw7j6Mfybj+giVecyGJR3k0C9Zt9HNHkhCnTp1FplIP98Oo39Mx2YXGUsPUWOnGtdn9x9XwSANx0G2fckXDnX/7gWCMtbvwEx4Lky+ic= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650540338; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=f47lw1QPcXaJplbJJd1gYAYuTWuO7WWJTSxjhTHJnU4=; b=Yj32Gg3AjFl6mfWPDNysMCMHs8y/QArNyI5P+ZQ5GETxD9Gi4Qr17fZnJcmL168GaH3uIJdCbLIg4XoEYFGLnWyH/u8kuy4m1wV4XYdWsA05oIy7JgfsVgRxxz4jwDEttD/lHy9ketNijnjR+yU4BxZSzLGf25I9lC/UjVK+mEU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650540338934791.3087932941577; Thu, 21 Apr 2022 04:25:38 -0700 (PDT) Received: from localhost ([::1]:42848 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhUwK-00038w-VO for importer@patchew.org; Thu, 21 Apr 2022 07:25:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59076) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhUpq-0002k5-6I for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:18:54 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:42864) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nhUpo-0003QB-0Y for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:18:53 -0400 Received: by mail-wr1-x429.google.com with SMTP id bv16so6181619wrb.9 for ; Thu, 21 Apr 2022 04:18:51 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e4-20020a5d6d04000000b0020a8bbbb72bsm2597694wrq.97.2022.04.21.04.18.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 04:18:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=f47lw1QPcXaJplbJJd1gYAYuTWuO7WWJTSxjhTHJnU4=; b=Ffg3eyFjT+HmD1OynSuN7IaOH5LGe6roPgC/RFrlP5CldS7QsqBrvOh9oV3kI7aOeY TjfhdZZgVRoEPk5vvWYBGvlpglQXnahTTiEmo5UdrNNX+SQM1EHa7ETkklb8eVJgbVzi vTKJ5FdY74l2dLK7Y7L9AKBRQzd5vD/NWkE0OtM5Nnwo4eRIw3bKC3Qp9JJqKPkSmIoY RU63Z22Lr3w1p5YsfoPoEGXS8Ub0uaykfcTp63IE4gxi0i4y8m1syHzzuK3S3dIO4VLj 8iCJkCtO1F2hS5wc9nBZjigomYcnQkbzR1WhHqoeEycJfiUKrV2NIWVp+TwB060+5Fwn 7Gow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=f47lw1QPcXaJplbJJd1gYAYuTWuO7WWJTSxjhTHJnU4=; b=rdroUZ+9vCWYvHrtMLEXjSqn13tv/5XVq+86DD24na9p7NxMhP+wwJnL4HaAXgZned OsE786GPhGmqrs0Qp5gUcJBks8xQk/N4jeJ3eRqmUFmJrdWTRHDVHBiUzI9Os0MdhwdY 8WQ4YVleIfYkzwSK8jXqSVip9i8oamA0emG/LrzY7X8+2kevlO0qCKDqL0J9URmIXBlh ocWJ4lNM5n1gIBGAV+klK7kcmF33QIX0NJYDPLPoD62XWq+odbiQiUZn/ukuCLQEpx8t JSjbncds+EhkYUHR1x1qJn1ElMqcLHeVjZ0Pf+TJx9u8tyomrnsrHh3k4cK/l6su7vY5 142Q== X-Gm-Message-State: AOAM5327/mMZyIXU0eiGvnfoipLTC80v0U4NrpZFIuz1giuBD27/N1tQ RHg0bfLbsK7qARW1v3+3LIuLCnf9HYDPIQ== X-Google-Smtp-Source: ABdhPJyfXnSbUvWYQDvnpgLsh49pZLkmgGtutdiNQW9xnLraJBnlVRVdjZxN3QJW56Y8dEW9s2x5Sg== X-Received: by 2002:a5d:4a81:0:b0:207:9abe:2908 with SMTP id o1-20020a5d4a81000000b002079abe2908mr18818289wrq.341.1650539930676; Thu, 21 Apr 2022 04:18:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/31] hw/arm/xlnx-zynqmp: Connect 4 TTC timers Date: Thu, 21 Apr 2022 12:18:18 +0100 Message-Id: <20220421111846.2011565-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org> References: <20220421111846.2011565-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650540339419100001 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Connect the 4 TTC timers on the ZynqMP. Signed-off-by: Edgar E. Iglesias Reviewed-by: Alistair Francis Reviewed-by: Luc Michel Reviewed-by: Francisco Iglesias Message-id: 20220331222017.2914409-3-edgar.iglesias@gmail.com Signed-off-by: Peter Maydell --- include/hw/arm/xlnx-zynqmp.h | 4 ++++ hw/arm/xlnx-zynqmp.c | 22 ++++++++++++++++++++++ 2 files changed, 26 insertions(+) diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h index 9d9a9d0bf9d..85fd9f53daa 100644 --- a/include/hw/arm/xlnx-zynqmp.h +++ b/include/hw/arm/xlnx-zynqmp.h @@ -41,6 +41,7 @@ #include "hw/or-irq.h" #include "hw/misc/xlnx-zynqmp-apu-ctrl.h" #include "hw/misc/xlnx-zynqmp-crf.h" +#include "hw/timer/cadence_ttc.h" =20 #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp" OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) @@ -84,6 +85,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP) #define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \ XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE) =20 +#define XLNX_ZYNQMP_NUM_TTC 4 + /* * Unimplemented mmio regions needed to boot some images. */ @@ -128,6 +131,7 @@ struct XlnxZynqMPState { qemu_or_irq qspi_irq_orgate; XlnxZynqMPAPUCtrl apu_ctrl; XlnxZynqMPCRF crf; + CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC]; =20 char *boot_cpu; ARMCPU *boot_cpu_ptr; diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 5bfe285a191..375309e68eb 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -68,6 +68,9 @@ #define APU_ADDR 0xfd5c0000 #define APU_IRQ 153 =20 +#define TTC0_ADDR 0xFF110000 +#define TTC0_IRQ 36 + #define IPI_ADDR 0xFF300000 #define IPI_IRQ 64 =20 @@ -316,6 +319,24 @@ static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s,= qemu_irq *gic) sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]); } =20 +static void xlnx_zynqmp_create_ttc(XlnxZynqMPState *s, qemu_irq *gic) +{ + SysBusDevice *sbd; + int i, irq; + + for (i =3D 0; i < XLNX_ZYNQMP_NUM_TTC; i++) { + object_initialize_child(OBJECT(s), "ttc[*]", &s->ttc[i], + TYPE_CADENCE_TTC); + sbd =3D SYS_BUS_DEVICE(&s->ttc[i]); + + sysbus_realize(sbd, &error_fatal); + sysbus_mmio_map(sbd, 0, TTC0_ADDR + i * 0x10000); + for (irq =3D 0; irq < 3; irq++) { + sysbus_connect_irq(sbd, irq, gic[TTC0_IRQ + i * 3 + irq]); + } + } +} + static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s) { static const struct UnimpInfo { @@ -721,6 +742,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error= **errp) xlnx_zynqmp_create_efuse(s, gic_spi); xlnx_zynqmp_create_apu_ctrl(s, gic_spi); xlnx_zynqmp_create_crf(s, gic_spi); + xlnx_zynqmp_create_ttc(s, gic_spi); xlnx_zynqmp_create_unimp_mmio(s); =20 for (i =3D 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) { --=20 2.25.1 From nobody Tue May 21 06:35:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650540457; cv=none; d=zohomail.com; s=zohoarc; b=IOvan5/yQjoVaCDXqe39Rx0unpBy7nJUVvq4SNJWjjmLiQbBK2sCXHYfy1Bp6vumoyS1z6QdwHdnV6gqtH/75iO+lumSNsZ7kAZ9qOAeF4bSGVvfP/ySjXNa09w/jrJgY8euwTBhVyUVmlqhR9iam4qFwQPpKv3QoxjrFHQdZPY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650540457; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=wfsVKDSs56nO298B9eGbm6n11u9EwnB13l23WZAxciw=; b=lXyAilnQyFQXfoxeFXYb4F/FXNZwaYBrG4MdaTiETRXbypnxPfMzq/Doe2TPFx7AuYzsYDjWkqcX9YJggewmoMut/7BM/zUqFQJ8vq6PBtJyKird70cHefllW+nFfd6ilNzrKa40P6Y3aR7kq0LK7n+WPkKI1aq1Slu2Pl6+G3c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650540457708692.2466265688015; Thu, 21 Apr 2022 04:27:37 -0700 (PDT) Received: from localhost ([::1]:45542 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhUyG-0005IL-8w for importer@patchew.org; Thu, 21 Apr 2022 07:27:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59098) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhUpq-0002ln-TL for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:18:54 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:33683) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nhUpp-0003QI-48 for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:18:54 -0400 Received: by mail-wr1-x429.google.com with SMTP id x18so6241562wrc.0 for ; Thu, 21 Apr 2022 04:18:52 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e4-20020a5d6d04000000b0020a8bbbb72bsm2597694wrq.97.2022.04.21.04.18.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 04:18:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=wfsVKDSs56nO298B9eGbm6n11u9EwnB13l23WZAxciw=; b=Tq/20ZDirVD5MPM9Tg3S22Mt9CzMpQEFaxl+LQPDNzTThjK5bt8bVB6k1X6hOzT+nd hAM06HKLbt4AT0bcE6xwVgJSaSICS6GbZTllrtIux11/VYZCgTxFkkPt2dVavJ+XU/AR fUd74zWmQZCbhOBy4KjX03qsaE/QxR94cMU6943fBpiWGGmNXyQjPIiu8lo1RH5QEryb HELbiX4G8JNZ5Ga8tRcVx5x80twdkG5iIoM317K1cypomsXEA09b8Te/scvXb0TIBl1F t0VjqKGTH+cygtVu2oTppWYe1vIg4LoN2aZutFC0Ydyo6ox/dagQTICXk1kOZDELphzK YKmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wfsVKDSs56nO298B9eGbm6n11u9EwnB13l23WZAxciw=; b=LvRR27z6oYwN8u/TrX4b5X7j373DRv9/TpiGAvv1o79Y88Vwdw8JcxCRX4r7LYLGLS khOK1EDejy+SamQm3vui84z3fkkh7X6/U4T1feWo2KUm+/spCXeapmN7N/sW3YM3KY5q 9RIXhHjnvT2xgE4wS1q3FLW10SZ/f8YNRllxhL71pSvRtsUkGOUZsXjyI9nGklKtnol2 l/QAdgYVh+F9Dv1YxmNoZGEgwtA1DWu1RYL+mggNmvPi7TmPZiPGWVpARyM6H24eRi6Q 76pO66quF12S8E4hwzOnTs6cHM8wby+xjUEvVZHBMZ44u+dAFWK5bqLF2pbLL0V6iyPn Rfjw== X-Gm-Message-State: AOAM533gaCI2nwkb8ozXA1y50uQ0v9A5xByPjOsGvmSgmjYo3/m8DiNP UDe84CrtLYF1TV1uEBI1zNS9fy7Hbct1jA== X-Google-Smtp-Source: ABdhPJwUhtqyYWrx6cXOilYvhbf3YTbHJQyPitps91dEKe5+rbOZxJJH41jqmpccNoHAZKM+/NWoYg== X-Received: by 2002:a5d:5604:0:b0:207:a2a3:2f3d with SMTP id l4-20020a5d5604000000b00207a2a32f3dmr18913328wrv.358.1650539931618; Thu, 21 Apr 2022 04:18:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/31] hw/arm: versal: Create an APU CPU Cluster Date: Thu, 21 Apr 2022 12:18:19 +0100 Message-Id: <20220421111846.2011565-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org> References: <20220421111846.2011565-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650540458069100001 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Create an APU CPU Cluster. This is in preparation to add the RPU. Signed-off-by: Edgar E. Iglesias Reviewed-by: Francisco Iglesias Message-id: 20220406174303.2022038-2-edgar.iglesias@xilinx.com Signed-off-by: Peter Maydell --- include/hw/arm/xlnx-versal.h | 2 ++ hw/arm/xlnx-versal.c | 9 ++++++++- 2 files changed, 10 insertions(+), 1 deletion(-) diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index 0728316ec77..d2d3028e185 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -14,6 +14,7 @@ =20 #include "hw/sysbus.h" #include "hw/arm/boot.h" +#include "hw/cpu/cluster.h" #include "hw/or-irq.h" #include "hw/sd/sdhci.h" #include "hw/intc/arm_gicv3.h" @@ -49,6 +50,7 @@ struct Versal { struct { struct { MemoryRegion mr; + CPUClusterState cluster; ARMCPU cpu[XLNX_VERSAL_NR_ACPUS]; GICv3State gic; } apu; diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 2551dfc22d6..4415ee413fc 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -34,10 +34,15 @@ static void versal_create_apu_cpus(Versal *s) { int i; =20 + object_initialize_child(OBJECT(s), "apu-cluster", &s->fpd.apu.cluster, + TYPE_CPU_CLUSTER); + qdev_prop_set_uint32(DEVICE(&s->fpd.apu.cluster), "cluster-id", 0); + for (i =3D 0; i < ARRAY_SIZE(s->fpd.apu.cpu); i++) { Object *obj; =20 - object_initialize_child(OBJECT(s), "apu-cpu[*]", &s->fpd.apu.cpu[i= ], + object_initialize_child(OBJECT(&s->fpd.apu.cluster), + "apu-cpu[*]", &s->fpd.apu.cpu[i], XLNX_VERSAL_ACPU_TYPE); obj =3D OBJECT(&s->fpd.apu.cpu[i]); if (i) { @@ -52,6 +57,8 @@ static void versal_create_apu_cpus(Versal *s) &error_abort); qdev_realize(DEVICE(obj), NULL, &error_fatal); } + + qdev_realize(DEVICE(&s->fpd.apu.cluster), NULL, &error_fatal); } =20 static void versal_create_apu_gic(Versal *s, qemu_irq *pic) --=20 2.25.1 From nobody Tue May 21 06:35:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650540593; cv=none; d=zohomail.com; s=zohoarc; b=BsHzwn3+o327oyvR130pn77+de29lXAOJOEXDaAz4JJN4xuxF0fXqZWR1ABQJNUzx/i/TYqLoTvSKMsbCm8cupt2RakpagkBOmMSaVFw5xN4NWoA2XuLJGFCIwARsmOVsXwuj+h1OMYETzyjsEs8qbh7ir67owM7n1Ps9I7eWpo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650540593; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BePwGfJ5XZrjJA9AlqDcYsFQYq5FiOLMVEDlWQi8GrM=; b=nxUkRAfGOJcW/P0A4HcqAP7Hp4RZYjIOBFmtPbMWgigZzeN9a0RrSubIcwe+C/Y+0wZPsecG9lDUI8A1bEw3ZwISKEc64qsCqx9Qi0eChqU6u9+8DovzICGxcBeTgfa8u5ZZEgj3i73yfoRIzCouCWOZz6Nm2tBDIE+SRPFC1O4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650540593059850.1079413608861; Thu, 21 Apr 2022 04:29:53 -0700 (PDT) Received: from localhost ([::1]:51604 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhV0R-0001vl-V4 for importer@patchew.org; Thu, 21 Apr 2022 07:29:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59120) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhUpr-0002oV-NW for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:18:55 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:34759) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nhUpp-0003Qe-R2 for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:18:55 -0400 Received: by mail-wr1-x429.google.com with SMTP id c10so6234376wrb.1 for ; Thu, 21 Apr 2022 04:18:53 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. 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Iglesias" Add the Cortex-R5Fs of the Versal RPU (Real-time Processing Unit) subsystem. Signed-off-by: Edgar E. Iglesias Reviewed-by: Francisco Iglesias Message-id: 20220406174303.2022038-3-edgar.iglesias@xilinx.com Signed-off-by: Peter Maydell --- include/hw/arm/xlnx-versal.h | 10 ++++++++++ hw/arm/xlnx-versal-virt.c | 6 +++--- hw/arm/xlnx-versal.c | 36 ++++++++++++++++++++++++++++++++++++ 3 files changed, 49 insertions(+), 3 deletions(-) diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index d2d3028e185..155e8c4b8cd 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -35,6 +35,7 @@ OBJECT_DECLARE_SIMPLE_TYPE(Versal, XLNX_VERSAL) =20 #define XLNX_VERSAL_NR_ACPUS 2 +#define XLNX_VERSAL_NR_RCPUS 2 #define XLNX_VERSAL_NR_UARTS 2 #define XLNX_VERSAL_NR_GEMS 2 #define XLNX_VERSAL_NR_ADMAS 8 @@ -73,6 +74,15 @@ struct Versal { VersalUsb2 usb; } iou; =20 + /* Real-time Processing Unit. */ + struct { + MemoryRegion mr; + MemoryRegion mr_ps_alias; + + CPUClusterState cluster; + ARMCPU cpu[XLNX_VERSAL_NR_RCPUS]; + } rpu; + struct { qemu_or_irq irq_orgate; XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM]; diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index 7c7baff8b7f..66a2de7e133 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -721,9 +721,9 @@ static void versal_virt_machine_class_init(ObjectClass = *oc, void *data) =20 mc->desc =3D "Xilinx Versal Virtual development board"; mc->init =3D versal_virt_init; - mc->min_cpus =3D XLNX_VERSAL_NR_ACPUS; - mc->max_cpus =3D XLNX_VERSAL_NR_ACPUS; - mc->default_cpus =3D XLNX_VERSAL_NR_ACPUS; + mc->min_cpus =3D XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS; + mc->max_cpus =3D XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS; + mc->default_cpus =3D XLNX_VERSAL_NR_ACPUS + XLNX_VERSAL_NR_RCPUS; mc->no_cdrom =3D true; mc->default_ram_id =3D "ddr"; } diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 4415ee413fc..ebad8dbb6d8 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -25,6 +25,7 @@ #include "hw/sysbus.h" =20 #define XLNX_VERSAL_ACPU_TYPE ARM_CPU_TYPE_NAME("cortex-a72") +#define XLNX_VERSAL_RCPU_TYPE ARM_CPU_TYPE_NAME("cortex-r5f") #define GEM_REVISION 0x40070106 =20 #define VERSAL_NUM_PMC_APB_IRQS 3 @@ -130,6 +131,35 @@ static void versal_create_apu_gic(Versal *s, qemu_irq = *pic) } } =20 +static void versal_create_rpu_cpus(Versal *s) +{ + int i; + + object_initialize_child(OBJECT(s), "rpu-cluster", &s->lpd.rpu.cluster, + TYPE_CPU_CLUSTER); + qdev_prop_set_uint32(DEVICE(&s->lpd.rpu.cluster), "cluster-id", 1); + + for (i =3D 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) { + Object *obj; + + object_initialize_child(OBJECT(&s->lpd.rpu.cluster), + "rpu-cpu[*]", &s->lpd.rpu.cpu[i], + XLNX_VERSAL_RCPU_TYPE); + obj =3D OBJECT(&s->lpd.rpu.cpu[i]); + object_property_set_bool(obj, "start-powered-off", true, + &error_abort); + + object_property_set_int(obj, "mp-affinity", 0x100 | i, &error_abor= t); + object_property_set_int(obj, "core-count", ARRAY_SIZE(s->lpd.rpu.c= pu), + &error_abort); + object_property_set_link(obj, "memory", OBJECT(&s->lpd.rpu.mr), + &error_abort); + qdev_realize(DEVICE(obj), NULL, &error_fatal); + } + + qdev_realize(DEVICE(&s->lpd.rpu.cluster), NULL, &error_fatal); +} + static void versal_create_uarts(Versal *s, qemu_irq *pic) { int i; @@ -638,6 +668,7 @@ static void versal_realize(DeviceState *dev, Error **er= rp) =20 versal_create_apu_cpus(s); versal_create_apu_gic(s, pic); + versal_create_rpu_cpus(s); versal_create_uarts(s, pic); versal_create_usbs(s, pic); versal_create_gems(s, pic); @@ -659,6 +690,8 @@ static void versal_realize(DeviceState *dev, Error **er= rp) =20 memory_region_add_subregion_overlap(&s->mr_ps, MM_OCM, &s->lpd.mr_ocm,= 0); memory_region_add_subregion_overlap(&s->fpd.apu.mr, 0, &s->mr_ps, 0); + memory_region_add_subregion_overlap(&s->lpd.rpu.mr, 0, + &s->lpd.rpu.mr_ps_alias, 0); } =20 static void versal_init(Object *obj) @@ -666,7 +699,10 @@ static void versal_init(Object *obj) Versal *s =3D XLNX_VERSAL(obj); =20 memory_region_init(&s->fpd.apu.mr, obj, "mr-apu", UINT64_MAX); + memory_region_init(&s->lpd.rpu.mr, obj, "mr-rpu", UINT64_MAX); memory_region_init(&s->mr_ps, obj, "mr-ps-switch", UINT64_MAX); + memory_region_init_alias(&s->lpd.rpu.mr_ps_alias, OBJECT(s), + "mr-rpu-ps-alias", &s->mr_ps, 0, UINT64_MAX); } =20 static Property versal_properties[] =3D { --=20 2.25.1 From nobody Tue May 21 06:35:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e4-20020a5d6d04000000b0020a8bbbb72bsm2597694wrq.97.2022.04.21.04.18.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 04:18:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=0h0Rvkwm6rsblcwsPxp9qPIXdkCkI7ax30Wxe1BZzVA=; b=CD/PiLoAr/lGQjPW0dqR/2R2juPclgbDVak4cLQiRUjqQ/5vCVCTvKkmGkeEmvSE29 slbDICrAhwPWWS17KAJ7dowZUgn5WSpHom2bfNXsC3GbRZB4d7P2Hyc5V3S1ur0vlqrx 3wkygZudbmxaYHZMj1s6alU9xZxVaZ5mleFXWAVHYQdKcYXvU5j4GRf70qEwO0wrSV+z ivFnCcZlmgr7ox95yRNOmT1BbHjF32KjRavsEZTKVyWRF67e9fLNbnxpwdqc849ZI6Co H8MlmNoiFLgaTqoC00516t3RMSRbAwj5TbElanon7Ykt+6G+Kx/XHBU979Og/jko5TPZ NfmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0h0Rvkwm6rsblcwsPxp9qPIXdkCkI7ax30Wxe1BZzVA=; b=7VV8vzvW3iJxILKUOvJcOzkSocZV9k0SrCt2DovYQkusf2NsoaKMRpOWRytUPwxKR7 YeUY2j+EoOeOSem1Ybqrjk85CYBQl0bvCDOp9NTO8aIgzBP0id26URxoCd49/4IGEN9B JTGzYoHm3GRD5h4FiNwEFg7hxuj6l1u342rQHBxsY29DJa1OzaKPpAn1JcP929Sg6/fr Okb4KM27NH0jK6svnR6eEv8vfPSwddCpnXfSi01SuL4ubhcNxgD0vPtwZxhyG+JOxUcC GwyXef5jt5x3Cm6jcehoKcDmjyEtKMSp2q65QshVF0zcsQuVHrGxCCmG/7zQ7wI3uOB/ dC0Q== X-Gm-Message-State: AOAM531EzfRrYZD9L3kwHA+P6R0MgxV2cllJDeErZ/+AxMXTxE3bRFWT wKu4l1bF2MnWjqT85sQFwlIYXuUAJv4+2Q== X-Google-Smtp-Source: ABdhPJxHgfUEWim6BcA6MXPvbl8lFwUXbFlp42/MwBrNuJ/gTLEfGmMpzofMSUr76dQXxXpcNas4Ug== X-Received: by 2002:a05:600c:1456:b0:38e:bd55:700 with SMTP id h22-20020a05600c145600b0038ebd550700mr8006170wmi.204.1650539933965; Thu, 21 Apr 2022 04:18:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/31] hw/misc: Add a model of the Xilinx Versal CRL Date: Thu, 21 Apr 2022 12:18:21 +0100 Message-Id: <20220421111846.2011565-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org> References: <20220421111846.2011565-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650540163963100001 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Add a model of the Xilinx Versal CRL. Signed-off-by: Edgar E. Iglesias Reviewed-by: Frederic Konrad Reviewed-by: Francisco Iglesias Message-id: 20220406174303.2022038-4-edgar.iglesias@xilinx.com Signed-off-by: Peter Maydell --- include/hw/misc/xlnx-versal-crl.h | 235 +++++++++++++++++ hw/misc/xlnx-versal-crl.c | 421 ++++++++++++++++++++++++++++++ hw/misc/meson.build | 1 + 3 files changed, 657 insertions(+) create mode 100644 include/hw/misc/xlnx-versal-crl.h create mode 100644 hw/misc/xlnx-versal-crl.c diff --git a/include/hw/misc/xlnx-versal-crl.h b/include/hw/misc/xlnx-versa= l-crl.h new file mode 100644 index 00000000000..2857f4169a5 --- /dev/null +++ b/include/hw/misc/xlnx-versal-crl.h @@ -0,0 +1,235 @@ +/* + * QEMU model of the Clock-Reset-LPD (CRL). + * + * Copyright (c) 2022 Xilinx Inc. + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Written by Edgar E. Iglesias + */ +#ifndef HW_MISC_XLNX_VERSAL_CRL_H +#define HW_MISC_XLNX_VERSAL_CRL_H + +#include "hw/sysbus.h" +#include "hw/register.h" +#include "target/arm/cpu.h" + +#define TYPE_XLNX_VERSAL_CRL "xlnx,versal-crl" +OBJECT_DECLARE_SIMPLE_TYPE(XlnxVersalCRL, XLNX_VERSAL_CRL) + +REG32(ERR_CTRL, 0x0) + FIELD(ERR_CTRL, SLVERR_ENABLE, 0, 1) +REG32(IR_STATUS, 0x4) + FIELD(IR_STATUS, ADDR_DECODE_ERR, 0, 1) +REG32(IR_MASK, 0x8) + FIELD(IR_MASK, ADDR_DECODE_ERR, 0, 1) +REG32(IR_ENABLE, 0xc) + FIELD(IR_ENABLE, ADDR_DECODE_ERR, 0, 1) +REG32(IR_DISABLE, 0x10) + FIELD(IR_DISABLE, ADDR_DECODE_ERR, 0, 1) +REG32(WPROT, 0x1c) + FIELD(WPROT, ACTIVE, 0, 1) +REG32(PLL_CLK_OTHER_DMN, 0x20) + FIELD(PLL_CLK_OTHER_DMN, APLL_BYPASS, 0, 1) +REG32(RPLL_CTRL, 0x40) + FIELD(RPLL_CTRL, POST_SRC, 24, 3) + FIELD(RPLL_CTRL, PRE_SRC, 20, 3) + FIELD(RPLL_CTRL, CLKOUTDIV, 16, 2) + FIELD(RPLL_CTRL, FBDIV, 8, 8) + FIELD(RPLL_CTRL, BYPASS, 3, 1) + FIELD(RPLL_CTRL, RESET, 0, 1) +REG32(RPLL_CFG, 0x44) + FIELD(RPLL_CFG, LOCK_DLY, 25, 7) + FIELD(RPLL_CFG, LOCK_CNT, 13, 10) + FIELD(RPLL_CFG, LFHF, 10, 2) + FIELD(RPLL_CFG, CP, 5, 4) + FIELD(RPLL_CFG, RES, 0, 4) +REG32(RPLL_FRAC_CFG, 0x48) + FIELD(RPLL_FRAC_CFG, ENABLED, 31, 1) + FIELD(RPLL_FRAC_CFG, SEED, 22, 3) + FIELD(RPLL_FRAC_CFG, ALGRTHM, 19, 1) + FIELD(RPLL_FRAC_CFG, ORDER, 18, 1) + FIELD(RPLL_FRAC_CFG, DATA, 0, 16) +REG32(PLL_STATUS, 0x50) + FIELD(PLL_STATUS, RPLL_STABLE, 2, 1) + FIELD(PLL_STATUS, RPLL_LOCK, 0, 1) +REG32(RPLL_TO_XPD_CTRL, 0x100) + FIELD(RPLL_TO_XPD_CTRL, CLKACT, 25, 1) + FIELD(RPLL_TO_XPD_CTRL, DIVISOR0, 8, 10) +REG32(LPD_TOP_SWITCH_CTRL, 0x104) + FIELD(LPD_TOP_SWITCH_CTRL, CLKACT_ADMA, 26, 1) + FIELD(LPD_TOP_SWITCH_CTRL, CLKACT, 25, 1) + FIELD(LPD_TOP_SWITCH_CTRL, DIVISOR0, 8, 10) + FIELD(LPD_TOP_SWITCH_CTRL, SRCSEL, 0, 3) +REG32(LPD_LSBUS_CTRL, 0x108) + FIELD(LPD_LSBUS_CTRL, CLKACT, 25, 1) + FIELD(LPD_LSBUS_CTRL, DIVISOR0, 8, 10) + FIELD(LPD_LSBUS_CTRL, SRCSEL, 0, 3) +REG32(CPU_R5_CTRL, 0x10c) + FIELD(CPU_R5_CTRL, CLKACT_OCM2, 28, 1) + FIELD(CPU_R5_CTRL, CLKACT_OCM, 27, 1) + FIELD(CPU_R5_CTRL, CLKACT_CORE, 26, 1) + FIELD(CPU_R5_CTRL, CLKACT, 25, 1) + FIELD(CPU_R5_CTRL, DIVISOR0, 8, 10) + FIELD(CPU_R5_CTRL, SRCSEL, 0, 3) +REG32(IOU_SWITCH_CTRL, 0x114) + FIELD(IOU_SWITCH_CTRL, CLKACT, 25, 1) + FIELD(IOU_SWITCH_CTRL, DIVISOR0, 8, 10) + FIELD(IOU_SWITCH_CTRL, SRCSEL, 0, 3) +REG32(GEM0_REF_CTRL, 0x118) + FIELD(GEM0_REF_CTRL, CLKACT_RX, 27, 1) + FIELD(GEM0_REF_CTRL, CLKACT_TX, 26, 1) + FIELD(GEM0_REF_CTRL, CLKACT, 25, 1) + FIELD(GEM0_REF_CTRL, DIVISOR0, 8, 10) + FIELD(GEM0_REF_CTRL, SRCSEL, 0, 3) +REG32(GEM1_REF_CTRL, 0x11c) + FIELD(GEM1_REF_CTRL, CLKACT_RX, 27, 1) + FIELD(GEM1_REF_CTRL, CLKACT_TX, 26, 1) + FIELD(GEM1_REF_CTRL, CLKACT, 25, 1) + FIELD(GEM1_REF_CTRL, DIVISOR0, 8, 10) + FIELD(GEM1_REF_CTRL, SRCSEL, 0, 3) +REG32(GEM_TSU_REF_CTRL, 0x120) + FIELD(GEM_TSU_REF_CTRL, CLKACT, 25, 1) + FIELD(GEM_TSU_REF_CTRL, DIVISOR0, 8, 10) + FIELD(GEM_TSU_REF_CTRL, SRCSEL, 0, 3) +REG32(USB0_BUS_REF_CTRL, 0x124) + FIELD(USB0_BUS_REF_CTRL, CLKACT, 25, 1) + FIELD(USB0_BUS_REF_CTRL, DIVISOR0, 8, 10) + FIELD(USB0_BUS_REF_CTRL, SRCSEL, 0, 3) +REG32(UART0_REF_CTRL, 0x128) + FIELD(UART0_REF_CTRL, CLKACT, 25, 1) + FIELD(UART0_REF_CTRL, DIVISOR0, 8, 10) + FIELD(UART0_REF_CTRL, SRCSEL, 0, 3) +REG32(UART1_REF_CTRL, 0x12c) + FIELD(UART1_REF_CTRL, CLKACT, 25, 1) + FIELD(UART1_REF_CTRL, DIVISOR0, 8, 10) + FIELD(UART1_REF_CTRL, SRCSEL, 0, 3) +REG32(SPI0_REF_CTRL, 0x130) + FIELD(SPI0_REF_CTRL, CLKACT, 25, 1) + FIELD(SPI0_REF_CTRL, DIVISOR0, 8, 10) + FIELD(SPI0_REF_CTRL, SRCSEL, 0, 3) +REG32(SPI1_REF_CTRL, 0x134) + FIELD(SPI1_REF_CTRL, CLKACT, 25, 1) + FIELD(SPI1_REF_CTRL, DIVISOR0, 8, 10) + FIELD(SPI1_REF_CTRL, SRCSEL, 0, 3) +REG32(CAN0_REF_CTRL, 0x138) + FIELD(CAN0_REF_CTRL, CLKACT, 25, 1) + FIELD(CAN0_REF_CTRL, DIVISOR0, 8, 10) + FIELD(CAN0_REF_CTRL, SRCSEL, 0, 3) +REG32(CAN1_REF_CTRL, 0x13c) + FIELD(CAN1_REF_CTRL, CLKACT, 25, 1) + FIELD(CAN1_REF_CTRL, DIVISOR0, 8, 10) + FIELD(CAN1_REF_CTRL, SRCSEL, 0, 3) +REG32(I2C0_REF_CTRL, 0x140) + FIELD(I2C0_REF_CTRL, CLKACT, 25, 1) + FIELD(I2C0_REF_CTRL, DIVISOR0, 8, 10) + FIELD(I2C0_REF_CTRL, SRCSEL, 0, 3) +REG32(I2C1_REF_CTRL, 0x144) + FIELD(I2C1_REF_CTRL, CLKACT, 25, 1) + FIELD(I2C1_REF_CTRL, DIVISOR0, 8, 10) + FIELD(I2C1_REF_CTRL, SRCSEL, 0, 3) +REG32(DBG_LPD_CTRL, 0x148) + FIELD(DBG_LPD_CTRL, CLKACT, 25, 1) + FIELD(DBG_LPD_CTRL, DIVISOR0, 8, 10) + FIELD(DBG_LPD_CTRL, SRCSEL, 0, 3) +REG32(TIMESTAMP_REF_CTRL, 0x14c) + FIELD(TIMESTAMP_REF_CTRL, CLKACT, 25, 1) + FIELD(TIMESTAMP_REF_CTRL, DIVISOR0, 8, 10) + FIELD(TIMESTAMP_REF_CTRL, SRCSEL, 0, 3) +REG32(CRL_SAFETY_CHK, 0x150) +REG32(PSM_REF_CTRL, 0x154) + FIELD(PSM_REF_CTRL, DIVISOR0, 8, 10) + FIELD(PSM_REF_CTRL, SRCSEL, 0, 3) +REG32(DBG_TSTMP_CTRL, 0x158) + FIELD(DBG_TSTMP_CTRL, CLKACT, 25, 1) + FIELD(DBG_TSTMP_CTRL, DIVISOR0, 8, 10) + FIELD(DBG_TSTMP_CTRL, SRCSEL, 0, 3) +REG32(CPM_TOPSW_REF_CTRL, 0x15c) + FIELD(CPM_TOPSW_REF_CTRL, CLKACT, 25, 1) + FIELD(CPM_TOPSW_REF_CTRL, DIVISOR0, 8, 10) + FIELD(CPM_TOPSW_REF_CTRL, SRCSEL, 0, 3) +REG32(USB3_DUAL_REF_CTRL, 0x160) + FIELD(USB3_DUAL_REF_CTRL, CLKACT, 25, 1) + FIELD(USB3_DUAL_REF_CTRL, DIVISOR0, 8, 10) + FIELD(USB3_DUAL_REF_CTRL, SRCSEL, 0, 3) +REG32(RST_CPU_R5, 0x300) + FIELD(RST_CPU_R5, RESET_PGE, 4, 1) + FIELD(RST_CPU_R5, RESET_AMBA, 2, 1) + FIELD(RST_CPU_R5, RESET_CPU1, 1, 1) + FIELD(RST_CPU_R5, RESET_CPU0, 0, 1) +REG32(RST_ADMA, 0x304) + FIELD(RST_ADMA, RESET, 0, 1) +REG32(RST_GEM0, 0x308) + FIELD(RST_GEM0, RESET, 0, 1) +REG32(RST_GEM1, 0x30c) + FIELD(RST_GEM1, RESET, 0, 1) +REG32(RST_SPARE, 0x310) + FIELD(RST_SPARE, RESET, 0, 1) +REG32(RST_USB0, 0x314) + FIELD(RST_USB0, RESET, 0, 1) +REG32(RST_UART0, 0x318) + FIELD(RST_UART0, RESET, 0, 1) +REG32(RST_UART1, 0x31c) + FIELD(RST_UART1, RESET, 0, 1) +REG32(RST_SPI0, 0x320) + FIELD(RST_SPI0, RESET, 0, 1) +REG32(RST_SPI1, 0x324) + FIELD(RST_SPI1, RESET, 0, 1) +REG32(RST_CAN0, 0x328) + FIELD(RST_CAN0, RESET, 0, 1) +REG32(RST_CAN1, 0x32c) + FIELD(RST_CAN1, RESET, 0, 1) +REG32(RST_I2C0, 0x330) + FIELD(RST_I2C0, RESET, 0, 1) +REG32(RST_I2C1, 0x334) + FIELD(RST_I2C1, RESET, 0, 1) +REG32(RST_DBG_LPD, 0x338) + FIELD(RST_DBG_LPD, RPU_DBG1_RESET, 5, 1) + FIELD(RST_DBG_LPD, RPU_DBG0_RESET, 4, 1) + FIELD(RST_DBG_LPD, RESET_HSDP, 1, 1) + FIELD(RST_DBG_LPD, RESET, 0, 1) +REG32(RST_GPIO, 0x33c) + FIELD(RST_GPIO, RESET, 0, 1) +REG32(RST_TTC, 0x344) + FIELD(RST_TTC, TTC3_RESET, 3, 1) + FIELD(RST_TTC, TTC2_RESET, 2, 1) + FIELD(RST_TTC, TTC1_RESET, 1, 1) + FIELD(RST_TTC, TTC0_RESET, 0, 1) +REG32(RST_TIMESTAMP, 0x348) + FIELD(RST_TIMESTAMP, RESET, 0, 1) +REG32(RST_SWDT, 0x34c) + FIELD(RST_SWDT, RESET, 0, 1) +REG32(RST_OCM, 0x350) + FIELD(RST_OCM, RESET, 0, 1) +REG32(RST_IPI, 0x354) + FIELD(RST_IPI, RESET, 0, 1) +REG32(RST_SYSMON, 0x358) + FIELD(RST_SYSMON, SEQ_RST, 1, 1) + FIELD(RST_SYSMON, CFG_RST, 0, 1) +REG32(RST_FPD, 0x360) + FIELD(RST_FPD, SRST, 1, 1) + FIELD(RST_FPD, POR, 0, 1) +REG32(PSM_RST_MODE, 0x370) + FIELD(PSM_RST_MODE, WAKEUP, 2, 1) + FIELD(PSM_RST_MODE, RST_MODE, 0, 2) + +#define CRL_R_MAX (R_PSM_RST_MODE + 1) + +#define RPU_MAX_CPU 2 + +struct XlnxVersalCRL { + SysBusDevice parent_obj; + qemu_irq irq; + + struct { + ARMCPU *cpu_r5[RPU_MAX_CPU]; + DeviceState *adma[8]; + DeviceState *uart[2]; + DeviceState *gem[2]; + DeviceState *usb; + } cfg; + + RegisterInfoArray *reg_array; + uint32_t regs[CRL_R_MAX]; + RegisterInfo regs_info[CRL_R_MAX]; +}; +#endif diff --git a/hw/misc/xlnx-versal-crl.c b/hw/misc/xlnx-versal-crl.c new file mode 100644 index 00000000000..767106b7a30 --- /dev/null +++ b/hw/misc/xlnx-versal-crl.c @@ -0,0 +1,421 @@ +/* + * QEMU model of the Clock-Reset-LPD (CRL). + * + * Copyright (c) 2022 Advanced Micro Devices, Inc. + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Written by Edgar E. Iglesias + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/log.h" +#include "qemu/bitops.h" +#include "migration/vmstate.h" +#include "hw/qdev-properties.h" +#include "hw/sysbus.h" +#include "hw/irq.h" +#include "hw/register.h" +#include "hw/resettable.h" + +#include "target/arm/arm-powerctl.h" +#include "hw/misc/xlnx-versal-crl.h" + +#ifndef XLNX_VERSAL_CRL_ERR_DEBUG +#define XLNX_VERSAL_CRL_ERR_DEBUG 0 +#endif + +static void crl_update_irq(XlnxVersalCRL *s) +{ + bool pending =3D s->regs[R_IR_STATUS] & ~s->regs[R_IR_MASK]; + qemu_set_irq(s->irq, pending); +} + +static void crl_status_postw(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(reg->opaque); + crl_update_irq(s); +} + +static uint64_t crl_enable_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(reg->opaque); + uint32_t val =3D val64; + + s->regs[R_IR_MASK] &=3D ~val; + crl_update_irq(s); + return 0; +} + +static uint64_t crl_disable_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(reg->opaque); + uint32_t val =3D val64; + + s->regs[R_IR_MASK] |=3D val; + crl_update_irq(s); + return 0; +} + +static void crl_reset_dev(XlnxVersalCRL *s, DeviceState *dev, + bool rst_old, bool rst_new) +{ + device_cold_reset(dev); +} + +static void crl_reset_cpu(XlnxVersalCRL *s, ARMCPU *armcpu, + bool rst_old, bool rst_new) +{ + if (rst_new) { + arm_set_cpu_off(armcpu->mp_affinity); + } else { + arm_set_cpu_on_and_reset(armcpu->mp_affinity); + } +} + +#define REGFIELD_RESET(type, s, reg, f, new_val, dev) { \ + bool old_f =3D ARRAY_FIELD_EX32((s)->regs, reg, f); \ + bool new_f =3D FIELD_EX32(new_val, reg, f); \ + \ + /* Detect edges. */ \ + if (dev && old_f !=3D new_f) { \ + crl_reset_ ## type(s, dev, old_f, new_f); \ + } \ +} + +static uint64_t crl_rst_r5_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(reg->opaque); + + REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU0, val64, s->cfg.cpu_r5[0]= ); + REGFIELD_RESET(cpu, s, RST_CPU_R5, RESET_CPU1, val64, s->cfg.cpu_r5[1]= ); + return val64; +} + +static uint64_t crl_rst_adma_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(reg->opaque); + int i; + + /* A single register fans out to all ADMA reset inputs. */ + for (i =3D 0; i < ARRAY_SIZE(s->cfg.adma); i++) { + REGFIELD_RESET(dev, s, RST_ADMA, RESET, val64, s->cfg.adma[i]); + } + return val64; +} + +static uint64_t crl_rst_uart0_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(reg->opaque); + + REGFIELD_RESET(dev, s, RST_UART0, RESET, val64, s->cfg.uart[0]); + return val64; +} + +static uint64_t crl_rst_uart1_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(reg->opaque); + + REGFIELD_RESET(dev, s, RST_UART1, RESET, val64, s->cfg.uart[1]); + return val64; +} + +static uint64_t crl_rst_gem0_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(reg->opaque); + + REGFIELD_RESET(dev, s, RST_GEM0, RESET, val64, s->cfg.gem[0]); + return val64; +} + +static uint64_t crl_rst_gem1_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(reg->opaque); + + REGFIELD_RESET(dev, s, RST_GEM1, RESET, val64, s->cfg.gem[1]); + return val64; +} + +static uint64_t crl_rst_usb_prew(RegisterInfo *reg, uint64_t val64) +{ + XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(reg->opaque); + + REGFIELD_RESET(dev, s, RST_USB0, RESET, val64, s->cfg.usb); + return val64; +} + +static const RegisterAccessInfo crl_regs_info[] =3D { + { .name =3D "ERR_CTRL", .addr =3D A_ERR_CTRL, + },{ .name =3D "IR_STATUS", .addr =3D A_IR_STATUS, + .w1c =3D 0x1, + .post_write =3D crl_status_postw, + },{ .name =3D "IR_MASK", .addr =3D A_IR_MASK, + .reset =3D 0x1, + .ro =3D 0x1, + },{ .name =3D "IR_ENABLE", .addr =3D A_IR_ENABLE, + .pre_write =3D crl_enable_prew, + },{ .name =3D "IR_DISABLE", .addr =3D A_IR_DISABLE, + .pre_write =3D crl_disable_prew, + },{ .name =3D "WPROT", .addr =3D A_WPROT, + },{ .name =3D "PLL_CLK_OTHER_DMN", .addr =3D A_PLL_CLK_OTHER_DMN, + .reset =3D 0x1, + .rsvd =3D 0xe, + },{ .name =3D "RPLL_CTRL", .addr =3D A_RPLL_CTRL, + .reset =3D 0x24809, + .rsvd =3D 0xf88c00f6, + },{ .name =3D "RPLL_CFG", .addr =3D A_RPLL_CFG, + .reset =3D 0x2000000, + .rsvd =3D 0x1801210, + },{ .name =3D "RPLL_FRAC_CFG", .addr =3D A_RPLL_FRAC_CFG, + .rsvd =3D 0x7e330000, + },{ .name =3D "PLL_STATUS", .addr =3D A_PLL_STATUS, + .reset =3D R_PLL_STATUS_RPLL_STABLE_MASK | + R_PLL_STATUS_RPLL_LOCK_MASK, + .rsvd =3D 0xfa, + .ro =3D 0x5, + },{ .name =3D "RPLL_TO_XPD_CTRL", .addr =3D A_RPLL_TO_XPD_CTRL, + .reset =3D 0x2000100, + .rsvd =3D 0xfdfc00ff, + },{ .name =3D "LPD_TOP_SWITCH_CTRL", .addr =3D A_LPD_TOP_SWITCH_CTRL, + .reset =3D 0x6000300, + .rsvd =3D 0xf9fc00f8, + },{ .name =3D "LPD_LSBUS_CTRL", .addr =3D A_LPD_LSBUS_CTRL, + .reset =3D 0x2000800, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "CPU_R5_CTRL", .addr =3D A_CPU_R5_CTRL, + .reset =3D 0xe000300, + .rsvd =3D 0xe1fc00f8, + },{ .name =3D "IOU_SWITCH_CTRL", .addr =3D A_IOU_SWITCH_CTRL, + .reset =3D 0x2000500, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "GEM0_REF_CTRL", .addr =3D A_GEM0_REF_CTRL, + .reset =3D 0xe000a00, + .rsvd =3D 0xf1fc00f8, + },{ .name =3D "GEM1_REF_CTRL", .addr =3D A_GEM1_REF_CTRL, + .reset =3D 0xe000a00, + .rsvd =3D 0xf1fc00f8, + },{ .name =3D "GEM_TSU_REF_CTRL", .addr =3D A_GEM_TSU_REF_CTRL, + .reset =3D 0x300, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "USB0_BUS_REF_CTRL", .addr =3D A_USB0_BUS_REF_CTRL, + .reset =3D 0x2001900, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "UART0_REF_CTRL", .addr =3D A_UART0_REF_CTRL, + .reset =3D 0xc00, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "UART1_REF_CTRL", .addr =3D A_UART1_REF_CTRL, + .reset =3D 0xc00, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "SPI0_REF_CTRL", .addr =3D A_SPI0_REF_CTRL, + .reset =3D 0x600, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "SPI1_REF_CTRL", .addr =3D A_SPI1_REF_CTRL, + .reset =3D 0x600, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "CAN0_REF_CTRL", .addr =3D A_CAN0_REF_CTRL, + .reset =3D 0xc00, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "CAN1_REF_CTRL", .addr =3D A_CAN1_REF_CTRL, + .reset =3D 0xc00, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "I2C0_REF_CTRL", .addr =3D A_I2C0_REF_CTRL, + .reset =3D 0xc00, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "I2C1_REF_CTRL", .addr =3D A_I2C1_REF_CTRL, + .reset =3D 0xc00, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "DBG_LPD_CTRL", .addr =3D A_DBG_LPD_CTRL, + .reset =3D 0x300, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "TIMESTAMP_REF_CTRL", .addr =3D A_TIMESTAMP_REF_CTRL, + .reset =3D 0x2000c00, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "CRL_SAFETY_CHK", .addr =3D A_CRL_SAFETY_CHK, + },{ .name =3D "PSM_REF_CTRL", .addr =3D A_PSM_REF_CTRL, + .reset =3D 0xf04, + .rsvd =3D 0xfffc00f8, + },{ .name =3D "DBG_TSTMP_CTRL", .addr =3D A_DBG_TSTMP_CTRL, + .reset =3D 0x300, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "CPM_TOPSW_REF_CTRL", .addr =3D A_CPM_TOPSW_REF_CTRL, + .reset =3D 0x300, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "USB3_DUAL_REF_CTRL", .addr =3D A_USB3_DUAL_REF_CTRL, + .reset =3D 0x3c00, + .rsvd =3D 0xfdfc00f8, + },{ .name =3D "RST_CPU_R5", .addr =3D A_RST_CPU_R5, + .reset =3D 0x17, + .rsvd =3D 0x8, + .pre_write =3D crl_rst_r5_prew, + },{ .name =3D "RST_ADMA", .addr =3D A_RST_ADMA, + .reset =3D 0x1, + .pre_write =3D crl_rst_adma_prew, + },{ .name =3D "RST_GEM0", .addr =3D A_RST_GEM0, + .reset =3D 0x1, + .pre_write =3D crl_rst_gem0_prew, + },{ .name =3D "RST_GEM1", .addr =3D A_RST_GEM1, + .reset =3D 0x1, + .pre_write =3D crl_rst_gem1_prew, + },{ .name =3D "RST_SPARE", .addr =3D A_RST_SPARE, + .reset =3D 0x1, + },{ .name =3D "RST_USB0", .addr =3D A_RST_USB0, + .reset =3D 0x1, + .pre_write =3D crl_rst_usb_prew, + },{ .name =3D "RST_UART0", .addr =3D A_RST_UART0, + .reset =3D 0x1, + .pre_write =3D crl_rst_uart0_prew, + },{ .name =3D "RST_UART1", .addr =3D A_RST_UART1, + .reset =3D 0x1, + .pre_write =3D crl_rst_uart1_prew, + },{ .name =3D "RST_SPI0", .addr =3D A_RST_SPI0, + .reset =3D 0x1, + },{ .name =3D "RST_SPI1", .addr =3D A_RST_SPI1, + .reset =3D 0x1, + },{ .name =3D "RST_CAN0", .addr =3D A_RST_CAN0, + .reset =3D 0x1, + },{ .name =3D "RST_CAN1", .addr =3D A_RST_CAN1, + .reset =3D 0x1, + },{ .name =3D "RST_I2C0", .addr =3D A_RST_I2C0, + .reset =3D 0x1, + },{ .name =3D "RST_I2C1", .addr =3D A_RST_I2C1, + .reset =3D 0x1, + },{ .name =3D "RST_DBG_LPD", .addr =3D A_RST_DBG_LPD, + .reset =3D 0x33, + .rsvd =3D 0xcc, + },{ .name =3D "RST_GPIO", .addr =3D A_RST_GPIO, + .reset =3D 0x1, + },{ .name =3D "RST_TTC", .addr =3D A_RST_TTC, + .reset =3D 0xf, + },{ .name =3D "RST_TIMESTAMP", .addr =3D A_RST_TIMESTAMP, + .reset =3D 0x1, + },{ .name =3D "RST_SWDT", .addr =3D A_RST_SWDT, + .reset =3D 0x1, + },{ .name =3D "RST_OCM", .addr =3D A_RST_OCM, + },{ .name =3D "RST_IPI", .addr =3D A_RST_IPI, + },{ .name =3D "RST_FPD", .addr =3D A_RST_FPD, + .reset =3D 0x3, + },{ .name =3D "PSM_RST_MODE", .addr =3D A_PSM_RST_MODE, + .reset =3D 0x1, + .rsvd =3D 0xf8, + } +}; + +static void crl_reset_enter(Object *obj, ResetType type) +{ + XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(obj); + unsigned int i; + + for (i =3D 0; i < ARRAY_SIZE(s->regs_info); ++i) { + register_reset(&s->regs_info[i]); + } +} + +static void crl_reset_hold(Object *obj) +{ + XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(obj); + + crl_update_irq(s); +} + +static const MemoryRegionOps crl_ops =3D { + .read =3D register_read_memory, + .write =3D register_write_memory, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4, + }, +}; + +static void crl_init(Object *obj) +{ + XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(obj); + SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); + int i; + + s->reg_array =3D + register_init_block32(DEVICE(obj), crl_regs_info, + ARRAY_SIZE(crl_regs_info), + s->regs_info, s->regs, + &crl_ops, + XLNX_VERSAL_CRL_ERR_DEBUG, + CRL_R_MAX * 4); + sysbus_init_mmio(sbd, &s->reg_array->mem); + sysbus_init_irq(sbd, &s->irq); + + for (i =3D 0; i < ARRAY_SIZE(s->cfg.cpu_r5); ++i) { + object_property_add_link(obj, "cpu_r5[*]", TYPE_ARM_CPU, + (Object **)&s->cfg.cpu_r5[i], + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG); + } + + for (i =3D 0; i < ARRAY_SIZE(s->cfg.adma); ++i) { + object_property_add_link(obj, "adma[*]", TYPE_DEVICE, + (Object **)&s->cfg.adma[i], + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG); + } + + for (i =3D 0; i < ARRAY_SIZE(s->cfg.uart); ++i) { + object_property_add_link(obj, "uart[*]", TYPE_DEVICE, + (Object **)&s->cfg.uart[i], + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG); + } + + for (i =3D 0; i < ARRAY_SIZE(s->cfg.gem); ++i) { + object_property_add_link(obj, "gem[*]", TYPE_DEVICE, + (Object **)&s->cfg.gem[i], + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG); + } + + object_property_add_link(obj, "usb", TYPE_DEVICE, + (Object **)&s->cfg.gem[i], + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG); +} + +static void crl_finalize(Object *obj) +{ + XlnxVersalCRL *s =3D XLNX_VERSAL_CRL(obj); + register_finalize_block(s->reg_array); +} + +static const VMStateDescription vmstate_crl =3D { + .name =3D TYPE_XLNX_VERSAL_CRL, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, XlnxVersalCRL, CRL_R_MAX), + VMSTATE_END_OF_LIST(), + } +}; + +static void crl_class_init(ObjectClass *klass, void *data) +{ + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->vmsd =3D &vmstate_crl; + + rc->phases.enter =3D crl_reset_enter; + rc->phases.hold =3D crl_reset_hold; +} + +static const TypeInfo crl_info =3D { + .name =3D TYPE_XLNX_VERSAL_CRL, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(XlnxVersalCRL), + .class_init =3D crl_class_init, + .instance_init =3D crl_init, + .instance_finalize =3D crl_finalize, +}; + +static void crl_register_types(void) +{ + type_register_static(&crl_info); +} + +type_init(crl_register_types) diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 6fb69612e06..2ff05c7afa9 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -86,6 +86,7 @@ softmmu_ss.add(when: 'CONFIG_SLAVIO', if_true: files('sla= vio_misc.c')) softmmu_ss.add(when: 'CONFIG_ZYNQ', if_true: files('zynq_slcr.c')) specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqm= p-crf.c')) specific_ss.add(when: 'CONFIG_XLNX_ZYNQMP_ARM', if_true: files('xlnx-zynqm= p-apu-ctrl.c')) +specific_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-cr= l.c')) softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files( 'xlnx-versal-xramc.c', 'xlnx-versal-pmc-iou-slcr.c', --=20 2.25.1 From nobody Tue May 21 06:35:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e4-20020a5d6d04000000b0020a8bbbb72bsm2597694wrq.97.2022.04.21.04.18.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 04:18:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ReWbTkMl4DXESP2NpUgeKJbFF10+7aoUcCCjIOL5Pg0=; b=cnXwucAX4ita/RXYBwOjjTX1ucS1P+1bWQByMWzDSrnjqWGFPedrryYLAbm985FRjL MQNoahUKBKUKVDIEfobInWrcfVnAf2L5g7Fxs+48/7Ve6mDZvdYaAZmdUkksYjYONxt8 MlHvDEliVM0kqU2P+kEqx0RSmHHcZ1y0wTBlNYRl7T3+CAvVJKJwJtiyweDUJyRbZN8I rVTpaKUTPymYV9m5YFxw30VXciVj4aDbrWeY4x53Joqb7L7MxtNmZHjeAiu/iCPksI4f aXoQ+sflE4f7cS+rN1lFDR3WPq6lztDwGHSFvEFTBX/XgR9LSANj47B305qAefCtJAfx UTYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ReWbTkMl4DXESP2NpUgeKJbFF10+7aoUcCCjIOL5Pg0=; b=lwU71gZmNQhcj9mFDCO6uGIq2Qd/GQ4USxSq0FSo4oyjPJDlueqqZOsJLgBkzBwl8O acsr2hq4s5/nVpRr2aLAMKCcEahscSyCjRfnUso29pRU/Jd62D+fATFs/KTC+rdLLlP8 uUN0paUQ6ZyRU17k29FajELj7MZzSSMLvjRloSYaO3IcxIw+itHkY2z1Z2nDsyenhSvl 8Y159IvFwRNGr/5BiIrHSg3Pqv4SyTORRarXRrflP1WstaJyxro39K45/mG92DZqxrUV NT5cjHeBJCRT+sO8g5yakUTGML9Q2FFcrTAPP/Lhm0ngc5SEMIadRlBu8JcrtDHjn7fz zRHw== X-Gm-Message-State: AOAM533YbCrtWMdHhENwiI/I8+pVRM038cNw4QEpOPH1DsFkqOiwa+RD 6S/dkEorBHudsFcXAqZvdGcGVyngBcYIZg== X-Google-Smtp-Source: ABdhPJzK0UPgKImE4KiKikblbSEvd1qxdJKlNuJlWclh3/2Cxj0Bv+gcbXAbMtosuHMl7prBdjwYJw== X-Received: by 2002:a05:6000:18c5:b0:207:ac0d:f32 with SMTP id w5-20020a05600018c500b00207ac0d0f32mr18555079wrq.574.1650539934888; Thu, 21 Apr 2022 04:18:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/31] hw/arm: versal: Connect the CRL Date: Thu, 21 Apr 2022 12:18:22 +0100 Message-Id: <20220421111846.2011565-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org> References: <20220421111846.2011565-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650540860740100001 Content-Type: text/plain; charset="utf-8" From: "Edgar E. Iglesias" Connect the CRL (Clock Reset LPD) to the Versal SoC. Signed-off-by: Edgar E. Iglesias Reviewed-by: Frederic Konrad Reviewed-by: Francisco Iglesias Message-id: 20220406174303.2022038-5-edgar.iglesias@xilinx.com Signed-off-by: Peter Maydell --- include/hw/arm/xlnx-versal.h | 4 +++ hw/arm/xlnx-versal.c | 54 ++++++++++++++++++++++++++++++++++-- 2 files changed, 56 insertions(+), 2 deletions(-) diff --git a/include/hw/arm/xlnx-versal.h b/include/hw/arm/xlnx-versal.h index 155e8c4b8cd..cbe8a19c10f 100644 --- a/include/hw/arm/xlnx-versal.h +++ b/include/hw/arm/xlnx-versal.h @@ -29,6 +29,7 @@ #include "hw/nvram/xlnx-versal-efuse.h" #include "hw/ssi/xlnx-versal-ospi.h" #include "hw/dma/xlnx_csu_dma.h" +#include "hw/misc/xlnx-versal-crl.h" #include "hw/misc/xlnx-versal-pmc-iou-slcr.h" =20 #define TYPE_XLNX_VERSAL "xlnx-versal" @@ -87,6 +88,8 @@ struct Versal { qemu_or_irq irq_orgate; XlnxXramCtrl ctrl[XLNX_VERSAL_NR_XRAM]; } xram; + + XlnxVersalCRL crl; } lpd; =20 /* The Platform Management Controller subsystem. */ @@ -127,6 +130,7 @@ struct Versal { #define VERSAL_TIMER_NS_EL1_IRQ 14 #define VERSAL_TIMER_NS_EL2_IRQ 10 =20 +#define VERSAL_CRL_IRQ 10 #define VERSAL_UART0_IRQ_0 18 #define VERSAL_UART1_IRQ_0 19 #define VERSAL_USB0_IRQ_0 22 diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index ebad8dbb6d8..57276e1506f 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -539,6 +539,57 @@ static void versal_create_ospi(Versal *s, qemu_irq *pi= c) qdev_connect_gpio_out(orgate, 0, pic[VERSAL_OSPI_IRQ]); } =20 +static void versal_create_crl(Versal *s, qemu_irq *pic) +{ + SysBusDevice *sbd; + int i; + + object_initialize_child(OBJECT(s), "crl", &s->lpd.crl, + TYPE_XLNX_VERSAL_CRL); + sbd =3D SYS_BUS_DEVICE(&s->lpd.crl); + + for (i =3D 0; i < ARRAY_SIZE(s->lpd.rpu.cpu); i++) { + g_autofree gchar *name =3D g_strdup_printf("cpu_r5[%d]", i); + + object_property_set_link(OBJECT(&s->lpd.crl), + name, OBJECT(&s->lpd.rpu.cpu[i]), + &error_abort); + } + + for (i =3D 0; i < ARRAY_SIZE(s->lpd.iou.gem); i++) { + g_autofree gchar *name =3D g_strdup_printf("gem[%d]", i); + + object_property_set_link(OBJECT(&s->lpd.crl), + name, OBJECT(&s->lpd.iou.gem[i]), + &error_abort); + } + + for (i =3D 0; i < ARRAY_SIZE(s->lpd.iou.adma); i++) { + g_autofree gchar *name =3D g_strdup_printf("adma[%d]", i); + + object_property_set_link(OBJECT(&s->lpd.crl), + name, OBJECT(&s->lpd.iou.adma[i]), + &error_abort); + } + + for (i =3D 0; i < ARRAY_SIZE(s->lpd.iou.uart); i++) { + g_autofree gchar *name =3D g_strdup_printf("uart[%d]", i); + + object_property_set_link(OBJECT(&s->lpd.crl), + name, OBJECT(&s->lpd.iou.uart[i]), + &error_abort); + } + + object_property_set_link(OBJECT(&s->lpd.crl), + "usb", OBJECT(&s->lpd.iou.usb), + &error_abort); + + sysbus_realize(sbd, &error_fatal); + memory_region_add_subregion(&s->mr_ps, MM_CRL, + sysbus_mmio_get_region(sbd, 0)); + sysbus_connect_irq(sbd, 0, pic[VERSAL_CRL_IRQ]); +} + /* This takes the board allocated linear DDR memory and creates aliases * for each split DDR range/aperture on the Versal address map. */ @@ -622,8 +673,6 @@ static void versal_unimp(Versal *s) =20 versal_unimp_area(s, "psm", &s->mr_ps, MM_PSM_START, MM_PSM_END - MM_PSM_START); - versal_unimp_area(s, "crl", &s->mr_ps, - MM_CRL, MM_CRL_SIZE); versal_unimp_area(s, "crf", &s->mr_ps, MM_FPD_CRF, MM_FPD_CRF_SIZE); versal_unimp_area(s, "apu", &s->mr_ps, @@ -681,6 +730,7 @@ static void versal_realize(DeviceState *dev, Error **er= rp) versal_create_efuse(s, pic); versal_create_pmc_iou_slcr(s, pic); versal_create_ospi(s, pic); + versal_create_crl(s, pic); versal_map_ddr(s); versal_unimp(s); =20 --=20 2.25.1 From nobody Tue May 21 06:35:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650540355; cv=none; d=zohomail.com; s=zohoarc; b=g+yKGbdJNHsNBM1H1hdTcSjE7gw6jEKoVYBcSar7nMVzz1lpn1dhGG312nRCC5OOLvdMVhYwMi9p1azF7wGtjuIrrYn9n40ho9uAu2WqcDpxdNU3RcE+0iZZrgzCAAdutrYxMfkXVu4W/wPQLywm69Y5HgN7BzqC2jtQmLloYIY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650540355; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QXsRoPUHqCo0IDRsRtZasRxyubwKd5nnuvujoVU4STM=; b=jzD2XZ53NtE3wGzrxwOuRXn1bbVtAxZyvnlk+6pTyrsjKsfn0lln37j5eHkXC7tZQPBe6sub2bEwyIXzOnBUjTg64c09aYZnEjJ8sBeiHZjAuVBoS4oHFIWOpUVVpFsku81AotRpj3/10eY9V7APF8JQk50tXxV54aJeDtwP2Y0= ARC-Authentication-Results: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e4-20020a5d6d04000000b0020a8bbbb72bsm2597694wrq.97.2022.04.21.04.18.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 04:18:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=QXsRoPUHqCo0IDRsRtZasRxyubwKd5nnuvujoVU4STM=; b=t1uGfVXbk4R7suZ/3tVt3awik1AUZu3LlHN4XGUyFmWcNQU6Vkvro3ZJ+PQ15h0Ilx NcCyN2ET3I/7UzweVHFxRSAQbE9X9LBqmCU4nbCsjMW7igWsNK4ssmIVkH3MnMKUlMay YcBf1Bzq8OUyNjN6ei1744WxAygVHhVwQKeJ9aGcygUinjBhrrTgXZWNtwW4qHijuDky ZWx65f0lIDogvjhS2s3EE2XHdzt4G/G/DMYZxQayMjBrXALvBkdhLxZk/CV+EUG6ijsJ aaw25+v4ZBavga8VRSSKGJAeovrd5ezDWl7XiJmu5Hc2Ize9EF5+ibPt4B8A6GFLjx5Z 6eBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QXsRoPUHqCo0IDRsRtZasRxyubwKd5nnuvujoVU4STM=; b=ud4+buKoyG8rag1goBLiVVPAKAh/zRH7RKA7cilN8IPXzg1OYfQZBGqzGCeOCQpuGH 3D+PVUasJBD7g712u9lSDFclyora1FqMrjL/ePe1IElPXiKe1T7m3FP4EsBKEgXfXFM4 3zm4a6MOMJN9U30aT2QOK7Ycv5EKUj3Dg5Q0xVWQiVBDEB6I0mhyXHAFh+eaMGVPmgi/ 2CCetcT2Xz4V7gcVgqBJ5gv1O8a+cMTKI0ACDz3wInNDuTdo/ZQ0DfRi/9LtxDmtBCNv zkybQ6t9Qe0WO59gciWg3W0Ubhuoi28HDhGYc3/srh0vQLe3aULmH+zzHaz4xfTzncoG PUhA== X-Gm-Message-State: AOAM533ov0Egmz9dh69/2cvsUMpxuW9oyO1NWtA9AcRR8Faf+jfiZWmY cgRCxHEgd4pug2FGPTnw1KKWqZ3ELbjE8A== X-Google-Smtp-Source: ABdhPJzD7YzhicaGwpxPzJwW6TkwEAi3C4PvblZ/2PEjGbTHQArC/CKMtfynTcSiuKZVtuUN2G8EZA== X-Received: by 2002:a5d:5005:0:b0:207:a7d7:ba4f with SMTP id e5-20020a5d5005000000b00207a7d7ba4fmr19148208wrt.163.1650539935722; Thu, 21 Apr 2022 04:18:55 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/31] hw/arm/exynos4210: Use TYPE_OR_IRQ instead of custom OR-gate device Date: Thu, 21 Apr 2022 12:18:23 +0100 Message-Id: <20220421111846.2011565-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org> References: <20220421111846.2011565-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650540357387100001 Content-Type: text/plain; charset="utf-8" The Exynos4210 SoC device currently uses a custom device "exynos4210.irq_gate" to model the OR gate that feeds each CPU's IRQ line. We have a standard TYPE_OR_IRQ device for this now, so use that instead. (This is a migration compatibility break, but that is OK for this machine type.) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220404154658.565020-2-peter.maydell@linaro.org --- include/hw/arm/exynos4210.h | 1 + hw/arm/exynos4210.c | 31 ++++++++++++++++--------------- 2 files changed, 17 insertions(+), 15 deletions(-) diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h index 60b9e126f55..3999034053e 100644 --- a/include/hw/arm/exynos4210.h +++ b/include/hw/arm/exynos4210.h @@ -102,6 +102,7 @@ struct Exynos4210State { MemoryRegion bootreg_mem; I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER]; qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA]; + qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; }; =20 #define TYPE_EXYNOS4210_SOC "exynos4210" diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 0299e81f853..dfc0a4eec25 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -205,7 +205,6 @@ static void exynos4210_realize(DeviceState *socdev, Err= or **errp) { Exynos4210State *s =3D EXYNOS4210_SOC(socdev); MemoryRegion *system_mem =3D get_system_memory(); - qemu_irq gate_irq[EXYNOS4210_NCPUS][EXYNOS4210_IRQ_GATE_NINPUTS]; SysBusDevice *busdev; DeviceState *dev, *uart[4], *pl330[3]; int i, n; @@ -235,18 +234,13 @@ static void exynos4210_realize(DeviceState *socdev, E= rror **errp) =20 /* IRQ Gate */ for (i =3D 0; i < EXYNOS4210_NCPUS; i++) { - dev =3D qdev_new("exynos4210.irq_gate"); - qdev_prop_set_uint32(dev, "n_in", EXYNOS4210_IRQ_GATE_NINPUTS); - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - /* Get IRQ Gate input in gate_irq */ - for (n =3D 0; n < EXYNOS4210_IRQ_GATE_NINPUTS; n++) { - gate_irq[i][n] =3D qdev_get_gpio_in(dev, n); - } - busdev =3D SYS_BUS_DEVICE(dev); - - /* Connect IRQ Gate output to CPU's IRQ line */ - sysbus_connect_irq(busdev, 0, - qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_IRQ= )); + DeviceState *orgate =3D DEVICE(&s->cpu_irq_orgate[i]); + object_property_set_int(OBJECT(orgate), "num-lines", + EXYNOS4210_IRQ_GATE_NINPUTS, + &error_abort); + qdev_realize(orgate, NULL, &error_abort); + qdev_connect_gpio_out(orgate, 0, + qdev_get_gpio_in(DEVICE(s->cpu[i]), ARM_CPU_= IRQ)); } =20 /* Private memory region and Internal GIC */ @@ -256,7 +250,8 @@ static void exynos4210_realize(DeviceState *socdev, Err= or **errp) sysbus_realize_and_unref(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); for (n =3D 0; n < EXYNOS4210_NCPUS; n++) { - sysbus_connect_irq(busdev, n, gate_irq[n][0]); + sysbus_connect_irq(busdev, n, + qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]),= 0)); } for (n =3D 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) { s->irqs.int_gic_irq[n] =3D qdev_get_gpio_in(dev, n); @@ -275,7 +270,8 @@ static void exynos4210_realize(DeviceState *socdev, Err= or **errp) /* Map Distributer interface */ sysbus_mmio_map(busdev, 1, EXYNOS4210_EXT_GIC_DIST_BASE_ADDR); for (n =3D 0; n < EXYNOS4210_NCPUS; n++) { - sysbus_connect_irq(busdev, n, gate_irq[n][1]); + sysbus_connect_irq(busdev, n, + qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]),= 1)); } for (n =3D 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) { s->irqs.ext_gic_irq[n] =3D qdev_get_gpio_in(dev, n); @@ -488,6 +484,11 @@ static void exynos4210_init(Object *obj) object_initialize_child(obj, name, orgate, TYPE_OR_IRQ); g_free(name); } + + for (i =3D 0; i < ARRAY_SIZE(s->cpu_irq_orgate); i++) { + g_autofree char *name =3D g_strdup_printf("cpu-irq-orgate%d", i); + object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_= IRQ); + } } =20 static void exynos4210_class_init(ObjectClass *klass, void *data) --=20 2.25.1 From nobody Tue May 21 06:35:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650540741; cv=none; d=zohomail.com; s=zohoarc; b=iNMpXNAFi4lSvqRlLiEXLbcdWMiAbuMrxUf6GOcR1Brv/qjKmz9LZhPfBr0n4h0znaDQtxwC1D8rWjHBjb1lH9d1aL1zk2VVdwNCmVOlZlz2UwXNfeZW5K5wANeiGw91WFfYAzfXnIci03hIOd+G2lxLOdbf3b962Xg74B6ui6Q= ARC-Message-Signature: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e4-20020a5d6d04000000b0020a8bbbb72bsm2597694wrq.97.2022.04.21.04.18.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 04:18:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=sDjN+WySih18ryXF6R3n9stfRQojyj640nNIa0UOxtI=; b=B97bjf+PebiFn+tJj+ywXJSHjx3y+nZBRVnRO8FJcyyp8PdLWH7EhiN/i+7F1ayvMY +rQBrSLnbzT1fJd6cAYSnQMqL6xqcTAHFW6+WacbPkIT5s91Pw/iHWy1hiZM8S3H5ErP YUgD1/Ldt9B2Y+gPkmDZS++vVODiFdyopD3VTQnLrJafF4yBRHxGbRf+2VCaMrN1NKT0 sPbVtJXCuEQbGWB5uif1IT3yGoYXY57PEo6RkSTTvvKnwRRBngI+Zcf1q8kin0HLlX7t oELm1ggZY1WmMfcl8zXWmtHVlnPbB7y4Zjmdx71RDkFjIIIPB9nWwemlfz7Am6FLCIfi 3qvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sDjN+WySih18ryXF6R3n9stfRQojyj640nNIa0UOxtI=; b=1ufueq6uYvvwWYRYwoLAEk9n7I1j8+aJQQ4fWcyfzE5fOmHJGMzGk1JEa4dLUSVuYT lyGhCm9ErfvqRcqVhZB6BEFHjxqSqNSHpCRopE0SYtJCzDyLdlmxSPQKNHjMhDOBP2B/ i2dRsAsX09YK+cswGwEbZN9JIz7ulzYnmS8gTAFh33dUljH5+Fp1m72CsFA1xwWDmPF+ AUktNJqA/RksE83HlYJOgEFM1StzYWky0/syM2MjY4j/clj3rVbdJAzv1zT4+zQN7d7w 2LixUrPDGKaMLsR6kqvmS9BEdqQ3MZX7D1i+WZy4HGotLRNBVZlrJMcAqqM5682/1mGq EoUw== X-Gm-Message-State: AOAM531QlQ2/5/DWiFVyncSNPcBiT91b18OPZ4e/mymycmpPbWW5uXLO 61ntyLY3TaXOtnNiK4+isk/leHeWwAJffg== X-Google-Smtp-Source: ABdhPJw9ZNdVjXmhOp0PVMQ0s2Zhri0OEizW5eLqnSv+P4xorL0vP3MwdwfL2xjhLNhBmhsT2F/LNg== X-Received: by 2002:a05:6000:16ce:b0:20a:88cf:c026 with SMTP id h14-20020a05600016ce00b0020a88cfc026mr18637549wrf.496.1650539936644; Thu, 21 Apr 2022 04:18:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/31] hw/intc/exynos4210_gic: Remove unused TYPE_EXYNOS4210_IRQ_GATE Date: Thu, 21 Apr 2022 12:18:24 +0100 Message-Id: <20220421111846.2011565-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org> References: <20220421111846.2011565-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650540742293100001 Content-Type: text/plain; charset="utf-8" Now we have removed the only use of TYPE_EXYNOS4210_IRQ_GATE we can delete the device entirely. Signed-off-by: Peter Maydell Reviewed-by: Francisco Iglesias Message-id: 20220404154658.565020-3-peter.maydell@linaro.org --- hw/intc/exynos4210_gic.c | 107 --------------------------------------- 1 file changed, 107 deletions(-) diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c index bc73d1f1152..794f6b5ac72 100644 --- a/hw/intc/exynos4210_gic.c +++ b/hw/intc/exynos4210_gic.c @@ -373,110 +373,3 @@ static void exynos4210_gic_register_types(void) } =20 type_init(exynos4210_gic_register_types) - -/* IRQ OR Gate struct. - * - * This device models an OR gate. There are n_in input qdev gpio lines and= one - * output sysbus IRQ line. The output IRQ level is formed as OR between all - * gpio inputs. - */ - -#define TYPE_EXYNOS4210_IRQ_GATE "exynos4210.irq_gate" -OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210IRQGateState, EXYNOS4210_IRQ_GATE) - -struct Exynos4210IRQGateState { - SysBusDevice parent_obj; - - uint32_t n_in; /* inputs amount */ - uint32_t *level; /* input levels */ - qemu_irq out; /* output IRQ */ -}; - -static Property exynos4210_irq_gate_properties[] =3D { - DEFINE_PROP_UINT32("n_in", Exynos4210IRQGateState, n_in, 1), - DEFINE_PROP_END_OF_LIST(), -}; - -static const VMStateDescription vmstate_exynos4210_irq_gate =3D { - .name =3D "exynos4210.irq_gate", - .version_id =3D 2, - .minimum_version_id =3D 2, - .fields =3D (VMStateField[]) { - VMSTATE_VBUFFER_UINT32(level, Exynos4210IRQGateState, 1, NULL, n_i= n), - VMSTATE_END_OF_LIST() - } -}; - -/* Process a change in IRQ input. */ -static void exynos4210_irq_gate_handler(void *opaque, int irq, int level) -{ - Exynos4210IRQGateState *s =3D (Exynos4210IRQGateState *)opaque; - uint32_t i; - - assert(irq < s->n_in); - - s->level[irq] =3D level; - - for (i =3D 0; i < s->n_in; i++) { - if (s->level[i] >=3D 1) { - qemu_irq_raise(s->out); - return; - } - } - - qemu_irq_lower(s->out); -} - -static void exynos4210_irq_gate_reset(DeviceState *d) -{ - Exynos4210IRQGateState *s =3D EXYNOS4210_IRQ_GATE(d); - - memset(s->level, 0, s->n_in * sizeof(*s->level)); -} - -/* - * IRQ Gate initialization. - */ -static void exynos4210_irq_gate_init(Object *obj) -{ - Exynos4210IRQGateState *s =3D EXYNOS4210_IRQ_GATE(obj); - SysBusDevice *sbd =3D SYS_BUS_DEVICE(obj); - - sysbus_init_irq(sbd, &s->out); -} - -static void exynos4210_irq_gate_realize(DeviceState *dev, Error **errp) -{ - Exynos4210IRQGateState *s =3D EXYNOS4210_IRQ_GATE(dev); - - /* Allocate general purpose input signals and connect a handler to eac= h of - * them */ - qdev_init_gpio_in(dev, exynos4210_irq_gate_handler, s->n_in); - - s->level =3D g_malloc0(s->n_in * sizeof(*s->level)); -} - -static void exynos4210_irq_gate_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc =3D DEVICE_CLASS(klass); - - dc->reset =3D exynos4210_irq_gate_reset; - dc->vmsd =3D &vmstate_exynos4210_irq_gate; - device_class_set_props(dc, exynos4210_irq_gate_properties); - dc->realize =3D exynos4210_irq_gate_realize; -} - -static const TypeInfo exynos4210_irq_gate_info =3D { - .name =3D TYPE_EXYNOS4210_IRQ_GATE, - .parent =3D TYPE_SYS_BUS_DEVICE, - .instance_size =3D sizeof(Exynos4210IRQGateState), - .instance_init =3D exynos4210_irq_gate_init, - .class_init =3D exynos4210_irq_gate_class_init, -}; - -static void exynos4210_irq_gate_register_types(void) -{ - type_register_static(&exynos4210_irq_gate_info); -} - -type_init(exynos4210_irq_gate_register_types) --=20 2.25.1 From nobody Tue May 21 06:35:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e4-20020a5d6d04000000b0020a8bbbb72bsm2597694wrq.97.2022.04.21.04.18.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 04:18:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=HtN0kqqvwwTdtiQPjMVdnwH1taYT1AjPI2wX6s5u1Aw=; b=Y1iQmWtM7G8bJJgbrlt0ara2NGUC3+0X2km8FlPbtXYGEI1mwHVM/4Rdhi5MZyC2aX 9y/P2gFNxyi165kQ1wLEXJvbVvIll3yOoiOyMuOTWceZj1IkDYsc8FRVuNKUDh1ddmTu ZEZGPv+EyUFFZNYxyqdanmo0FEVfqvq/dv5yI8XkPZ+HnNAxLyi9Vpf/eK9b/E98D3qv N5Z0ib1TZ+be91ypB2JmZ+rslI5UTRyN11OXsTWoRUhZMS2E7+J/U0xk7bfBxe2mKx6Z WqYlT1VLCoy7mPvKydfGxKfLx5iTjcMCyouJodbZE1/KDn8eMNqv5AF4r7HbjupR9mCt Oz9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HtN0kqqvwwTdtiQPjMVdnwH1taYT1AjPI2wX6s5u1Aw=; b=pY+T235nK+yMhoXwNfas4k303ebaerh5UaBpZTiD+nYMr+0lcZcCDy/hAktmPoULmA ykyBuiwgo4rR0zfyMPuFxKpSzoFX7yFw3dPVHpjclOANHrbCKdS4SqZF8KJeog97OGpE 9zDF0P2AVXflFNR/wyl/YkFqUTjQ3S0Ij/ABMEoTy6na5hqtW181P5MwPCrm6gxT8vxY t4/v7hTWMUsWiu+7R2wbOMn3OAjhYyw82y3k9eBbqoTybkxCXy3dQ0uxkj0pTDaqhIlv iTYAYipVqDeUv9Nlbut3WWnuloirWWIlPUOvggC/8GbyEdEnk6IbNRdC7C0y7eNnngXj 1A2g== X-Gm-Message-State: AOAM531uQ+yqPq5WOQA9bKu3BuyBjUWepZ0OA8rQeogUFyC6HO/UGrDo df3Hdrh9D2c1YaRvxmNR5unlon3iDFiAzQ== X-Google-Smtp-Source: ABdhPJzDfCVURl65P8HWAKl3+tyCZmZs3vGtb05vx2c8SvVHP1SWkabwPr+5zQ38kGqyJW0Go2eAsA== X-Received: by 2002:a05:6000:71c:b0:207:a807:e297 with SMTP id bs28-20020a056000071c00b00207a807e297mr18676051wrb.596.1650539937459; Thu, 21 Apr 2022 04:18:57 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/31] hw/arm/exynos4210: Put a9mpcore device into state struct Date: Thu, 21 Apr 2022 12:18:25 +0100 Message-Id: <20220421111846.2011565-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org> References: <20220421111846.2011565-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650540482283100001 Content-Type: text/plain; charset="utf-8" The exynos4210 SoC mostly creates its child devices as if it were board code. This includes the a9mpcore object. Switch that to a new-style "embedded in the state struct" creation, because in the next commit we're going to want to refer to the object again further down in the exynos4210_realize() function. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220404154658.565020-4-peter.maydell@linaro.org --- include/hw/arm/exynos4210.h | 2 ++ hw/arm/exynos4210.c | 11 ++++++----- 2 files changed, 8 insertions(+), 5 deletions(-) diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h index 3999034053e..215c039b414 100644 --- a/include/hw/arm/exynos4210.h +++ b/include/hw/arm/exynos4210.h @@ -26,6 +26,7 @@ =20 #include "hw/or-irq.h" #include "hw/sysbus.h" +#include "hw/cpu/a9mpcore.h" #include "target/arm/cpu-qom.h" #include "qom/object.h" =20 @@ -103,6 +104,7 @@ struct Exynos4210State { I2CBus *i2c_if[EXYNOS4210_I2C_NUMBER]; qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA]; qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; + A9MPPrivState a9mpcore; }; =20 #define TYPE_EXYNOS4210_SOC "exynos4210" diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index dfc0a4eec25..ef4d646eb91 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -244,17 +244,16 @@ static void exynos4210_realize(DeviceState *socdev, E= rror **errp) } =20 /* Private memory region and Internal GIC */ - dev =3D qdev_new(TYPE_A9MPCORE_PRIV); - qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); - busdev =3D SYS_BUS_DEVICE(dev); - sysbus_realize_and_unref(busdev, &error_fatal); + qdev_prop_set_uint32(DEVICE(&s->a9mpcore), "num-cpu", EXYNOS4210_NCPUS= ); + busdev =3D SYS_BUS_DEVICE(&s->a9mpcore); + sysbus_realize(busdev, &error_fatal); sysbus_mmio_map(busdev, 0, EXYNOS4210_SMP_PRIVATE_BASE_ADDR); for (n =3D 0; n < EXYNOS4210_NCPUS; n++) { sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]),= 0)); } for (n =3D 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) { - s->irqs.int_gic_irq[n] =3D qdev_get_gpio_in(dev, n); + s->irqs.int_gic_irq[n] =3D qdev_get_gpio_in(DEVICE(&s->a9mpcore), = n); } =20 /* Cache controller */ @@ -489,6 +488,8 @@ static void exynos4210_init(Object *obj) g_autofree char *name =3D g_strdup_printf("cpu-irq-orgate%d", i); object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_= IRQ); } + + object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_P= RIV); } =20 static void exynos4210_class_init(ObjectClass *klass, void *data) --=20 2.25.1 From nobody Tue May 21 06:35:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650540951; cv=none; d=zohomail.com; s=zohoarc; b=ZBH8mH2uMVcVHL6k4QaxYuS9o49Ep3iTLnPR6uXRv1Y5fStg+fZxiOWdYZBHAqzvc2cKTePXHRASlrZrvWHqK0uM3x0Dbq0qfrUgTE0+YYjv4JOGplmMCky0wnftWrmsUiq9Ro50CN0SAZFBF/b7amJF/6eYw3sTuru8NuIjHHo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650540951; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=f6gs5lG3WvFi/GkMdFvvztB0m3oPJAErdAfbpm6CH1E=; b=Nm1NPf+Qwh6r8N/CtOaQzI6QgMsmNN7bmkvI705vpNJfkeP69scVnFkZThLuXIcFHYR/rHXpd9nRm0l4HDbjF94CWn7qwPihv9K365FXdMJQmTswKUuYNOeY4LMTYs7OevbC/B4fGTRTlC9N3GKpJNHVJLPfdsNXC/dLtBSZYCs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650540951297516.4571780884114; Thu, 21 Apr 2022 04:35:51 -0700 (PDT) Received: from localhost ([::1]:34674 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhV6E-00024u-9I for importer@patchew.org; Thu, 21 Apr 2022 07:35:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59300) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhUpx-000314-Jc for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:19:01 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:38789) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nhUpv-0003Tf-Kj for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:19:01 -0400 Received: by mail-wr1-x42a.google.com with SMTP id p18so6213873wru.5 for ; Thu, 21 Apr 2022 04:18:59 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e4-20020a5d6d04000000b0020a8bbbb72bsm2597694wrq.97.2022.04.21.04.18.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 04:18:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=f6gs5lG3WvFi/GkMdFvvztB0m3oPJAErdAfbpm6CH1E=; b=A1oBjf+NwbvPyCzVI+knnD1KV5tPL1S0fAOZzBtYJRbVPwUtOZ6ZqSnSWS6SXWvs6f w1u5X1ypjyQwfVkvIM5iCof95Q5TzqeqaYSnRTtuwLqJQ3QswtPNGiTHfQU2ciuVh2fV q/a8Hanodlu5hAIiX8N+RN/RK07OkMk0C+ttDyihSd6YInHnoptaJrfs20E2EBsMxdIK 6xwmVl97rP+Q3PX2q4ACS8Tzr5IxNGo5LfcfkIrf6Rui/xgTWm6QyVkxzcDA3ma7PLWE ttn4Wb9nxkwZeoyOVhcLimxZtqO/56HS9HBV/aukOFqZyM1/m3sSpQBRkf6Yi0rHI0Td OR5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=f6gs5lG3WvFi/GkMdFvvztB0m3oPJAErdAfbpm6CH1E=; b=uJZazpUE/tOX5HRmT7v3838cjO+NBvO0+48l0j/kXEc7+iEP396kelOSLX4/tvpVVB ZZOw6Ac59PWLm/a+9ZYOJNFjSNee1p6fxqn3knNo0C07YY3COVAze0gFgheJaEYwmGuU 0YhgpXjIJkdLNXLmNmfCdKTvyVxLW1VRFcYffuCcaE+xUa16jFv2WlDBj9iVJd2ILSAP 25AX6JGKx5r9nHA3dukoMnl3WDrrkMbj8acWMNCdjgmuVQ8lwGhsWGFDQyIw0wKCWUNb AKmcWF8cAx2kvWdRSvJGT2JhHRsyoMDT9HC9PsUSZToUqjmtYjuBRbT5bcw4gNHL3wfd jVoQ== X-Gm-Message-State: AOAM531MUewyuI+1YCmMdvRuy0iZu/tLOtOqztSLn63fZuQoFga76ULC R6HizXfTOzOiG/BgFgct9cUxA2BMxvxFmA== X-Google-Smtp-Source: ABdhPJxpJ4iw0vL4F15EhCjAE21V7nV2XkvI8a1KQDpXapyiGSl4+V+zdp1T6nKZ+rD5ZldW2jYZLQ== X-Received: by 2002:a5d:64a3:0:b0:20a:7931:5b84 with SMTP id m3-20020a5d64a3000000b0020a79315b84mr19822561wrp.407.1650539938191; Thu, 21 Apr 2022 04:18:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/31] hw/arm/exynos4210: Drop int_gic_irq[] from Exynos4210Irq struct Date: Thu, 21 Apr 2022 12:18:26 +0100 Message-Id: <20220421111846.2011565-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org> References: <20220421111846.2011565-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650540952907100003 Content-Type: text/plain; charset="utf-8" The only time we use the int_gic_irq[] array in the Exynos4210Irq struct is in the exynos4210_realize() function: we initialize it with the GPIO inputs of the a9mpcore device, and then a bit later on we connect those to the outputs of the internal combiner. Now that the a9mpcore object is easily accessible as s->a9mpcore we can make the connection directly from one device to the other without going via this array. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220404154658.565020-5-peter.maydell@linaro.org --- include/hw/arm/exynos4210.h | 1 - hw/arm/exynos4210.c | 6 ++---- 2 files changed, 2 insertions(+), 5 deletions(-) diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h index 215c039b414..923ce987627 100644 --- a/include/hw/arm/exynos4210.h +++ b/include/hw/arm/exynos4210.h @@ -82,7 +82,6 @@ typedef struct Exynos4210Irq { qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ]; - qemu_irq int_gic_irq[EXYNOS4210_INT_GIC_NIRQ]; qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ]; qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; } Exynos4210Irq; diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index ef4d646eb91..60fc5a2ffe7 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -252,9 +252,6 @@ static void exynos4210_realize(DeviceState *socdev, Err= or **errp) sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]),= 0)); } - for (n =3D 0; n < EXYNOS4210_INT_GIC_NIRQ; n++) { - s->irqs.int_gic_irq[n] =3D qdev_get_gpio_in(DEVICE(&s->a9mpcore), = n); - } =20 /* Cache controller */ sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL); @@ -281,7 +278,8 @@ static void exynos4210_realize(DeviceState *socdev, Err= or **errp) busdev =3D SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); for (n =3D 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { - sysbus_connect_irq(busdev, n, s->irqs.int_gic_irq[n]); + sysbus_connect_irq(busdev, n, + qdev_get_gpio_in(DEVICE(&s->a9mpcore), n)); } exynos4210_combiner_get_gpioin(&s->irqs, dev, 0); sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); --=20 2.25.1 From nobody Tue May 21 06:35:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650540617; cv=none; d=zohomail.com; s=zohoarc; b=AZH97YAmHVB3qv7Yt+T/mNU5/2UT3ry7H2bta6DrFsnbuaiN72iBg76VQOJAhEQzUIJg/IsAWmbRYQ0yPAi7qpJ5XzQaZ0p27A/DIMcCo/vfK9pN32G/eiSsOq4uyYMuKzCG0++Rpa2LgndgthN1lKBOGgDBMnqCrBME0XQtdBM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650540617; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NxyRKNFl2O6E7I/QAVOYo1T3g62wFJsWVPRRmD11FmI=; b=VMVQZ8li6BqRO6L0We5ZmOqY8HzxcxiVwz7X+iRYlpgWb/1QtyPOzU+UL2r6uZjM1ZIkyNsbYdzQ9hgDFx4m4X7cRg3WGYHUrklcnbEwszAquJdmuFwAQniiNrYpNLfz4EAPDViz/dsZ7GZEXEbpfUGleDyo/5jLJeab11cRcCw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650540617146882.1228735151384; Thu, 21 Apr 2022 04:30:17 -0700 (PDT) Received: from localhost ([::1]:52576 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhV0q-0002fy-2O for importer@patchew.org; Thu, 21 Apr 2022 07:30:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59312) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhUpy-00033v-IO for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:19:02 -0400 Received: from mail-wr1-x42b.google.com ([2a00:1450:4864:20::42b]:43839) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nhUpw-0003Tz-JK for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:19:02 -0400 Received: by mail-wr1-x42b.google.com with SMTP id g18so6190568wrb.10 for ; Thu, 21 Apr 2022 04:19:00 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e4-20020a5d6d04000000b0020a8bbbb72bsm2597694wrq.97.2022.04.21.04.18.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 04:18:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=NxyRKNFl2O6E7I/QAVOYo1T3g62wFJsWVPRRmD11FmI=; b=llpp7lcbkUKy06ghh/lmPABu+jgefJcWc0HyuyXLGQ/TcwdezGUyp/79knaqmN2BMD WuK9qon6sPkfV7BiRO7BXVX5Q6wVG1t2ug5Miv8m3zVSrdC9ij/05LOussydzwkE29S9 wLGXoutBIhv1dGIVdNTydIYRGTYWJE9ZxlbjiIluv4UfSkkx4MtCPPiYW3ftHtBuhwqG Hgbg8T8/5Iu31ZBiOo7mj4L2eBSNwvTfI+uM6nosIOnymiCGASv9Y2w1Cg5yrLC0QRtm 3toqqi7V95Qkbqk/CXxas+05mI+M+wrdcSVCIX/P6vo2pqDle/AkjxQ64llbDlByxB1D kxdA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NxyRKNFl2O6E7I/QAVOYo1T3g62wFJsWVPRRmD11FmI=; b=hwq8bkB8AYsHZ/K3oNdYmlLOst4zFkmX4CShUUQrK4kLR0E4HIavNXxgrvNH9PSEvg QyIUs0BObShD7dV41rDHARekedDE6Gw/L/Urmq8qHkCNAC7CdzgxpZVEh4zevngjAMzF z7zZrixegib5ix7y5W9ypiRB9SnYr667HxYAlGaUb5xnwLm+brv19TkyoPX0NP8eU1nU s7DRne7nCF0oVqXopZRuPbEZQCa9pji5nc09m0cbOMdDd48S2LVdp5yh8NYkySBRQ0YU ojPebdoK1P5amASHiGKoPj4acqDbygn2lXPkWyY+o4TzSGJxT3HvY8HJCEal9wKKrLmc XI1A== X-Gm-Message-State: AOAM532r8ZglzScmbZk4Kw89XCDUtKL8hQIbgw6sPCEoL7RLYrAveUId aANsqoXIQlsAD2MGTLEv8SN8x3/ub+solA== X-Google-Smtp-Source: ABdhPJy5NbT+kOpGD/GKP/x6lPq9D/4F4yrQU1fZK/19H+SsqU//dN5JjjCKp/cf1aWL7MpWC/7vFQ== X-Received: by 2002:a5d:4a81:0:b0:207:9abe:2908 with SMTP id o1-20020a5d4a81000000b002079abe2908mr18818764wrq.341.1650539939070; Thu, 21 Apr 2022 04:18:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/31] hw/arm/exynos4210: Coalesce board_irqs and irq_table Date: Thu, 21 Apr 2022 12:18:27 +0100 Message-Id: <20220421111846.2011565-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org> References: <20220421111846.2011565-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650540619060100003 Content-Type: text/plain; charset="utf-8" The exynos4210 code currently has two very similar arrays of IRQs: * board_irqs is a field of the Exynos4210Irq struct which is filled in by exynos4210_init_board_irqs() with the appropriate qemu_irqs for each IRQ the board/SoC can assert * irq_table is a set of qemu_irqs pointed to from the Exynos4210State struct. It's allocated in exynos4210_init_irq, and the only behaviour these irqs have is that they pass on the level to the equivalent board_irqs[] irq The extra indirection through irq_table is unnecessary, so coalesce these into a single irq_table[] array as a direct field in Exynos4210State which exynos4210_init_board_irqs() fills in. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220404154658.565020-6-peter.maydell@linaro.org --- include/hw/arm/exynos4210.h | 8 ++------ hw/arm/exynos4210.c | 6 +----- hw/intc/exynos4210_gic.c | 32 ++++++++------------------------ 3 files changed, 11 insertions(+), 35 deletions(-) diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h index 923ce987627..a9f186370ee 100644 --- a/include/hw/arm/exynos4210.h +++ b/include/hw/arm/exynos4210.h @@ -83,7 +83,6 @@ typedef struct Exynos4210Irq { qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ]; qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ]; - qemu_irq board_irqs[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; } Exynos4210Irq; =20 struct Exynos4210State { @@ -92,7 +91,7 @@ struct Exynos4210State { /*< public >*/ ARMCPU *cpu[EXYNOS4210_NCPUS]; Exynos4210Irq irqs; - qemu_irq *irq_table; + qemu_irq irq_table[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; =20 MemoryRegion chipid_mem; MemoryRegion iram_mem; @@ -112,12 +111,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210= _SOC) void exynos4210_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info); =20 -/* Initialize exynos4210 IRQ subsystem stub */ -qemu_irq *exynos4210_init_irq(Exynos4210Irq *env); - /* Initialize board IRQs. * These IRQs contain splitted Int/External Combiner and External Gic IRQs= */ -void exynos4210_init_board_irqs(Exynos4210Irq *s); +void exynos4210_init_board_irqs(Exynos4210State *s); =20 /* Get IRQ number from exynos4210 IRQ subsystem stub. * To identify IRQ source use internal combiner group and bit number diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 60fc5a2ffe7..11e321d7830 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -228,10 +228,6 @@ static void exynos4210_realize(DeviceState *socdev, Er= ror **errp) qdev_realize(DEVICE(cpuobj), NULL, &error_fatal); } =20 - /*** IRQs ***/ - - s->irq_table =3D exynos4210_init_irq(&s->irqs); - /* IRQ Gate */ for (i =3D 0; i < EXYNOS4210_NCPUS; i++) { DeviceState *orgate =3D DEVICE(&s->cpu_irq_orgate[i]); @@ -296,7 +292,7 @@ static void exynos4210_realize(DeviceState *socdev, Err= or **errp) sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); =20 /* Initialize board IRQs. */ - exynos4210_init_board_irqs(&s->irqs); + exynos4210_init_board_irqs(s); =20 /*** Memory ***/ =20 diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c index 794f6b5ac72..ec79b96f6d1 100644 --- a/hw/intc/exynos4210_gic.c +++ b/hw/intc/exynos4210_gic.c @@ -192,30 +192,14 @@ combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER= _OUT_IRQ][8] =3D { #define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100 #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000 =20 -static void exynos4210_irq_handler(void *opaque, int irq, int level) -{ - Exynos4210Irq *s =3D (Exynos4210Irq *)opaque; - - /* Bypass */ - qemu_set_irq(s->board_irqs[irq], level); -} - -/* - * Initialize exynos4210 IRQ subsystem stub. - */ -qemu_irq *exynos4210_init_irq(Exynos4210Irq *s) -{ - return qemu_allocate_irqs(exynos4210_irq_handler, s, - EXYNOS4210_MAX_INT_COMBINER_IN_IRQ); -} - /* * Initialize board IRQs. * These IRQs contain splitted Int/External Combiner and External Gic IRQs. */ -void exynos4210_init_board_irqs(Exynos4210Irq *s) +void exynos4210_init_board_irqs(Exynos4210State *s) { uint32_t grp, bit, irq_id, n; + Exynos4210Irq *is =3D &s->irqs; =20 for (n =3D 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { irq_id =3D 0; @@ -230,11 +214,11 @@ void exynos4210_init_board_irqs(Exynos4210Irq *s) irq_id =3D EXT_GIC_ID_MCT_G1; } if (irq_id) { - s->board_irqs[n] =3D qemu_irq_split(s->int_combiner_irq[n], - s->ext_gic_irq[irq_id-32]); + s->irq_table[n] =3D qemu_irq_split(is->int_combiner_irq[n], + is->ext_gic_irq[irq_id - 32]); } else { - s->board_irqs[n] =3D qemu_irq_split(s->int_combiner_irq[n], - s->ext_combiner_irq[n]); + s->irq_table[n] =3D qemu_irq_split(is->int_combiner_irq[n], + is->ext_combiner_irq[n]); } } for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { @@ -245,8 +229,8 @@ void exynos4210_init_board_irqs(Exynos4210Irq *s) EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; =20 if (irq_id) { - s->board_irqs[n] =3D qemu_irq_split(s->int_combiner_irq[n], - s->ext_gic_irq[irq_id-32]); + s->irq_table[n] =3D qemu_irq_split(is->int_combiner_irq[n], + is->ext_gic_irq[irq_id - 32]); } } } --=20 2.25.1 From nobody Tue May 21 06:35:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650541111; cv=none; d=zohomail.com; s=zohoarc; b=D6gyzBLmAbbqBjPKiTH1g4wnQLuCBUPL4Vx0BvpPJn7poWQpY5OXGjYXctCuQtxRHLUmRvvJnEpR4/s0D/7/0nkWDcjRlkuTebo/kSQgfhFHou38U7QWB6b9W5imvkaq80dQQqJO0ykB1TQcY+9wuMVsAC+phpPrDjmXqWjp5ds= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650541111; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e4-20020a5d6d04000000b0020a8bbbb72bsm2597694wrq.97.2022.04.21.04.18.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 04:18:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=bxmVBnLL0UuF4+CoaLzsddoXXo7cHYtUouPIfgvtaUY=; b=p6NDZ1Ew73HpfEgMv2z6nHwUjJv8hThRBvuFlxwSK3ByuJ31BKV1u7iWkgV+msmU/p 7YdA4trxkmibIJ2JukjDTvX/LlyHD6pPtOsYCSWSN76OynV2NwPEVn5jUhXF3dlnM6G8 O+DOIpg1PZy/q90wvjT5/ZiKY+Qf1mjCKXrOLb7F20RrVS7a09ODPR6h07e4PC+KSJ0H IEKj2JOdfTqgObf0h3s2ymdmwpff5l5CfVe/H7zAOWZuvzIQvyOmlP62pCZjm1G2TPIy 8jyp2XnJkNxcCI3cUd7J3Sts3z6RHuK0div1xx04Y5L4tRU0gicF9FQUJ3r4cmmbgJwF AuQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bxmVBnLL0UuF4+CoaLzsddoXXo7cHYtUouPIfgvtaUY=; b=OWDWsFPjb050vfwb73sj/ZFEDFQljizHEXFbMmNzVeAGYtHp+LJkJVh7o2s1UJ7iHJ BA4n/zW+OLdmbH11oH3CLPXknWNClI/Pjvi3WdssxVGLmWFufko38+Im7d6vcrrqIQZd B4MZOiZKvqTNgF6p8sVC+OkqyJl6Q+d7cWnWvZtdTcPc+ApZVyoljnO0JbkNfZxKzdvS D63N6R0MD26XIpKKg7QTOx9xzC9QbqSQL4Vh+f1PaS43E6Z9306r/LqgBvfofvxOnmpH ZWiLI7OW/oAnduYYCCUDY6iTetkku2zPM7Eb5o6wKZm2pRKeYsJwYYhfrQwX5RENw/z/ oTBw== X-Gm-Message-State: AOAM532LjrkwNgUrQCk00mhtb+DqtYhwQQlUVPxwbOYPU45mS+Mmzh0T Nlnn0Ubvx39UKZakiaA5Zfjdsj6SDmgLFw== X-Google-Smtp-Source: ABdhPJxGDZeI/3CFBo/LModIyAC0BhfOnUPn759MKlgKuGUVPcLmMXWOOlhz6pukvWz4xCnNAcN0/g== X-Received: by 2002:a5d:424f:0:b0:20a:c08b:551a with SMTP id s15-20020a5d424f000000b0020ac08b551amr1580529wrr.521.1650539939827; Thu, 21 Apr 2022 04:18:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/31] hw/arm/exynos4210: Fix code style nit in combiner_grp_to_gic_id[] Date: Thu, 21 Apr 2022 12:18:28 +0100 Message-Id: <20220421111846.2011565-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org> References: <20220421111846.2011565-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650541111715100001 Content-Type: text/plain; charset="utf-8" Fix a missing set of spaces around '-' in the definition of combiner_grp_to_gic_id[]. We're about to move this code, so fix the style issue first to keep checkpatch happy with the code-motion patch. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220404154658.565020-7-peter.maydell@linaro.org --- hw/intc/exynos4210_gic.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c index ec79b96f6d1..3b77a485780 100644 --- a/hw/intc/exynos4210_gic.c +++ b/hw/intc/exynos4210_gic.c @@ -121,7 +121,7 @@ enum ExtInt { */ =20 static const uint32_t -combiner_grp_to_gic_id[64-EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] =3D { +combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] =3D { /* int combiner groups 16-19 */ { }, { }, { }, { }, /* int combiner group 20 */ --=20 2.25.1 From nobody Tue May 21 06:35:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650540950; cv=none; d=zohomail.com; s=zohoarc; b=VWMc5jX15o+KHQfehk0UMOVSgm4taxYajHFH++PnC6IEexWwYp5iwh5yBTm5616/1O7pS+ZS6Z+pMaotynnHbcMBVwbEJq9PsJfyoyi+sFG58+4+uOKoKP1Bi4n/aSMgJ45Ioy5mO9Vb5oD046rc4XEPMqLbfdZVftXasqOovM8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650540950; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=2NDP/T7Fv9/K0sGy4dyMoIgx7aLG/7J2aqJYascVVTc=; b=MEekh+8sSQGBcqDSWsOQnkZrJbtCMD8Ath2mgbmF+qwKgtN4vqW5GODW3TIhyez5kzAplZZ+Bc2ikMueMH6UZKJRBu19eSvmwk5dKiMBE6iRFuwGgaMtM3rZCm9ccvxXPXEI1+lhJVT9XvoO4KGevG4gqcjtv0dIr3sITp2YvX4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650540949921391.3259858604231; Thu, 21 Apr 2022 04:35:49 -0700 (PDT) Received: from localhost ([::1]:34496 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhV6C-0001xW-GQ for importer@patchew.org; Thu, 21 Apr 2022 07:35:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59368) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhUq0-00036i-P0 for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:19:06 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:33047) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nhUpy-0003Uf-Bi for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:19:04 -0400 Received: by mail-wm1-x329.google.com with SMTP id l3-20020a05600c1d0300b0038ff89c938bso3652998wms.0 for ; Thu, 21 Apr 2022 04:19:01 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e4-20020a5d6d04000000b0020a8bbbb72bsm2597694wrq.97.2022.04.21.04.18.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 04:19:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=2NDP/T7Fv9/K0sGy4dyMoIgx7aLG/7J2aqJYascVVTc=; b=bRLRnyp1S/zFTJP49eyClVBIPBujuMQv8TZ90eAGqTr57ZGL6Bp3EcVB0VvIaoi/wo 9cc/fC3lQJSvDtEVPHf10PiI0+EQn5OQbwzEuMa5+4fzmZIHrv6huwi0oAoDRKpQYeoY jMwzKXxdLYi+zLBF2AkVE/D2KReLVAqzM24/dG/e9S4JGq1+AQ1/d+2cOYYuK18Hz0dT 4oyvRJquqfrtJPtbZkD87cKTz2ts625pGvAsICsdeeouusZwOSRa8rm3jeS0Gpq+YNve 8ZPqSWbDc8eUXurvZhaSiJi49meH3nWxSvdZdiM4+1Bk4BrIvqIOVQUNFc+vy3DvmhxU 6BcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=2NDP/T7Fv9/K0sGy4dyMoIgx7aLG/7J2aqJYascVVTc=; b=3RZ50xTAexmdbnddTD5pwvJrL8ZYVPDDyJWg12WLOTrpteumjIYhb7yT+nWW+pJfcL kcFZnJGd5aTGF9tQC1diM0pBLsLkLYK4TWbvzrJ1bea7tZYC2honLIoC/QjQtRjEG1+j ysimWk5OJanNCS7dgJTy2mODG8wie6ajGgklPGNvcm5Jt6v5ZrSa3e3uUa0OT6LcQPA2 co2EbC0Oe3+zcFIkUcOOJ/PBhXIwIrDcvUr5v19xmgcJ7FZZtf9FbMWk9T3WLAqsXAEI OgqagWcUNkRPo9PMJGKokkCz6fwLcrwz5Z3waRt8M7EPZO8jgKPDBifcjD96EECzgLfG KWDQ== X-Gm-Message-State: AOAM530Rk1dhV/CDI+5H1mZBnLHtpNH34G3rAJ4LkZuNjDta6vnWsH62 xOEhecwIAeAoBCLwWfBRdV7e1Lt1zim5uQ== X-Google-Smtp-Source: ABdhPJy4/+7F0bIgHX3+mQYOnSHqb/X+Bdz+2nLqcNelbO6nGAjNIk76SzEMw/lchJSLhHF5TXjuQw== X-Received: by 2002:a1c:7415:0:b0:38e:bbbf:52d9 with SMTP id p21-20020a1c7415000000b0038ebbbf52d9mr8095277wmc.104.1650539940787; Thu, 21 Apr 2022 04:19:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/31] hw/arm/exynos4210: Move exynos4210_init_board_irqs() into exynos4210.c Date: Thu, 21 Apr 2022 12:18:29 +0100 Message-Id: <20220421111846.2011565-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org> References: <20220421111846.2011565-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650540950956100001 Content-Type: text/plain; charset="utf-8" The function exynos4210_init_board_irqs() currently lives in exynos4210_gic.c, but it isn't really part of the exynos4210.gic device -- it is a function that implements (some of) the wiring up of interrupts between the SoC's GIC and combiner components. This means it fits better in exynos4210.c, which is the SoC-level code. Move it there. Similarly, exynos4210_git_irq() is used almost only in the SoC-level code, so move it too. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220404154658.565020-8-peter.maydell@linaro.org --- include/hw/arm/exynos4210.h | 4 - hw/arm/exynos4210.c | 202 +++++++++++++++++++++++++++++++++++ hw/intc/exynos4210_gic.c | 204 ------------------------------------ 3 files changed, 202 insertions(+), 208 deletions(-) diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h index a9f186370ee..d83e96a091e 100644 --- a/include/hw/arm/exynos4210.h +++ b/include/hw/arm/exynos4210.h @@ -111,10 +111,6 @@ OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210State, EXYNOS4210= _SOC) void exynos4210_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info); =20 -/* Initialize board IRQs. - * These IRQs contain splitted Int/External Combiner and External Gic IRQs= */ -void exynos4210_init_board_irqs(Exynos4210State *s); - /* Get IRQ number from exynos4210 IRQ subsystem stub. * To identify IRQ source use internal combiner group and bit number * grp - group number diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 11e321d7830..742666ba779 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -101,6 +101,208 @@ #define EXYNOS4210_PL330_BASE1_ADDR 0x12690000 #define EXYNOS4210_PL330_BASE2_ADDR 0x12850000 =20 +enum ExtGicId { + EXT_GIC_ID_MDMA_LCD0 =3D 66, + EXT_GIC_ID_PDMA0, + EXT_GIC_ID_PDMA1, + EXT_GIC_ID_TIMER0, + EXT_GIC_ID_TIMER1, + EXT_GIC_ID_TIMER2, + EXT_GIC_ID_TIMER3, + EXT_GIC_ID_TIMER4, + EXT_GIC_ID_MCT_L0, + EXT_GIC_ID_WDT, + EXT_GIC_ID_RTC_ALARM, + EXT_GIC_ID_RTC_TIC, + EXT_GIC_ID_GPIO_XB, + EXT_GIC_ID_GPIO_XA, + EXT_GIC_ID_MCT_L1, + EXT_GIC_ID_IEM_APC, + EXT_GIC_ID_IEM_IEC, + EXT_GIC_ID_NFC, + EXT_GIC_ID_UART0, + EXT_GIC_ID_UART1, + EXT_GIC_ID_UART2, + EXT_GIC_ID_UART3, + EXT_GIC_ID_UART4, + EXT_GIC_ID_MCT_G0, + EXT_GIC_ID_I2C0, + EXT_GIC_ID_I2C1, + EXT_GIC_ID_I2C2, + EXT_GIC_ID_I2C3, + EXT_GIC_ID_I2C4, + EXT_GIC_ID_I2C5, + EXT_GIC_ID_I2C6, + EXT_GIC_ID_I2C7, + EXT_GIC_ID_SPI0, + EXT_GIC_ID_SPI1, + EXT_GIC_ID_SPI2, + EXT_GIC_ID_MCT_G1, + EXT_GIC_ID_USB_HOST, + EXT_GIC_ID_USB_DEVICE, + EXT_GIC_ID_MODEMIF, + EXT_GIC_ID_HSMMC0, + EXT_GIC_ID_HSMMC1, + EXT_GIC_ID_HSMMC2, + EXT_GIC_ID_HSMMC3, + EXT_GIC_ID_SDMMC, + EXT_GIC_ID_MIPI_CSI_4LANE, + EXT_GIC_ID_MIPI_DSI_4LANE, + EXT_GIC_ID_MIPI_CSI_2LANE, + EXT_GIC_ID_MIPI_DSI_2LANE, + EXT_GIC_ID_ONENAND_AUDI, + EXT_GIC_ID_ROTATOR, + EXT_GIC_ID_FIMC0, + EXT_GIC_ID_FIMC1, + EXT_GIC_ID_FIMC2, + EXT_GIC_ID_FIMC3, + EXT_GIC_ID_JPEG, + EXT_GIC_ID_2D, + EXT_GIC_ID_PCIe, + EXT_GIC_ID_MIXER, + EXT_GIC_ID_HDMI, + EXT_GIC_ID_HDMI_I2C, + EXT_GIC_ID_MFC, + EXT_GIC_ID_TVENC, +}; + +enum ExtInt { + EXT_GIC_ID_EXTINT0 =3D 48, + EXT_GIC_ID_EXTINT1, + EXT_GIC_ID_EXTINT2, + EXT_GIC_ID_EXTINT3, + EXT_GIC_ID_EXTINT4, + EXT_GIC_ID_EXTINT5, + EXT_GIC_ID_EXTINT6, + EXT_GIC_ID_EXTINT7, + EXT_GIC_ID_EXTINT8, + EXT_GIC_ID_EXTINT9, + EXT_GIC_ID_EXTINT10, + EXT_GIC_ID_EXTINT11, + EXT_GIC_ID_EXTINT12, + EXT_GIC_ID_EXTINT13, + EXT_GIC_ID_EXTINT14, + EXT_GIC_ID_EXTINT15 +}; + +/* + * External GIC sources which are not from External Interrupt Combiner or + * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_I= RQ, + * which is INTG16 in Internal Interrupt Combiner. + */ + +static const uint32_t +combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] =3D { + /* int combiner groups 16-19 */ + { }, { }, { }, { }, + /* int combiner group 20 */ + { 0, EXT_GIC_ID_MDMA_LCD0 }, + /* int combiner group 21 */ + { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 }, + /* int combiner group 22 */ + { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2, + EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 }, + /* int combiner group 23 */ + { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC }, + /* int combiner group 24 */ + { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA }, + /* int combiner group 25 */ + { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC }, + /* int combiner group 26 */ + { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UAR= T3, + EXT_GIC_ID_UART4 }, + /* int combiner group 27 */ + { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3, + EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6, + EXT_GIC_ID_I2C7 }, + /* int combiner group 28 */ + { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_H= OST}, + /* int combiner group 29 */ + { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2, + EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC }, + /* int combiner group 30 */ + { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE }, + /* int combiner group 31 */ + { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE }, + /* int combiner group 32 */ + { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 }, + /* int combiner group 33 */ + { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 }, + /* int combiner group 34 */ + { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC }, + /* int combiner group 35 */ + { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, + /* int combiner group 36 */ + { EXT_GIC_ID_MIXER }, + /* int combiner group 37 */ + { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6, + EXT_GIC_ID_EXTINT7 }, + /* groups 38-50 */ + { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, + /* int combiner group 51 */ + { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, + /* group 52 */ + { }, + /* int combiner group 53 */ + { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, + /* groups 54-63 */ + { }, { }, { }, { }, { }, { }, { }, { }, { }, { } +}; + +/* + * Initialize board IRQs. + * These IRQs contain splitted Int/External Combiner and External Gic IRQs. + */ +static void exynos4210_init_board_irqs(Exynos4210State *s) +{ + uint32_t grp, bit, irq_id, n; + Exynos4210Irq *is =3D &s->irqs; + + for (n =3D 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { + irq_id =3D 0; + if (n =3D=3D EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) || + n =3D=3D EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) { + /* MCT_G0 is passed to External GIC */ + irq_id =3D EXT_GIC_ID_MCT_G0; + } + if (n =3D=3D EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) || + n =3D=3D EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) { + /* MCT_G1 is passed to External and GIC */ + irq_id =3D EXT_GIC_ID_MCT_G1; + } + if (irq_id) { + s->irq_table[n] =3D qemu_irq_split(is->int_combiner_irq[n], + is->ext_gic_irq[irq_id - 32]); + } else { + s->irq_table[n] =3D qemu_irq_split(is->int_combiner_irq[n], + is->ext_combiner_irq[n]); + } + } + for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { + /* these IDs are passed to Internal Combiner and External GIC */ + grp =3D EXYNOS4210_COMBINER_GET_GRP_NUM(n); + bit =3D EXYNOS4210_COMBINER_GET_BIT_NUM(n); + irq_id =3D combiner_grp_to_gic_id[grp - + EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; + + if (irq_id) { + s->irq_table[n] =3D qemu_irq_split(is->int_combiner_irq[n], + is->ext_gic_irq[irq_id - 32]); + } + } +} + +/* + * Get IRQ number from exynos4210 IRQ subsystem stub. + * To identify IRQ source use internal combiner group and bit number + * grp - group number + * bit - bit number inside group + */ +uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) +{ + return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit); +} + static uint8_t chipid_and_omr[] =3D { 0x11, 0x02, 0x21, 0x43, 0x09, 0x00, 0x00, 0x00 }; =20 diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c index 3b77a485780..d8cad537fbf 100644 --- a/hw/intc/exynos4210_gic.c +++ b/hw/intc/exynos4210_gic.c @@ -30,154 +30,6 @@ #include "hw/arm/exynos4210.h" #include "qom/object.h" =20 -enum ExtGicId { - EXT_GIC_ID_MDMA_LCD0 =3D 66, - EXT_GIC_ID_PDMA0, - EXT_GIC_ID_PDMA1, - EXT_GIC_ID_TIMER0, - EXT_GIC_ID_TIMER1, - EXT_GIC_ID_TIMER2, - EXT_GIC_ID_TIMER3, - EXT_GIC_ID_TIMER4, - EXT_GIC_ID_MCT_L0, - EXT_GIC_ID_WDT, - EXT_GIC_ID_RTC_ALARM, - EXT_GIC_ID_RTC_TIC, - EXT_GIC_ID_GPIO_XB, - EXT_GIC_ID_GPIO_XA, - EXT_GIC_ID_MCT_L1, - EXT_GIC_ID_IEM_APC, - EXT_GIC_ID_IEM_IEC, - EXT_GIC_ID_NFC, - EXT_GIC_ID_UART0, - EXT_GIC_ID_UART1, - EXT_GIC_ID_UART2, - EXT_GIC_ID_UART3, - EXT_GIC_ID_UART4, - EXT_GIC_ID_MCT_G0, - EXT_GIC_ID_I2C0, - EXT_GIC_ID_I2C1, - EXT_GIC_ID_I2C2, - EXT_GIC_ID_I2C3, - EXT_GIC_ID_I2C4, - EXT_GIC_ID_I2C5, - EXT_GIC_ID_I2C6, - EXT_GIC_ID_I2C7, - EXT_GIC_ID_SPI0, - EXT_GIC_ID_SPI1, - EXT_GIC_ID_SPI2, - EXT_GIC_ID_MCT_G1, - EXT_GIC_ID_USB_HOST, - EXT_GIC_ID_USB_DEVICE, - EXT_GIC_ID_MODEMIF, - EXT_GIC_ID_HSMMC0, - EXT_GIC_ID_HSMMC1, - EXT_GIC_ID_HSMMC2, - EXT_GIC_ID_HSMMC3, - EXT_GIC_ID_SDMMC, - EXT_GIC_ID_MIPI_CSI_4LANE, - EXT_GIC_ID_MIPI_DSI_4LANE, - EXT_GIC_ID_MIPI_CSI_2LANE, - EXT_GIC_ID_MIPI_DSI_2LANE, - EXT_GIC_ID_ONENAND_AUDI, - EXT_GIC_ID_ROTATOR, - EXT_GIC_ID_FIMC0, - EXT_GIC_ID_FIMC1, - EXT_GIC_ID_FIMC2, - EXT_GIC_ID_FIMC3, - EXT_GIC_ID_JPEG, - EXT_GIC_ID_2D, - EXT_GIC_ID_PCIe, - EXT_GIC_ID_MIXER, - EXT_GIC_ID_HDMI, - EXT_GIC_ID_HDMI_I2C, - EXT_GIC_ID_MFC, - EXT_GIC_ID_TVENC, -}; - -enum ExtInt { - EXT_GIC_ID_EXTINT0 =3D 48, - EXT_GIC_ID_EXTINT1, - EXT_GIC_ID_EXTINT2, - EXT_GIC_ID_EXTINT3, - EXT_GIC_ID_EXTINT4, - EXT_GIC_ID_EXTINT5, - EXT_GIC_ID_EXTINT6, - EXT_GIC_ID_EXTINT7, - EXT_GIC_ID_EXTINT8, - EXT_GIC_ID_EXTINT9, - EXT_GIC_ID_EXTINT10, - EXT_GIC_ID_EXTINT11, - EXT_GIC_ID_EXTINT12, - EXT_GIC_ID_EXTINT13, - EXT_GIC_ID_EXTINT14, - EXT_GIC_ID_EXTINT15 -}; - -/* - * External GIC sources which are not from External Interrupt Combiner or - * External Interrupts are starting from EXYNOS4210_MAX_EXT_COMBINER_OUT_I= RQ, - * which is INTG16 in Internal Interrupt Combiner. - */ - -static const uint32_t -combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][8] =3D { - /* int combiner groups 16-19 */ - { }, { }, { }, { }, - /* int combiner group 20 */ - { 0, EXT_GIC_ID_MDMA_LCD0 }, - /* int combiner group 21 */ - { EXT_GIC_ID_PDMA0, EXT_GIC_ID_PDMA1 }, - /* int combiner group 22 */ - { EXT_GIC_ID_TIMER0, EXT_GIC_ID_TIMER1, EXT_GIC_ID_TIMER2, - EXT_GIC_ID_TIMER3, EXT_GIC_ID_TIMER4 }, - /* int combiner group 23 */ - { EXT_GIC_ID_RTC_ALARM, EXT_GIC_ID_RTC_TIC }, - /* int combiner group 24 */ - { EXT_GIC_ID_GPIO_XB, EXT_GIC_ID_GPIO_XA }, - /* int combiner group 25 */ - { EXT_GIC_ID_IEM_APC, EXT_GIC_ID_IEM_IEC }, - /* int combiner group 26 */ - { EXT_GIC_ID_UART0, EXT_GIC_ID_UART1, EXT_GIC_ID_UART2, EXT_GIC_ID_UAR= T3, - EXT_GIC_ID_UART4 }, - /* int combiner group 27 */ - { EXT_GIC_ID_I2C0, EXT_GIC_ID_I2C1, EXT_GIC_ID_I2C2, EXT_GIC_ID_I2C3, - EXT_GIC_ID_I2C4, EXT_GIC_ID_I2C5, EXT_GIC_ID_I2C6, - EXT_GIC_ID_I2C7 }, - /* int combiner group 28 */ - { EXT_GIC_ID_SPI0, EXT_GIC_ID_SPI1, EXT_GIC_ID_SPI2 , EXT_GIC_ID_USB_H= OST}, - /* int combiner group 29 */ - { EXT_GIC_ID_HSMMC0, EXT_GIC_ID_HSMMC1, EXT_GIC_ID_HSMMC2, - EXT_GIC_ID_HSMMC3, EXT_GIC_ID_SDMMC }, - /* int combiner group 30 */ - { EXT_GIC_ID_MIPI_CSI_4LANE, EXT_GIC_ID_MIPI_CSI_2LANE }, - /* int combiner group 31 */ - { EXT_GIC_ID_MIPI_DSI_4LANE, EXT_GIC_ID_MIPI_DSI_2LANE }, - /* int combiner group 32 */ - { EXT_GIC_ID_FIMC0, EXT_GIC_ID_FIMC1 }, - /* int combiner group 33 */ - { EXT_GIC_ID_FIMC2, EXT_GIC_ID_FIMC3 }, - /* int combiner group 34 */ - { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC }, - /* int combiner group 35 */ - { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, - /* int combiner group 36 */ - { EXT_GIC_ID_MIXER }, - /* int combiner group 37 */ - { EXT_GIC_ID_EXTINT4, EXT_GIC_ID_EXTINT5, EXT_GIC_ID_EXTINT6, - EXT_GIC_ID_EXTINT7 }, - /* groups 38-50 */ - { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, - /* int combiner group 51 */ - { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, - /* group 52 */ - { }, - /* int combiner group 53 */ - { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, - /* groups 54-63 */ - { }, { }, { }, { }, { }, { }, { }, { }, { }, { } -}; - #define EXYNOS4210_GIC_NIRQ 160 =20 #define EXYNOS4210_EXT_GIC_CPU_REGION_SIZE 0x10000 @@ -192,62 +44,6 @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER= _OUT_IRQ][8] =3D { #define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100 #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000 =20 -/* - * Initialize board IRQs. - * These IRQs contain splitted Int/External Combiner and External Gic IRQs. - */ -void exynos4210_init_board_irqs(Exynos4210State *s) -{ - uint32_t grp, bit, irq_id, n; - Exynos4210Irq *is =3D &s->irqs; - - for (n =3D 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { - irq_id =3D 0; - if (n =3D=3D EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) || - n =3D=3D EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) { - /* MCT_G0 is passed to External GIC */ - irq_id =3D EXT_GIC_ID_MCT_G0; - } - if (n =3D=3D EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) || - n =3D=3D EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) { - /* MCT_G1 is passed to External and GIC */ - irq_id =3D EXT_GIC_ID_MCT_G1; - } - if (irq_id) { - s->irq_table[n] =3D qemu_irq_split(is->int_combiner_irq[n], - is->ext_gic_irq[irq_id - 32]); - } else { - s->irq_table[n] =3D qemu_irq_split(is->int_combiner_irq[n], - is->ext_combiner_irq[n]); - } - } - for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { - /* these IDs are passed to Internal Combiner and External GIC */ - grp =3D EXYNOS4210_COMBINER_GET_GRP_NUM(n); - bit =3D EXYNOS4210_COMBINER_GET_BIT_NUM(n); - irq_id =3D combiner_grp_to_gic_id[grp - - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; - - if (irq_id) { - s->irq_table[n] =3D qemu_irq_split(is->int_combiner_irq[n], - is->ext_gic_irq[irq_id - 32]); - } - } -} - -/* - * Get IRQ number from exynos4210 IRQ subsystem stub. - * To identify IRQ source use internal combiner group and bit number - * grp - group number - * bit - bit number inside group - */ -uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) -{ - return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit); -} - -/********* GIC part *********/ - #define TYPE_EXYNOS4210_GIC "exynos4210.gic" OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC) =20 --=20 2.25.1 From nobody Tue May 21 06:35:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e4-20020a5d6d04000000b0020a8bbbb72bsm2597694wrq.97.2022.04.21.04.19.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 04:19:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=JyLLiVr6CM6ojc6EwZhzCmQ6kWAPOLYrRnM+QBWq57Q=; b=FhG83E+jrBBv6HzscjGozhqg8zyI6d/k2vicx5AaQgM+1ezyukHjwX/nLbCPV4zQDn zoRwTFS3Dyb7gyiesEIcPdOaAMkpPzqzyHcW72Gso120lny5ZGf2QxIFSW5G2vOVaw/K 3su2+8oD79Al5F36osqsYYXlial1tFs4a6bwqjuaYC/X+fGYk4KaE/+X9GPOD/tE+NpU EMs7bSgs6zgdoX1jOx+3VtuHqDJvE76Qzh52Fk4lrBJs+2XCxlWWUPY2xbJFF8vxKT9v R+EAoe0dKNEWxW17mLi+yuLh6x7RnHmejCTMDVf2skUcWcUZBhUeLHL6waxPgZFh1XCM SRvA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JyLLiVr6CM6ojc6EwZhzCmQ6kWAPOLYrRnM+QBWq57Q=; b=R/dR1anNX1sWrsV4MQtY1sI0LrazckLGizMkjFkMDSreen9YpPip21HifQQsPQ4Dtt k347R6YIkSdSmkjyO2Wr5tf8MAzx+Ed/gFYAkvheSCDR4AgMsUm6SXSx/cKwssoj1TjZ +MyIlf6RmUjWEuGaxU78v5K8l2wS5YtR7orboesCVnax1M6T7MUimxIWV9eV5bKT2It3 Vqy3pVQpu864VqiK4cyr7wk9HmA0MgOHuNVSx9DWEJx4WvXud7LKDWOpcXOm1PdTBqQZ kGa+KNNpLXyefA1MqBTJtCm5eVQ/ai0TJYSHO3z7XoA7ENUvX+FsQ7sBQE4PY38/AjUG vXJA== X-Gm-Message-State: AOAM530Hyw/jW9oWgYvO1VyrJqW9kDOf8fuT8Ml954J+1xwaZfSPNhMD paGVRNMEXs9MW0E5isQvWQNmFj7ugRy5EA== X-Google-Smtp-Source: ABdhPJyrPLv5JEtWYVC0f3YtClWutmT05pmegARQ8UWBd2bj9PHGJrOiUj9iHhSCKkX1tsGF2rPpxw== X-Received: by 2002:a05:600c:1e1e:b0:38e:baaa:aae0 with SMTP id ay30-20020a05600c1e1e00b0038ebaaaaae0mr7852688wmb.157.1650539941786; Thu, 21 Apr 2022 04:19:01 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/31] hw/arm/exynos4210: Put external GIC into state struct Date: Thu, 21 Apr 2022 12:18:30 +0100 Message-Id: <20220421111846.2011565-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org> References: <20220421111846.2011565-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650541484990100002 Content-Type: text/plain; charset="utf-8" Switch the creation of the external GIC to the new-style "embedded in state struct" approach, so we can easily refer to the object elsewhere during realize. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220404154658.565020-9-peter.maydell@linaro.org --- include/hw/arm/exynos4210.h | 2 ++ include/hw/intc/exynos4210_gic.h | 43 ++++++++++++++++++++++++++++++++ hw/arm/exynos4210.c | 10 ++++---- hw/intc/exynos4210_gic.c | 17 ++----------- MAINTAINERS | 2 +- 5 files changed, 53 insertions(+), 21 deletions(-) create mode 100644 include/hw/intc/exynos4210_gic.h diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h index d83e96a091e..f35ae90000f 100644 --- a/include/hw/arm/exynos4210.h +++ b/include/hw/arm/exynos4210.h @@ -27,6 +27,7 @@ #include "hw/or-irq.h" #include "hw/sysbus.h" #include "hw/cpu/a9mpcore.h" +#include "hw/intc/exynos4210_gic.h" #include "target/arm/cpu-qom.h" #include "qom/object.h" =20 @@ -103,6 +104,7 @@ struct Exynos4210State { qemu_or_irq pl330_irq_orgate[EXYNOS4210_NUM_DMA]; qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; A9MPPrivState a9mpcore; + Exynos4210GicState ext_gic; }; =20 #define TYPE_EXYNOS4210_SOC "exynos4210" diff --git a/include/hw/intc/exynos4210_gic.h b/include/hw/intc/exynos4210_= gic.h new file mode 100644 index 00000000000..f64c4069c6d --- /dev/null +++ b/include/hw/intc/exynos4210_gic.h @@ -0,0 +1,43 @@ +/* + * Samsung exynos4210 GIC implementation. Based on hw/arm_gic.c + * + * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd. + * All rights reserved. + * + * Evgeny Voevodin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ +#ifndef HW_INTC_EXYNOS4210_GIC_H +#define HW_INTC_EXYNOS4210_GIC_H + +#include "hw/sysbus.h" + +#define TYPE_EXYNOS4210_GIC "exynos4210.gic" +OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC) + +#define EXYNOS4210_GIC_NCPUS 2 + +struct Exynos4210GicState { + SysBusDevice parent_obj; + + MemoryRegion cpu_container; + MemoryRegion dist_container; + MemoryRegion cpu_alias[EXYNOS4210_GIC_NCPUS]; + MemoryRegion dist_alias[EXYNOS4210_GIC_NCPUS]; + uint32_t num_cpu; + DeviceState *gic; +}; + +#endif diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 742666ba779..2058df9aecf 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -455,10 +455,9 @@ static void exynos4210_realize(DeviceState *socdev, Er= ror **errp) sysbus_create_simple("l2x0", EXYNOS4210_L2X0_BASE_ADDR, NULL); =20 /* External GIC */ - dev =3D qdev_new("exynos4210.gic"); - qdev_prop_set_uint32(dev, "num-cpu", EXYNOS4210_NCPUS); - busdev =3D SYS_BUS_DEVICE(dev); - sysbus_realize_and_unref(busdev, &error_fatal); + qdev_prop_set_uint32(DEVICE(&s->ext_gic), "num-cpu", EXYNOS4210_NCPUS); + busdev =3D SYS_BUS_DEVICE(&s->ext_gic); + sysbus_realize(busdev, &error_fatal); /* Map CPU interface */ sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_GIC_CPU_BASE_ADDR); /* Map Distributer interface */ @@ -468,7 +467,7 @@ static void exynos4210_realize(DeviceState *socdev, Err= or **errp) qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]),= 1)); } for (n =3D 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) { - s->irqs.ext_gic_irq[n] =3D qdev_get_gpio_in(dev, n); + s->irqs.ext_gic_irq[n] =3D qdev_get_gpio_in(DEVICE(&s->ext_gic), n= ); } =20 /* Internal Interrupt Combiner */ @@ -686,6 +685,7 @@ static void exynos4210_init(Object *obj) } =20 object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_P= RIV); + object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_G= IC); } =20 static void exynos4210_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c index d8cad537fbf..71a88c86bc1 100644 --- a/hw/intc/exynos4210_gic.c +++ b/hw/intc/exynos4210_gic.c @@ -27,6 +27,7 @@ #include "qemu/module.h" #include "hw/irq.h" #include "hw/qdev-properties.h" +#include "hw/intc/exynos4210_gic.h" #include "hw/arm/exynos4210.h" #include "qom/object.h" =20 @@ -44,20 +45,6 @@ #define EXYNOS4210_GIC_CPU_REGION_SIZE 0x100 #define EXYNOS4210_GIC_DIST_REGION_SIZE 0x1000 =20 -#define TYPE_EXYNOS4210_GIC "exynos4210.gic" -OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210GicState, EXYNOS4210_GIC) - -struct Exynos4210GicState { - SysBusDevice parent_obj; - - MemoryRegion cpu_container; - MemoryRegion dist_container; - MemoryRegion cpu_alias[EXYNOS4210_NCPUS]; - MemoryRegion dist_alias[EXYNOS4210_NCPUS]; - uint32_t num_cpu; - DeviceState *gic; -}; - static void exynos4210_gic_set_irq(void *opaque, int irq, int level) { Exynos4210GicState *s =3D (Exynos4210GicState *)opaque; @@ -100,7 +87,7 @@ static void exynos4210_gic_realize(DeviceState *dev, Err= or **errp) * enough room for the cpu numbers. gcc 9.2.1 on 32-bit x86 * doesn't figure this out, otherwise and gives spurious warnings. */ - assert(n <=3D EXYNOS4210_NCPUS); + assert(n <=3D EXYNOS4210_GIC_NCPUS); for (i =3D 0; i < n; i++) { /* Map CPU interface per SMP Core */ sprintf(cpu_alias_name, "%s%x", cpu_prefix, i); diff --git a/MAINTAINERS b/MAINTAINERS index dcedfaed1f1..294c88ace9b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -648,7 +648,7 @@ M: Peter Maydell L: qemu-arm@nongnu.org S: Odd Fixes F: hw/*/exynos* -F: include/hw/arm/exynos4210.h +F: include/hw/*/exynos* =20 Calxeda Highbank M: Rob Herring --=20 2.25.1 From nobody Tue May 21 06:35:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e4-20020a5d6d04000000b0020a8bbbb72bsm2597694wrq.97.2022.04.21.04.19.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 04:19:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=/ffir/t2Hx0u1CtjBTRNm3H/5/bT+TQ8gxlGGj0T27Q=; b=br+s5mkL5fknQLnUEEjkazjt+BUZLYKwxAwJg22m7cPqwhiUsTYtNuTSw0GzCAS4ZB o+qosPgMSYfVlgXw+hDkwRbHnP+QY5TODlreOZ1ry2XJDkHLaI5VZWyaWu9R4s1Ha06e wgvJlgbPq4O/0OkwaSs/PNUzBSWEs8+/YqojC4iJVcudbnh6R7mPEOTkdQ+VWaG1QHeU uaPVMEv+XpPNj3+xKGXaolgLKzKa1ssbU7x3g/ID5GUO1raIWzyK1GuzqnheKYYoGJp9 XpZXBJwkpsreajfZoT4g8uNhk7HugBinsz3VPtnbUu4EDulTtK0+kSj8bwS2NSCBWYgD kVAw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/ffir/t2Hx0u1CtjBTRNm3H/5/bT+TQ8gxlGGj0T27Q=; b=cG79vDgURjaJBY9eqmMDykrSp9EIHOPtDVde9abFlWPcnfgP1c2XVdPAmudMS/lbTJ VOLQlu/fNUcF5EQ1H98NOnepVpZXB/AIbDiKWXNIZ9am1SzYHAqyGFactApz2NgHrnn9 y/GFrRIMZ2lDS8zWymsudc66Pyh/9KZhq1p/2c8zD/u3mrkatz8ZyTAGxmZnSdLizuDo zKwrZrhbJ0YtqFkKHgvugy4jLzbq8o4iqpkdhFfm67wb3ZDFct2Tkb6pyu12Hqyzc1Ve c4+Ch/Sxe7zk4OINxnkthC+p32Xe/syKAk+YUVA/UGX+DwPdke6Wf3ABu0LTWJ0baNSm xRBQ== X-Gm-Message-State: AOAM531XuxsNKfguJZ0kqtqTNK0BeJPxCUBP6cXTiAvqnuFduMEicX+6 Odg8rW/s8DBLWL8zhW8DJr6EpbjAapMqdg== X-Google-Smtp-Source: ABdhPJy5EO73Vn8P1zV0I0mglPXKsOI69D6yestYNDgLeEg6Z6s0sAOhTMWHTy/1tVbe6GycUN3Tkw== X-Received: by 2002:adf:e687:0:b0:207:a4c4:b928 with SMTP id r7-20020adfe687000000b00207a4c4b928mr18988594wrm.629.1650539942598; Thu, 21 Apr 2022 04:19:02 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/31] hw/arm/exynos4210: Drop ext_gic_irq[] from Exynos4210Irq struct Date: Thu, 21 Apr 2022 12:18:31 +0100 Message-Id: <20220421111846.2011565-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org> References: <20220421111846.2011565-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650540738566100001 Content-Type: text/plain; charset="utf-8" The only time we use the ext_gic_irq[] array in the Exynos4210Irq struct is during realize of the SoC -- we initialize it with the input IRQs of the external GIC device, and then connect those to outputs of other devices further on in realize (including in the exynos4210_init_board_irqs() function). Now that the ext_gic object is easily accessible as s->ext_gic we can make the connections directly from one device to the other without going via this array. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220404154658.565020-10-peter.maydell@linaro.org --- include/hw/arm/exynos4210.h | 1 - hw/arm/exynos4210.c | 12 ++++++------ 2 files changed, 6 insertions(+), 7 deletions(-) diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h index f35ae90000f..08f52c511ff 100644 --- a/include/hw/arm/exynos4210.h +++ b/include/hw/arm/exynos4210.h @@ -83,7 +83,6 @@ typedef struct Exynos4210Irq { qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ]; - qemu_irq ext_gic_irq[EXYNOS4210_EXT_GIC_NIRQ]; } Exynos4210Irq; =20 struct Exynos4210State { diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 2058df9aecf..5a41af089f9 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -257,6 +257,7 @@ static void exynos4210_init_board_irqs(Exynos4210State = *s) { uint32_t grp, bit, irq_id, n; Exynos4210Irq *is =3D &s->irqs; + DeviceState *extgicdev =3D DEVICE(&s->ext_gic); =20 for (n =3D 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { irq_id =3D 0; @@ -272,7 +273,8 @@ static void exynos4210_init_board_irqs(Exynos4210State = *s) } if (irq_id) { s->irq_table[n] =3D qemu_irq_split(is->int_combiner_irq[n], - is->ext_gic_irq[irq_id - 32]); + qdev_get_gpio_in(extgicdev, + irq_id - 32)= ); } else { s->irq_table[n] =3D qemu_irq_split(is->int_combiner_irq[n], is->ext_combiner_irq[n]); @@ -287,7 +289,8 @@ static void exynos4210_init_board_irqs(Exynos4210State = *s) =20 if (irq_id) { s->irq_table[n] =3D qemu_irq_split(is->int_combiner_irq[n], - is->ext_gic_irq[irq_id - 32]); + qdev_get_gpio_in(extgicdev, + irq_id - 32)= ); } } } @@ -466,9 +469,6 @@ static void exynos4210_realize(DeviceState *socdev, Err= or **errp) sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->cpu_irq_orgate[n]),= 1)); } - for (n =3D 0; n < EXYNOS4210_EXT_GIC_NIRQ; n++) { - s->irqs.ext_gic_irq[n] =3D qdev_get_gpio_in(DEVICE(&s->ext_gic), n= ); - } =20 /* Internal Interrupt Combiner */ dev =3D qdev_new("exynos4210.combiner"); @@ -487,7 +487,7 @@ static void exynos4210_realize(DeviceState *socdev, Err= or **errp) busdev =3D SYS_BUS_DEVICE(dev); sysbus_realize_and_unref(busdev, &error_fatal); for (n =3D 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { - sysbus_connect_irq(busdev, n, s->irqs.ext_gic_irq[n]); + sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic)= , n)); } exynos4210_combiner_get_gpioin(&s->irqs, dev, 1); sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); --=20 2.25.1 From nobody Tue May 21 06:35:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650541112; cv=none; d=zohomail.com; s=zohoarc; b=OtoRWmSISPEq/tmr9tuLyXtmnV0TKSlsz5I5shXW0GMwS5JgHreP+fKp4ncSzc5pr+24OnmMdsA3Jf2+7U0tEnbPMH+t7GwFx2o3Mcdpmw0hCH8DDXIjTuTU2ZSgTvDbHOOu2syVnZBurWDQWzWRkN2tTLaKBOsRJmHYuwftdQ0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650541112; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+j9q4V2tfWLss3L7M8noxjW9hKFspam5EgiESVzgKr8=; b=B8KM69wbAM7T1Y9Vkw0qIimX8N+IGPUVZJq0YsqdWjqx+Y+wfT4iO15p3kQ6vvMckQlQJlWKuVEuo7YjEXP2vf7Oi4F/0iltbN0YlJ3Tlam5DHY1IesgR9ZUYIYPuLKuULHAiaN9Sk9oSW4WWTL6dYYlksrPc3At0soI28637T8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650541112288250.2815415494132; Thu, 21 Apr 2022 04:38:32 -0700 (PDT) Received: from localhost ([::1]:43062 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhV8o-00084N-Ia for importer@patchew.org; Thu, 21 Apr 2022 07:38:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59418) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhUq3-00038H-1g for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:19:07 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:40521) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nhUq0-0003VP-Ti for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:19:06 -0400 Received: by mail-wm1-x32e.google.com with SMTP id v64-20020a1cac43000000b0038cfd1b3a6dso5635129wme.5 for ; Thu, 21 Apr 2022 04:19:04 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e4-20020a5d6d04000000b0020a8bbbb72bsm2597694wrq.97.2022.04.21.04.19.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 04:19:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=+j9q4V2tfWLss3L7M8noxjW9hKFspam5EgiESVzgKr8=; b=qqHja5fhYrGXsGbPswB0HsAJx6HaUk3AKol4573I3LjVDja13GBsheEg0vvUdXTbIo gbTOojWYja759m0mkfWuE5RPBjuZdvXo0BqxMP9U/NnTr9ZLCsYqXe2AKJnLghppOBmn dmWEjCM9ab0LGWcHcE4prZ9XTVN7+UUtfBeJGIATW/+kFgdGx5DJHA91rjkx6Qd4zIeh jOgNpyJbi1u+VUkGF+cVKxacMTNT8vm5A6jSRCWHo9fvaFTfS2BtEbpDdO5a0lrAhl4A GeUljrjMcv9i4SdGkD/CE/lWU1WA0aY3H2dWFW8OZRFRj/OE+wN9iV2zBkf8Qk9LpjrW mWPg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+j9q4V2tfWLss3L7M8noxjW9hKFspam5EgiESVzgKr8=; b=UXZhDLaI1CES78gIc1riZMxA+ieDGHfdxVMhfTvdobrxBVTiGbrnTvfjnpPi8qHDG8 Y3x+GhhDMBZKJStidjr8cnQ/eGaSxEtBhZINeo5L9C6oWLZagoE6eDi0B/1Aaa02yXYF CqtxJsMVU43ORnnN8+G2+BaxcCk4PmbOhN1GzCLk+H4l9Bu134eDPnQ+RW6f0aLpDcWG XUDfBTLluBgMwF8zfnU5BR/9PgTPf1h2AajC1LkMmodOl+YnwbwZ+21BIAOxjhoNbeUG yYAdptGunT3fphjNCz+kW5dzxA0Am625kB3UcFS4dBm3BYnEttage9aBdPXOGTTZoWZ2 +8vQ== X-Gm-Message-State: AOAM533B0v1Qxt8JLKeAsJPQ6sKDrx11DVRI+iFDPLfXL9MMpY/fe8AH 3eRjMA5K6pVDV+A9vZlMAi/M1KihjJadPQ== X-Google-Smtp-Source: ABdhPJzYGzrQQWtBJqesOnO4V4UiX8IQb6p3xs//Kbh08Cio76XVVr57h1D5YnW/1JqN//DpGr8Wng== X-Received: by 2002:a05:600c:4f56:b0:392:4cd4:b161 with SMTP id m22-20020a05600c4f5600b003924cd4b161mr8238111wmq.178.1650539943498; Thu, 21 Apr 2022 04:19:03 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/31] hw/arm/exynos4210: Move exynos4210_combiner_get_gpioin() into exynos4210.c Date: Thu, 21 Apr 2022 12:18:32 +0100 Message-Id: <20220421111846.2011565-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org> References: <20220421111846.2011565-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650541113696100003 Content-Type: text/plain; charset="utf-8" The function exynos4210_combiner_get_gpioin() currently lives in exynos4210_combiner.c, but it isn't really part of the combiner device itself -- it is a function that implements the wiring up of some interrupt sources to multiple combiner inputs. Move it to live with the other SoC-level code in exynos4210.c, along with a few macros previously defined in exynos4210.h which are now used only in exynos4210.c. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220404154658.565020-11-peter.maydell@linaro.org --- include/hw/arm/exynos4210.h | 11 ----- hw/arm/exynos4210.c | 82 +++++++++++++++++++++++++++++++++++ hw/intc/exynos4210_combiner.c | 77 -------------------------------- 3 files changed, 82 insertions(+), 88 deletions(-) diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h index 08f52c511ff..b564e3582bb 100644 --- a/include/hw/arm/exynos4210.h +++ b/include/hw/arm/exynos4210.h @@ -67,11 +67,6 @@ #define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ \ (EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8) =20 -#define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit) ((grp)*8 + (bit)) -#define EXYNOS4210_COMBINER_GET_GRP_NUM(irq) ((irq) / 8) -#define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \ - ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq)) - /* IRQs number for external and internal GIC */ #define EXYNOS4210_EXT_GIC_NIRQ (160-32) #define EXYNOS4210_INT_GIC_NIRQ 64 @@ -118,12 +113,6 @@ void exynos4210_write_secondary(ARMCPU *cpu, * bit - bit number inside group */ uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit); =20 -/* - * Get Combiner input GPIO into irqs structure - */ -void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev, - int ext); - /* * exynos4210 UART */ diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 5a41af089f9..86a9a0dae12 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -249,6 +249,11 @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINE= R_OUT_IRQ][8] =3D { { }, { }, { }, { }, { }, { }, { }, { }, { }, { } }; =20 +#define EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit) ((grp) * 8 + (bit)) +#define EXYNOS4210_COMBINER_GET_GRP_NUM(irq) ((irq) / 8) +#define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \ + ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq)) + /* * Initialize board IRQs. * These IRQs contain splitted Int/External Combiner and External Gic IRQs. @@ -306,6 +311,83 @@ uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit); } =20 +/* + * Get Combiner input GPIO into irqs structure + */ +static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, + DeviceState *dev, int ext) +{ + int n; + int bit; + int max; + qemu_irq *irq; + + max =3D ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ : + EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; + irq =3D ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq; + + /* + * Some IRQs of Int/External Combiner are going to two Combiners group= s, + * so let split them. + */ + for (n =3D 0; n < max; n++) { + + bit =3D EXYNOS4210_COMBINER_GET_BIT_NUM(n); + + switch (n) { + /* MDNIE_LCD1 INTG1 */ + case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ... + EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3): + irq[n] =3D qemu_irq_split(qdev_get_gpio_in(dev, n), + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]); + continue; + + /* TMU INTG3 */ + case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4): + irq[n] =3D qemu_irq_split(qdev_get_gpio_in(dev, n), + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]); + continue; + + /* LCD1 INTG12 */ + case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ... + EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3): + irq[n] =3D qemu_irq_split(qdev_get_gpio_in(dev, n), + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]); + continue; + + /* Multi-Core Timer INTG12 */ + case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ... + EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8): + irq[n] =3D qemu_irq_split(qdev_get_gpio_in(dev, n), + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); + continue; + + /* Multi-Core Timer INTG35 */ + case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ... + EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8): + irq[n] =3D qemu_irq_split(qdev_get_gpio_in(dev, n), + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); + continue; + + /* Multi-Core Timer INTG51 */ + case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ... + EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8): + irq[n] =3D qemu_irq_split(qdev_get_gpio_in(dev, n), + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); + continue; + + /* Multi-Core Timer INTG53 */ + case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ... + EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8): + irq[n] =3D qemu_irq_split(qdev_get_gpio_in(dev, n), + irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); + continue; + } + + irq[n] =3D qdev_get_gpio_in(dev, n); + } +} + static uint8_t chipid_and_omr[] =3D { 0x11, 0x02, 0x21, 0x43, 0x09, 0x00, 0x00, 0x00 }; =20 diff --git a/hw/intc/exynos4210_combiner.c b/hw/intc/exynos4210_combiner.c index 4534ee248db..83b42b9bce1 100644 --- a/hw/intc/exynos4210_combiner.c +++ b/hw/intc/exynos4210_combiner.c @@ -105,83 +105,6 @@ static const VMStateDescription vmstate_exynos4210_com= biner =3D { } }; =20 -/* - * Get Combiner input GPIO into irqs structure - */ -void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, DeviceState *dev, - int ext) -{ - int n; - int bit; - int max; - qemu_irq *irq; - - max =3D ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ : - EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; - irq =3D ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq; - - /* - * Some IRQs of Int/External Combiner are going to two Combiners group= s, - * so let split them. - */ - for (n =3D 0; n < max; n++) { - - bit =3D EXYNOS4210_COMBINER_GET_BIT_NUM(n); - - switch (n) { - /* MDNIE_LCD1 INTG1 */ - case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ... - EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3): - irq[n] =3D qemu_irq_split(qdev_get_gpio_in(dev, n), - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]); - continue; - - /* TMU INTG3 */ - case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4): - irq[n] =3D qemu_irq_split(qdev_get_gpio_in(dev, n), - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]); - continue; - - /* LCD1 INTG12 */ - case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ... - EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3): - irq[n] =3D qemu_irq_split(qdev_get_gpio_in(dev, n), - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]); - continue; - - /* Multi-Core Timer INTG12 */ - case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ... - EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8): - irq[n] =3D qemu_irq_split(qdev_get_gpio_in(dev, n), - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); - continue; - - /* Multi-Core Timer INTG35 */ - case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ... - EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8): - irq[n] =3D qemu_irq_split(qdev_get_gpio_in(dev, n), - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); - continue; - - /* Multi-Core Timer INTG51 */ - case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ... - EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8): - irq[n] =3D qemu_irq_split(qdev_get_gpio_in(dev, n), - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); - continue; - - /* Multi-Core Timer INTG53 */ - case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ... - EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8): - irq[n] =3D qemu_irq_split(qdev_get_gpio_in(dev, n), - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); - continue; - } - - irq[n] =3D qdev_get_gpio_in(dev, n); - } -} - static uint64_t exynos4210_combiner_read(void *opaque, hwaddr offset, unsigned size) { --=20 2.25.1 From nobody Tue May 21 06:35:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650541773; cv=none; d=zohomail.com; s=zohoarc; b=Bi4tZ44pdecO8bpLdS5ZC5zPOCV6gvmM7+6RDq4Zk8WSYJGLWDKYxRinSYw4WGFfcXaMkiKMf6epI3yBp3bPWubAGT7JnWPnR8ORnlg+K+tLP6bYWKoLHPgHF7eueZfPO4I5dMATYycWHtjntCn+1GUhxIcfuutqz5TIyBn8TZg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650541773; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Iwx4JxobNFjb6CXW4X/ZTu+ghI+lexKYib3ejhFEP0M=; b=TJNIDFW28lL29PfE72jSUL5UXeHQWORVXuju3eCmOhEOwnac3TpY3M55DwWpz/COIzkPwCCWG0BizNHjtwlu8DFd3SAfchInJfIR075wL6gTtLBNYDISNLUjZjWghOh9l8vwZaZqRSbMQdzj0wcgu8DfV1DygAmHD9E6IEimgKk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650541773272707.5101255899058; Thu, 21 Apr 2022 04:49:33 -0700 (PDT) Received: from localhost ([::1]:60300 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhVJR-0003pU-Vx for importer@patchew.org; Thu, 21 Apr 2022 07:49:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59420) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhUq3-00038e-3N for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:19:07 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:35753) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nhUq1-0003VX-IG for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:19:06 -0400 Received: by mail-wr1-x431.google.com with SMTP id k22so6228755wrd.2 for ; Thu, 21 Apr 2022 04:19:05 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e4-20020a5d6d04000000b0020a8bbbb72bsm2597694wrq.97.2022.04.21.04.19.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 04:19:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Iwx4JxobNFjb6CXW4X/ZTu+ghI+lexKYib3ejhFEP0M=; b=Kdgkb46swUg7oAnpP59auRbM8I2cxAKaoMOng966/zqzj+G7BIJglFKB99pn7U6zo7 yZrDCCcIO5KGWGN6T7pAgzPAMHbsr8j6/CbWUqE9wGPnFh/uGBFhafqZ9NokoL+nQyZ7 f7V6T67mjTMr6UJ+YNj01K1ZgeKjvUGUWHpZ7ewhVKCN5Als+zh63/uZnF8srqV3bgWu OLf0CBxYX2D8Jo6tn1O67oDtTTkY+j6GlSEVn5gC57BegI5eG8+2joBS7SE2yDxJwTVC ncTjWKAWT0oR/uyZb0RLNXdL9S3S+pQi9Ed7seCTobHhdenZGrKmzLMZzXCv16UvEIRn AZcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Iwx4JxobNFjb6CXW4X/ZTu+ghI+lexKYib3ejhFEP0M=; b=gQhKRp1vkCZEBL6EgojzsMYomEmAWakzLSyzTP/wAgxrKHea4ZzzgiE9AxjJOdaQhW dDu/62EsnmZi+4p6BcctZ5WBtnI6MS8HOGvBxk/B7dmdSQXZ5AZ74EL3mXwbtXbSv6Vr GLjHlHwmuiV6aVT7X26GOUvJUYU2WZgT2nKzrHu/A6BJ7gKWXeBnDL4ngHnTiCFIxl9B wTn2ZT8qMp8Ff4xopXbZK/HlyVI0Onjxja2UN2O+Lx6SFen3Z2lxkq9VMIzQ4wAYs6Xm C2RJIF9whq68Z/YwFPOrrU229sBRzxML5mx+psBXU6CutA1sFL/346d+hGHMcJ8D1h/+ 4Bfg== X-Gm-Message-State: AOAM532bU9mFIC8cqS+rzaf874Uu/AIICGc+hE3eKkGzGMgmqMCujV/Q d2W/oSm5MtClASFmcyGMKPEBaptvvajuaQ== X-Google-Smtp-Source: ABdhPJzsyupnoXWXZ5VbbiwWhlJU2OuleNH2cZFTD2ySLvDtWIVPCQdRHWSLmh9KDCbLOuly/ixviA== X-Received: by 2002:a05:6000:156a:b0:20a:9c1b:6b1b with SMTP id 10-20020a056000156a00b0020a9c1b6b1bmr13221774wrz.683.1650539944279; Thu, 21 Apr 2022 04:19:04 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/31] hw/arm/exynos4210: Delete unused macro definitions Date: Thu, 21 Apr 2022 12:18:33 +0100 Message-Id: <20220421111846.2011565-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org> References: <20220421111846.2011565-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650541774967100001 Content-Type: text/plain; charset="utf-8" Delete a couple of #defines which are never used. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220404154658.565020-12-peter.maydell@linaro.org --- include/hw/arm/exynos4210.h | 4 ---- 1 file changed, 4 deletions(-) diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h index b564e3582bb..f0769a4045b 100644 --- a/include/hw/arm/exynos4210.h +++ b/include/hw/arm/exynos4210.h @@ -67,10 +67,6 @@ #define EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ \ (EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ * 8) =20 -/* IRQs number for external and internal GIC */ -#define EXYNOS4210_EXT_GIC_NIRQ (160-32) -#define EXYNOS4210_INT_GIC_NIRQ 64 - #define EXYNOS4210_I2C_NUMBER 9 =20 #define EXYNOS4210_NUM_DMA 3 --=20 2.25.1 From nobody Tue May 21 06:35:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650540875; cv=none; d=zohomail.com; s=zohoarc; b=QOGIq8z5Y0lGyXfnbIBA44n0bU/lK8VKiCSfjxEYTcuTLlf+CeP4yMtRs5fWEek/dUKXiq6jEZtiioMPpPonGJ3JipTJtfd+imQcQfxCjwcw5wN5qCwE1hyaDghlCBpqrFsBsc2ewdg69SSuS/Ayc6Vh2Pdjci3CLP5fyojhHww= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650540875; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6iEh6vhBWVu8vdp664MaCGIOBRqTLHZP+x0CHEhw0js=; b=L1d1V5M3YL3T266Mj02VCdBpuYRi5gQfCvu5qHxESN1ui2fMS/Mqls+FM+ljdW7aWAdzrKgp3YZcFvV0HESghifZ6FJ1cus6+Kgt6foF2Z7by2RoRFs43fNSxPD9dTTBX8uhsqZloCj3HDce3xdR0zsgNQyqwqlpFqfaGP6ZcEI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650540875704736.251124454167; Thu, 21 Apr 2022 04:34:35 -0700 (PDT) Received: from localhost ([::1]:60908 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhV50-0000gL-Hr for importer@patchew.org; Thu, 21 Apr 2022 07:34:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59452) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhUq5-0003AC-3F for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:19:10 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:41812) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nhUq2-0003Vn-EF for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:19:08 -0400 Received: by mail-wr1-x42c.google.com with SMTP id s25so1326008wrb.8 for ; Thu, 21 Apr 2022 04:19:06 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e4-20020a5d6d04000000b0020a8bbbb72bsm2597694wrq.97.2022.04.21.04.19.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 04:19:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=6iEh6vhBWVu8vdp664MaCGIOBRqTLHZP+x0CHEhw0js=; b=Fm30hB+yVssk93ZtLO9H3OCgJ/vc2BiWLPA7lgfLDj/QcTjk3HDqW9hdzflhnzzTza sml/i3TJ2Q5w53rmmhx3kPVjOvJTWoN3ZA6eIushhhLOPKNWfVH129QFKN6/6PPD3dgP dXleNo6/nQfvgo+UhWTcx2ZLRTZ8C/j4vU+0hm05DmGT3DWTTcxJxINm5e7QnepCPP7h /R6USRYGkvxlq340C8dUUoWmam38nex5ro0b9TyIqZFYErCxfmJRGH5NTjhx/dtSUT7E /7lAReiPYVt4UPRQk1+49fDo7WtFd1sjDum1jbcJMI/S3mzwdCqqMSlWqiuDNTJQzWWX wRPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6iEh6vhBWVu8vdp664MaCGIOBRqTLHZP+x0CHEhw0js=; b=y1sf7AW3dLX9PTXIio4YRtrmOL2wL5HFYwDaGQMXiwPBWa2ZC01q8MojvG2AIKkBnu vId5kgk9x8LQZ6Pg3PKXCwnUqwfGoLx9f88PvpQYbVQbz8bu9xgkV0zebDABe5Wn8By3 E4CG9D6e1nNi9Qj3ElmiJLcJZT1FkQX57cvwa1raD6QJ4qUAXMF8AoND/PW6ybhA3BDO iwRzSv7M/KyeF50/0cnoyEoAkrQ8mKoc01Gtrxt3xE+weXHk5UmrQROELBz3MPiu65Fr FARVCzBDLAgnTuW/IPP943j/QkC+4V9X5jyzARQAMA3KsaBypRpPi5ySCYZQ8eW9WTnw Eefg== X-Gm-Message-State: AOAM531X4Rne7JF7RZjUEUBytBv0NKqhUMEnbFeMY07NLAaKIyPdgek5 EJafr11Z0kIF6a1KbaxTZBDFPFqZMPMCRA== X-Google-Smtp-Source: ABdhPJyzC007qti0UJXbR/6IVBZcFMETLIe+R83sOoCE8rILLPVp29fcjK7n6yNMcpkGLu3C2YS4qw== X-Received: by 2002:adf:f2cb:0:b0:20a:77c2:3958 with SMTP id d11-20020adff2cb000000b0020a77c23958mr18539139wrp.589.1650539945226; Thu, 21 Apr 2022 04:19:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/31] hw/arm/exynos4210: Use TYPE_SPLIT_IRQ in exynos4210_init_board_irqs() Date: Thu, 21 Apr 2022 12:18:34 +0100 Message-Id: <20220421111846.2011565-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org> References: <20220421111846.2011565-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650540876600100001 Content-Type: text/plain; charset="utf-8" In exynos4210_init_board_irqs(), use the TYPE_SPLIT_IRQ device instead of qemu_irq_split(). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220404154658.565020-13-peter.maydell@linaro.org --- include/hw/arm/exynos4210.h | 9 ++++++++ hw/arm/exynos4210.c | 41 +++++++++++++++++++++++++++++-------- 2 files changed, 42 insertions(+), 8 deletions(-) diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h index f0769a4045b..f58ee0f2686 100644 --- a/include/hw/arm/exynos4210.h +++ b/include/hw/arm/exynos4210.h @@ -28,6 +28,7 @@ #include "hw/sysbus.h" #include "hw/cpu/a9mpcore.h" #include "hw/intc/exynos4210_gic.h" +#include "hw/core/split-irq.h" #include "target/arm/cpu-qom.h" #include "qom/object.h" =20 @@ -71,6 +72,13 @@ =20 #define EXYNOS4210_NUM_DMA 3 =20 +/* + * We need one splitter for every external combiner input, plus + * one for every non-zero entry in combiner_grp_to_gic_id[]. + * We'll assert in exynos4210_init_board_irqs() if this is wrong. + */ +#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 60) + typedef struct Exynos4210Irq { qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ]; @@ -95,6 +103,7 @@ struct Exynos4210State { qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; A9MPPrivState a9mpcore; Exynos4210GicState ext_gic; + SplitIRQ splitter[EXYNOS4210_NUM_SPLITTERS]; }; =20 #define TYPE_EXYNOS4210_SOC "exynos4210" diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 86a9a0dae12..919821833b5 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -263,6 +263,8 @@ static void exynos4210_init_board_irqs(Exynos4210State = *s) uint32_t grp, bit, irq_id, n; Exynos4210Irq *is =3D &s->irqs; DeviceState *extgicdev =3D DEVICE(&s->ext_gic); + int splitcount =3D 0; + DeviceState *splitter; =20 for (n =3D 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { irq_id =3D 0; @@ -276,13 +278,19 @@ static void exynos4210_init_board_irqs(Exynos4210Stat= e *s) /* MCT_G1 is passed to External and GIC */ irq_id =3D EXT_GIC_ID_MCT_G1; } + + assert(splitcount < EXYNOS4210_NUM_SPLITTERS); + splitter =3D DEVICE(&s->splitter[splitcount]); + qdev_prop_set_uint16(splitter, "num-lines", 2); + qdev_realize(splitter, NULL, &error_abort); + splitcount++; + s->irq_table[n] =3D qdev_get_gpio_in(splitter, 0); + qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]); if (irq_id) { - s->irq_table[n] =3D qemu_irq_split(is->int_combiner_irq[n], - qdev_get_gpio_in(extgicdev, - irq_id - 32)= ); + qdev_connect_gpio_out(splitter, 1, + qdev_get_gpio_in(extgicdev, irq_id - 32)= ); } else { - s->irq_table[n] =3D qemu_irq_split(is->int_combiner_irq[n], - is->ext_combiner_irq[n]); + qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]); } } for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { @@ -293,11 +301,23 @@ static void exynos4210_init_board_irqs(Exynos4210Stat= e *s) EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; =20 if (irq_id) { - s->irq_table[n] =3D qemu_irq_split(is->int_combiner_irq[n], - qdev_get_gpio_in(extgicdev, - irq_id - 32)= ); + assert(splitcount < EXYNOS4210_NUM_SPLITTERS); + splitter =3D DEVICE(&s->splitter[splitcount]); + qdev_prop_set_uint16(splitter, "num-lines", 2); + qdev_realize(splitter, NULL, &error_abort); + splitcount++; + s->irq_table[n] =3D qdev_get_gpio_in(splitter, 0); + qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]); + qdev_connect_gpio_out(splitter, 1, + qdev_get_gpio_in(extgicdev, irq_id - 32)= ); } } + /* + * We check this here to avoid a more obscure assert later when + * qdev_assert_realized_properly() checks that we realized every + * child object we initialized. + */ + assert(splitcount =3D=3D EXYNOS4210_NUM_SPLITTERS); } =20 /* @@ -766,6 +786,11 @@ static void exynos4210_init(Object *obj) object_initialize_child(obj, name, &s->cpu_irq_orgate[i], TYPE_OR_= IRQ); } =20 + for (i =3D 0; i < ARRAY_SIZE(s->splitter); i++) { + g_autofree char *name =3D g_strdup_printf("irq-splitter%d", i); + object_initialize_child(obj, name, &s->splitter[i], TYPE_SPLIT_IRQ= ); + } + object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_P= RIV); object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_G= IC); } --=20 2.25.1 From nobody Tue May 21 06:35:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650541053; cv=none; d=zohomail.com; s=zohoarc; b=T9NhNo/oLuPmBp2IRbUZL2Ep+yTmZw3zbD7JQ1tgyRV+XI3qwMm5pO4IJd4FkIjsk8uiK4CpwLUAIeVJz7f4pi18XINApWWsNOvfoQqY+BxOW49nKlzMqhh1ju0iBwO4+oylcxSrUP4DRMuP/MDUE3uJUPZ43K6dyijfyfmohmU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650541053; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1PyZdnk6RoN3xmhb1oq389S8umKBSyZVP3ZN0NOpuv4=; b=QDATFUVm2zfPgV9mqWpywelc80aeF15Tuc3gtq2qcGMcfkOZqRoX4D1iUw1KL7zFTf6mele00W8tzRdLQurSW45fzWhl5aIvMolX1fbLtf84VLGfqF7v6WDA+nKyJ6C2vFLGUUVxRWqU+zSTb2d2P0hTkf6GYkO/r000i5mKy1c= ARC-Authentication-Results: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e4-20020a5d6d04000000b0020a8bbbb72bsm2597694wrq.97.2022.04.21.04.19.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 04:19:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1PyZdnk6RoN3xmhb1oq389S8umKBSyZVP3ZN0NOpuv4=; b=ezgU+k2K7uylQi+TnfdXloAlNPAhxPyPYVOnPWz1r98/ZviPpKcyyN1Smw2ArwhNzs dfg8mAphw5kwrUhN7YCKVDwC0cMaNM6SpoP0+YNmcEIhhuK8UarLQCzbTDmop5iq2qX5 4nmXnuE4smBtCUmkxljADcB2Eseyahuaq9ZxUxCpZWEjTfATGfuD5t/vY5pWUQ7hvgz7 GCAo/V0fYJafvDU8n1qvaunaOqgc35C41EXhCVhve4EZxUTXNvpc6tR3v3tFI2aY/ZNr 8PjkHlhpks/e+E2ZgMRHofdNMUTJ0+9ZfOb+8GVkJdhIBqo6E4L2msMz+T3IM5ZRC1vJ uZZQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1PyZdnk6RoN3xmhb1oq389S8umKBSyZVP3ZN0NOpuv4=; b=hxR5gqksoaZrsY8Rshzz1wFftY864Ao04a7Clv8VgzwhwR/BTZT/RbMIjiTbRcj44V 9F7pJuFlDKw0CiU3wOUX+EfTWnJYof2zEbkaIY/SV9PIECg8tqwevOefavftmGp7jJvh vdlLGONNU7Eh4p2KGEeA8xOS3wNFjT9oazF2J1X2/9faAYGv0aQu3p/T9StSyM9Zh5PL vNXhCbNHOWOMlJgizIaycM4fvFC4JUfr+wc5piKQxvVicSTYWPg6rU3RLQDGFRvVSinO zmBB0WV0tWMW6b67X3AnwbX2oL+GKQo0JEIMzX1tEP3eARcOGkcMyVQ/23DjTh/67aRk nK/Q== X-Gm-Message-State: AOAM530JTrnLi3drLodmS3aLq7+j0UxVEt3wSDL/BuYQWKU+XkXeLUoz C5LvVqRRzrAjgHao+vjVx7fyr2+3wlwYoA== X-Google-Smtp-Source: ABdhPJzTrchYsNBiR1O5YT4odZ9vSj6EM1GunEBIhJKTDL2sxCQYJPLXOj4DVd/4753BJO2+iTquHg== X-Received: by 2002:adf:ebd2:0:b0:20a:9c10:ab29 with SMTP id v18-20020adfebd2000000b0020a9c10ab29mr13124200wrn.212.1650539946108; Thu, 21 Apr 2022 04:19:06 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/31] hw/arm/exynos4210: Fill in irq_table[] for internal-combiner-only IRQ lines Date: Thu, 21 Apr 2022 12:18:35 +0100 Message-Id: <20220421111846.2011565-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org> References: <20220421111846.2011565-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650541055478100001 Content-Type: text/plain; charset="utf-8" In exynos4210_init_board_irqs(), the loop that handles IRQ lines that are in a range that applies to the internal combiner only creates a splitter for those interrupts which go to both the internal combiner and to the external GIC, but it does nothing at all for the interrupts which don't go to the external GIC, leaving the irq_table[] array element empty for those. (This will result in those interrupts simply being lost, not in a QEMU crash.) I don't have a reliable datasheet for this SoC, but since we do wire up one interrupt line in this category (the HDMI I2C device on interrupt 16,1), this seems like it must be a bug in the existing QEMU code. Fill in the irq_table[] entries where we're not splitting the IRQ to both the internal combiner and the external GIC with the IRQ line of the internal combiner. (That is, these IRQ lines go to just one device, not multiple.) This bug didn't have any visible guest effects because the only implemented device that was affected was the HDMI I2C controller, and we never connect any I2C devices to that bus. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220404154658.565020-14-peter.maydell@linaro.org --- hw/arm/exynos4210.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 919821833b5..a4527f819ef 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -310,6 +310,8 @@ static void exynos4210_init_board_irqs(Exynos4210State = *s) qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]); qdev_connect_gpio_out(splitter, 1, qdev_get_gpio_in(extgicdev, irq_id - 32)= ); + } else { + s->irq_table[n] =3D is->int_combiner_irq[n]; } } /* --=20 2.25.1 From nobody Tue May 21 06:35:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650541413; cv=none; d=zohomail.com; s=zohoarc; b=jRU7/LoxDRjzTB81ZU/vt/vW7jcPgaXNPfyYl2mCgAQKA2ka79RjmoQth+EIRFo0Wj5UsAOl40p3kmSID5eKz1UwqcO68tErgpQGkbg5n1RYg7oH0TSl+4cJHZcoj0U40s6mHJeA6GAz/QpudCbGmqVu20EYPzLojPyaMt/vt7k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650541413; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=eg02MfewzqD34GfCv6gUqyp7N32TaZTJUBAY/UnbV7k=; b=bN7xWEbNpi7CHEUt/duk/XluVb5K0sX/ReTX8HIf5OhODZ7GiEO3EEuJ4MDFtgwJ7CIGqFVZNKye3RfKt4cQ1aAjOnfxgKHfGyrl2PMBu6A3W6mJJNCqRFTjKBCGWBrBKYqFY2N8xvX94KWN8Ur2GXbHGFo1lSYOEqXrwJKXfWE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650541413820306.1429658120261; Thu, 21 Apr 2022 04:43:33 -0700 (PDT) Received: from localhost ([::1]:49614 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhVDg-0004S9-46 for importer@patchew.org; Thu, 21 Apr 2022 07:43:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59486) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhUq6-0003BT-SN for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:19:10 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:45931) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nhUq4-0003WH-N1 for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:19:10 -0400 Received: by mail-wr1-x429.google.com with SMTP id w4so6175904wrg.12 for ; Thu, 21 Apr 2022 04:19:07 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e4-20020a5d6d04000000b0020a8bbbb72bsm2597694wrq.97.2022.04.21.04.19.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 04:19:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=eg02MfewzqD34GfCv6gUqyp7N32TaZTJUBAY/UnbV7k=; b=tUtl+e+DxAOnuKU7tEpwTfSmYg3VZ+4yL4j9a6aSeve94IyBU1LaDvbE6HlfMSA9iI 1PyNctNWyj0b6dXeWrM+A5fJbjb22l4MO1W8mXZSyhl0gsAh3pM0gzRSnHs5qJ1WIaxj SKzDzV18Ip2ngRmi5ySJX4rnqZvue8oQeDbnWflGPosNImG3Kq8j6DmNgHmDDyixQtjs Wz10f/R8GxMIBtq5GGKEVohbF+2LhUVz6aeeCzYtlGNJR8pYQKAPNmfd5qd9HktIwYet y3dD3NaPt8vgL06PJpEsmEdA8hip7y2XqWGeYB9o5TS2r2SU3ZcYYz+sl16z/ftBmCNr 4PNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eg02MfewzqD34GfCv6gUqyp7N32TaZTJUBAY/UnbV7k=; b=e3n9bEjFdL45kBxO3Io3aM07ZDO/qvuvx97+An5X2i6G3MynD7qckJ07TNG6ZLyVLI udiOZkgy2k0YIfPS6swTMFTDiRf+nLs+vAX74eyUKJvWjv7hwOwtWmFcFCZ6EQ96JzF6 FhdNIH0S1nSfcvR88wj8pdill5io4nL3/9ENswGugvaBo+onH/zMEwwR2ZVcxLtC4JhA nxc0rtQvGgIDMliHVjfIjh8nmELoRurDt9NWqTDEa6vzkGXc22ijQjk1nkjeqcNjrLwQ sFdEqtm/Bjw08lya+xe7i+kAasiYBFCKyV5by9V4hxTdA7CVzL/rFr0rqafeTOsGnhNP dgnA== X-Gm-Message-State: AOAM533tfqXcDZutJZdvsHGC+Rxj2L2dg4RO3NEghrtafOAe2iHs8fdc HKZg6BvISdtab2lwpn7e1Q/ygZd/SZVbbQ== X-Google-Smtp-Source: ABdhPJyt32qHr17FnwOaot+NS87c6V423qkQwGuRJjNp7ozimOwsSIV8o1s+2joAhNZFDarw+m9o/g== X-Received: by 2002:a5d:4a81:0:b0:207:9abe:2908 with SMTP id o1-20020a5d4a81000000b002079abe2908mr18819233wrq.341.1650539946907; Thu, 21 Apr 2022 04:19:06 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/31] hw/arm/exynos4210: Connect MCT_G0 and MCT_G1 to both combiners Date: Thu, 21 Apr 2022 12:18:36 +0100 Message-Id: <20220421111846.2011565-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org> References: <20220421111846.2011565-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650541414633100001 Content-Type: text/plain; charset="utf-8" Currently for the interrupts MCT_G0 and MCT_G1 which are the only ones in the input range of the external combiner and which are also wired to the external GIC, we connect them only to the internal combiner and the external GIC. This seems likely to be a bug, as all other interrupts which are in the input range of both combiners are connected to both combiners. (The fact that the code in exynos4210_combiner_get_gpioin() is also trying to wire up these inputs on both combiners also suggests this.) Wire these interrupts up to both combiners, like the rest. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220404154658.565020-15-peter.maydell@linaro.org --- hw/arm/exynos4210.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index a4527f819ef..962d6d0ac2a 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -281,16 +281,15 @@ static void exynos4210_init_board_irqs(Exynos4210Stat= e *s) =20 assert(splitcount < EXYNOS4210_NUM_SPLITTERS); splitter =3D DEVICE(&s->splitter[splitcount]); - qdev_prop_set_uint16(splitter, "num-lines", 2); + qdev_prop_set_uint16(splitter, "num-lines", irq_id ? 3 : 2); qdev_realize(splitter, NULL, &error_abort); splitcount++; s->irq_table[n] =3D qdev_get_gpio_in(splitter, 0); qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]); + qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]); if (irq_id) { - qdev_connect_gpio_out(splitter, 1, + qdev_connect_gpio_out(splitter, 2, qdev_get_gpio_in(extgicdev, irq_id - 32)= ); - } else { - qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]); } } for (; n < EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; n++) { --=20 2.25.1 From nobody Tue May 21 06:35:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650541483; cv=none; d=zohomail.com; s=zohoarc; b=K5joGnyxtMES/jmGeO7fqRVDnC7iDZl3ei+7Q0rXau+fUChACDABQnZCrxQ0jZ7msZii9O1/uYin8XOkl7AP0R5Mg2dVEBuB21YKjFnOgHIsVelXzhbHBgzmrAU79FAOoUdZ5+PH7RsyFGw5vv4GYgBVfDBmXCbB0D/dUREqkoA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650541483; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=d+s9Ayr2MToy3NwUrcI6rbLNGvw59lNw6jFaFEZj0pg=; b=P57dLoyZQPWLqFU5b5d0lmStxkoSuLSbB4bObBxGq5D7sYCfr2RTTvSwG4ya2E/ob29sLAhEzyUVzvPDEKAjgjm1xxNuen/zjmdmn6JiMQLDr0r29hneUx0HpZDZ5qxnzwi8Esdp+IcyD7w8veWLi1b4273+aSAB/dSAYpRmwJM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650541483897918.3018264786489; Thu, 21 Apr 2022 04:44:43 -0700 (PDT) Received: from localhost ([::1]:51832 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhVEo-0006Fh-0q for importer@patchew.org; Thu, 21 Apr 2022 07:44:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59494) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhUq6-0003Ba-VG for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:19:10 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:45935) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nhUq5-0003WQ-5E for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:19:10 -0400 Received: by mail-wr1-x42d.google.com with SMTP id w4so6175948wrg.12 for ; Thu, 21 Apr 2022 04:19:08 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e4-20020a5d6d04000000b0020a8bbbb72bsm2597694wrq.97.2022.04.21.04.19.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 04:19:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=d+s9Ayr2MToy3NwUrcI6rbLNGvw59lNw6jFaFEZj0pg=; b=trl0v42oRATPMLSLwQnyQsz1N3yV0jiv33fUxMzqUe0cApeqCAkDL/2nV64QYsMapZ nvl4ifx70k/aUeGDr/BmLqlUvn3qJj+eDz+rSwSaLG3oOyw+wmJaJhwTOMDA4uL+vtyY a3aCNl+iMZnYoZ4N4rUAsfom8SpG3CANlbW+zia1I7RYjVzotWkBZn3uWnPqe8iA4X1Z ahhmoGJu8Bd76EB80UmkEDzdD3LbRQp+Vga/yv6XkzqpGpy7E9Aid7s3Pp+JA4gGjOlN Lk7cH89wqWxi+a5ehDhUrj7gdpJbRso9VIQDpT9vJVGHgRymH5O2FpwoKtDFdbOMD9MO ewwg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=d+s9Ayr2MToy3NwUrcI6rbLNGvw59lNw6jFaFEZj0pg=; b=4oSpbQBLah1NeM/HNNHl0ikff+LZyou8b/drI6iTWfxChWEOPqwZrsVgH1b3Ct3q1O iKuAho5160kJRJZ9hLlZOdTe1k9ERHsaaue1oEbADUFYW4xS+5l2HCT6u+t0KWBh/MYT MAWwskE6l4GQGyvdkF8zb/tN2fosvb1kKq7zX36MqAybL34juvCyaLgR7ZNaW0bTmsqu 1y/c5AabKCYtpg4gbSHBc5BKu8un2ZdDe2kbfYMTg78PgLzjlRxfXDqXUqM59/dljWX5 aGrf7lHpcLoRvNEhm8n1xNlCoRMbkKe41RyiKsb6odzcs3mwxvFBtMizmjWR4t0twtt4 8Lhg== X-Gm-Message-State: AOAM5322/jNupzocea3rHSMN9waj9v+sdTWOOn7NfkTXO7TbU/PcE+WK YT4WSHMd3t9p04lPDx4MCi5fd9Haq+UA9Q== X-Google-Smtp-Source: ABdhPJyT6kGMBhGk/dBkYKaG9DXMT8buMB++lfA+lDqbESdhmHi3u0/94k7vhMPqZNO3ltIyLRMTkA== X-Received: by 2002:a5d:4348:0:b0:206:1c79:fd57 with SMTP id u8-20020a5d4348000000b002061c79fd57mr19555430wrr.344.1650539947766; Thu, 21 Apr 2022 04:19:07 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/31] hw/arm/exynos4210: Don't connect multiple lines to external GIC inputs Date: Thu, 21 Apr 2022 12:18:37 +0100 Message-Id: <20220421111846.2011565-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org> References: <20220421111846.2011565-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650541484967100001 Content-Type: text/plain; charset="utf-8" The combiner_grp_to_gic_id[] array includes the EXT_GIC_ID_MCT_G0 and EXT_GIC_ID_MCT_G1 multiple times. This means that we will connect multiple IRQs up to the same external GIC input, which is not permitted. We do the same thing in the code in exynos4210_init_board_irqs() because the conditionals selecting an irq_id in the first loop match multiple interrupt IDs. Overall we do this for interrupt IDs (1, 4), (12, 4), (35, 4), (51, 4), (53, 4) for EXT_GIC_ID_MCT_G0 and (1, 5), (12, 5), (35, 5), (51, 5), (53, 5) for EXT_GIC_ID_MCT_G1 These correspond to the cases for the multi-core timer that we are wiring up to multiple inputs on the combiner in exynos4210_combiner_get_gpioin(). That code already deals with all these interrupt IDs being the same input source, so we don't need to connect the external GIC interrupt for any of them except the first (1, 4) and (1, 5). Remove the array entries and conditionals which were incorrectly causing us to wire up extra lines. This bug didn't cause any visible effects, because we only connect up a device to the "primary" ID values (1, 4) and (1, 5), so the extra lines would never be set to a level. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220404154658.565020-16-peter.maydell@linaro.org --- include/hw/arm/exynos4210.h | 2 +- hw/arm/exynos4210.c | 12 +++++------- 2 files changed, 6 insertions(+), 8 deletions(-) diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h index f58ee0f2686..7da3eddea5f 100644 --- a/include/hw/arm/exynos4210.h +++ b/include/hw/arm/exynos4210.h @@ -77,7 +77,7 @@ * one for every non-zero entry in combiner_grp_to_gic_id[]. * We'll assert in exynos4210_init_board_irqs() if this is wrong. */ -#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 60) +#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 54) =20 typedef struct Exynos4210Irq { qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 962d6d0ac2a..39e334e0773 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -231,7 +231,7 @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINER= _OUT_IRQ][8] =3D { /* int combiner group 34 */ { EXT_GIC_ID_ONENAND_AUDI, EXT_GIC_ID_NFC }, /* int combiner group 35 */ - { 0, 0, 0, EXT_GIC_ID_MCT_L1, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, + { 0, 0, 0, EXT_GIC_ID_MCT_L1 }, /* int combiner group 36 */ { EXT_GIC_ID_MIXER }, /* int combiner group 37 */ @@ -240,11 +240,11 @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBIN= ER_OUT_IRQ][8] =3D { /* groups 38-50 */ { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, { }, /* int combiner group 51 */ - { EXT_GIC_ID_MCT_L0, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, + { EXT_GIC_ID_MCT_L0 }, /* group 52 */ { }, /* int combiner group 53 */ - { EXT_GIC_ID_WDT, 0, 0, 0, EXT_GIC_ID_MCT_G0, EXT_GIC_ID_MCT_G1 }, + { EXT_GIC_ID_WDT }, /* groups 54-63 */ { }, { }, { }, { }, { }, { }, { }, { }, { }, { } }; @@ -268,13 +268,11 @@ static void exynos4210_init_board_irqs(Exynos4210Stat= e *s) =20 for (n =3D 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { irq_id =3D 0; - if (n =3D=3D EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4) || - n =3D=3D EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4)) { + if (n =3D=3D EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 4)) { /* MCT_G0 is passed to External GIC */ irq_id =3D EXT_GIC_ID_MCT_G0; } - if (n =3D=3D EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5) || - n =3D=3D EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 5)) { + if (n =3D=3D EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 5)) { /* MCT_G1 is passed to External and GIC */ irq_id =3D EXT_GIC_ID_MCT_G1; } --=20 2.25.1 From nobody Tue May 21 06:35:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650541047; cv=none; d=zohomail.com; s=zohoarc; b=bb0JmPObCk5U96ej374lkzHTb8gQa652O7aCP25gHCfKm4fHQ6smKrxkOhpNxriKm3lZKMAVhuY3lLYnYqcCNrqzf3MkJm2RhnrQvsULAOFm0ftbexgU+HgV0zefTOmABerFOQax6Vh8Dr7MzFaF1hPzSprpUlNuY13iOmx83ZU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650541047; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=oHJIYCR/bV2ZQNmrQ3vUauIwQavU4nVbs97MW/KeCJM=; b=mPKnQ8gdxz5FZy0Vzh/4IuSvK28RMjFIL27jeP5UJ2RYPXBoav2s4lDtLA5en5P3sOjtbudjjWQohduw2mVlAh+SuwayCH4h3qZ8HlQp+0GUvuLPeBG1Aek3YHoKVP5TtU2nGrVfY4NWxkVzBaTppoeDYNkFMQZm8GMSKz9FcSU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650541047385792.2361921550248; Thu, 21 Apr 2022 04:37:27 -0700 (PDT) Received: from localhost ([::1]:40426 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhV7l-0006JB-PU for importer@patchew.org; Thu, 21 Apr 2022 07:37:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59506) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhUq8-0003DG-S9 for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:19:14 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:42877) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nhUq6-0003Wy-OX for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:19:12 -0400 Received: by mail-wr1-x433.google.com with SMTP id bv16so6182742wrb.9 for ; Thu, 21 Apr 2022 04:19:10 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e4-20020a5d6d04000000b0020a8bbbb72bsm2597694wrq.97.2022.04.21.04.19.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 04:19:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=oHJIYCR/bV2ZQNmrQ3vUauIwQavU4nVbs97MW/KeCJM=; b=KtviYcsrJcSxVXC4hx/ThCiSV3Z/p015qnCJENSUK7dFp9KYYpcn3T2x6bXdrRwayL 5zPVlBKTjPGyxXEeB2fZq7jU5wNrMWgTC7TmgcPolcFZpV3sWxL9hNuuWZIouycYXkpL X7GAzEGPimWpyBUa8XriQZ21OhdCCPAn+46eUsQF/+J2V9DGn6dk/wJJnKrqcJ7SvfXA NtjtheLyShPa4goUcWBWvw+iMe0plYTAMtGzR8okcv5cqtH+bcmMIffdYIgr/HC6dmG1 fEvn/LwbEEek6YG/V115fDWdiNKr81tfCWAIuckPOzewFPYzvin+6CfVl3m0NTKv/cWx dCmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=oHJIYCR/bV2ZQNmrQ3vUauIwQavU4nVbs97MW/KeCJM=; b=rztZoF4LEkeJ8RxGLsSHfuTKh7Vj5EyBU4sriktuZ5CWXKN1icc2ZiBFPJt+OVFAdc uKdmCfbe7I3Im9QWMWFl4QXEKkdynpeS1E0JF7plq7iF9f8eycjDTGmSzSkQmTPePTi+ 93cJQXDdcvyJMaoqQsbh/nVejr4WafNiLZjlU+zc9jCNd6XDQPPxuuzBI7k9bVv0ielY 4QBgn0rDvwaFbpP408/DS8bMdfsxVY7ssNtfeeJLeZ4gMDKTjlKavD3lf6duA6qOS2Y9 wOD+ptPicaqCsZpdMU7P8F9lYePI0UuubNZMcBj9x1hSLAYuf6AS1qSA2NnzXJzou7Zc B8pw== X-Gm-Message-State: AOAM533QyKgWpskyNPcnmgfFtZyKAG5Ewl17prEcDr9nBk9X29LoD0Pa I2Oc5vzzKiPyISeTd/AV1FFvvChoclHqSw== X-Google-Smtp-Source: ABdhPJyYUKirZh7KrOEs+S9bDRvAHV4y+VcVZTyGAFcbJRoIxIWlMue2sK8X3O9qJpcAH8Kt5W79Cg== X-Received: by 2002:adf:f20d:0:b0:207:9a8f:ef9e with SMTP id p13-20020adff20d000000b002079a8fef9emr19543157wro.618.1650539949289; Thu, 21 Apr 2022 04:19:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/31] hw/arm/exynos4210: Fold combiner splits into exynos4210_init_board_irqs() Date: Thu, 21 Apr 2022 12:18:38 +0100 Message-Id: <20220421111846.2011565-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org> References: <20220421111846.2011565-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650541049570100001 Content-Type: text/plain; charset="utf-8" At this point, the function exynos4210_init_board_irqs() splits input IRQ lines to connect them to the input combiner, output combiner and external GIC. The function exynos4210_combiner_get_gpioin() splits some of the combiner input lines further to connect them to multiple different inputs on the combiner. Because (unlike qemu_irq_split()) the TYPE_SPLIT_IRQ device has a configurable number of outputs, we can do all this in one place, by making exynos4210_init_board_irqs() add extra outputs to the splitter device when it must be connected to more than one input on each combiner. We do this with a new data structure, the combinermap, which is an array each of whose elements is a list of the interrupt IDs on the combiner which must be tied together. As we loop through each interrupt ID, if we find that it is the first one in one of these lists, we configure the splitter device with eonugh extra outputs and wire them up to the other interrupt IDs in the list. Conveniently, for all the cases where this is necessary, the lowest-numbered interrupt ID in each group is in the range of the external combiner, so we only need to code for this in the first of the two loops in exynos4210_init_board_irqs(). The old code in exynos4210_combiner_get_gpioin() which is being deleted here had several problems which don't exist in the new code in its handling of the multi-core timer interrupts: (1) the case labels specified bits 4 ... 8, but bit '8' doesn't exist; these should have been 4 ... 7 (2) it used the input irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)] multiple times as the input of several different splitters, which isn't allowed (3) in an apparent cut-and-paste error, the cases for all the multi-core timer inputs used "bit + 4" even though the bit range for the case was (intended to be) 4 ... 7, which meant it was looking at non-existent bits 8 ... 11. None of these exist in the new code. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220404154658.565020-17-peter.maydell@linaro.org --- include/hw/arm/exynos4210.h | 6 +- hw/arm/exynos4210.c | 178 +++++++++++++++++++++++------------- 2 files changed, 119 insertions(+), 65 deletions(-) diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h index 7da3eddea5f..f24617f681d 100644 --- a/include/hw/arm/exynos4210.h +++ b/include/hw/arm/exynos4210.h @@ -74,10 +74,12 @@ =20 /* * We need one splitter for every external combiner input, plus - * one for every non-zero entry in combiner_grp_to_gic_id[]. + * one for every non-zero entry in combiner_grp_to_gic_id[], + * minus one for every external combiner ID in second or later + * places in a combinermap[] line. * We'll assert in exynos4210_init_board_irqs() if this is wrong. */ -#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 54) +#define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 38) =20 typedef struct Exynos4210Irq { qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 39e334e0773..05b28cf5905 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -254,6 +254,76 @@ combiner_grp_to_gic_id[64 - EXYNOS4210_MAX_EXT_COMBINE= R_OUT_IRQ][8] =3D { #define EXYNOS4210_COMBINER_GET_BIT_NUM(irq) \ ((irq) - 8 * EXYNOS4210_COMBINER_GET_GRP_NUM(irq)) =20 +/* + * Some interrupt lines go to multiple combiner inputs. + * This data structure defines those: each array element is + * a list of combiner inputs which are connected together; + * the one with the smallest interrupt ID value must be first. + * As with combiner_grp_to_gic_id[], we rely on (0, 0) not being + * wired to anything so we can use 0 as a terminator. + */ +#define IRQNO(G, B) EXYNOS4210_COMBINER_GET_IRQ_NUM(G, B) +#define IRQNONE 0 + +#define COMBINERMAP_SIZE 16 + +static const int combinermap[COMBINERMAP_SIZE][6] =3D { + /* MDNIE_LCD1 */ + { IRQNO(0, 4), IRQNO(1, 0), IRQNONE }, + { IRQNO(0, 5), IRQNO(1, 1), IRQNONE }, + { IRQNO(0, 6), IRQNO(1, 2), IRQNONE }, + { IRQNO(0, 7), IRQNO(1, 3), IRQNONE }, + /* TMU */ + { IRQNO(2, 4), IRQNO(3, 4), IRQNONE }, + { IRQNO(2, 5), IRQNO(3, 5), IRQNONE }, + { IRQNO(2, 6), IRQNO(3, 6), IRQNONE }, + { IRQNO(2, 7), IRQNO(3, 7), IRQNONE }, + /* LCD1 */ + { IRQNO(11, 4), IRQNO(12, 0), IRQNONE }, + { IRQNO(11, 5), IRQNO(12, 1), IRQNONE }, + { IRQNO(11, 6), IRQNO(12, 2), IRQNONE }, + { IRQNO(11, 7), IRQNO(12, 3), IRQNONE }, + /* Multi-core timer */ + { IRQNO(1, 4), IRQNO(12, 4), IRQNO(35, 4), IRQNO(51, 4), IRQNO(53, 4),= IRQNONE }, + { IRQNO(1, 5), IRQNO(12, 5), IRQNO(35, 5), IRQNO(51, 5), IRQNO(53, 5),= IRQNONE }, + { IRQNO(1, 6), IRQNO(12, 6), IRQNO(35, 6), IRQNO(51, 6), IRQNO(53, 6),= IRQNONE }, + { IRQNO(1, 7), IRQNO(12, 7), IRQNO(35, 7), IRQNO(51, 7), IRQNO(53, 7),= IRQNONE }, +}; + +#undef IRQNO + +static const int *combinermap_entry(int irq) +{ + /* + * If the interrupt number passed in is the first entry in some + * line of the combinermap, return a pointer to that line; + * otherwise return NULL. + */ + int i; + for (i =3D 0; i < COMBINERMAP_SIZE; i++) { + if (combinermap[i][0] =3D=3D irq) { + return combinermap[i]; + } + } + return NULL; +} + +static int mapline_size(const int *mapline) +{ + /* Return number of entries in this mapline in total */ + int i =3D 0; + + if (!mapline) { + /* Not in the map? IRQ goes to exactly one combiner input */ + return 1; + } + while (*mapline !=3D IRQNONE) { + mapline++; + i++; + } + return i; +} + /* * Initialize board IRQs. * These IRQs contain splitted Int/External Combiner and External Gic IRQs. @@ -265,6 +335,8 @@ static void exynos4210_init_board_irqs(Exynos4210State = *s) DeviceState *extgicdev =3D DEVICE(&s->ext_gic); int splitcount =3D 0; DeviceState *splitter; + const int *mapline; + int numlines, splitin, in; =20 for (n =3D 0; n < EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ; n++) { irq_id =3D 0; @@ -277,16 +349,46 @@ static void exynos4210_init_board_irqs(Exynos4210Stat= e *s) irq_id =3D EXT_GIC_ID_MCT_G1; } =20 + if (s->irq_table[n]) { + /* + * This must be some non-first entry in a combinermap line, + * and we've already filled it in. + */ + continue; + } + mapline =3D combinermap_entry(n); + /* + * We need to connect the IRQ to multiple inputs on both combiners + * and possibly also to the external GIC. + */ + numlines =3D 2 * mapline_size(mapline); + if (irq_id) { + numlines++; + } assert(splitcount < EXYNOS4210_NUM_SPLITTERS); splitter =3D DEVICE(&s->splitter[splitcount]); - qdev_prop_set_uint16(splitter, "num-lines", irq_id ? 3 : 2); + qdev_prop_set_uint16(splitter, "num-lines", numlines); qdev_realize(splitter, NULL, &error_abort); splitcount++; - s->irq_table[n] =3D qdev_get_gpio_in(splitter, 0); - qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]); - qdev_connect_gpio_out(splitter, 1, is->ext_combiner_irq[n]); + + in =3D n; + splitin =3D 0; + for (;;) { + s->irq_table[in] =3D qdev_get_gpio_in(splitter, 0); + qdev_connect_gpio_out(splitter, splitin, is->int_combiner_irq[= in]); + qdev_connect_gpio_out(splitter, splitin + 1, is->ext_combiner_= irq[in]); + splitin +=3D 2; + if (!mapline) { + break; + } + mapline++; + in =3D *mapline; + if (in =3D=3D IRQNONE) { + break; + } + } if (irq_id) { - qdev_connect_gpio_out(splitter, 2, + qdev_connect_gpio_out(splitter, splitin, qdev_get_gpio_in(extgicdev, irq_id - 32)= ); } } @@ -297,6 +399,14 @@ static void exynos4210_init_board_irqs(Exynos4210State= *s) irq_id =3D combiner_grp_to_gic_id[grp - EXYNOS4210_MAX_EXT_COMBINER_OUT_IRQ][bit]; =20 + if (s->irq_table[n]) { + /* + * This must be some non-first entry in a combinermap line, + * and we've already filled it in. + */ + continue; + } + if (irq_id) { assert(splitcount < EXYNOS4210_NUM_SPLITTERS); splitter =3D DEVICE(&s->splitter[splitcount]); @@ -337,7 +447,6 @@ static void exynos4210_combiner_get_gpioin(Exynos4210Ir= q *irqs, DeviceState *dev, int ext) { int n; - int bit; int max; qemu_irq *irq; =20 @@ -345,64 +454,7 @@ static void exynos4210_combiner_get_gpioin(Exynos4210I= rq *irqs, EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; irq =3D ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq; =20 - /* - * Some IRQs of Int/External Combiner are going to two Combiners group= s, - * so let split them. - */ for (n =3D 0; n < max; n++) { - - bit =3D EXYNOS4210_COMBINER_GET_BIT_NUM(n); - - switch (n) { - /* MDNIE_LCD1 INTG1 */ - case EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 0) ... - EXYNOS4210_COMBINER_GET_IRQ_NUM(1, 3): - irq[n] =3D qemu_irq_split(qdev_get_gpio_in(dev, n), - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(0, bit + 4)]); - continue; - - /* TMU INTG3 */ - case EXYNOS4210_COMBINER_GET_IRQ_NUM(3, 4): - irq[n] =3D qemu_irq_split(qdev_get_gpio_in(dev, n), - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(2, bit)]); - continue; - - /* LCD1 INTG12 */ - case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 0) ... - EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 3): - irq[n] =3D qemu_irq_split(qdev_get_gpio_in(dev, n), - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(11, bit + 4)]); - continue; - - /* Multi-Core Timer INTG12 */ - case EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 4) ... - EXYNOS4210_COMBINER_GET_IRQ_NUM(12, 8): - irq[n] =3D qemu_irq_split(qdev_get_gpio_in(dev, n), - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); - continue; - - /* Multi-Core Timer INTG35 */ - case EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 4) ... - EXYNOS4210_COMBINER_GET_IRQ_NUM(35, 8): - irq[n] =3D qemu_irq_split(qdev_get_gpio_in(dev, n), - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); - continue; - - /* Multi-Core Timer INTG51 */ - case EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 4) ... - EXYNOS4210_COMBINER_GET_IRQ_NUM(51, 8): - irq[n] =3D qemu_irq_split(qdev_get_gpio_in(dev, n), - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); - continue; - - /* Multi-Core Timer INTG53 */ - case EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 4) ... - EXYNOS4210_COMBINER_GET_IRQ_NUM(53, 8): - irq[n] =3D qemu_irq_split(qdev_get_gpio_in(dev, n), - irq[EXYNOS4210_COMBINER_GET_IRQ_NUM(1, bit + 4)]); - continue; - } - irq[n] =3D qdev_get_gpio_in(dev, n); } } --=20 2.25.1 From nobody Tue May 21 06:35:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650541965; cv=none; d=zohomail.com; s=zohoarc; b=CgBGjZJxKXvKAfKF+N5eHFjIbypoNPvJ5AQdTDW2q9yYX0fIpHd8UyqckW7al4gjcZGgGcz9emtUVXyds60uyz+yAJPcxWV2gi3tXkOXzl9Ce93hv2ppbBQwQRmyhQZp5NsBFKI0N7yYtxXvGmQ/jO8LwwOI0nU8+kN2QsAdq0s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650541965; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=g+Co51E/+7lmbmTDyWaG5WQzn5vB4kGUC/Z7E1cxKEA=; b=fbbfcHIDdGqU1aVPNGZlwc3CifHes7B+fg1+tQxKs8oLA4rTG5WCNKX3jsUhox9dx/CwIYar6VpewqaIbqHokAEbG3Kj6nQ8L3bIss6YlAkCjm9xrTwFd1cJlb5fhpQtLHibvouCYdmcyy8L+WWpkClts5Spax/UNHji1Ey/Ld0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650541965290956.2967871929937; Thu, 21 Apr 2022 04:52:45 -0700 (PDT) Received: from localhost ([::1]:40748 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhVMa-0001NQ-9n for importer@patchew.org; Thu, 21 Apr 2022 07:52:44 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59544) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhUqM-0003Fz-Pl for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:19:28 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:42868) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nhUq8-0003XN-RR for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:19:14 -0400 Received: by mail-wr1-x429.google.com with SMTP id bv16so6182866wrb.9 for ; Thu, 21 Apr 2022 04:19:12 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e4-20020a5d6d04000000b0020a8bbbb72bsm2597694wrq.97.2022.04.21.04.19.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 04:19:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=g+Co51E/+7lmbmTDyWaG5WQzn5vB4kGUC/Z7E1cxKEA=; b=CEIxTB0REDzYgul9ceihtBhXVeRfPk37c/BBdLplsKSp14Edx5ilPcLUzLC8w+O8Ru IE8EdaPwhc6Jk3neEXZCnv1bKrfWkJd0NWjE+5301JiUgrsfJWafyGFNA/UaJhgQqk+Z WAHVeggQCk/QvTQt6Gu9oBnpI0cQZDCViiXHO7Oiymta7IZWcfI5JvBTf3NNSFXmsMFN Xyka+RcPz1b9/KJcAYn4rBG+bxzgG0K+Jvfra0FfpvUipp5bQkeeYVUk9LHN6rhq5aOG 917xYn8lUuBASC1XmFABGouRDuloJ3AOq1oPMTlBaiBOJVskP+rM2l1i1dEBwklauQE8 c7Aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=g+Co51E/+7lmbmTDyWaG5WQzn5vB4kGUC/Z7E1cxKEA=; b=iP6mClSR/D+lKt+9Ld6Uvt8OUBkLoXOpfslwMpJNa4BFk5lclrBsxO63pv7sLBcICH yfw0BE+3xvBvZaHIiZ26Dv1a5jinaBZjDZ0sELE+oUXF4q4hc5jh4j1qL92v3sVyqKzZ zG+OXcqp/N2TYnoG/TYYYnI7qJCpBLutogzDyMJx0GRopC7t2aavmwZBN4YuWFDIct4K +wfE7LaM52evFPcCLcUJWHu0cbva3BJIDhm+RbEBRtMHZa7vLoUBZRocbnW/UaNg8bHk q0UVeJVRWY4cC6hFrc/G4W2OQL3+U0VDaj95SOVOIySqudbr7hUolp6G0gE7naRSnWON 3gBg== X-Gm-Message-State: AOAM531YsQe7n9K+2hsr9OoG//6+LJ4OkAiIvUw2cLAxl3cPEREdbI8/ Aqkl4wADgOLlF+BUhzWamUieuAXWzgRdBA== X-Google-Smtp-Source: ABdhPJxrtj+kvksjw4+Kp5NkWYpdZqtNeFty9/FrK14rnGQFGn1nKLjsEA6wpjkUInNAhl3X0/xvsg== X-Received: by 2002:a05:6000:2cb:b0:20a:88c4:ec9f with SMTP id o11-20020a05600002cb00b0020a88c4ec9fmr18060482wry.43.1650539951597; Thu, 21 Apr 2022 04:19:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/31] hw/arm/exynos4210: Put combiners into state struct Date: Thu, 21 Apr 2022 12:18:39 +0100 Message-Id: <20220421111846.2011565-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org> References: <20220421111846.2011565-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650541966098100001 Content-Type: text/plain; charset="utf-8" Switch the creation of the combiner devices to the new-style "embedded in state struct" approach, so we can easily refer to the object elsewhere during realize. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220404154658.565020-18-peter.maydell@linaro.org --- include/hw/arm/exynos4210.h | 3 ++ include/hw/intc/exynos4210_combiner.h | 57 +++++++++++++++++++++++++++ hw/arm/exynos4210.c | 20 +++++----- hw/intc/exynos4210_combiner.c | 31 +-------------- 4 files changed, 72 insertions(+), 39 deletions(-) create mode 100644 include/hw/intc/exynos4210_combiner.h diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h index f24617f681d..d38be8767b3 100644 --- a/include/hw/arm/exynos4210.h +++ b/include/hw/arm/exynos4210.h @@ -28,6 +28,7 @@ #include "hw/sysbus.h" #include "hw/cpu/a9mpcore.h" #include "hw/intc/exynos4210_gic.h" +#include "hw/intc/exynos4210_combiner.h" #include "hw/core/split-irq.h" #include "target/arm/cpu-qom.h" #include "qom/object.h" @@ -105,6 +106,8 @@ struct Exynos4210State { qemu_or_irq cpu_irq_orgate[EXYNOS4210_NCPUS]; A9MPPrivState a9mpcore; Exynos4210GicState ext_gic; + Exynos4210CombinerState int_combiner; + Exynos4210CombinerState ext_combiner; SplitIRQ splitter[EXYNOS4210_NUM_SPLITTERS]; }; =20 diff --git a/include/hw/intc/exynos4210_combiner.h b/include/hw/intc/exynos= 4210_combiner.h new file mode 100644 index 00000000000..429844fed41 --- /dev/null +++ b/include/hw/intc/exynos4210_combiner.h @@ -0,0 +1,57 @@ +/* + * Samsung exynos4210 Interrupt Combiner + * + * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd. + * All rights reserved. + * + * Evgeny Voevodin + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. + * See the GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see . + */ + +#ifndef HW_INTC_EXYNOS4210_COMBINER +#define HW_INTC_EXYNOS4210_COMBINER + +#include "hw/sysbus.h" + +/* + * State for each output signal of internal combiner + */ +typedef struct CombinerGroupState { + uint8_t src_mask; /* 1 - source enabled, 0 - disabled */ + uint8_t src_pending; /* Pending source interrupts before maskin= g */ +} CombinerGroupState; + +#define TYPE_EXYNOS4210_COMBINER "exynos4210.combiner" +OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210CombinerState, EXYNOS4210_COMBINER) + +/* Number of groups and total number of interrupts for the internal combin= er */ +#define IIC_NGRP 64 +#define IIC_NIRQ (IIC_NGRP * 8) +#define IIC_REGSET_SIZE 0x41 + +struct Exynos4210CombinerState { + SysBusDevice parent_obj; + + MemoryRegion iomem; + + struct CombinerGroupState group[IIC_NGRP]; + uint32_t reg_set[IIC_REGSET_SIZE]; + uint32_t icipsr[2]; + uint32_t external; /* 1 means that this combiner is external = */ + + qemu_irq output_irq[IIC_NGRP]; +}; + +#endif diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 05b28cf5905..27c6ab27123 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -624,25 +624,23 @@ static void exynos4210_realize(DeviceState *socdev, E= rror **errp) } =20 /* Internal Interrupt Combiner */ - dev =3D qdev_new("exynos4210.combiner"); - busdev =3D SYS_BUS_DEVICE(dev); - sysbus_realize_and_unref(busdev, &error_fatal); + busdev =3D SYS_BUS_DEVICE(&s->int_combiner); + sysbus_realize(busdev, &error_fatal); for (n =3D 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->a9mpcore), n)); } - exynos4210_combiner_get_gpioin(&s->irqs, dev, 0); + exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->int_combiner), 0); sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); =20 /* External Interrupt Combiner */ - dev =3D qdev_new("exynos4210.combiner"); - qdev_prop_set_uint32(dev, "external", 1); - busdev =3D SYS_BUS_DEVICE(dev); - sysbus_realize_and_unref(busdev, &error_fatal); + qdev_prop_set_uint32(DEVICE(&s->ext_combiner), "external", 1); + busdev =3D SYS_BUS_DEVICE(&s->ext_combiner); + sysbus_realize(busdev, &error_fatal); for (n =3D 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic)= , n)); } - exynos4210_combiner_get_gpioin(&s->irqs, dev, 1); + exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->ext_combiner), 1); sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); =20 /* Initialize board IRQs. */ @@ -844,6 +842,10 @@ static void exynos4210_init(Object *obj) =20 object_initialize_child(obj, "a9mpcore", &s->a9mpcore, TYPE_A9MPCORE_P= RIV); object_initialize_child(obj, "ext-gic", &s->ext_gic, TYPE_EXYNOS4210_G= IC); + object_initialize_child(obj, "int-combiner", &s->int_combiner, + TYPE_EXYNOS4210_COMBINER); + object_initialize_child(obj, "ext-combiner", &s->ext_combiner, + TYPE_EXYNOS4210_COMBINER); } =20 static void exynos4210_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/exynos4210_combiner.c b/hw/intc/exynos4210_combiner.c index 83b42b9bce1..a289510bdb8 100644 --- a/hw/intc/exynos4210_combiner.c +++ b/hw/intc/exynos4210_combiner.c @@ -31,7 +31,7 @@ #include "hw/sysbus.h" #include "migration/vmstate.h" #include "qemu/module.h" - +#include "hw/intc/exynos4210_combiner.h" #include "hw/arm/exynos4210.h" #include "hw/hw.h" #include "hw/irq.h" @@ -48,36 +48,7 @@ #define DPRINTF(fmt, ...) do {} while (0) #endif =20 -#define IIC_NGRP 64 /* Internal Interrupt Combiner - Groups number */ -#define IIC_NIRQ (IIC_NGRP * 8)/* Internal Interrupt Combiner - Interrupts number */ #define IIC_REGION_SIZE 0x108 /* Size of memory mapped region */ -#define IIC_REGSET_SIZE 0x41 - -/* - * State for each output signal of internal combiner - */ -typedef struct CombinerGroupState { - uint8_t src_mask; /* 1 - source enabled, 0 - disabled */ - uint8_t src_pending; /* Pending source interrupts before maskin= g */ -} CombinerGroupState; - -#define TYPE_EXYNOS4210_COMBINER "exynos4210.combiner" -OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210CombinerState, EXYNOS4210_COMBINER) - -struct Exynos4210CombinerState { - SysBusDevice parent_obj; - - MemoryRegion iomem; - - struct CombinerGroupState group[IIC_NGRP]; - uint32_t reg_set[IIC_REGSET_SIZE]; - uint32_t icipsr[2]; - uint32_t external; /* 1 means that this combiner is external = */ - - qemu_irq output_irq[IIC_NGRP]; -}; =20 static const VMStateDescription vmstate_exynos4210_combiner_group_state = =3D { .name =3D "exynos4210.combiner.groupstate", --=20 2.25.1 From nobody Tue May 21 06:35:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e4-20020a5d6d04000000b0020a8bbbb72bsm2597694wrq.97.2022.04.21.04.19.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 04:19:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=yNOaXUrJUAeJ+AixS5fcfCSvW1JdJPD9+7LfvbRwH6I=; b=aA/uLGOQsns/PX4347e8rd7Y08PUpzNqA8Pi3t/J/s4riXwYLlqIOfjzXRvlY6+35u TyuIwZiAliJ9Yd0gD53ytcH/BV9jyLnOkduKIZDxk9mdCPtIHkldXOtw/ppoI0ScpgnA yubLZf2oOlZqXVaiQ1b7VCt1uMGXUuoNK+36oD/sTgktbl3edCCqJ8Qj8V5/rPkKVAgc j7jRRsZXEZZ64mXRtJ8kGubKALqOhj8dL8vqoTavfbLCFgixRn7nONXMXoQD0BYbp0Ix tWSON7WbvSluiARaih7Ugy8DEwb6K2wcf+baz/vNO2JQLeNs0J0rGDb8HEZQMYf8pI2u aAIw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yNOaXUrJUAeJ+AixS5fcfCSvW1JdJPD9+7LfvbRwH6I=; b=4GozdLVR3xqNzfl3yiLAtKUeKKfOai9n526I2PDSjm6jVpQUD8oq8gTbdk89yj28gj tacXDzBWQSXiHPVuZI8Z0YXmmLOIwC9Xt4l43oblS45wwVlXUotxyxK/WKEKuEl6B87L 3E+Q1APV6SrF57pdNBLtEoAJj5+PU0++2rJUXjuZJg3ma0SVavuCnOLMM2EsC3v3p+WK OddKPICplMb+lqU7n9R/e52asXYsJIBOrVYF6D9mrxvETrX6L8W3VS/7e0Dm1ja7h/XS oAV8EG0vTPSY/sB4espYJ4oDqRm7TpSyp3iOqHLxnkzE26iXnbzfRAIER6nlbOzbQ9Bv d7yw== X-Gm-Message-State: AOAM530NKWuG7eyULG2z6+CbYSPApjHFZ3DqAorvi+CIhoXZ15oIZVxl dQ76mvaQ+SE5KJ8qbM9w6WQR+zdcgOPh1g== X-Google-Smtp-Source: ABdhPJxn2oZX9qFgaE+Ck6PCYAcg18FFsCknXiZN+Rb5yZAE/Zdhfj18jEAeSy1YCa+nEb+0yXnFqg== X-Received: by 2002:a05:6000:156a:b0:20a:9c1b:6b1b with SMTP id 10-20020a056000156a00b0020a9c1b6b1bmr13222289wrz.683.1650539952579; Thu, 21 Apr 2022 04:19:12 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/31] hw/arm/exynos4210: Drop Exynos4210Irq struct Date: Thu, 21 Apr 2022 12:18:40 +0100 Message-Id: <20220421111846.2011565-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org> References: <20220421111846.2011565-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42b; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650541782834100001 Content-Type: text/plain; charset="utf-8" The only time we use the int_combiner_irq[] and ext_combiner_irq[] arrays in the Exynos4210Irq struct is during realize of the SoC -- we initialize them with the input IRQs of the combiner devices, and then connect those to outputs of other devices in exynos4210_init_board_irqs(). Now that the combiner objects are easily accessible as s->int_combiner and s->ext_combiner we can make the connections directly from one device to the other without going via these arrays. Since these are the only two remaining elements of Exynos4210Irq, we can remove that struct entirely. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson Message-id: 20220404154658.565020-19-peter.maydell@linaro.org --- include/hw/arm/exynos4210.h | 6 ------ hw/arm/exynos4210.c | 34 ++++++++-------------------------- 2 files changed, 8 insertions(+), 32 deletions(-) diff --git a/include/hw/arm/exynos4210.h b/include/hw/arm/exynos4210.h index d38be8767b3..97353f1c02f 100644 --- a/include/hw/arm/exynos4210.h +++ b/include/hw/arm/exynos4210.h @@ -82,17 +82,11 @@ */ #define EXYNOS4210_NUM_SPLITTERS (EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ + 38) =20 -typedef struct Exynos4210Irq { - qemu_irq int_combiner_irq[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; - qemu_irq ext_combiner_irq[EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ]; -} Exynos4210Irq; - struct Exynos4210State { /*< private >*/ SysBusDevice parent_obj; /*< public >*/ ARMCPU *cpu[EXYNOS4210_NCPUS]; - Exynos4210Irq irqs; qemu_irq irq_table[EXYNOS4210_MAX_INT_COMBINER_IN_IRQ]; =20 MemoryRegion chipid_mem; diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index 27c6ab27123..8dafa2215b6 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -331,8 +331,9 @@ static int mapline_size(const int *mapline) static void exynos4210_init_board_irqs(Exynos4210State *s) { uint32_t grp, bit, irq_id, n; - Exynos4210Irq *is =3D &s->irqs; DeviceState *extgicdev =3D DEVICE(&s->ext_gic); + DeviceState *intcdev =3D DEVICE(&s->int_combiner); + DeviceState *extcdev =3D DEVICE(&s->ext_combiner); int splitcount =3D 0; DeviceState *splitter; const int *mapline; @@ -375,8 +376,10 @@ static void exynos4210_init_board_irqs(Exynos4210State= *s) splitin =3D 0; for (;;) { s->irq_table[in] =3D qdev_get_gpio_in(splitter, 0); - qdev_connect_gpio_out(splitter, splitin, is->int_combiner_irq[= in]); - qdev_connect_gpio_out(splitter, splitin + 1, is->ext_combiner_= irq[in]); + qdev_connect_gpio_out(splitter, splitin, + qdev_get_gpio_in(intcdev, in)); + qdev_connect_gpio_out(splitter, splitin + 1, + qdev_get_gpio_in(extcdev, in)); splitin +=3D 2; if (!mapline) { break; @@ -414,11 +417,11 @@ static void exynos4210_init_board_irqs(Exynos4210Stat= e *s) qdev_realize(splitter, NULL, &error_abort); splitcount++; s->irq_table[n] =3D qdev_get_gpio_in(splitter, 0); - qdev_connect_gpio_out(splitter, 0, is->int_combiner_irq[n]); + qdev_connect_gpio_out(splitter, 0, qdev_get_gpio_in(intcdev, n= )); qdev_connect_gpio_out(splitter, 1, qdev_get_gpio_in(extgicdev, irq_id - 32)= ); } else { - s->irq_table[n] =3D is->int_combiner_irq[n]; + s->irq_table[n] =3D qdev_get_gpio_in(intcdev, n); } } /* @@ -440,25 +443,6 @@ uint32_t exynos4210_get_irq(uint32_t grp, uint32_t bit) return EXYNOS4210_COMBINER_GET_IRQ_NUM(grp, bit); } =20 -/* - * Get Combiner input GPIO into irqs structure - */ -static void exynos4210_combiner_get_gpioin(Exynos4210Irq *irqs, - DeviceState *dev, int ext) -{ - int n; - int max; - qemu_irq *irq; - - max =3D ext ? EXYNOS4210_MAX_EXT_COMBINER_IN_IRQ : - EXYNOS4210_MAX_INT_COMBINER_IN_IRQ; - irq =3D ext ? irqs->ext_combiner_irq : irqs->int_combiner_irq; - - for (n =3D 0; n < max; n++) { - irq[n] =3D qdev_get_gpio_in(dev, n); - } -} - static uint8_t chipid_and_omr[] =3D { 0x11, 0x02, 0x21, 0x43, 0x09, 0x00, 0x00, 0x00 }; =20 @@ -630,7 +614,6 @@ static void exynos4210_realize(DeviceState *socdev, Err= or **errp) sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->a9mpcore), n)); } - exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->int_combiner), 0); sysbus_mmio_map(busdev, 0, EXYNOS4210_INT_COMBINER_BASE_ADDR); =20 /* External Interrupt Combiner */ @@ -640,7 +623,6 @@ static void exynos4210_realize(DeviceState *socdev, Err= or **errp) for (n =3D 0; n < EXYNOS4210_MAX_INT_COMBINER_OUT_IRQ; n++) { sysbus_connect_irq(busdev, n, qdev_get_gpio_in(DEVICE(&s->ext_gic)= , n)); } - exynos4210_combiner_get_gpioin(&s->irqs, DEVICE(&s->ext_combiner), 1); sysbus_mmio_map(busdev, 0, EXYNOS4210_EXT_COMBINER_BASE_ADDR); =20 /* Initialize board IRQs. */ --=20 2.25.1 From nobody Tue May 21 06:35:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650542267; cv=none; d=zohomail.com; s=zohoarc; b=cQADVISDgM7mxh3+xraCKutr1UOCsO13my+cLrR+vyRxOD24OUPaTV5uLUDpTkoE1QlcP/Y/9DpPRFsn7lkd3QcFb5TgTPMLcEAWtUONFzu4ooI9ARXkvaFJgreosAsuLBQQjOgFhQf6mGohmdtZrBHjGuSRBSoirAWBOqA75yM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650542267; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=c+3p6Fbz730AqqAeRKPa+9fqaNknD7WBGqtKg8sQzjk=; b=Q5BDNtiJ5+rxPeyUZNBx03tBoCa9DeMGPntZd9S+ex5KViW6Z8/QntLTj5qQKeBnBsKYo2yGiHmTov583Kp4JY5Jq6+GTamI054529PfxE9kUgwzOViyE2erCFzRQjrQ1QpeQxbpsVk7CjHbVacdDFasaQkiHZK2G4YckUp2rx8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16505422676549.801327131081052; Thu, 21 Apr 2022 04:57:47 -0700 (PDT) Received: from localhost ([::1]:49924 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhVRS-0001gK-5y for importer@patchew.org; Thu, 21 Apr 2022 07:57:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59718) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhUqX-0003Nc-AO for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:19:37 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:36824) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nhUqS-0003Xm-US for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:19:35 -0400 Received: by mail-wm1-x32c.google.com with SMTP id u17-20020a05600c211100b0038eaf4cdaaeso5654523wml.1 for ; Thu, 21 Apr 2022 04:19:14 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e4-20020a5d6d04000000b0020a8bbbb72bsm2597694wrq.97.2022.04.21.04.19.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 04:19:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=c+3p6Fbz730AqqAeRKPa+9fqaNknD7WBGqtKg8sQzjk=; b=dAll3k0YjZvgD8NsoQayAtE85398/oh29v8IvYyQzzlNSjJdFkP0mhcWD35FAHnUpN Oko1uVeU6Ug8Xf76FqYaIqrVHbF5ACH6kY2VRcGk5Ha/BeCE33xN/nVygL6L5SQdkc0o tNdCAeeGua3R6JUn5KqLDhcEb1FIpFsXLvE/DCw6/GKpb3NqPCGhEtAHl69XFHzPYUHG 5cVXVBsR+NFxJkjUF5x0GWLj4G5otN1AnYxv6UJN/ytlCQYZcE5HY+XTkSJq3bM6jcsH c1mf4OSCFVMGcySBREJuCOx3PR6J7tD1z64Hq8pgszQuHR/p1JtuZvZJ1oVCyFWtEuHB E5gA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=c+3p6Fbz730AqqAeRKPa+9fqaNknD7WBGqtKg8sQzjk=; b=vGaIG1TXwRqrFeDojoDUTF/91/lbQO4QXut0FJK4totP7mBXtgcgdCeB0JHh5d+ux5 HoFYwqLYGpX9QE78BBeQG0UBmwTi+SLhiAhjNWbbGjx8hp7ht5BivlzcEx/IioQ1KT1Y /gi+k2tJCyRpO9cUUNAwIyID2iM6e6Tt9el73qKHuRxLBqIqh0axFOzAYfLMkKLJfGpr 214sDGvJ7fIrEbmDkIUbkqlkAZkMcvo24b9vWEpQpUeinmcR+6xN1i1zKGSk2Bk/1F57 HHSqkLG6kcJcVaxST20xRaKMquqW94kVnu16aLnF4016GH71FQUn/N0UTEW8U6S6u4/O Nqxg== X-Gm-Message-State: AOAM532yxzRhSXwl5iSKchBkWBuFKfDa4KG2V6rbDtG5klUhbzkQPoUD NnOl8HDQwo6R8DzF5zDgvldoik3peQXE6g== X-Google-Smtp-Source: ABdhPJwpuJkmU/Qzf9XBrNSuRF2abl2Y8DnRAEIJtXRZN3cVhIeRmo21WsIx26/8Uf0MRS++iY5ixA== X-Received: by 2002:a7b:cb0d:0:b0:38e:aaf3:b08f with SMTP id u13-20020a7bcb0d000000b0038eaaf3b08fmr8135396wmj.12.1650539953371; Thu, 21 Apr 2022 04:19:13 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/31] hw/arm/realview: replace 'qemu_split_irq' with 'TYPE_SPLIT_IRQ' Date: Thu, 21 Apr 2022 12:18:41 +0100 Message-Id: <20220421111846.2011565-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org> References: <20220421111846.2011565-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650542268043100001 Content-Type: text/plain; charset="utf-8" From: Zongyuan Li Signed-off-by: Zongyuan Li Reviewed-by: Peter Maydell Message-id: 20220324181557.203805-2-zongyuan.li@smartx.com Signed-off-by: Peter Maydell --- hw/arm/realview.c | 33 ++++++++++++++++++++++++--------- 1 file changed, 24 insertions(+), 9 deletions(-) diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 7b424e94a5f..d2dc8a89525 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -13,9 +13,11 @@ #include "hw/sysbus.h" #include "hw/arm/boot.h" #include "hw/arm/primecell.h" +#include "hw/core/split-irq.h" #include "hw/net/lan9118.h" #include "hw/net/smc91c111.h" #include "hw/pci/pci.h" +#include "hw/qdev-core.h" #include "net/net.h" #include "sysemu/sysemu.h" #include "hw/boards.h" @@ -53,6 +55,20 @@ static const int realview_board_id[] =3D { 0x76d }; =20 +static void split_irq_from_named(DeviceState *src, const char* outname, + qemu_irq out1, qemu_irq out2) { + DeviceState *splitter =3D qdev_new(TYPE_SPLIT_IRQ); + + qdev_prop_set_uint32(splitter, "num-lines", 2); + + qdev_realize_and_unref(splitter, NULL, &error_fatal); + + qdev_connect_gpio_out(splitter, 0, out1); + qdev_connect_gpio_out(splitter, 1, out2); + qdev_connect_gpio_out_named(src, outname, 0, + qdev_get_gpio_in(splitter, 0)); +} + static void realview_init(MachineState *machine, enum realview_board_type board_type) { @@ -66,7 +82,6 @@ static void realview_init(MachineState *machine, DeviceState *dev, *sysctl, *gpio2, *pl041; SysBusDevice *busdev; qemu_irq pic[64]; - qemu_irq mmc_irq[2]; PCIBus *pci_bus =3D NULL; NICInfo *nd; DriveInfo *dinfo; @@ -229,14 +244,14 @@ static void realview_init(MachineState *machine, * and the PL061 has them the other way about. Also the card * detect line is inverted. */ - mmc_irq[0] =3D qemu_irq_split( - qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT), - qdev_get_gpio_in(gpio2, 1)); - mmc_irq[1] =3D qemu_irq_split( - qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN), - qemu_irq_invert(qdev_get_gpio_in(gpio2, 0))); - qdev_connect_gpio_out_named(dev, "card-read-only", 0, mmc_irq[0]); - qdev_connect_gpio_out_named(dev, "card-inserted", 0, mmc_irq[1]); + split_irq_from_named(dev, "card-read-only", + qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_WPROT), + qdev_get_gpio_in(gpio2, 1)); + + split_irq_from_named(dev, "card-inserted", + qdev_get_gpio_in(sysctl, ARM_SYSCTL_GPIO_MMC_CARDIN), + qemu_irq_invert(qdev_get_gpio_in(gpio2, 0))); + dinfo =3D drive_get(IF_SD, 0, 0); if (dinfo) { DeviceState *card; --=20 2.25.1 From nobody Tue May 21 06:35:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650541395; cv=none; d=zohomail.com; s=zohoarc; b=TlZZaANv52BizNfQ1RxJzXInsO6iwJERtrtA+guFTf7v+fQOfbXQtIauGO8ExAbA5vD1WMfMV9fajgAPycBscGf430p5LttlDhL8y1a7jXoUT0UjkLqrpIN5DPKtPKAU5WHKiy3nzQjNUeRzeHHicr6ZDEjrHDivQxmovujwFtM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650541395; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=uM2Z8pOmM345Tmz6p1sACjfjRoZTp+FYU6GMrrVCQUQ=; b=HjkASgHgPuzroZlEmhYCLNq7VUuv8ORhb2T3hmcfK0cXBoWF4NxnIKlwExcjzhnBlpKzBKI8Oci9NHBobVvhI2SD92hmf6S18PMOwe2XrFYwafytxptJ+l0PKzk++dfNCvy09zknaym635VA4E5uP0YzKPHM/KaYjGnNv+pnM34= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650541395276531.4972997057848; Thu, 21 Apr 2022 04:43:15 -0700 (PDT) Received: from localhost ([::1]:49210 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhVDM-0004Bp-Lo for importer@patchew.org; Thu, 21 Apr 2022 07:43:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59674) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhUqU-0003MM-Ik for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:19:35 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:46608) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nhUqR-0003Xx-Ps for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:19:34 -0400 Received: by mail-wr1-x42a.google.com with SMTP id h25so177568wrc.13 for ; Thu, 21 Apr 2022 04:19:14 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e4-20020a5d6d04000000b0020a8bbbb72bsm2597694wrq.97.2022.04.21.04.19.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 04:19:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=uM2Z8pOmM345Tmz6p1sACjfjRoZTp+FYU6GMrrVCQUQ=; b=HHP4jVN51SEgdlWe4LzqFH5voCB/4YczYRRrdxwYWYgCT6M5jvbyi9c/KfFDNOUnnT vzkVdOX65/0Jyv3u2D2uEujgNdJGqgQIWG2YsHc6G6vCiWhk1BbMLKkD6e43Gd7pqAyH JKPZKFRFRE6SWP6uqm2vyQm4MJqZpe0toM3B/SnCVutKcbmif3LTooz8TYYyZyL2n9Fn 0MxAJxUwarv8Q6PJptvD1VNxiiyBozdsNS8RVKbaNVQSM+eVM5MJJVmmPUqlceBppmOa Q5XrV9pAAVdu9+sas4aDVhCu5p569eXoTdfByLh9r17RtqgSb1k1sVY6nStzS2Eq0ty9 bFnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650541396788100001 Content-Type: text/plain; charset="utf-8" From: Zongyuan Li Signed-off-by: Zongyuan Li Reviewed-by: Peter Maydell Message-id: 20220324181557.203805-3-zongyuan.li@smartx.com Signed-off-by: Peter Maydell --- hw/arm/stellaris.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index b6c8a5d6098..12c673c9172 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -9,6 +9,7 @@ =20 #include "qemu/osdep.h" #include "qapi/error.h" +#include "hw/core/split-irq.h" #include "hw/sysbus.h" #include "hw/sd/sd.h" #include "hw/ssi/ssi.h" @@ -1160,6 +1161,7 @@ static void stellaris_init(MachineState *ms, stellari= s_board_info *board) DeviceState *ssddev; DriveInfo *dinfo; DeviceState *carddev; + DeviceState *gpio_d_splitter; BlockBackend *blk; =20 /* @@ -1237,9 +1239,18 @@ static void stellaris_init(MachineState *ms, stellar= is_board_info *board) &error_fatal); =20 ssddev =3D ssi_create_peripheral(bus, "ssd0323"); - gpio_out[GPIO_D][0] =3D qemu_irq_split( - qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0), + + gpio_d_splitter =3D qdev_new(TYPE_SPLIT_IRQ); + qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2); + qdev_realize_and_unref(gpio_d_splitter, NULL, &error_fatal); + qdev_connect_gpio_out( + gpio_d_splitter, 0, + qdev_get_gpio_in_named(sddev, SSI_GPIO_CS, 0)); + qdev_connect_gpio_out( + gpio_d_splitter, 1, qdev_get_gpio_in_named(ssddev, SSI_GPIO_CS, 0)); + gpio_out[GPIO_D][0] =3D qdev_get_gpio_in(gpio_d_splitter, 0); + gpio_out[GPIO_C][7] =3D qdev_get_gpio_in(ssddev, 0); =20 /* Make sure the select pin is high. */ --=20 2.25.1 From nobody Tue May 21 06:35:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e4-20020a5d6d04000000b0020a8bbbb72bsm2597694wrq.97.2022.04.21.04.19.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 04:19:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=dDB/DivYt5DY6348otTzGl2ix/NfxmzFGVdHPWkVBdI=; b=WBgqe8q/1zdY+mVF4a7rEp1dSPgWyTIWKfJ94Ma58bP95zIvbGxEHclaPsq5S+5ru+ zvnrIbANRoWWYTo2YNq/Px4KX04dRU63qs/v64nC2+rP51HNLfmugyDZg+voTkI4/7Mg nhexUze/u6aJr2A38yld+qYoIi3OQ3XuWjBUOLOnoC3BrHobsn9Mofm8yH06A8Q6V3Nl 4EIu6aVK/ixlDrgTDID2ozy3Ed+G3we1YC5Gp9B3Kywd9J+IWM9t3ZypuwsKT7Rc7F6u R83uCfjScjPkmqI8cL7/stkg95ztCAef84spGW19nP9tIVPi0s3SYBSAmU8efnxpQNhl DXtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dDB/DivYt5DY6348otTzGl2ix/NfxmzFGVdHPWkVBdI=; b=nEMPNqGFcRSZ4z1UNzFYlLBNnEHAHqBRInPKmq2p9q3PKRD6HELl68NdGiNRW1+Ghw WpFWWYYqvPB+Lj8Lw/2ihs92U710mL1SbZTYrXco+6+1lIwbhzgwrsEDRWAi6TAvZI22 3ykml7B6ntLHKqSva5JYP3b0JxfzEW0Yyx8B/cXTdGB6rRX2rbpW4e4TQsQ9jAjKk1LM IkL2jwGJnhvYj/XZUWIaPydQwxuu5ExGFuzt12M9/Rz2YYbrK2+8LUVGd/z0Gb2tg6sZ eP7xz+d3GFXSXSn+zA4Mxo6kqDZdTZSWpisqSnT+YOi5qdIwel19TQ09ekDUA81ZAAHf M8wA== X-Gm-Message-State: AOAM530XPyUcvV8Ke/GgIVSwADO9G36tqrcTn45vyfMzlEhhchtraTT4 cTD5SFkz6onVfZJOgB5s805d7L0Pc8M+ZA== X-Google-Smtp-Source: ABdhPJxBxxjYQPpAG7pfaMgzw157/giI84DMTD6e1YAO62pVD6+Pq0/5jkOBE+HrfaMU70vfq0wKzg== X-Received: by 2002:a05:6000:2ac:b0:20a:77c1:c64f with SMTP id l12-20020a05600002ac00b0020a77c1c64fmr18914416wry.588.1650539955088; Thu, 21 Apr 2022 04:19:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/31] hw/core/irq: remove unused 'qemu_irq_split' function Date: Thu, 21 Apr 2022 12:18:43 +0100 Message-Id: <20220421111846.2011565-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org> References: <20220421111846.2011565-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650541982111100001 Content-Type: text/plain; charset="utf-8" From: Zongyuan Li Signed-off-by: Zongyuan Li Reviewed-by: Peter Maydell Message-id: 20220324181557.203805-5-zongyuan.li@smartx.com Resolves: https://gitlab.com/qemu-project/qemu/-/issues/811 Signed-off-by: Peter Maydell --- include/hw/irq.h | 5 ----- hw/core/irq.c | 15 --------------- 2 files changed, 20 deletions(-) diff --git a/include/hw/irq.h b/include/hw/irq.h index dc7abf199e3..645b73d2512 100644 --- a/include/hw/irq.h +++ b/include/hw/irq.h @@ -46,11 +46,6 @@ void qemu_free_irq(qemu_irq irq); /* Returns a new IRQ with opposite polarity. */ qemu_irq qemu_irq_invert(qemu_irq irq); =20 -/* Returns a new IRQ which feeds into both the passed IRQs. - * It's probably better to use the TYPE_SPLIT_IRQ device instead. - */ -qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2); - /* For internal use in qtest. Similar to qemu_irq_split, but operating on an existing vector of qemu_irq. */ void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, in= t n); diff --git a/hw/core/irq.c b/hw/core/irq.c index 741219277b1..3623f711fe6 100644 --- a/hw/core/irq.c +++ b/hw/core/irq.c @@ -106,21 +106,6 @@ qemu_irq qemu_irq_invert(qemu_irq irq) return qemu_allocate_irq(qemu_notirq, irq, 0); } =20 -static void qemu_splitirq(void *opaque, int line, int level) -{ - struct IRQState **irq =3D opaque; - irq[0]->handler(irq[0]->opaque, irq[0]->n, level); - irq[1]->handler(irq[1]->opaque, irq[1]->n, level); -} - -qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2) -{ - qemu_irq *s =3D g_new0(qemu_irq, 2); - s[0] =3D irq1; - s[1] =3D irq2; - return qemu_allocate_irq(qemu_splitirq, s, 0); -} - void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, in= t n) { int i; --=20 2.25.1 From nobody Tue May 21 06:35:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650541774; cv=none; d=zohomail.com; s=zohoarc; b=Ukrdnifv+si5KGppQFR0Z1ZbsrYQXh3HSftRJyL5ZWhsFWibdWxvvxYjXR7nZ2ap45OxuFkZA7TYaY1ACqsu8rOqzb382f1Wt8jvX7KEHmI2Kd8Bo/W21Tm/XXyIwTjN+XGk4CNGciAHuuPF6hrhvVrbqBwf4F9lW3kvo2T20ro= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650541774; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=iC1dx7osygPCKxzESmzHpFu3XuxeglPRcqZ1T2HastM=; b=MQX06aW+Oflc3iVLf8bmFDyV70/NhpFhGflpWbN1xj9T0QxLutP2Tu+ayXyuT3B0GC+EYdNG9kxgfbnxkQn6tgttfLfyh/OoVavEc8B3WdgcfuYtzjCxshRn0UQBl2GRhNVaViunfkzmUoKzZgi1q4rISSGWqJtxIGr+nINcUMs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650541774258425.2708305435392; Thu, 21 Apr 2022 04:49:34 -0700 (PDT) Received: from localhost ([::1]:60380 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhVJV-0003tk-7a for importer@patchew.org; Thu, 21 Apr 2022 07:49:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59562) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhUqR-0003Gm-QY for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:19:31 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:43848) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nhUqM-0003YY-9z for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:19:27 -0400 Received: by mail-wr1-x431.google.com with SMTP id g18so6191583wrb.10 for ; Thu, 21 Apr 2022 04:19:17 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e4-20020a5d6d04000000b0020a8bbbb72bsm2597694wrq.97.2022.04.21.04.19.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 04:19:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=iC1dx7osygPCKxzESmzHpFu3XuxeglPRcqZ1T2HastM=; b=KO5f4YOle1iTvySe8e1oM8XoLsD3opyfMk7EHr9qLoXEljVzTy9UCGkrsm67mujFSE yFV3ubjfceRnCsm2Xh9B8zymzZHonJcizS144dnoSMjI1gp/sQC3IsKo83zzWHRm8K6i MueX/HLArfBIX3LRREDodrqrEyKRYtYn7tsGfGv1GTkPf32zo4xVR6Lwk0+Dm043FOW6 DJW3jP1qUCSmJtvo2W3c1X1AQVkih8yAUiksLEiUYKnc+7cTgujnqFpSqa08O2pn5JXC DxxXymm/QBJd0V9lTHepTyTrLPWCzqmjKAH4C7uB71Eu7Sb/NSsthHLAIzgfJ8R9yDXH KhQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iC1dx7osygPCKxzESmzHpFu3XuxeglPRcqZ1T2HastM=; b=cOCXQFyT06BSpmls5obUacojczcIyHw8W3Oi6uuEuKeBncKg7y4GJFShcgkXtHP+o3 yTUt45v3kJt1y5vgmrI+N7/Vo6jS1gw3jqXPAs91RzliloqOwMrkaxVVKXdPKpSWEKqd iYk4gBayl1DpBYjHc5PfERcvJvg3xve4+ITIfKXwZy3T474B0C9z4qpQQQHqBdVAffkq 39VTib0KaFJ1XYxt/mVvaAXh/u8TOdQYHNh9xERb7Gk0MgS5I5k5C5G8E+6V8TuimJ6h lhlREBWT9XTZcNOOY+j7YCVmqvAeFD2FEUSjmIQodAY1jqqfGOuA1zOGtGJTv4sylEdh mIFQ== X-Gm-Message-State: AOAM532h31477bL3MO3+61lX5xToiAr819RsWIlytyJEEoERYXFRrGt1 if65QoxxjW/yQ49Q+a3K1vcV4vZ94GKF3w== X-Google-Smtp-Source: ABdhPJzMzgNdV+BiGH2etqFG4Tp8Yza2v38bu0+s0+OVITDvMkw/bjaXVYTfTV0yAZwjqzkbAy2sAQ== X-Received: by 2002:a05:6000:2cb:b0:20a:88c4:ec9f with SMTP id o11-20020a05600002cb00b0020a88c4ec9fmr18060790wry.43.1650539956750; Thu, 21 Apr 2022 04:19:16 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/31] hw/arm/virt: impact of gic-version on max CPUs Date: Thu, 21 Apr 2022 12:18:44 +0100 Message-Id: <20220421111846.2011565-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org> References: <20220421111846.2011565-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650541774968100002 Content-Type: text/plain; charset="utf-8" From: Heinrich Schuchardt Describe that the gic-version influences the maximum number of CPUs. Signed-off-by: Heinrich Schuchardt Message-id: 20220413231456.35811-1-heinrich.schuchardt@canonical.com [PMM: minor punctuation tweaks] Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- docs/system/arm/virt.rst | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index 1544632b674..1297dff5228 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -96,9 +96,9 @@ gic-version Valid values are: =20 ``2`` - GICv2 + GICv2. Note that this limits the number of CPUs to 8. ``3`` - GICv3 + GICv3. This allows up to 512 CPUs. ``host`` Use the same GIC version the host provides, when using KVM ``max`` --=20 2.25.1 From nobody Tue May 21 06:35:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650542227; cv=none; d=zohomail.com; s=zohoarc; b=axyx0Y5rdFFzbWOx9DfGPuHtSm6FdfDyfSzjCTFzoPqfu6hD7EmYgb29yZZXSP1I6N6hy316/OwzwqGAwIDhJHzMxpUMIzxDJXAQakzY8iYLsbnzDC3yQfyhpnEUoaoG4Isux6Fh13lQaN0S5maLslT4ZuhSJRQat00xu4GB1Yc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650542227; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1vQQmnvrDnu1486ihClizISxJdbac6HgCRxcsBLC0jQ=; b=YqTg1th9WKjM0iTJqz20hk9f9Oh88R9BKjL0J7oN5ZnwXZua7zgl90pod/LFV+7OGc3M2GeOEG1j7NZeY3M2DhQlikkHuj8qqzS8ET/v6b/Vg/4KAIuRLiCTdur+dq7ju6ecob3uQaQfK65tOOK+zZLJSEw9MYBJEJSjn/wmUoI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650542227482751.6273346263232; Thu, 21 Apr 2022 04:57:07 -0700 (PDT) Received: from localhost ([::1]:49296 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhVQn-0001CO-3u for importer@patchew.org; Thu, 21 Apr 2022 07:57:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59714) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhUqW-0003NF-4a for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:19:36 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:45940) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nhUqR-0003Yf-QD for qemu-devel@nongnu.org; Thu, 21 Apr 2022 07:19:35 -0400 Received: by mail-wr1-x430.google.com with SMTP id w4so6176572wrg.12 for ; Thu, 21 Apr 2022 04:19:18 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e4-20020a5d6d04000000b0020a8bbbb72bsm2597694wrq.97.2022.04.21.04.19.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 04:19:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1vQQmnvrDnu1486ihClizISxJdbac6HgCRxcsBLC0jQ=; b=ses9ETiUbAm0kzmUJWLRZdA9dCCpjd848fLEzR6NyJ6Z0dJFazIaAr3VggB+0JUzC8 cawe4ULRfCuzZ2pk1Wm/L7sbKJaaUCDJ/SqtgbcI6B6t3bqfcgIeLogWUdYCqZSzLEsh Wmln/ckjtbQB7W72EDHipCY4ew/RxcLKtz2BPHfRTHgGAf8LuEFRSKI+dmsp09tKD/vP 9x8t/0DB16I/8+vKdJLx6NuvgxZvCynrjxRO8zJpiOiTdHp8IMMbypQeozQ7W7PzXVF1 s/F+YM0BcnJSCq66DD4YUJ7K2kDyMhLSVBCRBhJDosBop/PlWrI/Qn6QArLj9UuuxLS9 fvuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1vQQmnvrDnu1486ihClizISxJdbac6HgCRxcsBLC0jQ=; b=KFLL4+2rIj5wCGNlhIXyryj4giH/tzd4L4ndq1k36RN/BbM4ll037figDyLnn6uUw4 /xwsRVQ07gZxRp9AcfYY2wkdsJ9/UjQ62leILjFM6LUN1F98Uan6fTI5bLDsAhLOMd4y AdELdHnjeN2Ix0xTr5BS2ja25TitwqqGU41EcjMgR+z5SQ2b67vbpDZ18h0z8VgsFX33 fyCSJVQyI6rboeESj7jYrmB1wdPE8zPj7HBSwXiZxO5A4B8Dnz1srUEP3mGIF7OC4pyt K0bwKKqU44m0fJ8lTOqPeM+RLIEOlkc5/btpJKaAKDd1lG7W2Ow0rpHKA+mdjldLymUP H49g== X-Gm-Message-State: AOAM533/aHKBvYA/Jd6qM2uM+zMZaRmEIhabsQ7WN6DMGcldEUCYza3q 1Mom9ERsMyjI7/jRdoKNefZenwZONomFtw== X-Google-Smtp-Source: ABdhPJzXO1zgZXWfw4zUVISFd4LhZJHLsaoL9P7JE82AuIPSx32M3CBJbf3yuIp4rxbaoGUEkbyP+w== X-Received: by 2002:a5d:64c7:0:b0:20a:8785:eb43 with SMTP id f7-20020a5d64c7000000b0020a8785eb43mr18353638wri.210.1650539957539; Thu, 21 Apr 2022 04:19:17 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/31] hw/misc: Add PWRON STRAP bit fields in GCR module Date: Thu, 21 Apr 2022 12:18:45 +0100 Message-Id: <20220421111846.2011565-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org> References: <20220421111846.2011565-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650542227939100001 Content-Type: text/plain; charset="utf-8" From: Hao Wu Similar to the Aspeed code in include/misc/aspeed_scu.h, we define the PWRON STRAP fields in their corresponding module for NPCM7XX. Signed-off-by: Hao Wu Reviewed-by: Patrick Venture Message-id: 20220411165842.3912945-2-wuhaotsh@google.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- include/hw/misc/npcm7xx_gcr.h | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/include/hw/misc/npcm7xx_gcr.h b/include/hw/misc/npcm7xx_gcr.h index 13109d9d324..9419e0a7d2a 100644 --- a/include/hw/misc/npcm7xx_gcr.h +++ b/include/hw/misc/npcm7xx_gcr.h @@ -19,6 +19,36 @@ #include "exec/memory.h" #include "hw/sysbus.h" =20 +/* + * NPCM7XX PWRON STRAP bit fields + * 12: SPI0 powered by VSBV3 at 1.8V + * 11: System flash attached to BMC + * 10: BSP alternative pins. + * 9:8: Flash UART command route enabled. + * 7: Security enabled. + * 6: HI-Z state control. + * 5: ECC disabled. + * 4: Reserved + * 3: JTAG2 enabled. + * 2:0: CPU and DRAM clock frequency. + */ +#define NPCM7XX_PWRON_STRAP_SPI0F18 BIT(12) +#define NPCM7XX_PWRON_STRAP_SFAB BIT(11) +#define NPCM7XX_PWRON_STRAP_BSPA BIT(10) +#define NPCM7XX_PWRON_STRAP_FUP(x) ((x) << 8) +#define FUP_NORM_UART2 3 +#define FUP_PROG_UART3 2 +#define FUP_PROG_UART2 1 +#define FUP_NORM_UART3 0 +#define NPCM7XX_PWRON_STRAP_SECEN BIT(7) +#define NPCM7XX_PWRON_STRAP_HIZ BIT(6) +#define NPCM7XX_PWRON_STRAP_ECC BIT(5) +#define NPCM7XX_PWRON_STRAP_RESERVE1 BIT(4) +#define NPCM7XX_PWRON_STRAP_J2EN BIT(3) +#define NPCM7XX_PWRON_STRAP_CKFRQ(x) (x) +#define CKFRQ_SKIPINIT 0x000 +#define CKFRQ_DEFAULT 0x111 + /* * Number of registers in our device state structure. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e4-20020a5d6d04000000b0020a8bbbb72bsm2597694wrq.97.2022.04.21.04.19.18 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 21 Apr 2022 04:19:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=VUeeNu4fbGv2sc/gKkaaAIAzl6d3eREzjCssGM3/Sx0=; b=LLRSaHt2MTUvjCW0k5r/i0vM56a2nM8UmXvsN1nlemxtwLbmsTt5LiiiNpsTJSmMGB g7rhw9goVmWM9PtBHaZY9fpExD0I6SSsybl+RaPpT/DkO8NmU0b9PslPqIzjeORtTCsW qKOWac3VpdhgSeqtcR2FpVsEtY8akNihOl0INLSEOnbPgPCByCuu+YJUuktOXRwb5YpP +2pnj3+yfU5X8RgpB3VPEf6gJaHbiCCiaJ4BE0sPWy3ipVRzP90kvcIEtZKYhtDh4z+b ycrZXgQRyN7EzPhHn76wFa1Y3ATVkIYD1Ds4/M0gTgWQdufGnbTI5tZsv9PB8Td6fKqg HYvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VUeeNu4fbGv2sc/gKkaaAIAzl6d3eREzjCssGM3/Sx0=; b=beNwGHQwUrWVzlZtnJhL0y6vJUlz5+eVA93t1xN084lQ6DHZXO+N2LfIl+kiZQ2KBG Gzc5n5ktxhHBvG98TWW0ibSFQOf/X8V8jMWYeXtTowkhAAh02WxwbAmBf5RSc2NF0tI0 M3uYqd+gv89FNvwCg1hOZas27j6KvqwM2DjRvX9WOiIEJ746ab/Qmx4Ayb7pdvOuLryl Zg6Y7SMggdD7Kcy3M+NO21WfGEIZ9wClDICAeHPwtAs1XUm7Ejihkx81EZuGp9VcZtKl Hk1WnXvsvExXQH1ou8NdRhy96Dm/LwoLqQJNE1pQo7xZqYUYFKjwo0cEapAcbBDHOwGw sB7g== X-Gm-Message-State: AOAM531RGeUkQjJGHG/+V92gj1dPWq5g5CMgWy1mekB7lXUYogYpb1SA Av/3OGaW7sSwtxUQkF47RAEtOJ4q6ODx2w== X-Google-Smtp-Source: ABdhPJyXHjGFoNcCTci0yMsONOA5W17mzQj0Luuuqn6pyA/BfYAleMCS5dhIAj7MmdUj/7f0JYpwMw== X-Received: by 2002:a5d:4a81:0:b0:207:9abe:2908 with SMTP id o1-20020a5d4a81000000b002079abe2908mr18820062wrq.341.1650539959284; Thu, 21 Apr 2022 04:19:19 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/31] hw/arm: Use bit fields for NPCM7XX PWRON STRAPs Date: Thu, 21 Apr 2022 12:18:46 +0100 Message-Id: <20220421111846.2011565-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220421111846.2011565-1-peter.maydell@linaro.org> References: <20220421111846.2011565-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650542479451100001 Content-Type: text/plain; charset="utf-8" From: Hao Wu This patch uses the defined fields to describe PWRON STRAPs for better readability. Signed-off-by: Hao Wu Reviewed-by: Patrick Venture Message-id: 20220411165842.3912945-3-wuhaotsh@google.com Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/npcm7xx_boards.c | 24 +++++++++++++++++++----- 1 file changed, 19 insertions(+), 5 deletions(-) diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index 0678a56156f..6bc6f5d2fe2 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -30,11 +30,25 @@ #include "sysemu/sysemu.h" #include "sysemu/block-backend.h" =20 -#define NPCM750_EVB_POWER_ON_STRAPS 0x00001ff7 -#define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff -#define QUANTA_GBS_POWER_ON_STRAPS 0x000017ff -#define KUDO_BMC_POWER_ON_STRAPS 0x00001fff -#define MORI_BMC_POWER_ON_STRAPS 0x00001fff +#define NPCM7XX_POWER_ON_STRAPS_DEFAULT ( \ + NPCM7XX_PWRON_STRAP_SPI0F18 | \ + NPCM7XX_PWRON_STRAP_SFAB | \ + NPCM7XX_PWRON_STRAP_BSPA | \ + NPCM7XX_PWRON_STRAP_FUP(FUP_NORM_UART2) | \ + NPCM7XX_PWRON_STRAP_SECEN | \ + NPCM7XX_PWRON_STRAP_HIZ | \ + NPCM7XX_PWRON_STRAP_ECC | \ + NPCM7XX_PWRON_STRAP_RESERVE1 | \ + NPCM7XX_PWRON_STRAP_J2EN | \ + NPCM7XX_PWRON_STRAP_CKFRQ(CKFRQ_DEFAULT)) + +#define NPCM750_EVB_POWER_ON_STRAPS ( \ + NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_J2EN) +#define QUANTA_GSJ_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT +#define QUANTA_GBS_POWER_ON_STRAPS ( \ + NPCM7XX_POWER_ON_STRAPS_DEFAULT & ~NPCM7XX_PWRON_STRAP_SFAB) +#define KUDO_BMC_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT +#define MORI_BMC_POWER_ON_STRAPS NPCM7XX_POWER_ON_STRAPS_DEFAULT =20 static const char npcm7xx_default_bootrom[] =3D "npcm7xx_bootrom.bin"; =20 --=20 2.25.1