From nobody Tue May 21 09:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650523530784320.99099572842044; Wed, 20 Apr 2022 23:45:30 -0700 (PDT) Received: from localhost ([::1]:44132 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhQZF-0003eO-Lv for importer@patchew.org; Thu, 21 Apr 2022 02:45:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53442) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQR0-0004nw-DT for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:36:58 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:13298) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQQw-0007v3-BG for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:36:57 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 21 Apr 2022 14:36:52 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:07:55 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:36:53 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KkSW84QNsz1SVnx for ; Wed, 20 Apr 2022 23:36:52 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id 3zZOwDR8mR8R for ; Wed, 20 Apr 2022 23:36:51 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.119]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KkSW42HgMz1Rwrw; Wed, 20 Apr 2022 23:36:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1650523014; x=1682059014; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=F4iQWwDMbAqXHN76890GL06y1AC10V3mfe7lRMBhOrk=; b=adQqltTqIw8PGVbxV740FfWyHBc1VnSB0mEHulKrk623UPfK41zFDl0d KC26XubEGMwFBp7wlu2OnIsiWEC1aBTfTO/SWQPyNn6UyFPSf90CjALWQ uwIeJObns4zzLE/9ng/W1e/R0oIBwOuGhKlp5r85fe7aTHgHwnzJM/rLD 99nBuvnCGbZD1QP5X6dGjdUN3wV0n432GQcLVcLmKi3pDB+PtFF30KpdL XREV97p9nOId+3MG2Ychq+JLx+/yQnMK9oK3qC33JkFtVsgQj/uweyuJP I4QjjeswhWmHaijJq6jcHElmgQLgFxmoGZUxwNUj5+2MXyq8N0hTtecy6 w==; X-IronPort-AV: E=Sophos;i="5.90,278,1643644800"; d="scan'208";a="302639919" IronPort-SDR: L/338KDdV/UnFkFQMD7g62P0/6ZIkx0BDjryM9rV+IF2lAIq+yMLcujdjhHaLs1RwlwY4pqSQR WcRJuaomWBpXV/yZcwfGpOki9hUW8ZyO2UAB7hKX3G/EUd3WQdwhEIkplKq8uDZJ08APOqXfrB +COmwh1+//3e0zCGHT0purcVcNU0L5aaGMSaxXmp/n4zRS7Ak/zTFwkcrQHNYk3cjvhwroRxP1 PauZczlVmm3ZUWOwnhKoOu77tkv6RyX4UWBeR0ZOpFZfbyCJ1THZCF+mUiEfgnQkQ0vNlJM223 S6SOKO9XUaZgQBO8lDnkGzpg IronPort-SDR: rPJCAnbQbL07Yk0LsddjfVSxg3Hdzasa2ON0qAdIUKBiVh1LyOE8hkN28xQoTwPr0dkNLH27SH DENh/B78ItKlJIiftUTNrx/iMDsfiFUTc+T0nsapFXZPKX+Ro+5pB2cFpS97rqZAm05NOMlJsD xqxMGCe0heu1+XgIRn7Pfp9kqOrfAqqLC1KLZtVLEPqUK3Ql2N2QY53d04nn/M9gaWkq0YVNzt TIGYGI1FOF0sJLlXc8c03C/LBKFNMG9HiHr7EwJi63b/ZkMCAQUU6dtiFURVvyibawlm0ji/Xn WJo= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:content-type :mime-version:references:in-reply-to:x-mailer:message-id:date :subject:to:from; s=dkim; t=1650523011; x=1653115012; bh=F4iQWwD MbAqXHN76890GL06y1AC10V3mfe7lRMBhOrk=; b=bgiZ79SpUg8+95JhZGiuOpc dbPz2Fgwk+8d+hSpGDrZauyG54WS/XDSpUBzizfzPD2aGkqU3F3QJkb0BR5naam4 08ySDaaINad6QikOUgNUK0JoNjmNli6cdijI03eVmvePD9PKiCo8awiP3d/o+coU RE6+ABvdddmPN4dgaZOzOkvHQ13UvxN/j5NEzphY5OSxBSAt2GuAPirbA8ABehgc ql+V3Kq2Fr2OwqPjH2Gf7eJ/7e7SsmWpO09R06sJpF3ubFKnEDgun6Gh3vbXeDLe lwB4OlSNDZUw8n2kmemjJBqzi9vj/ZUSB+QV5OtrONDAKUc7npGHalUU0Tj6hug= = X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Wilfred Mallawa , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 01/31] hw/ssi: Add Ibex SPI device model Date: Thu, 21 Apr 2022 16:36:00 +1000 Message-Id: <20220421063630.1033608-2-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650523531728100001 Content-Type: text/plain; charset="utf-8" From: Wilfred Mallawa Adds the SPI_HOST device model for ibex. The device specification is as per [1]. The model has been tested on opentitan with spi_host unit tests written for TockOS. [1] https://docs.opentitan.org/hw/ip/spi_host/doc/ Signed-off-by: Wilfred Mallawa Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220303045426.511588-1-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis --- include/hw/ssi/ibex_spi_host.h | 94 +++++ hw/ssi/ibex_spi_host.c | 612 +++++++++++++++++++++++++++++++++ hw/ssi/meson.build | 1 + hw/ssi/trace-events | 7 + 4 files changed, 714 insertions(+) create mode 100644 include/hw/ssi/ibex_spi_host.h create mode 100644 hw/ssi/ibex_spi_host.c diff --git a/include/hw/ssi/ibex_spi_host.h b/include/hw/ssi/ibex_spi_host.h new file mode 100644 index 0000000000..3fedcb6805 --- /dev/null +++ b/include/hw/ssi/ibex_spi_host.h @@ -0,0 +1,94 @@ + +/* + * QEMU model of the Ibex SPI Controller + * SPEC Reference: https://docs.opentitan.org/hw/ip/spi_host/doc/ + * + * Copyright (C) 2022 Western Digital + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef IBEX_SPI_HOST_H +#define IBEX_SPI_HOST_H + +#include "hw/sysbus.h" +#include "hw/hw.h" +#include "hw/ssi/ssi.h" +#include "qemu/fifo8.h" +#include "qom/object.h" +#include "hw/registerfields.h" +#include "qemu/timer.h" + +#define TYPE_IBEX_SPI_HOST "ibex-spi" +#define IBEX_SPI_HOST(obj) \ + OBJECT_CHECK(IbexSPIHostState, (obj), TYPE_IBEX_SPI_HOST) + +/* SPI Registers */ +#define IBEX_SPI_HOST_INTR_STATE (0x00 / 4) /* rw */ +#define IBEX_SPI_HOST_INTR_ENABLE (0x04 / 4) /* rw */ +#define IBEX_SPI_HOST_INTR_TEST (0x08 / 4) /* wo */ +#define IBEX_SPI_HOST_ALERT_TEST (0x0c / 4) /* wo */ +#define IBEX_SPI_HOST_CONTROL (0x10 / 4) /* rw */ +#define IBEX_SPI_HOST_STATUS (0x14 / 4) /* ro */ +#define IBEX_SPI_HOST_CONFIGOPTS (0x18 / 4) /* rw */ +#define IBEX_SPI_HOST_CSID (0x1c / 4) /* rw */ +#define IBEX_SPI_HOST_COMMAND (0x20 / 4) /* wo */ +/* RX/TX Modelled by FIFO */ +#define IBEX_SPI_HOST_RXDATA (0x24 / 4) +#define IBEX_SPI_HOST_TXDATA (0x28 / 4) + +#define IBEX_SPI_HOST_ERROR_ENABLE (0x2c / 4) /* rw */ +#define IBEX_SPI_HOST_ERROR_STATUS (0x30 / 4) /* rw */ +#define IBEX_SPI_HOST_EVENT_ENABLE (0x34 / 4) /* rw */ + +/* FIFO Len in Bytes */ +#define IBEX_SPI_HOST_TXFIFO_LEN 288 +#define IBEX_SPI_HOST_RXFIFO_LEN 256 + +/* Max Register (Based on addr) */ +#define IBEX_SPI_HOST_MAX_REGS (IBEX_SPI_HOST_EVENT_ENABLE + 1) + +/* MISC */ +#define TX_INTERRUPT_TRIGGER_DELAY_NS 100 +#define BIDIRECTIONAL_TRANSFER 3 + +typedef struct { + /* */ + SysBusDevice parent_obj; + + /* */ + MemoryRegion mmio; + uint32_t regs[IBEX_SPI_HOST_MAX_REGS]; + /* Multi-reg that sets config opts per CS */ + uint32_t *config_opts; + Fifo8 rx_fifo; + Fifo8 tx_fifo; + QEMUTimer *fifo_trigger_handle; + + qemu_irq event; + qemu_irq host_err; + uint32_t num_cs; + qemu_irq *cs_lines; + SSIBus *ssi; + + /* Used to track the init status, for replicating TXDATA ghost writes = */ + bool init_status; +} IbexSPIHostState; + +#endif diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c new file mode 100644 index 0000000000..d14580b409 --- /dev/null +++ b/hw/ssi/ibex_spi_host.c @@ -0,0 +1,612 @@ +/* + * QEMU model of the Ibex SPI Controller + * SPEC Reference: https://docs.opentitan.org/hw/ip/spi_host/doc/ + * + * Copyright (C) 2022 Western Digital + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/ssi/ibex_spi_host.h" +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/qdev-properties-system.h" +#include "migration/vmstate.h" +#include "trace.h" + +REG32(INTR_STATE, 0x00) + FIELD(INTR_STATE, ERROR, 0, 1) + FIELD(INTR_STATE, SPI_EVENT, 1, 1) +REG32(INTR_ENABLE, 0x04) + FIELD(INTR_ENABLE, ERROR, 0, 1) + FIELD(INTR_ENABLE, SPI_EVENT, 1, 1) +REG32(INTR_TEST, 0x08) + FIELD(INTR_TEST, ERROR, 0, 1) + FIELD(INTR_TEST, SPI_EVENT, 1, 1) +REG32(ALERT_TEST, 0x0c) + FIELD(ALERT_TEST, FETAL_TEST, 0, 1) +REG32(CONTROL, 0x10) + FIELD(CONTROL, RX_WATERMARK, 0, 8) + FIELD(CONTROL, TX_WATERMARK, 1, 8) + FIELD(CONTROL, OUTPUT_EN, 29, 1) + FIELD(CONTROL, SW_RST, 30, 1) + FIELD(CONTROL, SPIEN, 31, 1) +REG32(STATUS, 0x14) + FIELD(STATUS, TXQD, 0, 8) + FIELD(STATUS, RXQD, 18, 8) + FIELD(STATUS, CMDQD, 16, 3) + FIELD(STATUS, RXWM, 20, 1) + FIELD(STATUS, BYTEORDER, 22, 1) + FIELD(STATUS, RXSTALL, 23, 1) + FIELD(STATUS, RXEMPTY, 24, 1) + FIELD(STATUS, RXFULL, 25, 1) + FIELD(STATUS, TXWM, 26, 1) + FIELD(STATUS, TXSTALL, 27, 1) + FIELD(STATUS, TXEMPTY, 28, 1) + FIELD(STATUS, TXFULL, 29, 1) + FIELD(STATUS, ACTIVE, 30, 1) + FIELD(STATUS, READY, 31, 1) +REG32(CONFIGOPTS, 0x18) + FIELD(CONFIGOPTS, CLKDIV_0, 0, 16) + FIELD(CONFIGOPTS, CSNIDLE_0, 16, 4) + FIELD(CONFIGOPTS, CSNTRAIL_0, 20, 4) + FIELD(CONFIGOPTS, CSNLEAD_0, 24, 4) + FIELD(CONFIGOPTS, FULLCYC_0, 29, 1) + FIELD(CONFIGOPTS, CPHA_0, 30, 1) + FIELD(CONFIGOPTS, CPOL_0, 31, 1) +REG32(CSID, 0x1c) + FIELD(CSID, CSID, 0, 32) +REG32(COMMAND, 0x20) + FIELD(COMMAND, LEN, 0, 8) + FIELD(COMMAND, CSAAT, 9, 1) + FIELD(COMMAND, SPEED, 10, 2) + FIELD(COMMAND, DIRECTION, 12, 2) +REG32(ERROR_ENABLE, 0x2c) + FIELD(ERROR_ENABLE, CMDBUSY, 0, 1) + FIELD(ERROR_ENABLE, OVERFLOW, 1, 1) + FIELD(ERROR_ENABLE, UNDERFLOW, 2, 1) + FIELD(ERROR_ENABLE, CMDINVAL, 3, 1) + FIELD(ERROR_ENABLE, CSIDINVAL, 4, 1) +REG32(ERROR_STATUS, 0x30) + FIELD(ERROR_STATUS, CMDBUSY, 0, 1) + FIELD(ERROR_STATUS, OVERFLOW, 1, 1) + FIELD(ERROR_STATUS, UNDERFLOW, 2, 1) + FIELD(ERROR_STATUS, CMDINVAL, 3, 1) + FIELD(ERROR_STATUS, CSIDINVAL, 4, 1) + FIELD(ERROR_STATUS, ACCESSINVAL, 5, 1) +REG32(EVENT_ENABLE, 0x30) + FIELD(EVENT_ENABLE, RXFULL, 0, 1) + FIELD(EVENT_ENABLE, TXEMPTY, 1, 1) + FIELD(EVENT_ENABLE, RXWM, 2, 1) + FIELD(EVENT_ENABLE, TXWM, 3, 1) + FIELD(EVENT_ENABLE, READY, 4, 1) + FIELD(EVENT_ENABLE, IDLE, 5, 1) + +static inline uint8_t div4_round_up(uint8_t dividend) +{ + return (dividend + 3) / 4; +} + +static void ibex_spi_rxfifo_reset(IbexSPIHostState *s) +{ + /* Empty the RX FIFO and assert RXEMPTY */ + fifo8_reset(&s->rx_fifo); + s->regs[IBEX_SPI_HOST_STATUS] &=3D ~R_STATUS_RXFULL_MASK; + s->regs[IBEX_SPI_HOST_STATUS] |=3D R_STATUS_RXEMPTY_MASK; +} + +static void ibex_spi_txfifo_reset(IbexSPIHostState *s) +{ + /* Empty the TX FIFO and assert TXEMPTY */ + fifo8_reset(&s->tx_fifo); + s->regs[IBEX_SPI_HOST_STATUS] &=3D ~R_STATUS_TXFULL_MASK; + s->regs[IBEX_SPI_HOST_STATUS] |=3D R_STATUS_TXEMPTY_MASK; +} + +static void ibex_spi_host_reset(DeviceState *dev) +{ + IbexSPIHostState *s =3D IBEX_SPI_HOST(dev); + trace_ibex_spi_host_reset("Resetting Ibex SPI"); + + /* SPI Host Register Reset */ + s->regs[IBEX_SPI_HOST_INTR_STATE] =3D 0x00; + s->regs[IBEX_SPI_HOST_INTR_ENABLE] =3D 0x00; + s->regs[IBEX_SPI_HOST_INTR_TEST] =3D 0x00; + s->regs[IBEX_SPI_HOST_ALERT_TEST] =3D 0x00; + s->regs[IBEX_SPI_HOST_CONTROL] =3D 0x7f; + s->regs[IBEX_SPI_HOST_STATUS] =3D 0x00; + s->regs[IBEX_SPI_HOST_CONFIGOPTS] =3D 0x00; + s->regs[IBEX_SPI_HOST_CSID] =3D 0x00; + s->regs[IBEX_SPI_HOST_COMMAND] =3D 0x00; + /* RX/TX Modelled by FIFO */ + s->regs[IBEX_SPI_HOST_RXDATA] =3D 0x00; + s->regs[IBEX_SPI_HOST_TXDATA] =3D 0x00; + + s->regs[IBEX_SPI_HOST_ERROR_ENABLE] =3D 0x1F; + s->regs[IBEX_SPI_HOST_ERROR_STATUS] =3D 0x00; + s->regs[IBEX_SPI_HOST_EVENT_ENABLE] =3D 0x00; + + ibex_spi_rxfifo_reset(s); + ibex_spi_txfifo_reset(s); + + s->init_status =3D true; + return; +} + +/* + * Check if we need to trigger an interrupt. + * The two interrupts lines (host_err and event) can + * be enabled separately in 'IBEX_SPI_HOST_INTR_ENABLE'. + * + * Interrupts are triggered based on the ones + * enabled in the `IBEX_SPI_HOST_EVENT_ENABLE` and `IBEX_SPI_HOST_ERROR_EN= ABLE`. + */ +static void ibex_spi_host_irq(IbexSPIHostState *s) +{ + bool error_en =3D s->regs[IBEX_SPI_HOST_INTR_ENABLE] + & R_INTR_ENABLE_ERROR_MASK; + bool event_en =3D s->regs[IBEX_SPI_HOST_INTR_ENABLE] + & R_INTR_ENABLE_SPI_EVENT_MASK; + bool err_pending =3D s->regs[IBEX_SPI_HOST_INTR_STATE] + & R_INTR_STATE_ERROR_MASK; + bool status_pending =3D s->regs[IBEX_SPI_HOST_INTR_STATE] + & R_INTR_STATE_SPI_EVENT_MASK; + int err_irq =3D 0, event_irq =3D 0; + + /* Error IRQ enabled and Error IRQ Cleared*/ + if (error_en && !err_pending) { + /* Event enabled, Interrupt Test Error */ + if (s->regs[IBEX_SPI_HOST_INTR_TEST] & R_INTR_TEST_ERROR_MASK) { + err_irq =3D 1; + } else if ((s->regs[IBEX_SPI_HOST_ERROR_ENABLE] + & R_ERROR_ENABLE_CMDBUSY_MASK) && + s->regs[IBEX_SPI_HOST_ERROR_STATUS] + & R_ERROR_STATUS_CMDBUSY_MASK) { + /* Wrote to COMMAND when not READY */ + err_irq =3D 1; + } else if ((s->regs[IBEX_SPI_HOST_ERROR_ENABLE] + & R_ERROR_ENABLE_CMDINVAL_MASK) && + s->regs[IBEX_SPI_HOST_ERROR_STATUS] + & R_ERROR_STATUS_CMDINVAL_MASK) { + /* Invalid command segment */ + err_irq =3D 1; + } else if ((s->regs[IBEX_SPI_HOST_ERROR_ENABLE] + & R_ERROR_ENABLE_CSIDINVAL_MASK) && + s->regs[IBEX_SPI_HOST_ERROR_STATUS] + & R_ERROR_STATUS_CSIDINVAL_MASK) { + /* Invalid value for CSID */ + err_irq =3D 1; + } + if (err_irq) { + s->regs[IBEX_SPI_HOST_INTR_STATE] |=3D R_INTR_STATE_ERROR_MASK; + } + qemu_set_irq(s->host_err, err_irq); + } + + /* Event IRQ Enabled and Event IRQ Cleared */ + if (event_en && !status_pending) { + if (s->regs[IBEX_SPI_HOST_INTR_TEST] & R_INTR_TEST_SPI_EVENT_MASK)= { + /* Event enabled, Interrupt Test Event */ + event_irq =3D 1; + } else if ((s->regs[IBEX_SPI_HOST_EVENT_ENABLE] + & R_EVENT_ENABLE_READY_MASK) && + (s->regs[IBEX_SPI_HOST_STATUS] & R_STATUS_READY_MASK))= { + /* SPI Host ready for next command */ + event_irq =3D 1; + } else if ((s->regs[IBEX_SPI_HOST_EVENT_ENABLE] + & R_EVENT_ENABLE_TXEMPTY_MASK) && + (s->regs[IBEX_SPI_HOST_STATUS] & R_STATUS_TXEMPTY_MASK= )) { + /* SPI TXEMPTY, TXFIFO drained */ + event_irq =3D 1; + } else if ((s->regs[IBEX_SPI_HOST_EVENT_ENABLE] + & R_EVENT_ENABLE_RXFULL_MASK) && + (s->regs[IBEX_SPI_HOST_STATUS] & R_STATUS_RXFULL_MASK)= ) { + /* SPI RXFULL, RXFIFO full */ + event_irq =3D 1; + } + if (event_irq) { + s->regs[IBEX_SPI_HOST_INTR_STATE] |=3D R_INTR_STATE_SPI_EVENT_= MASK; + } + qemu_set_irq(s->event, event_irq); + } +} + +static void ibex_spi_host_transfer(IbexSPIHostState *s) +{ + uint32_t rx, tx; + /* Get num of one byte transfers */ + uint8_t segment_len =3D ((s->regs[IBEX_SPI_HOST_COMMAND] & R_COMMAND_L= EN_MASK) + >> R_COMMAND_LEN_SHIFT); + while (segment_len > 0) { + if (fifo8_is_empty(&s->tx_fifo)) { + /* Assert Stall */ + s->regs[IBEX_SPI_HOST_STATUS] |=3D R_STATUS_TXSTALL_MASK; + break; + } else if (fifo8_is_full(&s->rx_fifo)) { + /* Assert Stall */ + s->regs[IBEX_SPI_HOST_STATUS] |=3D R_STATUS_RXSTALL_MASK; + break; + } else { + tx =3D fifo8_pop(&s->tx_fifo); + } + + rx =3D ssi_transfer(s->ssi, tx); + + trace_ibex_spi_host_transfer(tx, rx); + + if (!fifo8_is_full(&s->rx_fifo)) { + fifo8_push(&s->rx_fifo, rx); + } else { + /* Assert RXFULL */ + s->regs[IBEX_SPI_HOST_STATUS] |=3D R_STATUS_RXFULL_MASK; + } + --segment_len; + } + + /* Assert Ready */ + s->regs[IBEX_SPI_HOST_STATUS] |=3D R_STATUS_READY_MASK; + /* Set RXQD */ + s->regs[IBEX_SPI_HOST_STATUS] &=3D ~R_STATUS_RXQD_MASK; + s->regs[IBEX_SPI_HOST_STATUS] |=3D (R_STATUS_RXQD_MASK + & div4_round_up(segment_len)); + /* Set TXQD */ + s->regs[IBEX_SPI_HOST_STATUS] &=3D ~R_STATUS_TXQD_MASK; + s->regs[IBEX_SPI_HOST_STATUS] |=3D (fifo8_num_used(&s->tx_fifo) / 4) + & R_STATUS_TXQD_MASK; + /* Clear TXFULL */ + s->regs[IBEX_SPI_HOST_STATUS] &=3D ~R_STATUS_TXFULL_MASK; + /* Assert TXEMPTY and drop remaining bytes that exceed segment_len */ + ibex_spi_txfifo_reset(s); + /* Reset RXEMPTY */ + s->regs[IBEX_SPI_HOST_STATUS] &=3D ~R_STATUS_RXEMPTY_MASK; + + ibex_spi_host_irq(s); +} + +static uint64_t ibex_spi_host_read(void *opaque, hwaddr addr, + unsigned int size) +{ + IbexSPIHostState *s =3D opaque; + uint32_t rc =3D 0; + uint8_t rx_byte =3D 0; + + trace_ibex_spi_host_read(addr, size); + + /* Match reg index */ + addr =3D addr >> 2; + switch (addr) { + /* Skipping any W/O registers */ + case IBEX_SPI_HOST_INTR_STATE...IBEX_SPI_HOST_INTR_ENABLE: + case IBEX_SPI_HOST_CONTROL...IBEX_SPI_HOST_STATUS: + rc =3D s->regs[addr]; + break; + case IBEX_SPI_HOST_CSID: + rc =3D s->regs[addr]; + break; + case IBEX_SPI_HOST_CONFIGOPTS: + rc =3D s->config_opts[s->regs[IBEX_SPI_HOST_CSID]]; + break; + case IBEX_SPI_HOST_TXDATA: + rc =3D s->regs[addr]; + break; + case IBEX_SPI_HOST_RXDATA: + /* Clear RXFULL */ + s->regs[IBEX_SPI_HOST_STATUS] &=3D ~R_STATUS_RXFULL_MASK; + + for (int i =3D 0; i < 4; ++i) { + if (fifo8_is_empty(&s->rx_fifo)) { + /* Assert RXEMPTY, no IRQ */ + s->regs[IBEX_SPI_HOST_STATUS] |=3D R_STATUS_RXEMPTY_MASK; + s->regs[IBEX_SPI_HOST_ERROR_STATUS] |=3D + R_ERROR_STATUS_UNDERFLOW_M= ASK; + return rc; + } + rx_byte =3D fifo8_pop(&s->rx_fifo); + rc |=3D rx_byte << (i * 8); + } + break; + case IBEX_SPI_HOST_ERROR_ENABLE...IBEX_SPI_HOST_EVENT_ENABLE: + rc =3D s->regs[addr]; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "Bad offset 0x%" HWADDR_PRIx "\n", + addr << 2); + } + return rc; +} + + +static void ibex_spi_host_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + IbexSPIHostState *s =3D opaque; + uint32_t val32 =3D val64; + uint32_t shift_mask =3D 0xff; + uint8_t txqd_len; + + trace_ibex_spi_host_write(addr, size, val64); + + /* Match reg index */ + addr =3D addr >> 2; + + switch (addr) { + /* Skipping any R/O registers */ + case IBEX_SPI_HOST_INTR_STATE...IBEX_SPI_HOST_INTR_ENABLE: + s->regs[addr] =3D val32; + break; + case IBEX_SPI_HOST_INTR_TEST: + s->regs[addr] =3D val32; + ibex_spi_host_irq(s); + break; + case IBEX_SPI_HOST_ALERT_TEST: + s->regs[addr] =3D val32; + qemu_log_mask(LOG_UNIMP, + "%s: SPI_ALERT_TEST is not supported\n", __func__); + break; + case IBEX_SPI_HOST_CONTROL: + s->regs[addr] =3D val32; + + if (val32 & R_CONTROL_SW_RST_MASK) { + ibex_spi_host_reset((DeviceState *)s); + /* Clear active if any */ + s->regs[IBEX_SPI_HOST_STATUS] &=3D ~R_STATUS_ACTIVE_MASK; + } + + if (val32 & R_CONTROL_OUTPUT_EN_MASK) { + qemu_log_mask(LOG_UNIMP, + "%s: CONTROL_OUTPUT_EN is not supported\n", __fu= nc__); + } + break; + case IBEX_SPI_HOST_CONFIGOPTS: + /* Update the respective config-opts register based on CSIDth inde= x */ + s->config_opts[s->regs[IBEX_SPI_HOST_CSID]] =3D val32; + qemu_log_mask(LOG_UNIMP, + "%s: CONFIGOPTS Hardware settings not supported\n", + __func__); + break; + case IBEX_SPI_HOST_CSID: + if (val32 >=3D s->num_cs) { + /* CSID exceeds max num_cs */ + s->regs[IBEX_SPI_HOST_ERROR_STATUS] |=3D + R_ERROR_STATUS_CSIDINVAL_M= ASK; + ibex_spi_host_irq(s); + return; + } + s->regs[addr] =3D val32; + break; + case IBEX_SPI_HOST_COMMAND: + s->regs[addr] =3D val32; + + /* STALL, IP not enabled */ + if (!(s->regs[IBEX_SPI_HOST_CONTROL] & R_CONTROL_SPIEN_MASK)) { + return; + } + + /* SPI not ready, IRQ Error */ + if (!(s->regs[IBEX_SPI_HOST_STATUS] & R_STATUS_READY_MASK)) { + s->regs[IBEX_SPI_HOST_ERROR_STATUS] |=3D R_ERROR_STATUS_CMDBUS= Y_MASK; + ibex_spi_host_irq(s); + return; + } + /* Assert Not Ready */ + s->regs[IBEX_SPI_HOST_STATUS] &=3D ~R_STATUS_READY_MASK; + + if (((val32 & R_COMMAND_DIRECTION_MASK) >> R_COMMAND_DIRECTION_SHI= FT) + !=3D BIDIRECTIONAL_TRANSFER) { + qemu_log_mask(LOG_UNIMP, + "%s: Rx Only/Tx Only are not supported\n", __fun= c__); + } + + if (val32 & R_COMMAND_CSAAT_MASK) { + qemu_log_mask(LOG_UNIMP, + "%s: CSAAT is not supported\n", __func__); + } + if (val32 & R_COMMAND_SPEED_MASK) { + qemu_log_mask(LOG_UNIMP, + "%s: SPEED is not supported\n", __func__); + } + + /* Set Transfer Callback */ + timer_mod(s->fifo_trigger_handle, + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + + (TX_INTERRUPT_TRIGGER_DELAY_NS)); + + break; + case IBEX_SPI_HOST_TXDATA: + /* + * This is a hardware `feature` where + * the first word written TXDATA after init is omitted entirely + */ + if (s->init_status) { + s->init_status =3D false; + return; + } + + for (int i =3D 0; i < 4; ++i) { + /* Attempting to write when TXFULL */ + if (fifo8_is_full(&s->tx_fifo)) { + /* Assert RXEMPTY, no IRQ */ + s->regs[IBEX_SPI_HOST_STATUS] |=3D R_STATUS_TXFULL_MASK; + s->regs[IBEX_SPI_HOST_ERROR_STATUS] |=3D + R_ERROR_STATUS_OVERFLOW_M= ASK; + ibex_spi_host_irq(s); + return; + } + /* Byte ordering is set by the IP */ + if ((s->regs[IBEX_SPI_HOST_STATUS] & + R_STATUS_BYTEORDER_MASK) =3D=3D 0) { + /* LE: LSB transmitted first (default for ibex processor) = */ + shift_mask =3D 0xff << (i * 8); + } else { + /* BE: MSB transmitted first */ + qemu_log_mask(LOG_UNIMP, + "%s: Big endian is not supported\n", __func__= ); + } + + fifo8_push(&s->tx_fifo, (val32 & shift_mask) >> (i * 8)); + } + + /* Reset TXEMPTY */ + s->regs[IBEX_SPI_HOST_STATUS] &=3D ~R_STATUS_TXEMPTY_MASK; + /* Update TXQD */ + txqd_len =3D (s->regs[IBEX_SPI_HOST_STATUS] & + R_STATUS_TXQD_MASK) >> R_STATUS_TXQD_SHIFT; + /* Partial bytes (size < 4) are padded, in words. */ + txqd_len +=3D 1; + s->regs[IBEX_SPI_HOST_STATUS] &=3D ~R_STATUS_TXQD_MASK; + s->regs[IBEX_SPI_HOST_STATUS] |=3D txqd_len; + /* Assert Ready */ + s->regs[IBEX_SPI_HOST_STATUS] |=3D R_STATUS_READY_MASK; + break; + case IBEX_SPI_HOST_ERROR_ENABLE: + s->regs[addr] =3D val32; + + if (val32 & R_ERROR_ENABLE_CMDINVAL_MASK) { + qemu_log_mask(LOG_UNIMP, + "%s: Segment Length is not supported\n", __func_= _); + } + break; + case IBEX_SPI_HOST_ERROR_STATUS: + /* + * Indicates that any errors that have occurred. + * When an error occurs, the corresponding bit must be cleared + * here before issuing any further commands + */ + s->regs[addr] =3D val32; + break; + case IBEX_SPI_HOST_EVENT_ENABLE: + /* Controls which classes of SPI events raise an interrupt. */ + s->regs[addr] =3D val32; + + if (val32 & R_EVENT_ENABLE_RXWM_MASK) { + qemu_log_mask(LOG_UNIMP, + "%s: RXWM is not supported\n", __func__); + } + if (val32 & R_EVENT_ENABLE_TXWM_MASK) { + qemu_log_mask(LOG_UNIMP, + "%s: TXWM is not supported\n", __func__); + } + + if (val32 & R_EVENT_ENABLE_IDLE_MASK) { + qemu_log_mask(LOG_UNIMP, + "%s: IDLE is not supported\n", __func__); + } + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "Bad offset 0x%" HWADDR_PRIx "\n", + addr << 2); + } +} + +static const MemoryRegionOps ibex_spi_ops =3D { + .read =3D ibex_spi_host_read, + .write =3D ibex_spi_host_write, + /* Ibex default LE */ + .endianness =3D DEVICE_LITTLE_ENDIAN, +}; + +static Property ibex_spi_properties[] =3D { + DEFINE_PROP_UINT32("num_cs", IbexSPIHostState, num_cs, 1), + DEFINE_PROP_END_OF_LIST(), +}; + +static const VMStateDescription vmstate_ibex =3D { + .name =3D TYPE_IBEX_SPI_HOST, + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, IbexSPIHostState, IBEX_SPI_HOST_MAX_REG= S), + VMSTATE_VARRAY_UINT32(config_opts, IbexSPIHostState, + num_cs, 0, vmstate_info_uint32, uint32_t), + VMSTATE_FIFO8(rx_fifo, IbexSPIHostState), + VMSTATE_FIFO8(tx_fifo, IbexSPIHostState), + VMSTATE_TIMER_PTR(fifo_trigger_handle, IbexSPIHostState), + VMSTATE_BOOL(init_status, IbexSPIHostState), + VMSTATE_END_OF_LIST() + } +}; + +static void fifo_trigger_update(void *opaque) +{ + IbexSPIHostState *s =3D opaque; + ibex_spi_host_transfer(s); +} + +static void ibex_spi_host_realize(DeviceState *dev, Error **errp) +{ + IbexSPIHostState *s =3D IBEX_SPI_HOST(dev); + int i; + + s->ssi =3D ssi_create_bus(dev, "ssi"); + s->cs_lines =3D g_new0(qemu_irq, s->num_cs); + + for (i =3D 0; i < s->num_cs; ++i) { + sysbus_init_irq(SYS_BUS_DEVICE(dev), &s->cs_lines[i]); + } + + /* Setup CONFIGOPTS Multi-register */ + s->config_opts =3D g_new0(uint32_t, s->num_cs); + + /* Setup FIFO Interrupt Timer */ + s->fifo_trigger_handle =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, + fifo_trigger_update, s); + + /* FIFO sizes as per OT Spec */ + fifo8_create(&s->tx_fifo, IBEX_SPI_HOST_TXFIFO_LEN); + fifo8_create(&s->rx_fifo, IBEX_SPI_HOST_RXFIFO_LEN); +} + +static void ibex_spi_host_init(Object *obj) +{ + IbexSPIHostState *s =3D IBEX_SPI_HOST(obj); + + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->host_err); + sysbus_init_irq(SYS_BUS_DEVICE(obj), &s->event); + + memory_region_init_io(&s->mmio, obj, &ibex_spi_ops, s, + TYPE_IBEX_SPI_HOST, 0x1000); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); +} + +static void ibex_spi_host_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + dc->realize =3D ibex_spi_host_realize; + dc->reset =3D ibex_spi_host_reset; + dc->vmsd =3D &vmstate_ibex; + device_class_set_props(dc, ibex_spi_properties); +} + +static const TypeInfo ibex_spi_host_info =3D { + .name =3D TYPE_IBEX_SPI_HOST, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(IbexSPIHostState), + .instance_init =3D ibex_spi_host_init, + .class_init =3D ibex_spi_host_class_init, +}; + +static void ibex_spi_host_register_types(void) +{ + type_register_static(&ibex_spi_host_info); +} + +type_init(ibex_spi_host_register_types) diff --git a/hw/ssi/meson.build b/hw/ssi/meson.build index 0ded9cd092..702aa5e4df 100644 --- a/hw/ssi/meson.build +++ b/hw/ssi/meson.build @@ -10,3 +10,4 @@ softmmu_ss.add(when: 'CONFIG_XILINX_SPIPS', if_true: file= s('xilinx_spips.c')) softmmu_ss.add(when: 'CONFIG_XLNX_VERSAL', if_true: files('xlnx-versal-osp= i.c')) softmmu_ss.add(when: 'CONFIG_IMX', if_true: files('imx_spi.c')) softmmu_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_spi.c')) +softmmu_ss.add(when: 'CONFIG_IBEX', if_true: files('ibex_spi_host.c')) diff --git a/hw/ssi/trace-events b/hw/ssi/trace-events index 612d3d6087..c707d4aaba 100644 --- a/hw/ssi/trace-events +++ b/hw/ssi/trace-events @@ -20,3 +20,10 @@ npcm7xx_fiu_ctrl_read(const char *id, uint64_t addr, uin= t32_t data) "%s offset: npcm7xx_fiu_ctrl_write(const char *id, uint64_t addr, uint32_t data) "%s o= ffset: 0x%04" PRIx64 " value: 0x%08" PRIx32 npcm7xx_fiu_flash_read(const char *id, int cs, uint64_t addr, unsigned int= size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value: 0x%"= PRIx64 npcm7xx_fiu_flash_write(const char *id, unsigned cs, uint64_t addr, unsign= ed int size, uint64_t value) "%s[%d] offset: 0x%08" PRIx64 " size: %u value= : 0x%" PRIx64 + +# ibex_spi_host.c + +ibex_spi_host_reset(const char *msg) "%s" +ibex_spi_host_transfer(uint32_t tx_data, uint32_t rx_data) "tx_data: 0x%" = PRIx32 " rx_data: @0x%" PRIx32 +ibex_spi_host_write(uint64_t addr, uint32_t size, uint64_t data) "@0x%" PR= Ix64 " size %u: 0x%" PRIx64 +ibex_spi_host_read(uint64_t addr, uint32_t size) "@0x%" PRIx64 " size %u:" --=20 2.35.1 From nobody Tue May 21 09:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650523872306610.475369817988; Wed, 20 Apr 2022 23:51:12 -0700 (PDT) Received: from localhost ([::1]:52966 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhQel-0001LF-AD for importer@patchew.org; Thu, 21 Apr 2022 02:51:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53444) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQR0-0004oF-AG for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:36:58 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:13303) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQQy-0007vC-8i for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:36:57 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 21 Apr 2022 14:36:55 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:07:57 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:36:55 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KkSWB5lJ1z1SVnx for ; Wed, 20 Apr 2022 23:36:54 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id YvMJqPtyENcK for ; Wed, 20 Apr 2022 23:36:54 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.119]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KkSW76hFyz1Rvlx; Wed, 20 Apr 2022 23:36:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1650523016; x=1682059016; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=ZgC2XGZNz9GOqFHwEiweZQEoaeQwoAuD6cvXgf97ucI=; b=Lffn0byPWYKa2vxw/dhf080T54t9ZPkYKO2tmIEK2y4pfQtuKslxdePu 5hiMICQub3FuGI7o6DnjyzE0133whr+7N7odGd+HkcYYRAMod0IMg1ZXm 7bg08ln60Tz3S+rnWNUl0WKpDubAZOwAriJ/21FeIifDtH2Q+t6K2PO6Q tmKhA4jL3Cc9hfBev+ARKNnURlxWOHfTeyD8bggdr4Ar+i5BkoxRN/gDQ 537O+NbsmuLyywVDyIhuAUK3gEDb3Z0UL9i+CVRvglNB1aUPRkkGSMomH uHAAaw4YM7Sc6/V2mDme017b3H8rcagf/AcuZ6vxO8QvwPvnjaYwRn+SZ A==; X-IronPort-AV: E=Sophos;i="5.90,278,1643644800"; d="scan'208";a="302639924" IronPort-SDR: qGTA5uu/FdYHfVAZr5mlSgl7crnQlrbAAOYwO6u9pWrVHB5FkeNiDWVO+6WDGzkolH3kL+xz1j ZjBiDFmN/u8RcNGdMwLNDPf5Kv93zxPMqB1UaU8V/389AtXQ9rkwXmAmOhP76TxSj1I0aLUhlU ZKOzlZ4srUpumUJmHi38frnPXALgcGkpdvh0FDyrFrqrEDn6JzkqgnLbcCVl1uXBcZ4ZJWNvN7 Kx/py0Ztc55bfHE/NR1z1r4vwpQb4f6W+s9e3SFarMo0A4/NZojPsSVOhpUQxH5nQX48scNePZ a/SckR1v1yJTGi3sjl+1k92D IronPort-SDR: RQT9jL0Yj/vj5cJ+RCe61MVJvZ8S3pSVTKB5XgWRA8AJr2rf/6XF8pqZhC4OvpsP+UP1XJz16L bD79bCvZHEHI9izNt3PwgKzPJ8y8V70b36mKwt2gJhrP3ue+fMOMxcH4nCwRpRGVU6G8olOBS+ FZ7BrRl5cN5FGJ4tnKXyhg6XYuGnLYAd5Spo5k3IPaeqVihedFuMlnY9w+kw3QUJiiZzKMMTuj pzwBCH/UEI2wMUnLmHF9xXiNklOqzwRtP5r4A0wmqqL0FVRy1ep/3sm9YEGWJKxv6UPEl8+tVx wmQ= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:content-type :mime-version:references:in-reply-to:x-mailer:message-id:date :subject:to:from; s=dkim; t=1650523014; x=1653115015; bh=ZgC2XGZ Nz9GOqFHwEiweZQEoaeQwoAuD6cvXgf97ucI=; b=h+LlDoQcFabKG5J2JJHBI/S hZl15DsUZ+Gkh/ZeLxe+aDWS89HJekypZ2RALeoAtkN32ajVF5i9ft73s9KAO1E2 WmpHZnvQLzJbYqHutQ8D+d00owog2mr7rIeq7rl8QOtx11X53+aU5pT6QAsGPex4 h0mfllANCuKzOCFzJyZSLArkwQrvAQrP+7yocwKZMYdLx4bVqmOvKJiKLry3LHwt 3gyJsL1gvHJVk1V7R22RE6UtFdVay1DZK9pnOTk8lbPiYE1lcy0KraDJDvCWjOy4 QbPL6c7BZqVzBZO22Hik9ehbeB6hnfWmeL5DR77SqTV24g9BcpYwjw7KZ6X9b1g= = X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Wilfred Mallawa , Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 02/31] riscv: opentitan: Connect opentitan SPI Host Date: Thu, 21 Apr 2022 16:36:01 +1000 Message-Id: <20220421063630.1033608-3-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650523874182100001 Content-Type: text/plain; charset="utf-8" From: Wilfred Mallawa Connect spi host[1/0] to opentitan. Signed-off-by: Wilfred Mallawa Reviewed-by: Alistair Francis Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220303045426.511588-2-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis --- include/hw/riscv/opentitan.h | 30 +++++++++++++++++++++--------- hw/riscv/opentitan.c | 36 ++++++++++++++++++++++++++++++++---- 2 files changed, 53 insertions(+), 13 deletions(-) diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h index 00da9ded43..68892cd8e5 100644 --- a/include/hw/riscv/opentitan.h +++ b/include/hw/riscv/opentitan.h @@ -23,11 +23,18 @@ #include "hw/intc/sifive_plic.h" #include "hw/char/ibex_uart.h" #include "hw/timer/ibex_timer.h" +#include "hw/ssi/ibex_spi_host.h" #include "qom/object.h" =20 #define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc" OBJECT_DECLARE_SIMPLE_TYPE(LowRISCIbexSoCState, RISCV_IBEX_SOC) =20 +enum { + OPENTITAN_SPI_HOST0, + OPENTITAN_SPI_HOST1, + OPENTITAN_NUM_SPI_HOSTS, +}; + struct LowRISCIbexSoCState { /*< private >*/ SysBusDevice parent_obj; @@ -37,6 +44,7 @@ struct LowRISCIbexSoCState { SiFivePLICState plic; IbexUartState uart; IbexTimerState timer; + IbexSPIHostState spi_host[OPENTITAN_NUM_SPI_HOSTS]; =20 MemoryRegion flash_mem; MemoryRegion rom; @@ -89,15 +97,19 @@ enum { }; =20 enum { - IBEX_TIMER_TIMEREXPIRED0_0 =3D 126, - IBEX_UART0_RX_PARITY_ERR_IRQ =3D 8, - IBEX_UART0_RX_TIMEOUT_IRQ =3D 7, - IBEX_UART0_RX_BREAK_ERR_IRQ =3D 6, - IBEX_UART0_RX_FRAME_ERR_IRQ =3D 5, - IBEX_UART0_RX_OVERFLOW_IRQ =3D 4, - IBEX_UART0_TX_EMPTY_IRQ =3D 3, - IBEX_UART0_RX_WATERMARK_IRQ =3D 2, - IBEX_UART0_TX_WATERMARK_IRQ =3D 1, + IBEX_UART0_TX_WATERMARK_IRQ =3D 1, + IBEX_UART0_RX_WATERMARK_IRQ =3D 2, + IBEX_UART0_TX_EMPTY_IRQ =3D 3, + IBEX_UART0_RX_OVERFLOW_IRQ =3D 4, + IBEX_UART0_RX_FRAME_ERR_IRQ =3D 5, + IBEX_UART0_RX_BREAK_ERR_IRQ =3D 6, + IBEX_UART0_RX_TIMEOUT_IRQ =3D 7, + IBEX_UART0_RX_PARITY_ERR_IRQ =3D 8, + IBEX_TIMER_TIMEREXPIRED0_0 =3D 126, + IBEX_SPI_HOST0_ERR_IRQ =3D 150, + IBEX_SPI_HOST0_SPI_EVENT_IRQ =3D 151, + IBEX_SPI_HOST1_ERR_IRQ =3D 152, + IBEX_SPI_HOST1_SPI_EVENT_IRQ =3D 153, }; =20 #endif diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 833624d66c..2d401dcb23 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -120,11 +120,18 @@ static void lowrisc_ibex_soc_init(Object *obj) object_initialize_child(obj, "uart", &s->uart, TYPE_IBEX_UART); =20 object_initialize_child(obj, "timer", &s->timer, TYPE_IBEX_TIMER); + + for (int i =3D 0; i < OPENTITAN_NUM_SPI_HOSTS; i++) { + object_initialize_child(obj, "spi_host[*]", &s->spi_host[i], + TYPE_IBEX_SPI_HOST); + } } =20 static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) { const MemMapEntry *memmap =3D ibex_memmap; + DeviceState *dev; + SysBusDevice *busdev; MachineState *ms =3D MACHINE(qdev_get_machine()); LowRISCIbexSoCState *s =3D RISCV_IBEX_SOC(dev_soc); MemoryRegion *sys_mem =3D get_system_memory(); @@ -209,14 +216,35 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev= _soc, Error **errp) qdev_get_gpio_in(DEVICE(qemu_get_cpu(0)), IRQ_M_TIMER)); =20 + /* SPI-Hosts */ + for (int i =3D 0; i < OPENTITAN_NUM_SPI_HOSTS; ++i) { + dev =3D DEVICE(&(s->spi_host[i])); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi_host[i]), errp)) { + return; + } + busdev =3D SYS_BUS_DEVICE(dev); + sysbus_mmio_map(busdev, 0, memmap[IBEX_DEV_SPI_HOST0 + i].base); + + switch (i) { + case OPENTITAN_SPI_HOST0: + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic= ), + IBEX_SPI_HOST0_ERR_IRQ)); + sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(&s->plic= ), + IBEX_SPI_HOST0_SPI_EVENT_IRQ)); + break; + case OPENTITAN_SPI_HOST1: + sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(DEVICE(&s->plic= ), + IBEX_SPI_HOST1_ERR_IRQ)); + sysbus_connect_irq(busdev, 1, qdev_get_gpio_in(DEVICE(&s->plic= ), + IBEX_SPI_HOST1_SPI_EVENT_IRQ)); + break; + } + } + create_unimplemented_device("riscv.lowrisc.ibex.gpio", memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size); create_unimplemented_device("riscv.lowrisc.ibex.spi_device", memmap[IBEX_DEV_SPI_DEVICE].base, memmap[IBEX_DEV_SPI_DEVICE].size= ); - create_unimplemented_device("riscv.lowrisc.ibex.spi_host0", - memmap[IBEX_DEV_SPI_HOST0].base, memmap[IBEX_DEV_SPI_HOST0].size); - create_unimplemented_device("riscv.lowrisc.ibex.spi_host1", - memmap[IBEX_DEV_SPI_HOST1].base, memmap[IBEX_DEV_SPI_HOST1].size); create_unimplemented_device("riscv.lowrisc.ibex.i2c", memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size); create_unimplemented_device("riscv.lowrisc.ibex.pattgen", --=20 2.35.1 From nobody Tue May 21 09:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650523681667776.8520283396274; Wed, 20 Apr 2022 23:48:01 -0700 (PDT) Received: from localhost ([::1]:47264 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhQbg-0005mz-6E for importer@patchew.org; Thu, 21 Apr 2022 02:48:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53470) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQR2-0004r3-DR for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:37:00 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:13303) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQR0-0007vC-Pu for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:37:00 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 21 Apr 2022 14:36:58 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:08:00 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:36:58 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KkSWF5bs4z1SVnx for ; Wed, 20 Apr 2022 23:36:57 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id racnkTBpioUt for ; Wed, 20 Apr 2022 23:36:57 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.119]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KkSWB6zF0z1Rvlx; Wed, 20 Apr 2022 23:36:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1650523018; x=1682059018; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UFx0II7r+/IMMvsE44IscHFSDYBmBDBN4/jnXYV89rU=; b=HeZpHEnZcGp0qRUCtGIQpPei0qbG7FAQ2LpM3eVCsRJVDzvskx9Kl1W/ +XDQUiKbBU8Tia42nHHjmPMgCQxfX0oZWeePFQyDMeGDkdATnF4TE9I9w MM1S+VE3CUhzKEA14EaGermPoTXj7bmxaRoVomWJEaasQoiM1lceDQjxr smScXXMqlklzHgivRYDH3zdr/k+4TWt39UH4JrGJHWlRaYjk96MWe7yNU YH+5tKyBufNNSrx/woo0FpDDpdFKIKoeBTB/cnGjQTH/3gDBBebiEmWu8 fZnrulEBB/fTJOy8y96YXR3kfQ+9YiYphPaUscRNij7SaC2rphKR7U3ls g==; X-IronPort-AV: E=Sophos;i="5.90,278,1643644800"; d="scan'208";a="302639933" IronPort-SDR: 3/6jhgZ1iZzQvYE4VbKnkngwC1aDpOxNfrjDUwvXbBq2GGb1LCLjyVm7ACVsSbjNhXFyX2WehD aKU9s1IdRqIW4NfBlYIEtHXgSzE37iHuP6QS1eQVdFWykYnYJvmjuf17PgNlUBXq23CHids4dx gWCeOTmx1IIDSaxMuKMwqEAUcyr8xphX0dpVG7rfSgZ9rL9otoxhowGUkJOLJBriK2oqgOSTNl lz9g7OZ2rqlWb9EjqeD8U5r4WK+tiF0FxkO1TJHMkWDlrf4jNddISZEUdTnyjmk6OMCouYuZI2 1YGIdOqZA4ek8RaReV/Why4k IronPort-SDR: vj2ntjoAHUu59NLGFold9oAdeNDPdMt24+x4IcjgPtZ9WHrQxzNJkSWr33WcbTW8Xev1KlrS9H xsvuWz7uG2zPYGDuWRUKiqg0JeR3nCEAoLMpv5s6sMjVD89FsuDpab+QZRXldtVdur+hp3OiMT OV53bKAeBMJiqSXHSdyH41s43uepFrH7QAeBATRFkQ+Q7B122QKuVnWgP7IBC0aXtXLqqu4gV1 W5V79Dllb7aknbMC3/Pc8aRjjdqyCN0TDHPW2QpKR3FUyY8yd1tsBCoG/sVcIKnD534iEnzAWJ KcM= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1650523017; x=1653115018; bh=UFx0II7r+/IMMvsE44 IscHFSDYBmBDBN4/jnXYV89rU=; b=ZLAwDijsjeV3jKNgsCjrVmssL/cU+UkPld PPIdVhWz5RMhXvpyVtFjbJ3WBM7/1fDrEIeeCend6D3GczdjchOd8fIvjSkjGBAS uWNa9ZdaDBtl2p/yvH5H02/eJrV+je++Pl8A2pf5yvrvpmuk/aMHiULZLOcA5EXa ExlyWKHjNBhYkZvmte3h2FdRMQH/OIY1uqM01JdzwWw21wv2pUcxwotUzTaOIJQX AUVbE+mouCdja6Xo7QX2HfeD7aXmG46F+kYaIWO8OWIvgOr8B/X+FijLadAhaUJP jQX5WQ/IPwUqTqUR7RkOpz3xGSjJp+eHx8AmLPFPmiQcq4XfMoww== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Atish Patra , Richard Henderson , Alistair Francis Subject: [PULL 03/31] target/riscv: Define simpler privileged spec version numbering Date: Thu, 21 Apr 2022 16:36:02 +1000 Message-Id: <20220421063630.1033608-4-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650523682500100001 Content-Type: text/plain; charset="utf-8" From: Atish Patra Currently, the privileged specification version are defined in a complex manner for no benefit. Simplify it by changing it to a simple enum based on. Suggested-by: Richard Henderson Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-Id: <20220303185440.512391-2-atishp@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index e1d976bdef..0d63786ece 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -82,8 +82,11 @@ enum { RISCV_FEATURE_AIA }; =20 -#define PRIV_VERSION_1_10_0 0x00011000 -#define PRIV_VERSION_1_11_0 0x00011100 +/* Privileged specification version */ +enum { + PRIV_VERSION_1_10_0 =3D 0, + PRIV_VERSION_1_11_0, +}; =20 #define VEXT_VERSION_1_00_0 0x00010000 =20 --=20 2.35.1 From nobody Tue May 21 09:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165052400460751.5270552941995; Wed, 20 Apr 2022 23:53:24 -0700 (PDT) Received: from localhost ([::1]:55820 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhQgt-0003ST-JL for importer@patchew.org; Thu, 21 Apr 2022 02:53:23 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53490) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQR5-0004ti-0j for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:37:03 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:13303) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQR3-0007vC-9n for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:37:02 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 21 Apr 2022 14:37:00 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:08:03 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:37:01 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KkSWJ2Rvfz1SVnx for ; Wed, 20 Apr 2022 23:37:00 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id rTS58kmjRLPy for ; Wed, 20 Apr 2022 23:37:00 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.119]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KkSWG0JlDz1Rvlx; Wed, 20 Apr 2022 23:36:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1650523021; x=1682059021; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=fhDY4ISUrE/lXX0U0FSMThvCPL/bGsVI5kG8GJaiJVw=; b=I4LwoSBrpBe1FdaSyYnc6jFsboLF3pPxSjV7lhxfycVAcKDx12bUkaKz UDMbGERSYyOfHVNeVg7sw4lUuk5m50ttVCkQedTM0OqBZ8CxqSFN3ptDi n7R9Uawg3wSy6FGeydgBST4Z6xA5wWL+dls7dGUCP6uuJZ+okaEA5i09D xgXjP60vuOXXzOCB15NhDSVlzep/vooEIyZSH4+OuTs21vUyC0mnik8ED jxH4k97afcglpIGuO8cTCAkD9iNX1JETscSNwWfSm4ipANQbCix58FjvT 5sbBnskwY58u9K6cV2UXXPGfHLl7yffNe0xBPOZcccU0boyLunfycB0G8 Q==; X-IronPort-AV: E=Sophos;i="5.90,278,1643644800"; d="scan'208";a="302639936" IronPort-SDR: dPwsPvIZul9nrfzoXyC03eGY2tlljoN7aFMw6QeHa+VKqIjO/Ina3u93/Gx3VUtFQlKVz8xoFJ +8WwKx8ySSaJK0YfzZs4N+p6GdKh9d2yUieVLHEEKyMp6iIRkr/9V3dOythZdvBPVvEez3dR8M o/BWe1C+2FVau43RCIa4Ceh6JdNPmlQ/g7h3bHhyRyglUdsZi9mJn20RiMvsaLNfCDOp67NfFr /jp+hQ43UcZnD34P16+RX9h7QlIAIw14ZYBFT5n9hWKtkZTmt4KSfiuGsWA4CZsxZzWiN167mP JizMSkjJMEVUYW5txNQZKE+1 IronPort-SDR: mh+BQhfHH+eXZIJYcuREsrjfFxq0wht9JdGn8D59MfJ+3FCDriIIxtXVMEPFEeKtD/M0Grwtdl Lr/kA+2zHgAViCIBf5/1aXASxAEG6Bap2AEIcKy3PXo4Bcz+C78GCtcTeQZ6QE55J8FYNozqfx BfXFzHceiZLu+L/e3ohkWd7q+6ryleO68w/C7RBuDcRj/feN+LRpGF2YZGIKJVqtw58/Et0xF2 aIQ7omhAGW7QdHlzTIKzla6jyNyR/LK3jfkAkKNEPdFr2eH/z/f/ZFfo3dg4wyX1VTnhzjKSoj aaQ= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1650523020; x=1653115021; bh=fhDY4ISUrE/lXX0U0F SMThvCPL/bGsVI5kG8GJaiJVw=; b=BbzqKskniAnYP7TfDlRy1GIIN7RFAxu13M 3IN4ISHBHhubgp++kQCbFfDl92beepX0j/hiUfCutogkzbvpFkWpv+9Y9Pu1U+3f NL2sPIUzxfEQ1EG1ktYrXKzc2mrk8kG0Jr8k5qwjENuK8lvvb+a7tmdIczSYKDa8 fJkB/kSe/jO5Jb0JEXm9U8AxAuFEcJe1/C+UeOY3Tq/iYcHi3/SAfw/Y3zAMI9Al aYprYjcLexyy+OjsziT6/Wzi6pgr6YmgwqlR0iY5Ts9X721owJ18h3MlteIkNkjg 4hNkTcbvslJvROGa821ybyT6lynKBTfTR7kfQzBNl9h3gyKPeR2A== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Atish Patra , Alistair Francis Subject: [PULL 04/31] target/riscv: Add the privileged spec version 1.12.0 Date: Thu, 21 Apr 2022 16:36:03 +1000 Message-Id: <20220421063630.1033608-5-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650524006778100001 Content-Type: text/plain; charset="utf-8" From: Atish Patra Add the definition for ratified privileged specification version v1.12 Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-Id: <20220303185440.512391-3-atishp@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0d63786ece..0f3ed88f04 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -86,6 +86,7 @@ enum { enum { PRIV_VERSION_1_10_0 =3D 0, PRIV_VERSION_1_11_0, + PRIV_VERSION_1_12_0, }; =20 #define VEXT_VERSION_1_00_0 0x00010000 --=20 2.35.1 From nobody Tue May 21 09:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650524312223977.7925297462964; Wed, 20 Apr 2022 23:58:32 -0700 (PDT) Received: from localhost ([::1]:33396 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhQlo-0007Wz-6i for importer@patchew.org; Thu, 21 Apr 2022 02:58:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53522) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQR8-0004xQ-OI for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:37:06 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:13303) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQR6-0007vC-LF for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:37:06 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 21 Apr 2022 14:37:03 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:08:06 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:37:04 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KkSWM2Svpz1SVp1 for ; Wed, 20 Apr 2022 23:37:03 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id 1J2_kd6zpkiX for ; Wed, 20 Apr 2022 23:37:02 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.119]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KkSWJ51w6z1Rvlx; Wed, 20 Apr 2022 23:37:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1650523024; x=1682059024; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0AQADVTjrYUVUCkfogfTVgDDTKhSthvqYgTuHQlYhm0=; b=gaL6+H+VUmQQjvP4Sx5peTmKIffDwKaR/xnLCNwbJiaSQ/IEMyNe50j8 465wOpmd5H4fT0G3W4ne9aZmC2rhrjwM5KgLb0voLMpjO/JkYy74hdfq4 DI/vdMiqo4hvSQ1NMb6G+oZBShfVtJVbO7yATNCPRXaTk6t1AV08HXpX/ YZEh4SP2SmYBzwzF8rYtWqU2+/OduPohkeknvKBNQiUz3HiidhaOd9Q2E R5a56nEkJ/NdN3oXK1jz3FiH+v3zJSQynanymhm1R2Dkl4E5bMk8/SrV2 MSxnj6sPfrcy6OlbH+IW5l1aC0Mpgk4FMB3e1db+gytPOpxv9mcnYiVfd Q==; X-IronPort-AV: E=Sophos;i="5.90,278,1643644800"; d="scan'208";a="302639941" IronPort-SDR: 7+VJqCesimzxk1U6MqbqWrbQbhufnYkd7oD0753A2cHJ0I4GBm8tvRrZEcee3t2AE2DqtcPIFx Fq+xcHxwa/O4sBMlGQqx/AdPTKIoZWJskAwnufo/RcjoBwhr0tvIyeE8JteMlIK2ZPoA25XHCv fbXXa3GUX9tIPQez0/lTzsmn+WZg8TQges9wPS1YkwAVSaO1ZossFydnIUPnVsUvhzg8Y78Ds8 iBUTw7+yCC8MdnE6ZrPO18pZlYfe3nL+N1+qZc28oydxDP7SNe8GFnCmqllkl+eVy5vyIU2+s1 N2D8Puva0k9AtSkS5o6v34EM IronPort-SDR: maeFZTrLJNIR8AEiJUMEO53qJb6uvTfwnLNFJ3uEOzMWexWy7W88atMc+8Pe16ZAzjPtui6u0G 6CbqckQL7lf5op0PqtjcLjL9NU4CT74+Ym91iXDEPZUCnkiNilelatyGYevXmlBMKK3PexNktE vCTC1aShgpV83slHe1cLLPfsdPDdD/cHEQ22olayVu2kwK0WgMVFxl9bHCgfZfMvXrAAZ/xzpI XMbvpBCDGjpOf5JOgvSUTuJa+9WIqe68IpqixU2lge2stAnMLkrbTdVCcC2ZsZjLWaBRG5Z0bE GDM= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1650523022; x=1653115023; bh=0AQADVTjrYUVUCkfog fTVgDDTKhSthvqYgTuHQlYhm0=; b=mFzaAxYBXrpRNjb+ns1pUKf+JCRGuaDa6z nZZexE9v6swZhnfpFzVYxMQ96NB/qNxHuyJ7FHC6w2FbPvkg+qYV+ZIiHFId7yuC LKuB+HPPHaUwsn7qq1i71FUZdrKBkEtD9Lv1DSEZhdePzZYFCBbYZklUNFPy1iK4 BShz6tapS31//wEuTNgFxB6rmj/6RwB5DtT/nc/INAMyAOgnnbosx/m7v7ydOm5Q i8uLcyj21HijZFTdkxHkwKxtGwZwW1qOJrxFmGOl2A5dyFyOjdPxSyy8BtoZwikn o4jRPEmq/P60ANpUr3xVo+RglU1saCtkmfYHUtVdF2rgeS5pUbMg== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Atish Patra , Alistair Francis Subject: [PULL 05/31] target/riscv: Introduce privilege version field in the CSR ops. Date: Thu, 21 Apr 2022 16:36:04 +1000 Message-Id: <20220421063630.1033608-6-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650524314443100001 Content-Type: text/plain; charset="utf-8" From: Atish Patra To allow/disallow the CSR access based on the privilege spec, a new field in the csr_ops is introduced. It also adds the privileged specification version (v1.12) for the CSRs introduced in the v1.12. This includes the new ratified extensions such as Vector, Hypervisor and secconfig CSR. However, it doesn't enforce the privilege version in this commit. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-Id: <20220303185440.512391-4-atishp@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 2 + target/riscv/csr.c | 103 ++++++++++++++++++++++++++++++--------------- 2 files changed, 70 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 0f3ed88f04..7a92892cd6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -658,6 +658,8 @@ typedef struct { riscv_csr_op_fn op; riscv_csr_read128_fn read128; riscv_csr_write128_fn write128; + /* The default priv spec version should be PRIV_VERSION_1_10_0 (i.e 0)= */ + uint32_t min_priv_ver; } riscv_csr_operations; =20 /* CSR function table constants */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 341c2e6f23..1400027158 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3070,13 +3070,20 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_FRM] =3D { "frm", fs, read_frm, write_frm }, [CSR_FCSR] =3D { "fcsr", fs, read_fcsr, write_fcsr }, /* Vector CSRs */ - [CSR_VSTART] =3D { "vstart", vs, read_vstart, write_vstart }, - [CSR_VXSAT] =3D { "vxsat", vs, read_vxsat, write_vxsat }, - [CSR_VXRM] =3D { "vxrm", vs, read_vxrm, write_vxrm }, - [CSR_VCSR] =3D { "vcsr", vs, read_vcsr, write_vcsr }, - [CSR_VL] =3D { "vl", vs, read_vl }, - [CSR_VTYPE] =3D { "vtype", vs, read_vtype }, - [CSR_VLENB] =3D { "vlenb", vs, read_vlenb }, + [CSR_VSTART] =3D { "vstart", vs, read_vstart, write_vstart, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_VXSAT] =3D { "vxsat", vs, read_vxsat, write_vxsat, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_VXRM] =3D { "vxrm", vs, read_vxrm, write_vxrm, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_VCSR] =3D { "vcsr", vs, read_vcsr, write_vcsr, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_VL] =3D { "vl", vs, read_vl, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_VTYPE] =3D { "vtype", vs, read_vtype, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_VLENB] =3D { "vlenb", vs, read_vlenb, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, /* User Timers and Counters */ [CSR_CYCLE] =3D { "cycle", ctr, read_instret }, [CSR_INSTRET] =3D { "instret", ctr, read_instret }, @@ -3185,33 +3192,58 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_SIEH] =3D { "sieh", aia_smode32, NULL, NULL, rmw_sieh }, [CSR_SIPH] =3D { "siph", aia_smode32, NULL, NULL, rmw_siph }, =20 - [CSR_HSTATUS] =3D { "hstatus", hmode, read_hstatus, writ= e_hstatus }, - [CSR_HEDELEG] =3D { "hedeleg", hmode, read_hedeleg, writ= e_hedeleg }, - [CSR_HIDELEG] =3D { "hideleg", hmode, NULL, NULL, rmw_= hideleg }, - [CSR_HVIP] =3D { "hvip", hmode, NULL, NULL, rmw_= hvip }, - [CSR_HIP] =3D { "hip", hmode, NULL, NULL, rmw_= hip }, - [CSR_HIE] =3D { "hie", hmode, NULL, NULL, rmw_= hie }, - [CSR_HCOUNTEREN] =3D { "hcounteren", hmode, read_hcounteren, writ= e_hcounteren }, - [CSR_HGEIE] =3D { "hgeie", hmode, read_hgeie, writ= e_hgeie }, - [CSR_HTVAL] =3D { "htval", hmode, read_htval, writ= e_htval }, - [CSR_HTINST] =3D { "htinst", hmode, read_htinst, writ= e_htinst }, - [CSR_HGEIP] =3D { "hgeip", hmode, read_hgeip, NULL= }, - [CSR_HGATP] =3D { "hgatp", hmode, read_hgatp, writ= e_hgatp }, - [CSR_HTIMEDELTA] =3D { "htimedelta", hmode, read_htimedelta, writ= e_htimedelta }, - [CSR_HTIMEDELTAH] =3D { "htimedeltah", hmode32, read_htimedeltah, writ= e_htimedeltah }, - - [CSR_VSSTATUS] =3D { "vsstatus", hmode, read_vsstatus, writ= e_vsstatus }, - [CSR_VSIP] =3D { "vsip", hmode, NULL, NULL, rmw_= vsip }, - [CSR_VSIE] =3D { "vsie", hmode, NULL, NULL, rmw_= vsie }, - [CSR_VSTVEC] =3D { "vstvec", hmode, read_vstvec, writ= e_vstvec }, - [CSR_VSSCRATCH] =3D { "vsscratch", hmode, read_vsscratch, writ= e_vsscratch }, - [CSR_VSEPC] =3D { "vsepc", hmode, read_vsepc, writ= e_vsepc }, - [CSR_VSCAUSE] =3D { "vscause", hmode, read_vscause, writ= e_vscause }, - [CSR_VSTVAL] =3D { "vstval", hmode, read_vstval, writ= e_vstval }, - [CSR_VSATP] =3D { "vsatp", hmode, read_vsatp, writ= e_vsatp }, - - [CSR_MTVAL2] =3D { "mtval2", hmode, read_mtval2, writ= e_mtval2 }, - [CSR_MTINST] =3D { "mtinst", hmode, read_mtinst, writ= e_mtinst }, + [CSR_HSTATUS] =3D { "hstatus", hmode, read_hstatus, write_= hstatus, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_HEDELEG] =3D { "hedeleg", hmode, read_hedeleg, write_= hedeleg, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_HIDELEG] =3D { "hideleg", hmode, NULL, NULL, rmw_hide= leg, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_HVIP] =3D { "hvip", hmode, NULL, NULL, rmw_hv= ip, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_HIP] =3D { "hip", hmode, NULL, NULL, rmw_hi= p, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_HIE] =3D { "hie", hmode, NULL, NULL, rmw_h= ie, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_HCOUNTEREN] =3D { "hcounteren", hmode, read_hcounteren, write= _hcounteren, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_HGEIE] =3D { "hgeie", hmode, read_hgeie, writ= e_hgeie, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_HTVAL] =3D { "htval", hmode, read_htval, write_= htval, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_HTINST] =3D { "htinst", hmode, read_htinst, write_= htinst, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_HGEIP] =3D { "hgeip", hmode, read_hgeip, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_HGATP] =3D { "hgatp", hmode, read_hgatp, write_= hgatp, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_HTIMEDELTA] =3D { "htimedelta", hmode, read_htimedelta, write= _htimedelta, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_HTIMEDELTAH] =3D { "htimedeltah", hmode32, read_htimedeltah, writ= e_htimedeltah, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + + [CSR_VSSTATUS] =3D { "vsstatus", hmode, read_vsstatus, write_= vsstatus, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_VSIP] =3D { "vsip", hmode, NULL, NULL, rmw_vs= ip, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_VSIE] =3D { "vsie", hmode, NULL, NULL, rmw_= vsie , + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_VSTVEC] =3D { "vstvec", hmode, read_vstvec, write_= vstvec, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_VSSCRATCH] =3D { "vsscratch", hmode, read_vsscratch, write_= vsscratch, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_VSEPC] =3D { "vsepc", hmode, read_vsepc, write_= vsepc, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_VSCAUSE] =3D { "vscause", hmode, read_vscause, write_= vscause, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_VSTVAL] =3D { "vstval", hmode, read_vstval, write_= vstval, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_VSATP] =3D { "vsatp", hmode, read_vsatp, write_= vsatp, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + + [CSR_MTVAL2] =3D { "mtval2", hmode, read_mtval2, write_= mtval2, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, + [CSR_MTINST] =3D { "mtinst", hmode, read_mtinst, write_= mtinst, + .min_priv_ver =3D PRIV_VERSION_1_= 12_0 }, =20 /* Virtual Interrupts and Interrupt Priorities (H-extension with AIA) = */ [CSR_HVIEN] =3D { "hvien", aia_hmode, read_zero, write_ign= ore }, @@ -3245,7 +3277,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_VSIPH] =3D { "vsiph", aia_hmode32, NULL, NULL, rmw_vs= iph }, =20 /* Physical Memory Protection */ - [CSR_MSECCFG] =3D { "mseccfg", epmp, read_mseccfg, write_mseccfg }, + [CSR_MSECCFG] =3D { "mseccfg", epmp, read_mseccfg, write_mseccfg, + .min_priv_ver =3D PRIV_VERSION_1_12_0= }, [CSR_PMPCFG0] =3D { "pmpcfg0", pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPCFG1] =3D { "pmpcfg1", pmp, read_pmpcfg, write_pmpcfg }, [CSR_PMPCFG2] =3D { "pmpcfg2", pmp, read_pmpcfg, write_pmpcfg }, --=20 2.35.1 From nobody Tue May 21 09:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650523750622566.5834134489486; Wed, 20 Apr 2022 23:49:10 -0700 (PDT) Received: from localhost ([::1]:48692 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhQcm-0006lr-GG for importer@patchew.org; Thu, 21 Apr 2022 02:49:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53540) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQRA-00050u-JR for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:37:08 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:13313) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQR8-0007wT-TS for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:37:08 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 21 Apr 2022 14:37:05 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:08:08 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:37:06 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KkSWP3RgXz1SHwl for ; Wed, 20 Apr 2022 23:37:05 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id BNNeZPFEk2nX for ; Wed, 20 Apr 2022 23:37:05 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.119]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KkSWM1yckz1SVnx; Wed, 20 Apr 2022 23:37:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1650523026; x=1682059026; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=mIE9dCUX/jW+hjEy3ZZiVtVl9b76i9LoJDy8JKCEnJQ=; b=kAHCqj62tOS01ow6TCAQPS2/VwybTt1wsop2Axv2BNOIph4l5PW0nnMg eLYZoRrPghM3TTIowtjGj7Z0eNHlsjgUj1icdZ/PgUTXY+nLLRKJsjWE8 /FvemkbkJetTS3oWiy13NsVYXl+dCEgwES/Zab1t4IIisN4PYkZwNgdkx 0Ek1SZXHTsCp2wF2sAwPcdtzwcT8X1dgmKFTXxJIFtR0AkzdZIcXJdV7w 53MMcyniVyAJLsqGv5DIMOTTKUBXggEm6xwazprEgV3ZF5JP/BLvcAezo pr8CJYg3mY6V6LyvdtOFt7vSHKxcfiCCBzoHx7vJRT4M4PPNs5p2MEcaC g==; X-IronPort-AV: E=Sophos;i="5.90,278,1643644800"; d="scan'208";a="302639944" IronPort-SDR: JQg1ZGt2xEAhI1QhQkHzjN1qXHxcdf2sLHQzxv/m6rMWcEC7YKH1kRqnF/O0CXueyK61a+cgGk 6mH3wtBMaSPsGfvbJS7sI+6sIVNtFyQNoWCiF03r/3HqRJNAEIK9Tu6gmA3PgOH8mgAsvCq9st efJ10hJMBUZ/ukYsZvwIvvIp9TI2u+5IwtubHqY6n23J+L7tas9W4N/MpcjEv+gxss13cSNfFn 3+pMCneMbtexVKQ/0xPq2yxCRF6n+0dx8VfsnBN4kE8XnLuwEU0AqxUv7vrQmCmyUUvptgD6pC KxnJgnkrNADxyk/1a7f8i1lE IronPort-SDR: UUVGqwCVpQZJbJwkj1GmGNnkR9MN4FxybTSeCZtPukNwy6qUZMieaofqzce6mSUf/kikM3s788 hmwwiJhlInjVDUwsqHReN6gNaZ4hfQ6ler3/1EdEIeLjSgQgiCNQI/c3DOVHUhZv5gyp8qIdaP GmjVFQB/lE9wiO1KS0vFTeAHiMhklFgfV7QoMlV+409slCKH3LwoF5v+l1S9WduGFyANJfuSkc b5ptV1j5dxYgqZ/fvs/JBaOsmife2RJkLx45Kpj8R8M0o9h1VxlXf+orKgIuEEf+GnafWSg6Dm D1I= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1650523025; x=1653115026; bh=mIE9dCUX/jW+hjEy3Z ZiVtVl9b76i9LoJDy8JKCEnJQ=; b=KwWveOEbe0PSsVU/YVEHO4MP2Vl9SL7784 ezwv19bB1B3NEDMIq+sBwzvDO3YMtjNfbBYg7uVslGjwNuMlwbVgkRTJ3VqUIPl9 Ne/eewdWpXjAHUbMOeBVfCZsDgM/CjVO8wLidNVwFAte937pLgQsrFKL6N6rtmu8 ggEiwBvfZ5DiMn/s2fIvVIuzNJWLXn1ZVD/UomQi8EuzrYH41TRxN68x4Qic0Aai 7LSuqnsijUmdpVj8rJXIpzSJmP+lHemtLlZ4ti1yuf/2+IrvvVZ/9xXpyY1/FnSp VEkimDlX7P1UWhYP7HAP8KM/akF8J8lSyw86PzId4UTE3zJS5h8Q== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Atish Patra , Alistair Francis Subject: [PULL 06/31] target/riscv: Add support for mconfigptr Date: Thu, 21 Apr 2022 16:36:05 +1000 Message-Id: <20220421063630.1033608-7-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650523752768100001 Content-Type: text/plain; charset="utf-8" From: Atish Patra RISC-V privileged specification v1.12 introduced a mconfigptr which will hold the physical address of a configuration data structure. As Qemu doesn't have a configuration data structure, is read as zero which is valid as per the priv spec. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-Id: <20220303185440.512391-5-atishp@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu_bits.h | 1 + target/riscv/csr.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 0fe01d7da5..48d92a81c3 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -148,6 +148,7 @@ #define CSR_MARCHID 0xf12 #define CSR_MIMPID 0xf13 #define CSR_MHARTID 0xf14 +#define CSR_MCONFIGPTR 0xf15 =20 /* Machine Trap Setup */ #define CSR_MSTATUS 0x300 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 1400027158..6590cc8aa7 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3110,6 +3110,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MIMPID] =3D { "mimpid", any, read_zero }, [CSR_MHARTID] =3D { "mhartid", any, read_mhartid }, =20 + [CSR_MCONFIGPTR] =3D { "mconfigptr", any, read_zero, + .min_priv_ver =3D PRIV_VERSION_1_1= 2_0 }, /* Machine Trap Setup */ [CSR_MSTATUS] =3D { "mstatus", any, read_mstatus, write_m= status, NULL, read_mstatus_i128 = }, --=20 2.35.1 From nobody Tue May 21 09:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650524053629709.9092402327635; Wed, 20 Apr 2022 23:54:13 -0700 (PDT) Received: from localhost ([::1]:57186 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhQhg-0004Oz-FT for importer@patchew.org; Thu, 21 Apr 2022 02:54:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53582) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQRF-00059X-Cv for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:37:13 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:13321) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQRD-0007wz-BT for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:37:13 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 21 Apr 2022 14:37:10 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:08:12 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:37:10 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KkSWT6PFTz1SHwl for ; Wed, 20 Apr 2022 23:37:09 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id s2gN6uAkzuAz for ; Wed, 20 Apr 2022 23:37:09 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.119]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KkSWQ2N73z1Rvlx; Wed, 20 Apr 2022 23:37:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1650523031; x=1682059031; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=4PC5cmhiA/VscMc7l+/UctJxXA0S+Ha0rF+NodFEV30=; b=i22hS+YQ52Mq2jMRE07XgUMc8qpHDSb+MwrlFBPHY7auqZYdr+t+hrJt UwsHhYeme85q/QTp1ExAU4TBWeufNUZm+j0loDNQVlXMX+Qen+JkK/Xci dOFnOueaUxj61hJX+GjhDyn7QVI5YSvwiZw+tzp2S9UraiCacU3a6cAl0 FmG7azCRZvPl7IKCaHfLSofYqG2ayyKyljmSZD/aFFnfv49vlRVHOT7X7 nutvd1d2uJboCdx3z6e+Y9fokP5jzwsT/pP40V3EUXaVu8R0c/245wD0l 5QWDtdfmz/mUdm0jXStYe3nNAUgteeh57FI5bG+YGxdrra1guUAv2NMZh g==; X-IronPort-AV: E=Sophos;i="5.90,278,1643644800"; d="scan'208";a="302639948" IronPort-SDR: atqnvi4FT+fziUQt5mEBuy+9EoHS7NftiwQqb9+dxZoXmvdsFdjTg5xGIxCKzLTyI4BUdFrIgv WXVro1h7RIBER5C7yUygSg8JNHB8Rtm/Y/QvtQTMeh8aJk7c9YbDsL16PNdpN35xUohTWhQVFH 5eZB0zlMzFByXkSxfbGNlPqx00szUwFMSJ2f3EBirpA98yvH9TItulChjT1KLIfJpWYrm1Acsi c0fMhi6nH8ENwVMtdw8ovojQJeVzVWVlWXzr+v9w1Jtqs6cuKCBh5ERMEFQFaioalepagVsnUj nLi8T+BrSQaie7fC02I0/LR9 IronPort-SDR: MX50LrkXLPqGt7QfHhcfO+85V5ZPLFdBXfeuHM4qw8nQ/NpRbiG1GYxEFo8t/LV0uvSeNovhQw G1qUmiiTNC5DjEulQENLLKYIaIT6pDVgyBQK8lYwO6tzgkYbfsc8pgDjb893DGcu4WEsnTjJnP cvx8PQ0jkkW9zBeeBrgFvn8H3oV6qPa1UW4BaVIrR4cruJf9BYB1GjG3x+Ug2MwViu1461DL9M PVG5LZ/4zLMzUvzn59SHTeiX+7ad/IDBSRlciH+3Fijl3vNxrviEmRyqixcr6iNqUaqW74xKzt dUY= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1650523029; x=1653115030; bh=4PC5cmhiA/VscMc7l+ /UctJxXA0S+Ha0rF+NodFEV30=; b=tt6BPyRzJejBH0oX2goF2imCaCJfNzGQWh bmJ0Th7nMU9dhrxb60CgU+JoZZj7lBPDubfUvrevmiW0pm8K3jkyEjvhGLxbTElC +0ODFijcPEWItFXsnIea2aptoIbV8jcivbS/vpwwQcDSU2Y1KYsk6bDv6bShCEU7 nVAF7wc7P8d8qRCzLEQ4vZWsDBIBBs3rWlaHwN+o3GoQaYYXOCfO0m3pPddwUA5q y0zCVbFXtt6Z+kR51Sny7WX7wiOAdWS5AEwvjh4z68SF2qHudsaQaFVCLN6nz9TQ IDd+PxbkQgUCJ3OBpwA6fD8q/Gi5dNv0M9grqW+K0e1N6yypSS+A== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Atish Patra , Alistair Francis Subject: [PULL 07/31] target/riscv: Add *envcfg* CSRs support Date: Thu, 21 Apr 2022 16:36:06 +1000 Message-Id: <20220421063630.1033608-8-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650524055026100001 Content-Type: text/plain; charset="utf-8" From: Atish Patra The RISC-V privileged specification v1.12 defines few execution environment configuration CSRs that can be used enable/disable extensions per privilege levels. Add the basic support for these CSRs. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-Id: <20220303185440.512391-6-atishp@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 5 ++ target/riscv/cpu_bits.h | 39 +++++++++++++++ target/riscv/csr.c | 107 ++++++++++++++++++++++++++++++++++++++++ target/riscv/machine.c | 23 +++++++++ 4 files changed, 174 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 7a92892cd6..1ef1b9162f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -304,6 +304,11 @@ struct CPUArchState { target_ulong spmbase; target_ulong upmmask; target_ulong upmbase; + + /* CSRs for execution enviornment configuration */ + uint64_t menvcfg; + target_ulong senvcfg; + uint64_t henvcfg; #endif target_ulong cur_pmmask; target_ulong cur_pmbase; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 48d92a81c3..bb47cf7e77 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -202,6 +202,9 @@ #define CSR_STVEC 0x105 #define CSR_SCOUNTEREN 0x106 =20 +/* Supervisor Configuration CSRs */ +#define CSR_SENVCFG 0x10A + /* Supervisor Trap Handling */ #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 @@ -247,6 +250,10 @@ #define CSR_HTIMEDELTA 0x605 #define CSR_HTIMEDELTAH 0x615 =20 +/* Hypervisor Configuration CSRs */ +#define CSR_HENVCFG 0x60A +#define CSR_HENVCFGH 0x61A + /* Virtual CSRs */ #define CSR_VSSTATUS 0x200 #define CSR_VSIE 0x204 @@ -290,6 +297,10 @@ #define CSR_VSIEH 0x214 #define CSR_VSIPH 0x254 =20 +/* Machine Configuration CSRs */ +#define CSR_MENVCFG 0x30A +#define CSR_MENVCFGH 0x31A + /* Enhanced Physical Memory Protection (ePMP) */ #define CSR_MSECCFG 0x747 #define CSR_MSECCFGH 0x757 @@ -663,6 +674,34 @@ typedef enum RISCVException { #define PM_EXT_CLEAN 0x00000002ULL #define PM_EXT_DIRTY 0x00000003ULL =20 +/* Execution enviornment configuration bits */ +#define MENVCFG_FIOM BIT(0) +#define MENVCFG_CBIE (3UL << 4) +#define MENVCFG_CBCFE BIT(6) +#define MENVCFG_CBZE BIT(7) +#define MENVCFG_PBMTE BIT(62) +#define MENVCFG_STCE BIT(63) + +/* For RV32 */ +#define MENVCFGH_PBMTE BIT(30) +#define MENVCFGH_STCE BIT(31) + +#define SENVCFG_FIOM MENVCFG_FIOM +#define SENVCFG_CBIE MENVCFG_CBIE +#define SENVCFG_CBCFE MENVCFG_CBCFE +#define SENVCFG_CBZE MENVCFG_CBZE + +#define HENVCFG_FIOM MENVCFG_FIOM +#define HENVCFG_CBIE MENVCFG_CBIE +#define HENVCFG_CBCFE MENVCFG_CBCFE +#define HENVCFG_CBZE MENVCFG_CBZE +#define HENVCFG_PBMTE MENVCFG_PBMTE +#define HENVCFG_STCE MENVCFG_STCE + +/* For RV32 */ +#define HENVCFGH_PBMTE MENVCFGH_PBMTE +#define HENVCFGH_STCE MENVCFGH_STCE + /* Offsets for every pair of control bits per each priv level */ #define XS_OFFSET 0ULL #define U_OFFSET 2ULL diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6590cc8aa7..84a398b205 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1398,6 +1398,101 @@ static RISCVException write_mtval(CPURISCVState *en= v, int csrno, return RISCV_EXCP_NONE; } =20 +/* Execution environment configuration setup */ +static RISCVException read_menvcfg(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->menvcfg; + return RISCV_EXCP_NONE; +} + +static RISCVException write_menvcfg(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mask =3D MENVCFG_FIOM | MENVCFG_CBIE | MENVCFG_CBCFE | MENVCF= G_CBZE; + + if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { + mask |=3D MENVCFG_PBMTE | MENVCFG_STCE; + } + env->menvcfg =3D (env->menvcfg & ~mask) | (val & mask); + + return RISCV_EXCP_NONE; +} + +static RISCVException read_menvcfgh(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->menvcfg >> 32; + return RISCV_EXCP_NONE; +} + +static RISCVException write_menvcfgh(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mask =3D MENVCFG_PBMTE | MENVCFG_STCE; + uint64_t valh =3D (uint64_t)val << 32; + + env->menvcfg =3D (env->menvcfg & ~mask) | (valh & mask); + + return RISCV_EXCP_NONE; +} + +static RISCVException read_senvcfg(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->senvcfg; + return RISCV_EXCP_NONE; +} + +static RISCVException write_senvcfg(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mask =3D SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCF= G_CBZE; + + env->senvcfg =3D (env->senvcfg & ~mask) | (val & mask); + + return RISCV_EXCP_NONE; +} + +static RISCVException read_henvcfg(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->henvcfg; + return RISCV_EXCP_NONE; +} + +static RISCVException write_henvcfg(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mask =3D HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCF= G_CBZE; + + if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { + mask |=3D HENVCFG_PBMTE | HENVCFG_STCE; + } + + env->henvcfg =3D (env->henvcfg & ~mask) | (val & mask); + + return RISCV_EXCP_NONE; +} + +static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->henvcfg >> 32; + return RISCV_EXCP_NONE; +} + +static RISCVException write_henvcfgh(CPURISCVState *env, int csrno, + target_ulong val) +{ + uint64_t mask =3D HENVCFG_PBMTE | HENVCFG_STCE; + uint64_t valh =3D (uint64_t)val << 32; + + env->henvcfg =3D (env->henvcfg & ~mask) | (valh & mask); + + return RISCV_EXCP_NONE; +} + static RISCVException rmw_mip64(CPURISCVState *env, int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) @@ -3158,6 +3253,18 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MVIPH] =3D { "mviph", aia_any32, read_zero, write_ignore }, [CSR_MIPH] =3D { "miph", aia_any32, NULL, NULL, rmw_miph }, =20 + /* Execution environment configuration */ + [CSR_MENVCFG] =3D { "menvcfg", any, read_menvcfg, write_menvcfg, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_MENVCFGH] =3D { "menvcfgh", any32, read_menvcfgh, write_menvcfgh, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_SENVCFG] =3D { "senvcfg", smode, read_senvcfg, write_senvcfg, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_HENVCFG] =3D { "henvcfg", hmode, read_henvcfg, write_henvcfg, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_HENVCFGH] =3D { "henvcfgh", hmode32, read_henvcfgh, write_henvcfg= h, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + /* Supervisor Trap Setup */ [CSR_SSTATUS] =3D { "sstatus", smode, read_sstatus, write_sst= atus, NULL, read_sstatus_i128 = }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 5178b3fec9..243f567949 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -231,6 +231,28 @@ static int riscv_cpu_post_load(void *opaque, int versi= on_id) return 0; } =20 +static bool envcfg_needed(void *opaque) +{ + RISCVCPU *cpu =3D opaque; + CPURISCVState *env =3D &cpu->env; + + return (env->priv_ver >=3D PRIV_VERSION_1_12_0 ? 1 : 0); +} + +static const VMStateDescription vmstate_envcfg =3D { + .name =3D "cpu/envcfg", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D envcfg_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.menvcfg, RISCVCPU), + VMSTATE_UINTTL(env.senvcfg, RISCVCPU), + VMSTATE_UINT64(env.henvcfg, RISCVCPU), + + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_riscv_cpu =3D { .name =3D "cpu", .version_id =3D 3, @@ -292,6 +314,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { &vmstate_pointermasking, &vmstate_rv128, &vmstate_kvmtimer, + &vmstate_envcfg, NULL } }; --=20 2.35.1 From nobody Tue May 21 09:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650524828197219.96591020943504; Thu, 21 Apr 2022 00:07:08 -0700 (PDT) Received: from localhost ([::1]:42132 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhQuA-0006M5-Tk for importer@patchew.org; Thu, 21 Apr 2022 03:07:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53606) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQRH-0005C1-AO for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:37:15 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:13328) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQRF-0007xM-K2 for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:37:15 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 21 Apr 2022 14:37:12 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:08:14 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:37:13 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KkSWX1788z1Rvlx for ; Wed, 20 Apr 2022 23:37:12 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id xJuhrP3Ub1gs for ; Wed, 20 Apr 2022 23:37:11 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.119]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KkSWT6jFKz1SVp1; Wed, 20 Apr 2022 23:37:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1650523033; x=1682059033; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=FrQXpr5Vxfb8nWiDsJDGy1Vhs7NRhjml2Jwy5spgypw=; b=rZlitVFh8taDHArq0HCkIAX/bjAgmjGF1NwApRjZZWUJYOWbArDjor53 MiCwl6ACtxltC1IG91I9BnsyLQNy9BFB5u7iF3Rbv8dIxGayHWk+wsNOb +wq6pwZ2s9q03pSMoAWJ17taCyVDnxO+flWtY8Hi6v6821H6Cm4+i3RRW Ynnhg1BQ6hFuFO/srKEfY2efIRAu231e2tb67O7NUogMR0tnr0ffoa/bj UNjivf0ND+uc/m3PDCJsrtSVdLeN8R7BoBma/XSjiAuSOlP51NLRjyl3h 7nCIIEcGV7NUbMkBIo6Lu9s/Th9KpHVULa893PQMrAcJYAloBs6e2BSCK w==; X-IronPort-AV: E=Sophos;i="5.90,278,1643644800"; d="scan'208";a="302639956" IronPort-SDR: fUmdYeU4aJE5/W/OOzE5A302kaKrxMXI6RtwjnordwoUJCtaOsyJP0spuZk+uWcrOAQ9Zpaj9p TceSR0yiBYRPHW9hNXeHv9ziH0OXoyxfo24HP99H2mGbAk4YySOFsA2Hwmg0yHQOxfQ6hR9ZXP oCBsfSjYOTJU+w00vVjlOpgNRvLHixX/unuk6X9M9fPJ53ioYRhmPV+7bxvnFpwh7iOpxkuYvk pt2E485cAj+dXt32/CX4t8q6A+8i3VrKgXjB6zY6OQ19Zk3wRw91DyfkGWlS2PlRO2pPBfp9v/ 40lCESEv+7tTHpgUIzgXVEnH IronPort-SDR: yfs/kuXnNyq7LEgydR9EYwDLsN8PRFJubzmhlHuDzD96ASrPOSukHnYUmzZCCaRIXfhTzWnz3j ZPxhgLx4TOFXItpdCMzr9JAZJXHhR7lWrPJs6qeNbbmtzj1HlnmOhZYzvyKPnN95e87pSZ26/F 2g1uMeLYltUw3Sr/5/wa5qFP95X56GTzIvIn0xlEMZl7L4q49EH8ibsdidyCwSORt4XvOSlYBG IKMNJl+TjSdNyCX1KVC8Q0IoCd+OEv5Fe//WRX7JERWcIdaC5wJoitZ0nev4HG5hn9MlgpwX2W nAM= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1650523031; x=1653115032; bh=FrQXpr5Vxfb8nWiDsJ DGy1Vhs7NRhjml2Jwy5spgypw=; b=PLNcOUQPt5Xtp5B4BPBOAvMoXZ8YcLKBKR YruDVyUe63sc8GTqstGqtH5juVCkQ7DtTw8tpzMf9eWTn7+7fR1ECEPL4nbLl1oX EUU0cgEyEQqfNKgR3mnhTseDsooRNXFDEihZoXHV6o2IHlQ9TW92R1lpAcoCex2i Id5hKmoSDaGofzCp5oRcIErfHUk5cKi0FiYQ3WuDMpkwm4/EQ7mX3gXwnE+OWxi6 ElRBf97yh/EE5XG1BhJFAPIBfQ5rdW/I2lKmiExKJzbf0NqEBeo11PrDIHRORUfT Q/xgGmJyzAbbEMuR556qj9r7VtBdsHF+oeAmAHeWGzygP1zHHz9w== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Atish Patra , Alistair Francis Subject: [PULL 08/31] target/riscv: Enable privileged spec version 1.12 Date: Thu, 21 Apr 2022 16:36:07 +1000 Message-Id: <20220421063630.1033608-9-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650524829691100001 Content-Type: text/plain; charset="utf-8" From: Atish Patra Virt machine uses privileged specification version 1.12 now. All other machine continue to use the default one defined for that machine unless changed to 1.12 by the user explicitly. This commit enforces the privilege version for csrs introduced in v1.12 or after. Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Message-Id: <20220303185440.512391-7-atishp@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 8 +++++--- target/riscv/csr.c | 5 +++++ 2 files changed, 10 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ddda4906ff..c3fd018ecb 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -150,7 +150,7 @@ static void riscv_any_cpu_init(Object *obj) #elif defined(TARGET_RISCV64) set_misa(env, MXL_RV64, RVI | RVM | RVA | RVF | RVD | RVC | RVU); #endif - set_priv_version(env, PRIV_VERSION_1_11_0); + set_priv_version(env, PRIV_VERSION_1_12_0); } =20 #if defined(TARGET_RISCV64) @@ -503,7 +503,9 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) } =20 if (cpu->cfg.priv_spec) { - if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { + if (!g_strcmp0(cpu->cfg.priv_spec, "v1.12.0")) { + priv_version =3D PRIV_VERSION_1_12_0; + } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.11.0")) { priv_version =3D PRIV_VERSION_1_11_0; } else if (!g_strcmp0(cpu->cfg.priv_spec, "v1.10.0")) { priv_version =3D PRIV_VERSION_1_10_0; @@ -518,7 +520,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) if (priv_version) { set_priv_version(env, priv_version); } else if (!env->priv_ver) { - set_priv_version(env, PRIV_VERSION_1_11_0); + set_priv_version(env, PRIV_VERSION_1_12_0); } =20 if (cpu->cfg.mmu) { diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 84a398b205..8b6a1b90f1 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2975,6 +2975,7 @@ static inline RISCVException riscv_csrrw_check(CPURIS= CVState *env, { /* check privileges and return RISCV_EXCP_ILLEGAL_INST if check fails = */ int read_only =3D get_field(csrno, 0xC00) =3D=3D 3; + int csr_min_priv =3D csr_ops[csrno].min_priv_ver; #if !defined(CONFIG_USER_ONLY) int effective_priv =3D env->priv; =20 @@ -3007,6 +3008,10 @@ static inline RISCVException riscv_csrrw_check(CPURI= SCVState *env, return RISCV_EXCP_ILLEGAL_INST; } =20 + if (env->priv_ver < csr_min_priv) { + return RISCV_EXCP_ILLEGAL_INST; + } + return csr_ops[csrno].predicate(env, csrno); } =20 --=20 2.35.1 From nobody Tue May 21 09:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650524543533158.05251872997417; Thu, 21 Apr 2022 00:02:23 -0700 (PDT) Received: from localhost ([::1]:37360 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhQpa-0001ur-AG for importer@patchew.org; Thu, 21 Apr 2022 03:02:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53632) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQRK-0005Ft-9s for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:37:18 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:13339) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQRI-0007xw-Ly for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:37:18 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 21 Apr 2022 14:37:15 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:08:17 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:37:16 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KkSWZ6r48z1SVp0 for ; Wed, 20 Apr 2022 23:37:14 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id 1mYs0dQtgofm for ; Wed, 20 Apr 2022 23:37:14 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.119]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KkSWX2hWPz1Rvlx; Wed, 20 Apr 2022 23:37:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1650523036; x=1682059036; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=X22Gk/zZHhqY/tFx/pG4kivGfaZbRT7+ckrdVTNf79E=; b=LIe/M+pg2D0YOJ1J110qGRK7SXWq7KfzmfO1J1nB+2mSMAEvW1Zvqj4+ GNbhZ98s6x71494hdyzrIbv4s0aydhZLLQkFCAlvACbIfnhRvE2qwkFKd MZYMIRjZw2BveaUVc8WySUmcJH38qo3gheveDv1cCtOq6dR8w3Gjoe3BV Bu2AamM1EdkQOXdTQpp5WCOBFKBi6a/V+RF27Q3Gc2YXrNfMFvhA+rJ1Q yxAdb+3UF17iYxwFWJfWfWzW++MswZyC20NmAeB5C5pJjYxXJVHqTWyuW yIj8MgpXh/hpGj9l5+T6SXFVHZdZkZoTPWOLfm6SUGH6cXjmrXZozVgu/ w==; X-IronPort-AV: E=Sophos;i="5.90,278,1643644800"; d="scan'208";a="302639963" IronPort-SDR: jcxzerP5YdZx9lzparjTfeT8QaQS3uZpsSiPJR2N3xa/ij+ezu5jUaeqEU99WTBVUHPfENYgrX 5VMCE0MSOKe9/f1XIzfjOU9tMiKMnzm3NWdX3k4ruP8X+mSIjkRFXwktqr8hZsWfzLhVm4aEUF YcDrq5urgzyoosdUH4pPsGb8N8MoJxlyDxHEXkpQetgmsKGS6bxrMWVrgbb/jMPs+FGMdu6+al nx5BHHOUXtHQsDqAxghfBfDAvVrbfmKvRMbclAU+6zs5fr3CnhvRq8HJi6qJT3cqkv7+M/Qk5y EBd7GMOvElD8ZOG6lRHB2lfp IronPort-SDR: DOAuENAH7qmYGi5MIsX1eJe6Nv8hkPAxvu+eflgEWPyy76LJi2mPz61WRBNsAzgZ+c8VP89gK8 ++ABVsBbl5JYVnZkntTrsYwKkE5q3dyKcbpE2ptB9U+L8mgYCep3ZTg6TkUBIKvUCMTRN399+O wotIZmwvNcWwYMa6OaFoX0iqH8UHVPpZ+0pTatbG+pP1mo1ONB47mufBnS67y/VfnQXj6My7Bu 2Rx85CQNSNdMZRb8og/WNBnFWlQ6QUsZq5SXUvXOkbRb1DapiDZIWapMhDcJpN+2QRSw8iuOvC q+I= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1650523034; x=1653115035; bh=X22Gk/zZHhqY/tFx/p G4kivGfaZbRT7+ckrdVTNf79E=; b=JZasZDboMNUdRJydkDoMOkgrISDLFIeGMl DuYhWMFtEQuaKLxV08nnQ2hIYwHSwymlXdAGW8bPH3NQIIys7Qvhu6cyR5OXEGaW DmNuGfWGaymalANQLKpKNiyx8eKSJww/10vXCRQTea3PkIjHKX0bhJbgnrZ/7Ay2 D20v0c99ithfOzOChm5J0AID0v7mJR8Tntuua8EauwYkS7LfoLmV5z7CVHwD64kh t6ub/u79wx0O8UheT+axhxxcjVXGj+vLKZ0fpzBHMnB/YQIE483Hk8lm59RWEj2Z tOnfPeR/a4TkmW3yDjbWAn0qSqgo+JmNprgatoCO762tvpGav99g== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Alistair Francis , Bin Meng , Richard Henderson Subject: [PULL 09/31] target/riscv: cpu: Fixup indentation Date: Thu, 21 Apr 2022 16:36:08 +1000 Message-Id: <20220421063630.1033608-10-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650524545468100001 Content-Type: text/plain; charset="utf-8" From: Alistair Francis Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Richard Henderson Message-Id: <20220317061817.3856850-2-alistair.francis@opensource.wdc.com> --- target/riscv/cpu.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index c3fd018ecb..78fc7b22ed 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -569,18 +569,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) if (cpu->cfg.ext_i && cpu->cfg.ext_e) { error_setg(errp, "I and E extensions are incompatible"); - return; - } + return; + } =20 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { error_setg(errp, "Either I or E extension must be set"); - return; - } + return; + } =20 - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & - cpu->cfg.ext_a & cpu->cfg.ext_f & - cpu->cfg.ext_d)) { + if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & + cpu->cfg.ext_a & cpu->cfg.ext_f & + cpu->cfg.ext_d)) { warn_report("Setting G will also set IMAFD"); cpu->cfg.ext_i =3D true; cpu->cfg.ext_m =3D true; @@ -711,11 +711,11 @@ static void riscv_cpu_set_irq(void *opaque, int irq, = int level) case IRQ_S_EXT: case IRQ_VS_EXT: case IRQ_M_EXT: - if (kvm_enabled()) { + if (kvm_enabled()) { kvm_riscv_set_irq(cpu, irq, level); - } else { + } else { riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); - } + } break; default: g_assert_not_reached(); --=20 2.35.1 From nobody Tue May 21 09:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650523458473686.8694458787775; Wed, 20 Apr 2022 23:44:18 -0700 (PDT) Received: from localhost ([::1]:42224 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhQY3-0002L0-Jo for importer@patchew.org; Thu, 21 Apr 2022 02:44:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53650) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQRN-0005Im-0H for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:37:21 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:13339) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQRL-0007xw-06 for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:37:20 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 21 Apr 2022 14:37:18 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:08:20 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:37:19 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KkSWf0G1Rz1SVp1 for ; Wed, 20 Apr 2022 23:37:18 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id 0DdrIkTtgYHX for ; Wed, 20 Apr 2022 23:37:17 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.119]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KkSWb0s2Wz1Rvlx; Wed, 20 Apr 2022 23:37:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1650523038; x=1682059038; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lvbWS8dUER0K+FCnC0yXx7N/Nyk2+FNL0e/7MV+/RHY=; b=CAv/Cks0QUk9bCFPZ9P9aKDpnHrqIeVqLioF4BOKy76n98hDk5l96fA3 zkm2xln0GNQhdQSNu6VXbqalu8Wf7AUdAxyA/DC+OBNvrRexL2cBueEDB yZiX8hGEHdg5cv7xKc2oORzGgrSdSZ6aZk/XGaKjs2i7JxMLlJ4cpYCvu OmhGgkhsI+JqIJZd7gkcJJIV729zpKJ7bwj78Qq0JHicYx9HX7HLlhT1x 9Y7HixcKYz0wzUP8rwfH4w3bB2vBHGOCeO4vUYNMaPzOJANKDs0GhhBae 583tQq8fQ8t//SgZZwi48mA8s4oYVCdY84+UZYewCuAptTY6S4q6OnheE Q==; X-IronPort-AV: E=Sophos;i="5.90,278,1643644800"; d="scan'208";a="302639969" IronPort-SDR: 4G1rmboXoLWGuY4KsJTl/bW89OS9y3CB0l5UvB6PGd4gLNkRKO+FwzCIjx+Z0dT17I/QejNA88 ab3BSIkKw6fEhpv+SoAs6HQrOCXU60HbfWvHQWVDW7+ddct1BGodLB9pAiGMnqZahbvASDyr2T BRyS1c23prXAfKKNDlr3W3t/iJnEWzcLNKieGuwtV/JEMYwL6Nh2rNrrwE1zSnp+ZFdUSvties yIWv5VGDatktG4DucqoC9yvlYV9hMXgVCvSptugtjXWt4PMbydtE3jTxdA4IWVwwRoDRGX0JJU aKGfWMbpYlJxqJolyKsxQj38 IronPort-SDR: duk75FmLWL3tcT9UGrW+ILASaKkRl22mO5lf3DSI+ls3DEf6PD5ZSYy3+BPvfrW64dNku+6kv0 SXrdYEwIxhligziU/uxTjA8xYmEOAqjx/8rTaCTCtrmXqc5RdeMxtUxOSFGL0V5l2i2C4Mqp1w 3cJirdSEgBqQ8KEWwyGmFvXh5sa9k6TJTG4XrKxSo6o08vGFh+qfQKJyZDLeYZ2POH+pz1O2g9 45ZQXt7G0XXxhX7o99jM44jh7thquWkDN008+7J88BzMkUcRcOBrl41mv7u8DF8qfZQDCTq4mW CoY= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1650523037; x=1653115038; bh=lvbWS8dUER0K+FCnC0 yXx7N/Nyk2+FNL0e/7MV+/RHY=; b=HsDAPAz1Tu5BWzsCAX+NRSniMxjcUJAlDS Wmm6IKP3CCKBlJkl2I0EaqxHOsQZknVOVWE3m1ep68biPs2XPL54jojXOdiGC6lF 95y2aNUjJ/P5E5+Iq47Dr1F9nZVxJif/HkcJh5E3FemKnEaTxVRjn6hGkAKuIVKx jhNdUCH4u6m0D9ObS5Y4TjZ1ikLFJ+bdNavvM3o4LQujCP9x6hQXB5W9eBsIPmr3 JGAZvK1iLUW1o5Hcgccsh72GsYJ02VZDcPqd61cQRypQyKXyuKQ4yu/eeFeyp9is 1OfNgbs3EuqnPAMbO7MRIOJuCX2M9PmQdnFr84YDyCkcnN7yR2MA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Alistair Francis , Bin Meng , Richard Henderson Subject: [PULL 10/31] target/riscv: Allow software access to MIP SEIP Date: Thu, 21 Apr 2022 16:36:09 +1000 Message-Id: <20220421063630.1033608-11-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650523459650100001 Content-Type: text/plain; charset="utf-8" From: Alistair Francis The RISC-V specification states that: "Supervisor-level external interrupts are made pending based on the logical-OR of the software-writable SEIP bit and the signal from the external interrupt controller." We currently only allow either the interrupt controller or software to set the bit, which is incorrect. This patch removes the miclaim mask when writing MIP to allow M-mode software to inject interrupts, even with an interrupt controller. We then also need to keep track of which source is setting MIP_SEIP. The final value is a OR of both, so we add two bools and use that to keep track of the current state. This way either source can change without losing the correct value. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/904 Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Richard Henderson Message-Id: <20220317061817.3856850-3-alistair.francis@opensource.wdc.com> --- target/riscv/cpu.h | 8 ++++++++ target/riscv/cpu.c | 10 +++++++++- target/riscv/csr.c | 8 ++++++-- 3 files changed, 23 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 1ef1b9162f..d7322df4fd 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -177,6 +177,14 @@ struct CPUArchState { uint64_t mstatus; =20 uint64_t mip; + /* + * MIP contains the software writable version of SEIP ORed with the + * external interrupt value. The MIP register is always up-to-date. + * To keep track of the current source, we also save booleans of the v= alues + * here. + */ + bool external_seip; + bool software_seip; =20 uint64_t miclaim; =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 78fc7b22ed..cfdfe787de 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -708,7 +708,6 @@ static void riscv_cpu_set_irq(void *opaque, int irq, in= t level) case IRQ_VS_TIMER: case IRQ_M_TIMER: case IRQ_U_EXT: - case IRQ_S_EXT: case IRQ_VS_EXT: case IRQ_M_EXT: if (kvm_enabled()) { @@ -717,6 +716,15 @@ static void riscv_cpu_set_irq(void *opaque, int irq, i= nt level) riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); } break; + case IRQ_S_EXT: + if (kvm_enabled()) { + kvm_riscv_set_irq(cpu, irq, level); + } else { + env->external_seip =3D level; + riscv_cpu_update_mip(cpu, 1 << irq, + BOOL_TO_MASK(level | env->software_se= ip)); + } + break; default: g_assert_not_reached(); } diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 8b6a1b90f1..a09126a011 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1498,10 +1498,14 @@ static RISCVException rmw_mip64(CPURISCVState *env,= int csrno, uint64_t new_val, uint64_t wr_mask) { RISCVCPU *cpu =3D env_archcpu(env); - /* Allow software control of delegable interrupts not claimed by hardw= are */ - uint64_t old_mip, mask =3D wr_mask & delegable_ints & ~env->miclaim; + uint64_t old_mip, mask =3D wr_mask & delegable_ints; uint32_t gin; =20 + if (mask & MIP_SEIP) { + env->software_seip =3D new_val & MIP_SEIP; + new_val |=3D env->external_seip * MIP_SEIP; + } + if (mask) { old_mip =3D riscv_cpu_update_mip(cpu, mask, (new_val & mask)); } else { --=20 2.35.1 From nobody Tue May 21 09:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650525003418629.5726080031862; Thu, 21 Apr 2022 00:10:03 -0700 (PDT) Received: from localhost ([::1]:46094 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhQx0-0001E5-7v for importer@patchew.org; Thu, 21 Apr 2022 03:10:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53706) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQRS-0005MN-RV for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:37:31 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:13339) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQRO-0007xw-Ei for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:37:25 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 21 Apr 2022 14:37:21 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:08:24 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:37:22 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KkSWj2nBqz1SVp0 for ; Wed, 20 Apr 2022 23:37:21 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id p9_FivETDaXN for ; Wed, 20 Apr 2022 23:37:20 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.119]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KkSWd6MKJz1Rwrw; Wed, 20 Apr 2022 23:37:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1650523042; x=1682059042; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=0Dh27pbqlXWY2QigmLdOSQHbeQdA3PeVM+uzdNFi6cc=; b=bMbEx8w81h3Mx1i7S8gxq1VLG3Mf2LjLw8l9AJa5NwL7BlApITcA0/rz METK+PHShe7nsKt2IHx48ijf0Ooh8ETcw6N8+zL8rPKhBajWH83JJEC0a cXVi9DgTOB7mrGyrRerbOcqbB8IHKzy9CHOqiQoY+/TUUljFl8v9lpb/h PoEou33EoHtSNCxSZ5zl3X+38rVqav/1tI4hFmNhX3pR2hJOku9OeVgsE Z+DPv5pbjDRQ/xmWnRAe3OG4Xp4weUwAPF/4UNzjCLeMOfaL7D5P4jtoE TUwLR4qL5SyQSAw5Jv9fzhFtiFHz6pBEyD2/S6UH7SkyaNgzBKX9p/L/o g==; X-IronPort-AV: E=Sophos;i="5.90,278,1643644800"; d="scan'208";a="302639975" IronPort-SDR: 9uyG97ADkSQQGYToD7i66UfVhM1z4r/iuLvM59RIRZZ8V3GC4/aCRiIH8ZECnKrOnV5rYQWKpI EHe7Xnm8s6zXc/4d9OJy9KY7cxYLEmZbiuLClnPDgiAOy1pv3CyI2xq9Qf1bvfevJ3etXgH+5a ManhlzDvjRfnf6j0CK3Rv+oqTIXOQyqGBfJ1fUP4kjKmZ6AGpon/FQ2BKZ0hF4P5zy+x3c39gx 3wpXFwqN35PF1GBNqRXbYF8+2IWaKmBUqFgvx2xozSKo21ZzScEEhaV8VqH78eCNXCy3lbjd0e Co0dO55ZVEJ6qR+tHxZGstsX IronPort-SDR: /8VM5HAVk7q5GzZ3GVd1kq41kMRNJrW6KmCrNsSAFSxMhhf6xiIof7DqRNqsr70qMuBDjR3eOS EbDWxn4RTLynTTnP0/CLTPVDkwl/aJLHBU5NC4DbZZJBUkGnPawdjqR1nqIsxPzQ544nPSRgU/ /DXRiiXpgeFKHhQ0OAPIFCagVLK4GY/CPKhd96Sa3ZsIgqmbHG+NncQPR35NSKGnVQyTgDby/Q RAdqCnnSSzUnxHTzl6RmvUU8XlUbv1pi6Fm1bOP6Y5YbVM4XrgCOOpjTeLNUsRsWlQUVlpBsPk wQo= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1650523040; x=1653115041; bh=0Dh27pbqlXWY2QigmL dOSQHbeQdA3PeVM+uzdNFi6cc=; b=IdShZmcQUQloFUgYKquvaLp7yIBWRXvIkX 2itYeAXEk6a8bXhYr93lSQcBcNTtOmEFKhDQNIP3lBQwO35MYJebzMwrtaWeH6EH G80axvfZjeSP8GkNMXt9HCZPDb3EE3v+suKHE8zlkhQnBV6EQypZPJnfCrSPi0a7 O337bTFKyzTA/dXiWSZ3Ky8acKnDP17Q0AUeAW2Br+bk7vhWNoFH4X+p8X9Zj3Aj 9ZGKq53xAQeNvpdq1LiBp/pyQgxFFzPvi5oaal5QFLg2901N9s9cxY6/xfOaDZNS Y27WNp5/Z9//lwJGS6JGvgEQAf2gSh+0WxuEGrnD8a2tuYCmF6ow== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Bin Meng , Alistair Francis Subject: [PULL 11/31] target/riscv: Add initial support for the Sdtrig extension Date: Thu, 21 Apr 2022 16:36:10 +1000 Message-Id: <20220421063630.1033608-12-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650525005602100001 Content-Type: text/plain; charset="utf-8" From: Bin Meng This adds initial support for the Sdtrig extension via the Trigger Module, as defined in the RISC-V Debug Specification [1]. Only "Address / Data Match" trigger (type 2) is implemented as of now, which is mainly used for hardware breakpoint and watchpoint. The number of type 2 triggers implemented is 2, which is the number that we can find in the SiFive U54/U74 cores. [1] https://github.com/riscv/riscv-debug-spec/raw/master/riscv-debug-stable= .pdf Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-Id: <20220315065529.62198-2-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 5 + target/riscv/debug.h | 108 +++++++++++++ target/riscv/debug.c | 339 +++++++++++++++++++++++++++++++++++++++ target/riscv/meson.build | 1 + 4 files changed, 453 insertions(+) create mode 100644 target/riscv/debug.h create mode 100644 target/riscv/debug.c diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index d7322df4fd..3f7553c0b5 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -106,6 +106,7 @@ typedef struct CPUArchState CPURISCVState; =20 #if !defined(CONFIG_USER_ONLY) #include "pmp.h" +#include "debug.h" #endif =20 #define RV_VLEN_MAX 1024 @@ -279,6 +280,10 @@ struct CPUArchState { pmp_table_t pmp_state; target_ulong mseccfg; =20 + /* trigger module */ + target_ulong trigger_cur; + type2_trigger_t type2_trig[TRIGGER_TYPE2_NUM]; + /* machine specific rdtime callback */ uint64_t (*rdtime_fn)(uint32_t); uint32_t rdtime_fn_arg; diff --git a/target/riscv/debug.h b/target/riscv/debug.h new file mode 100644 index 0000000000..fbc5f946e2 --- /dev/null +++ b/target/riscv/debug.h @@ -0,0 +1,108 @@ +/* + * QEMU RISC-V Native Debug Support + * + * Copyright (c) 2022 Wind River Systems, Inc. + * + * Author: + * Bin Meng + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef RISCV_DEBUG_H +#define RISCV_DEBUG_H + +/* trigger indexes implemented */ +enum { + TRIGGER_TYPE2_IDX_0 =3D 0, + TRIGGER_TYPE2_IDX_1, + TRIGGER_TYPE2_NUM, + TRIGGER_NUM =3D TRIGGER_TYPE2_NUM +}; + +/* register index of tdata CSRs */ +enum { + TDATA1 =3D 0, + TDATA2, + TDATA3, + TDATA_NUM +}; + +typedef enum { + TRIGGER_TYPE_NO_EXIST =3D 0, /* trigger does not exist */ + TRIGGER_TYPE_AD_MATCH =3D 2, /* address/data match trigger */ + TRIGGER_TYPE_INST_CNT =3D 3, /* instruction count trigger */ + TRIGGER_TYPE_INT =3D 4, /* interrupt trigger */ + TRIGGER_TYPE_EXCP =3D 5, /* exception trigger */ + TRIGGER_TYPE_AD_MATCH6 =3D 6, /* new address/data match trigger */ + TRIGGER_TYPE_EXT_SRC =3D 7, /* external source trigger */ + TRIGGER_TYPE_UNAVAIL =3D 15 /* trigger exists, but unavailable */ +} trigger_type_t; + +typedef struct { + target_ulong mcontrol; + target_ulong maddress; + struct CPUBreakpoint *bp; + struct CPUWatchpoint *wp; +} type2_trigger_t; + +/* tdata field masks */ + +#define RV32_TYPE(t) ((uint32_t)(t) << 28) +#define RV32_TYPE_MASK (0xf << 28) +#define RV32_DMODE BIT(27) +#define RV64_TYPE(t) ((uint64_t)(t) << 60) +#define RV64_TYPE_MASK (0xfULL << 60) +#define RV64_DMODE BIT_ULL(59) + +/* mcontrol field masks */ + +#define TYPE2_LOAD BIT(0) +#define TYPE2_STORE BIT(1) +#define TYPE2_EXEC BIT(2) +#define TYPE2_U BIT(3) +#define TYPE2_S BIT(4) +#define TYPE2_M BIT(6) +#define TYPE2_MATCH (0xf << 7) +#define TYPE2_CHAIN BIT(11) +#define TYPE2_ACTION (0xf << 12) +#define TYPE2_SIZELO (0x3 << 16) +#define TYPE2_TIMING BIT(18) +#define TYPE2_SELECT BIT(19) +#define TYPE2_HIT BIT(20) +#define TYPE2_SIZEHI (0x3 << 21) /* RV64 only */ + +/* access size */ +enum { + SIZE_ANY =3D 0, + SIZE_1B, + SIZE_2B, + SIZE_4B, + SIZE_6B, + SIZE_8B, + SIZE_10B, + SIZE_12B, + SIZE_14B, + SIZE_16B, + SIZE_NUM =3D 16 +}; + +bool tdata_available(CPURISCVState *env, int tdata_index); + +target_ulong tselect_csr_read(CPURISCVState *env); +void tselect_csr_write(CPURISCVState *env, target_ulong val); + +target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index); +void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val= ); + +#endif /* RISCV_DEBUG_H */ diff --git a/target/riscv/debug.c b/target/riscv/debug.c new file mode 100644 index 0000000000..c8cec39217 --- /dev/null +++ b/target/riscv/debug.c @@ -0,0 +1,339 @@ +/* + * QEMU RISC-V Native Debug Support + * + * Copyright (c) 2022 Wind River Systems, Inc. + * + * Author: + * Bin Meng + * + * This provides the native debug support via the Trigger Module, as defin= ed + * in the RISC-V Debug Specification: + * https://github.com/riscv/riscv-debug-spec/raw/master/riscv-debug-stable= .pdf + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qapi/error.h" +#include "cpu.h" +#include "trace.h" +#include "exec/exec-all.h" + +/* + * The following M-mode trigger CSRs are implemented: + * + * - tselect + * - tdata1 + * - tdata2 + * - tdata3 + * + * We don't support writable 'type' field in the tdata1 register, so there= is + * no need to implement the "tinfo" CSR. + * + * The following triggers are implemented: + * + * Index | Type | tdata mapping | Description + * ------+------+------------------------+------------ + * 0 | 2 | tdata1, tdata2 | Address / Data Match + * 1 | 2 | tdata1, tdata2 | Address / Data Match + */ + +/* tdata availability of a trigger */ +typedef bool tdata_avail[TDATA_NUM]; + +static tdata_avail tdata_mapping[TRIGGER_NUM] =3D { + [TRIGGER_TYPE2_IDX_0 ... TRIGGER_TYPE2_IDX_1] =3D { true, true, false = }, +}; + +/* only breakpoint size 1/2/4/8 supported */ +static int access_size[SIZE_NUM] =3D { + [SIZE_ANY] =3D 0, + [SIZE_1B] =3D 1, + [SIZE_2B] =3D 2, + [SIZE_4B] =3D 4, + [SIZE_6B] =3D -1, + [SIZE_8B] =3D 8, + [6 ... 15] =3D -1, +}; + +static inline target_ulong trigger_type(CPURISCVState *env, + trigger_type_t type) +{ + target_ulong tdata1; + + switch (riscv_cpu_mxl(env)) { + case MXL_RV32: + tdata1 =3D RV32_TYPE(type); + break; + case MXL_RV64: + tdata1 =3D RV64_TYPE(type); + break; + default: + g_assert_not_reached(); + } + + return tdata1; +} + +bool tdata_available(CPURISCVState *env, int tdata_index) +{ + if (unlikely(tdata_index >=3D TDATA_NUM)) { + return false; + } + + if (unlikely(env->trigger_cur >=3D TRIGGER_NUM)) { + return false; + } + + return tdata_mapping[env->trigger_cur][tdata_index]; +} + +target_ulong tselect_csr_read(CPURISCVState *env) +{ + return env->trigger_cur; +} + +void tselect_csr_write(CPURISCVState *env, target_ulong val) +{ + /* all target_ulong bits of tselect are implemented */ + env->trigger_cur =3D val; +} + +static target_ulong tdata1_validate(CPURISCVState *env, target_ulong val, + trigger_type_t t) +{ + uint32_t type, dmode; + target_ulong tdata1; + + switch (riscv_cpu_mxl(env)) { + case MXL_RV32: + type =3D extract32(val, 28, 4); + dmode =3D extract32(val, 27, 1); + tdata1 =3D RV32_TYPE(t); + break; + case MXL_RV64: + type =3D extract64(val, 60, 4); + dmode =3D extract64(val, 59, 1); + tdata1 =3D RV64_TYPE(t); + break; + default: + g_assert_not_reached(); + } + + if (type !=3D t) { + qemu_log_mask(LOG_GUEST_ERROR, + "ignoring type write to tdata1 register\n"); + } + if (dmode !=3D 0) { + qemu_log_mask(LOG_UNIMP, "debug mode is not supported\n"); + } + + return tdata1; +} + +static inline void warn_always_zero_bit(target_ulong val, target_ulong mas= k, + const char *msg) +{ + if (val & mask) { + qemu_log_mask(LOG_UNIMP, "%s bit is always zero\n", msg); + } +} + +static uint32_t type2_breakpoint_size(CPURISCVState *env, target_ulong ctr= l) +{ + uint32_t size, sizelo, sizehi =3D 0; + + if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { + sizehi =3D extract32(ctrl, 21, 2); + } + sizelo =3D extract32(ctrl, 16, 2); + size =3D (sizehi << 2) | sizelo; + + return size; +} + +static inline bool type2_breakpoint_enabled(target_ulong ctrl) +{ + bool mode =3D !!(ctrl & (TYPE2_U | TYPE2_S | TYPE2_M)); + bool rwx =3D !!(ctrl & (TYPE2_LOAD | TYPE2_STORE | TYPE2_EXEC)); + + return mode && rwx; +} + +static target_ulong type2_mcontrol_validate(CPURISCVState *env, + target_ulong ctrl) +{ + target_ulong val; + uint32_t size; + + /* validate the generic part first */ + val =3D tdata1_validate(env, ctrl, TRIGGER_TYPE_AD_MATCH); + + /* validate unimplemented (always zero) bits */ + warn_always_zero_bit(ctrl, TYPE2_MATCH, "match"); + warn_always_zero_bit(ctrl, TYPE2_CHAIN, "chain"); + warn_always_zero_bit(ctrl, TYPE2_ACTION, "action"); + warn_always_zero_bit(ctrl, TYPE2_TIMING, "timing"); + warn_always_zero_bit(ctrl, TYPE2_SELECT, "select"); + warn_always_zero_bit(ctrl, TYPE2_HIT, "hit"); + + /* validate size encoding */ + size =3D type2_breakpoint_size(env, ctrl); + if (access_size[size] =3D=3D -1) { + qemu_log_mask(LOG_UNIMP, "access size %d is not supported, using S= IZE_ANY\n", + size); + } else { + val |=3D (ctrl & TYPE2_SIZELO); + if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { + val |=3D (ctrl & TYPE2_SIZEHI); + } + } + + /* keep the mode and attribute bits */ + val |=3D (ctrl & (TYPE2_U | TYPE2_S | TYPE2_M | + TYPE2_LOAD | TYPE2_STORE | TYPE2_EXEC)); + + return val; +} + +static void type2_breakpoint_insert(CPURISCVState *env, target_ulong index) +{ + target_ulong ctrl =3D env->type2_trig[index].mcontrol; + target_ulong addr =3D env->type2_trig[index].maddress; + bool enabled =3D type2_breakpoint_enabled(ctrl); + CPUState *cs =3D env_cpu(env); + int flags =3D BP_CPU | BP_STOP_BEFORE_ACCESS; + uint32_t size; + + if (!enabled) { + return; + } + + if (ctrl & TYPE2_EXEC) { + cpu_breakpoint_insert(cs, addr, flags, &env->type2_trig[index].bp); + } + + if (ctrl & TYPE2_LOAD) { + flags |=3D BP_MEM_READ; + } + if (ctrl & TYPE2_STORE) { + flags |=3D BP_MEM_WRITE; + } + + if (flags & BP_MEM_ACCESS) { + size =3D type2_breakpoint_size(env, ctrl); + if (size !=3D 0) { + cpu_watchpoint_insert(cs, addr, size, flags, + &env->type2_trig[index].wp); + } else { + cpu_watchpoint_insert(cs, addr, 8, flags, + &env->type2_trig[index].wp); + } + } +} + +static void type2_breakpoint_remove(CPURISCVState *env, target_ulong index) +{ + CPUState *cs =3D env_cpu(env); + + if (env->type2_trig[index].bp) { + cpu_breakpoint_remove_by_ref(cs, env->type2_trig[index].bp); + env->type2_trig[index].bp =3D NULL; + } + + if (env->type2_trig[index].wp) { + cpu_watchpoint_remove_by_ref(cs, env->type2_trig[index].wp); + env->type2_trig[index].wp =3D NULL; + } +} + +static target_ulong type2_reg_read(CPURISCVState *env, + target_ulong trigger_index, int tdata_i= ndex) +{ + uint32_t index =3D trigger_index - TRIGGER_TYPE2_IDX_0; + target_ulong tdata; + + switch (tdata_index) { + case TDATA1: + tdata =3D env->type2_trig[index].mcontrol; + break; + case TDATA2: + tdata =3D env->type2_trig[index].maddress; + break; + default: + g_assert_not_reached(); + } + + return tdata; +} + +static void type2_reg_write(CPURISCVState *env, target_ulong trigger_index, + int tdata_index, target_ulong val) +{ + uint32_t index =3D trigger_index - TRIGGER_TYPE2_IDX_0; + target_ulong new_val; + + switch (tdata_index) { + case TDATA1: + new_val =3D type2_mcontrol_validate(env, val); + if (new_val !=3D env->type2_trig[index].mcontrol) { + env->type2_trig[index].mcontrol =3D new_val; + type2_breakpoint_remove(env, index); + type2_breakpoint_insert(env, index); + } + break; + case TDATA2: + if (val !=3D env->type2_trig[index].maddress) { + env->type2_trig[index].maddress =3D val; + type2_breakpoint_remove(env, index); + type2_breakpoint_insert(env, index); + } + break; + default: + g_assert_not_reached(); + } + + return; +} + +typedef target_ulong (*tdata_read_func)(CPURISCVState *env, + target_ulong trigger_index, + int tdata_index); + +static tdata_read_func trigger_read_funcs[TRIGGER_NUM] =3D { + [TRIGGER_TYPE2_IDX_0 ... TRIGGER_TYPE2_IDX_1] =3D type2_reg_read, +}; + +typedef void (*tdata_write_func)(CPURISCVState *env, + target_ulong trigger_index, + int tdata_index, + target_ulong val); + +static tdata_write_func trigger_write_funcs[TRIGGER_NUM] =3D { + [TRIGGER_TYPE2_IDX_0 ... TRIGGER_TYPE2_IDX_1] =3D type2_reg_write, +}; + +target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index) +{ + tdata_read_func read_func =3D trigger_read_funcs[env->trigger_cur]; + + return read_func(env, env->trigger_cur, tdata_index); +} + +void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val) +{ + tdata_write_func write_func =3D trigger_write_funcs[env->trigger_cur]; + + return write_func(env, env->trigger_cur, tdata_index, val); +} diff --git a/target/riscv/meson.build b/target/riscv/meson.build index 91f0ac32ff..2c20f3dd8e 100644 --- a/target/riscv/meson.build +++ b/target/riscv/meson.build @@ -27,6 +27,7 @@ riscv_softmmu_ss =3D ss.source_set() riscv_softmmu_ss.add(files( 'arch_dump.c', 'pmp.c', + 'debug.c', 'monitor.c', 'machine.c' )) --=20 2.35.1 From nobody Tue May 21 09:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650525273442948.2906751456596; Thu, 21 Apr 2022 00:14:33 -0700 (PDT) Received: from localhost ([::1]:53690 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhR1M-0007Fu-9l for importer@patchew.org; Thu, 21 Apr 2022 03:14:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53754) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQRW-0005MX-H9 for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:37:32 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:13363) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQRS-0007yk-LT for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:37:30 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 21 Apr 2022 14:37:24 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:08:27 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:37:25 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KkSWm2ZTlz1SVp2 for ; Wed, 20 Apr 2022 23:37:24 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id B9gNJtzr3kMI for ; Wed, 20 Apr 2022 23:37:23 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.119]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KkSWj0S7gz1Rvlx; Wed, 20 Apr 2022 23:37:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1650523046; x=1682059046; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NW3kHKqkkttjg3GYn6KXhnRKzaKSjFmEneLo4jSSW+g=; b=HyOA+tvomdgJSE6Q9ehFqF+ddhdxyJ+2Nm4FutFSbZDXbe1nU35WH+5m KKXKNDU0zN6PUFx67nM0Qsf2cvrW1qVWhXG1/IwqzGY03s5catIA07B+r FyqAsIHJ0hmWDWS5lf2kqLi4U7TDlOfCWmfyfEUJyKM7qDslo2+wVlCDM dwSv5PWoaMw0zdIBIHe5Yv+T5lwD8Sf6PwZOwJiC3sqesc4Mc/ohCe2ZS xOtuCNCVEvkhtWci+FE1oJNc9bLc2a8bRtUV6TKFmBG7zYOKA7kfFfIoi F3vFKRfxBM1k5xEwoJD1kxYZH7Qs9kVnAB+XPGY9uWNoiTuyAEmQ7/HAQ g==; X-IronPort-AV: E=Sophos;i="5.90,278,1643644800"; d="scan'208";a="302639979" IronPort-SDR: zEcJcEaXthpCl7veffl740Ao6/Oc2+evLq8cpiSc6Zhr50oj+12WXl5VJW8CZbE8JAmrhg7LIk AzPF3sXBVgtNL3yuzKxRimMDFdgvxezWXZFYZ6/ZDiRI0kdjt47SKhcN/f3OsJyfAgJJ6PG0Lz 6SqeDX2mqMpujzb31OjXM6G1EWApRsdru2e7T0d77BeFrxwOwff3cddRGIVcF0k82GnlWVAGy1 ciyM4zK6EDmf6986KPuvnpfTUFvPUvvfajwtW0sRI0Ma7ZpK7HFcuxMv6ubXB2ZArwzj5K5bWZ NljkwgzBoFy349RWK49uF9gG IronPort-SDR: LmtgSoBoS84+XZgihvNzXNwuATkD2Her0YO2hVShI9/NlALT9H1I9dV0JlgCYZwWgHegzdPj3v k+Oacpk4YvbfGkLRGEQuCHW0fR+rbQRoKhlGicSfhwgbhsUVTsjkrKz2Tfo1NtmH+Va+Fd8jqJ 9w+kINg+6GnTa4K1vo/kragkR26rLn07QmQyn4T7E0kUD+KNdoa1DsIJD+iuT2afWt0BeV9Rn6 3F1suSOdwnyWy/KWktMApn7Lvziy4lWWEhFx31b/NaN+3g8Jqw4lp42WBQuB14GqbDOOyY3xOI 9hc= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1650523043; x=1653115044; bh=NW3kHKqkkttjg3GYn6 KXhnRKzaKSjFmEneLo4jSSW+g=; b=gD1gtm22ntyCxDQNF/bo377EKHOOBhDvho MdQllcRnToWAWiljDFLfefOuHFWXYflsJde0nnEdhwsrzZTmJgn7sfpU5U+DH2BS zZxXiyOVpJETMgvY/3UYyGmEUruAN2OMfZHqFK7yn27ODEHcyD01j0s7tpDMzqzF lk8GXEnPoqUrKcGCK50PvMN5JiZXOfhiMFIO00mabKzNoNYiS9ydSezb1no/RKqg QMwPZO0SQ1RjPLdUIz5CCr3f0zPqKeNtvvm/TgnbOKHFJGXdhsVu7OedDmgxihk8 7i+JIz+NpxbZS6DYWQXEbF6l1c+zsa+LMRJ1u156Y7AGJgu1G7pA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Frank Chang , Alistair Francis Subject: [PULL 12/31] target/riscv: optimize condition assign for scale < 0 Date: Thu, 21 Apr 2022 16:36:11 +1000 Message-Id: <20220421063630.1033608-13-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650525275017100001 Content-Type: text/plain; charset="utf-8" From: Weiwei Li for some cases, scale is always equal or less than 0, since lmul is not lar= ger than 3 Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Frank Chang Acked-by: Alistair Francis Message-Id: <20220325085902.29500-1-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvv.c.inc | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index 8d675db9a2..b336d57270 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -1198,7 +1198,7 @@ GEN_LDST_WHOLE_TRANS(vs8r_v, 8, true) static inline uint32_t MAXSZ(DisasContext *s) { int scale =3D s->lmul - 3; - return scale < 0 ? s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << sc= ale; + return s->cfg_ptr->vlen >> -scale; } =20 static bool opivv_check(DisasContext *s, arg_rmrr *a) @@ -3597,8 +3597,7 @@ static bool trans_vrgather_vx(DisasContext *s, arg_rm= rr *a) =20 if (a->vm && s->vl_eq_vlmax) { int scale =3D s->lmul - (s->sew + 3); - int vlmax =3D scale < 0 ? - s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << sc= ale; + int vlmax =3D s->cfg_ptr->vlen >> -scale; TCGv_i64 dest =3D tcg_temp_new_i64(); =20 if (a->rs1 =3D=3D 0) { @@ -3630,8 +3629,7 @@ static bool trans_vrgather_vi(DisasContext *s, arg_rm= rr *a) =20 if (a->vm && s->vl_eq_vlmax) { int scale =3D s->lmul - (s->sew + 3); - int vlmax =3D scale < 0 ? - s->cfg_ptr->vlen >> -scale : s->cfg_ptr->vlen << sc= ale; + int vlmax =3D s->cfg_ptr->vlen >> -scale; if (a->rs1 >=3D vlmax) { tcg_gen_gvec_dup_imm(MO_64, vreg_ofs(s, a->rd), MAXSZ(s), MAXSZ(s), 0); --=20 2.35.1 From nobody Tue May 21 09:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650525693100629.5843088120677; Thu, 21 Apr 2022 00:21:33 -0700 (PDT) Received: from localhost ([::1]:37544 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhR88-0007ac-38 for importer@patchew.org; Thu, 21 Apr 2022 03:21:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53796) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQRi-0005OZ-GX for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:37:44 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:13339) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQRe-0007xw-Gf for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:37:41 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 21 Apr 2022 14:37:27 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:08:30 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:37:28 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KkSWq3s01z1Rvlx for ; Wed, 20 Apr 2022 23:37:27 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id KxvdNHFJUek1 for ; Wed, 20 Apr 2022 23:37:27 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.119]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KkSWm2jvWz1SVp3; Wed, 20 Apr 2022 23:37:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1650523058; x=1682059058; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=su5YxZklaH/xa9o3VVgOYBluOVxxEPtn6VK/HCmbu3Q=; b=I1JqLbJkRJwJOjZ95IfnZZcI5iaCf9SfG0btUw1SisN0qiXmSh8vKvnt pr5AfAVc36lbhQiN2G8AVbhElt4ClIIiF4XYm7BPD+BCHsRsVKpSnWqYk Llo/Y+MfbZISlAB+2FTS9zvjhURy/2IBwGnXwPhSlz5aV49QFug04kcGr rQihI1XxrJ+f/ucn2DouhzjSihWyfWkMU/xf8yxlU4Lq32lT+WzE2QJ83 1yquIK8pSB3HsMaLxCwXv7Qh0pwWSTueTMcUx5aOqIh46r31VnvtQFPTg /BeftEK/z6JCXm9BONTSnEzW/pMK6DF+hgP3Pa+B4Rp2Ly0JbV8DHwp/E g==; X-IronPort-AV: E=Sophos;i="5.90,278,1643644800"; d="scan'208";a="302639980" IronPort-SDR: SanGyfZjc6DyUDCR5rTvFkkoa76OIe81HWWyOi9gyqAXmNsMROkHyqKYvCtZ2GOy2SLOsF3JK+ SkSG1VJLI1UEhPImbZebmL0OH1TDuEKQcK+irKVNWNRuY4eD4x9YsOk8KV6LMd5NSVBZMKzlLh jOZTEq9WIl2yVcBD/iQsFXaTo4Hz3VnVOqCqmVHvHC+xEmXl9rJZitjHWgs0W56q9tDLAEgpjx 2vW30tFq7ZWF0QskqSWkEKON1nL01/9a0uVqgtsCWNXp/Fg9+slQL77Pn1oG7Y0JU00asClQrm ZLtSzTUBfgys+aRSiHhz/Ijk IronPort-SDR: N7+6Jz6Q1Rylnl0sxi67ks03jsnz3yZEqzMUgaJlQ9bEWuzCkccU+xvO6ai3qQnTOm8ZQncPvr FMR8HHARvUiOZpm+3eg+7dtvfozuI0OhgK0E7dzZzbekLTboc1NofAc49qxOYN4TDFv2d7VeZQ 3QQCP+pE2im4KDAypJ9jZWCgT0Ymu35bslenNmCEzD5dsK2U/5CNI5PsOTYEM/7pRE52M3OYyj inS1A3T4W0hVfOSR+KPdqU5v3AJxehHQAmGg3n6P6oankEbcOSUVznox3tWmfBZ/whxTHCuT3z MV8= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1650523047; x=1653115048; bh=su5YxZklaH/xa9o3VV gOYBluOVxxEPtn6VK/HCmbu3Q=; b=rKQC00HyODvvdMtKVccjXsRYAuSSHkWc/m EEvc4+3inq2MrfHlhTy1r3vjGzzyjewabv1j4wU3ob+WgquEkGTEQk/FITuJ6zO3 hDGkcRLwTA1PYuW0q5N3S1suN5ISyu6fVQmU7IcCuqVwroaxnFtCOFX+w3pVDc1U aGOZo9dE7TxhxTtxgGVCyNU7zy3Uxul+hE4DJ+k76q04b4PsmAJ1rHFOFHfb2dtO g3esglRtyemlR+foPOJR3m+//NNb32FId5Wt9v7Dzdk149XZlTc10C5igfa1TeES trgIIVoyhwLTOvjx5/UoviAPV2rB2kNEO9tRuiX9u+mweCEJzDcQ== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Frank Chang , Alistair Francis Subject: [PULL 13/31] target/riscv: optimize helper for vmvr.v Date: Thu, 21 Apr 2022 16:36:12 +1000 Message-Id: <20220421063630.1033608-14-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650525693414100001 Content-Type: text/plain; charset="utf-8" From: Weiwei Li LEN is not used for GEN_VEXT_VMV_WHOLE macro, so vmvr.v can share the same helper Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20220325085902.29500-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 5 +---- target/riscv/vector_helper.c | 29 ++++++++++--------------- target/riscv/insn_trans/trans_rvv.c.inc | 17 +++++---------- 3 files changed, 18 insertions(+), 33 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 26bbab2fab..a669d0187b 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -1086,10 +1086,7 @@ DEF_HELPER_6(vcompress_vm_h, void, ptr, ptr, ptr, pt= r, env, i32) DEF_HELPER_6(vcompress_vm_w, void, ptr, ptr, ptr, ptr, env, i32) DEF_HELPER_6(vcompress_vm_d, void, ptr, ptr, ptr, ptr, env, i32) =20 -DEF_HELPER_4(vmv1r_v, void, ptr, ptr, env, i32) -DEF_HELPER_4(vmv2r_v, void, ptr, ptr, env, i32) -DEF_HELPER_4(vmv4r_v, void, ptr, ptr, env, i32) -DEF_HELPER_4(vmv8r_v, void, ptr, ptr, env, i32) +DEF_HELPER_4(vmvr_v, void, ptr, ptr, env, i32) =20 DEF_HELPER_5(vzext_vf2_h, void, ptr, ptr, ptr, env, i32) DEF_HELPER_5(vzext_vf2_w, void, ptr, ptr, ptr, env, i32) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 7a6ce0a3bc..99f3134aa0 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4888,25 +4888,18 @@ GEN_VEXT_VCOMPRESS_VM(vcompress_vm_w, uint32_t, H4) GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8) =20 /* Vector Whole Register Move */ -#define GEN_VEXT_VMV_WHOLE(NAME, LEN) \ -void HELPER(NAME)(void *vd, void *vs2, CPURISCVState *env, \ - uint32_t desc) \ -{ \ - /* EEW =3D 8 */ \ - uint32_t maxsz =3D simd_maxsz(desc); \ - uint32_t i =3D env->vstart; \ - \ - memcpy((uint8_t *)vd + H1(i), \ - (uint8_t *)vs2 + H1(i), \ - maxsz - env->vstart); \ - \ - env->vstart =3D 0; \ -} +void HELPER(vmvr_v)(void *vd, void *vs2, CPURISCVState *env, uint32_t desc) +{ + /* EEW =3D 8 */ + uint32_t maxsz =3D simd_maxsz(desc); + uint32_t i =3D env->vstart; + + memcpy((uint8_t *)vd + H1(i), + (uint8_t *)vs2 + H1(i), + maxsz - env->vstart); =20 -GEN_VEXT_VMV_WHOLE(vmv1r_v, 1) -GEN_VEXT_VMV_WHOLE(vmv2r_v, 2) -GEN_VEXT_VMV_WHOLE(vmv4r_v, 4) -GEN_VEXT_VMV_WHOLE(vmv8r_v, 8) + env->vstart =3D 0; +} =20 /* Vector Integer Extension */ #define GEN_VEXT_INT_EXT(NAME, ETYPE, DTYPE, HD, HS1) \ diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_tr= ans/trans_rvv.c.inc index b336d57270..90327509f7 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3695,7 +3695,7 @@ static bool trans_vcompress_vm(DisasContext *s, arg_r= *a) * Whole Vector Register Move Instructions ignore vtype and vl setting. * Thus, we don't need to check vill bit. (Section 16.6) */ -#define GEN_VMV_WHOLE_TRANS(NAME, LEN, SEQ) \ +#define GEN_VMV_WHOLE_TRANS(NAME, LEN) \ static bool trans_##NAME(DisasContext *s, arg_##NAME * a) \ { \ if (require_rvv(s) && \ @@ -3710,13 +3710,8 @@ static bool trans_##NAME(DisasContext *s, arg_##NAME= * a) \ } else { \ TCGLabel *over =3D gen_new_label(); \ tcg_gen_brcondi_tl(TCG_COND_GEU, cpu_vstart, maxsz, over); \ - \ - static gen_helper_gvec_2_ptr * const fns[4] =3D { \ - gen_helper_vmv1r_v, gen_helper_vmv2r_v, \ - gen_helper_vmv4r_v, gen_helper_vmv8r_v, \ - }; \ tcg_gen_gvec_2_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, a->rs2), \ - cpu_env, maxsz, maxsz, 0, fns[SEQ]); \ + cpu_env, maxsz, maxsz, 0, gen_helper_vmvr_v= ); \ mark_vs_dirty(s); \ gen_set_label(over); \ } \ @@ -3725,10 +3720,10 @@ static bool trans_##NAME(DisasContext *s, arg_##NAM= E * a) \ return false; \ } =20 -GEN_VMV_WHOLE_TRANS(vmv1r_v, 1, 0) -GEN_VMV_WHOLE_TRANS(vmv2r_v, 2, 1) -GEN_VMV_WHOLE_TRANS(vmv4r_v, 4, 2) -GEN_VMV_WHOLE_TRANS(vmv8r_v, 8, 3) +GEN_VMV_WHOLE_TRANS(vmv1r_v, 1) +GEN_VMV_WHOLE_TRANS(vmv2r_v, 2) +GEN_VMV_WHOLE_TRANS(vmv4r_v, 4) +GEN_VMV_WHOLE_TRANS(vmv8r_v, 8) =20 static bool int_ext_check(DisasContext *s, arg_rmr *a, uint8_t div) { --=20 2.35.1 From nobody Tue May 21 09:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650526151551648.4503584539941; Thu, 21 Apr 2022 00:29:11 -0700 (PDT) Received: from localhost ([::1]:46746 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhRFV-0006QT-26 for importer@patchew.org; Thu, 21 Apr 2022 03:29:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53822) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQRk-0005P4-O5 for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:37:46 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:13363) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQRg-0007yk-Rs for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:37:43 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 21 Apr 2022 14:37:30 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:08:32 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:37:30 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KkSWs6cqDz1SVp0 for ; Wed, 20 Apr 2022 23:37:29 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id yU4d_YRaBJzY for ; Wed, 20 Apr 2022 23:37:29 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.119]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KkSWq4V0Zz1SVnx; Wed, 20 Apr 2022 23:37:27 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1650523060; x=1682059060; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=NKi7BnguHKbUSL57AN/Ltful3DUcgnNz6gagWdPlB8c=; b=D+TGPnFnnuVKgSHjZk6SSn8GJ211jan/iajTx9bcXJMg2ZSKdb/lfNvl GS50oJoptsxtlZtrklgqK24Voewjr8H6WwerlVrAnOXCxc8h2NT8P4GR0 q3dMW9S9afbPzd7ugWLRS87o6nxQvOrQWCIkoEZXvXOJEk3TYFeAPYPfG 1wVWXKkwszGhBDJIzk1UhEkDLQ+ehc+KriGHGtY4RWZYCR6P/DUwBvReq DdSF5zAilFyYfST3hmIVSrLyU9Mul6PQfyzn5y18VrBUpDh1JEXSxusSj DHUzgArAE+OQlx0CNyYQ2PDmDjZj0Jc24AZ6548uPdAXRzSYnLGCFHTBY A==; X-IronPort-AV: E=Sophos;i="5.90,278,1643644800"; d="scan'208";a="302639984" IronPort-SDR: ITSBcYToVbzd6Jn8Zhaa4B+zAi0Krf0i/MoV9TfAYwOk78QpxPCB95DFHxTeOo0m7G2SC8wLwh MpTQZlDz5+hogTL+MFwMyGLmM3raeXXwxKbXi8AtTJpfvWK9nMDk7um50BnFhucuaqGKx/9W66 X8LAciLJkno//exYyibe7Jm88EHuXpvDYvkjrCaQxZUmX21CcOtCPr11SaAUzlROCscG5ddL/X NfCdLLbToC6pAP2fr+W+foxSqJwRWOscVEc1y7gcYDcg6yGthc9v+Cc0fnWso5qMf2NqYeV1eH p62RyLXtPLkvyhHW9ruiXuAt IronPort-SDR: IqB5FS7IxVBqU7CCdiig5Yv78E/P/CD991sTl5AmXdFK73pISDXH1RhvkVkp+wh+aotXT7cI2U hUnRS6LMP23zxW9cMUBK5N12l/qu2GFvOScNTypiWUQJesvNsY+wS/oqK+buGKtE4QDBOWbCc4 pckiKz958bE5nPeoyUsfJj8D7y+bSsjVrXRFKQy05OY3o4VnFD2uFbQtrWDgelE7ugENXJbymH /4XnHv2O7prUgNZCuT3Fs9F0syIOVKtMSxvRYuQSBELUEpFgOPlYciz3bcsZZ2/b5HllDOkVzc 1IU= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1650523049; x=1653115050; bh=NKi7BnguHKbUSL57AN /Ltful3DUcgnNz6gagWdPlB8c=; b=uP9p3wmcyPZDerwiUqC7nipGlcGVTlhQEg Z1SEYwbr0++aj7+fOJMF2dT3IFeQhTRcQTFqdnTp0c93XIkCTTjh6a6AAoNYOGHP 4eSPAzuSi1ant+uu/mTlSmuoJeMibFU45mSAJ7udaMqBaFFc5QhfU411zZZGKUdU 2dzhOEB1NOOzo+S7dgT1u/7deZAbyuWklkhHX1VS8y7bYyge/vwRMpnZ1w6z72OA 7rLClpK9HduW7jBWfEIeDspaFQjKLG47pfwWZCs95eM72V1fkhnenyn1IYr79/I0 gzR3/o0GmUNRHpOtmRwU1PGIZQGPXD+YfvmkZDOWGLETUT0a2eYg== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Tsukasa OI , Alistair Francis Subject: [PULL 14/31] target/riscv: misa to ISA string conversion fix Date: Thu, 21 Apr 2022 16:36:13 +1000 Message-Id: <20220421063630.1033608-15-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650526153917100001 Content-Type: text/plain; charset="utf-8" From: Tsukasa OI Some bits in RISC-V `misa' CSR should not be reflected in the ISA string. For instance, `S' and `U' (represents existence of supervisor and user mode, respectively) in `misa' CSR must not be copied since neither `S' nor `U' are valid single-letter extensions. This commit also removes all reserved/dropped single-letter "extensions" from the list. - "B": Not going to be a single-letter extension (misa.B is reserved). - "J": Not going to be a single-letter extension (misa.J is reserved). - "K": Not going to be a single-letter extension (misa.K is reserved). - "L": Dropped. - "N": Dropped. - "T": Dropped. It also clarifies that the variable `riscv_single_letter_exts' is a single-letter extension order list. Signed-off-by: Tsukasa OI Reviewed-by: Alistair Francis Message-Id: <4a4c11213a161a7eedabe46abe58b351bb0e2ef2.1648473008.git.resear= ch_trasio@irq.a4lg.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index cfdfe787de..edc33c44dd 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -34,7 +34,7 @@ =20 /* RISC-V CPU definitions */ =20 -static const char riscv_exts[26] =3D "IEMAFDQCLBJTPVNSUHKORWXYZG"; +static const char riscv_single_letter_exts[] =3D "IEMAFDQCPVH"; =20 const char * const riscv_int_regnames[] =3D { "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", @@ -911,12 +911,12 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) char *riscv_isa_string(RISCVCPU *cpu) { int i; - const size_t maxlen =3D sizeof("rv128") + sizeof(riscv_exts) + 1; + const size_t maxlen =3D sizeof("rv128") + sizeof(riscv_single_letter_e= xts); char *isa_str =3D g_new(char, maxlen); char *p =3D isa_str + snprintf(isa_str, maxlen, "rv%d", TARGET_LONG_BI= TS); - for (i =3D 0; i < sizeof(riscv_exts); i++) { - if (cpu->env.misa_ext & RV(riscv_exts[i])) { - *p++ =3D qemu_tolower(riscv_exts[i]); + for (i =3D 0; i < sizeof(riscv_single_letter_exts) - 1; i++) { + if (cpu->env.misa_ext & RV(riscv_single_letter_exts[i])) { + *p++ =3D qemu_tolower(riscv_single_letter_exts[i]); } } *p =3D '\0'; --=20 2.35.1 From nobody Tue May 21 09:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650526562512537.7798865837334; Thu, 21 Apr 2022 00:36:02 -0700 (PDT) Received: from localhost ([::1]:55612 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhRM9-00055G-3B for importer@patchew.org; Thu, 21 Apr 2022 03:36:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53852) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQRo-0005Pp-Dq for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:37:49 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:13374) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQRm-0007zd-4k for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:37:47 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 21 Apr 2022 14:37:34 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:08:37 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:37:35 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KkSWy1mkJz1SVp3 for ; Wed, 20 Apr 2022 23:37:34 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id bIUnBiql1Fkz for ; Wed, 20 Apr 2022 23:37:33 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.119]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KkSWt0kKdz1Rvlx; Wed, 20 Apr 2022 23:37:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1650523065; x=1682059065; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=zbmyGmJOcyh44B97juv66ZS7UlMtHdTZEo46jwcnD94=; b=kuQdkEfwHul4ipmIg1F10opcgaQo62+sWfm/9wqr/XCTF/bAt/AVrF6/ okopmvz3UePNL7iGpFoQSbpJutaNpoECQOPUOH95KPFBjSXBLaJFj6J+U kaFaHkekDpa6SxIuE1DlW0221MepvzEi9+zrwndk+6ZWUgTREI68IH2jI TEn6icmJ9j2k0M8sV4dfQbZxIRHPt9UNz7ZEfvmpMcBWLDsUNdPDc2O2+ XAi9bJpYwDU8G/ZSWLqymdymM/ek3Rr0jkQkSLBeZgCTQIBUyULlZOj0/ BNPkH6jlp1ivJtN3fnfJ0FrhyHJt/8zBMaIYB+ItuwU8YhAkLilbp05hg A==; X-IronPort-AV: E=Sophos;i="5.90,278,1643644800"; d="scan'208";a="302639990" IronPort-SDR: BwWl8y7AyjFBgoEKnwW/bqMaDiPByQkbyd09aP9I+wdFOanjSAC6gCQDFIH20iIkggUo1oOai3 90l0exXA819COX1NniyBBW7WMCK+gwW9isV3XqaOpS5YetIyeP6ogNeVeBCaeI1//s1k34zeQE WdWdZeKO/k/WQqiOofWizvd41BZRomq4ETR811p8DzAgTBLmoHkr87I7rewkw7+a+KazT9cUxd 4W9Np4RWp21blSKslDwyfIxBwEEnpoehLDAiDnPwwOlwGXdzrvk9uC7n9MQIPtjA1gDa97dcHr BVZzkQrLlb4mum8u8uQc+VLU IronPort-SDR: VJBmuavS8SGYimhNZPo4nOoh5XPa70u000rlwZ2zEkwFIMFM9BKMEnXAmx/uOj3/RmslZ0IFQ2 L7w0Ud9pUWsqFGjQf8MxI8kx6s+Q+ilj39IfeDjKeaKy1Y1S62nNnE5dt0CcoQkFrxX/LIL42C dJP2RdoL9PrdIsrS4jpVSInLkmgb6GF9rpLudIIEtmNRqH/dKVkRwaDZPFpYc15NqxHp3hh/Ok W1pZhCCZPpDYJCCc168A6RBaTzPK8Bx8+OK+xvqhWVRsYTynX4Fo2KK/DO9el8KzWB3hCE8Au9 bSk= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1650523053; x=1653115054; bh=zbmyGmJOcyh44B97ju v66ZS7UlMtHdTZEo46jwcnD94=; b=Qk/lH6+nZrMzS31tTI6e9HW3PX2QgglDfB rMPM+8wh7oeApaC0P3/E/OJmHyUKk7YFa9kZlUxmHAk1un0yQqg3ofBRfX5Yl5XQ Sheu6FRDawL9yeDbvLC4PcT/QETD1HxV0PpqkPK0Am6qZToYN8iqDdp5FZEzduI3 3+lv01i/F7/wWzgLpRmJ8a5Cf0g9u9LJ/DgjHKeNXXH2aZkKdSLAU8RquekBfMjH ajmUESQZKQu4XZhl1G99dwKTvhc4A2QNECoxPfjFGfoUp9cNxkZA9i10uu/SBmb4 AbdrJKn2RN6DQ4RxBsH/CpUxqLUay6J9IcE/NemhDggU4rGcjwYg== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Atish Patra , Anup Patel , Alistair Francis , Frank Chang , Bin Meng , Heiko Stubner Subject: [PULL 15/31] target/riscv: Add isa extenstion strings to the device tree Date: Thu, 21 Apr 2022 16:36:14 +1000 Message-Id: <20220421063630.1033608-16-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650526564715100001 Content-Type: text/plain; charset="utf-8" From: Atish Patra The Linux kernel parses the ISA extensions from "riscv,isa" DT property. It used to parse only the single letter base extensions until now. A generic ISA extension parsing framework was proposed[1] recently that can parse multi-letter ISA extensions as well. Generate the extended ISA string by appending the available ISA extensions to the "riscv,isa" string if it is enabled so that kernel can process it. [1] https://lkml.org/lkml/2022/2/15/263 Reviewed-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Reviewed-by: Bin Meng Tested-by: Bin Meng Signed-off-by: Atish Patra Suggested-by: Heiko Stubner Signed-off-by: Atish Patra Message-Id: <20220329195657.1725425-1-atishp@rivosinc.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 60 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 60 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index edc33c44dd..94f9434411 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -36,6 +36,11 @@ =20 static const char riscv_single_letter_exts[] =3D "IEMAFDQCPVH"; =20 +struct isa_ext_data { + const char *name; + bool enabled; +}; + const char * const riscv_int_regnames[] =3D { "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", @@ -908,6 +913,60 @@ static void riscv_cpu_class_init(ObjectClass *c, void = *data) device_class_set_props(dc, riscv_cpu_properties); } =20 +#define ISA_EDATA_ENTRY(name, prop) {#name, cpu->cfg.prop} + +static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_st= r_len) +{ + char *old =3D *isa_str; + char *new =3D *isa_str; + int i; + + /** + * Here are the ordering rules of extension naming defined by RISC-V + * specification : + * 1. All extensions should be separated from other multi-letter exten= sions + * by an underscore. + * 2. The first letter following the 'Z' conventionally indicates the = most + * closely related alphabetical extension category, IMAFDQLCBKJTPVH. + * If multiple 'Z' extensions are named, they should be ordered fir= st + * by category, then alphabetically within a category. + * 3. Standard supervisor-level extensions (starts with 'S') should be + * listed after standard unprivileged extensions. If multiple + * supervisor-level extensions are listed, they should be ordered + * alphabetically. + * 4. Non-standard extensions (starts with 'X') must be listed after a= ll + * standard extensions. They must be separated from other multi-let= ter + * extensions by an underscore. + */ + struct isa_ext_data isa_edata_arr[] =3D { + ISA_EDATA_ENTRY(zfh, ext_zfh), + ISA_EDATA_ENTRY(zfhmin, ext_zfhmin), + ISA_EDATA_ENTRY(zfinx, ext_zfinx), + ISA_EDATA_ENTRY(zhinx, ext_zhinx), + ISA_EDATA_ENTRY(zhinxmin, ext_zhinxmin), + ISA_EDATA_ENTRY(zdinx, ext_zdinx), + ISA_EDATA_ENTRY(zba, ext_zba), + ISA_EDATA_ENTRY(zbb, ext_zbb), + ISA_EDATA_ENTRY(zbc, ext_zbc), + ISA_EDATA_ENTRY(zbs, ext_zbs), + ISA_EDATA_ENTRY(zve32f, ext_zve32f), + ISA_EDATA_ENTRY(zve64f, ext_zve64f), + ISA_EDATA_ENTRY(svinval, ext_svinval), + ISA_EDATA_ENTRY(svnapot, ext_svnapot), + ISA_EDATA_ENTRY(svpbmt, ext_svpbmt), + }; + + for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { + if (isa_edata_arr[i].enabled) { + new =3D g_strconcat(old, "_", isa_edata_arr[i].name, NULL); + g_free(old); + old =3D new; + } + } + + *isa_str =3D new; +} + char *riscv_isa_string(RISCVCPU *cpu) { int i; @@ -920,6 +979,7 @@ char *riscv_isa_string(RISCVCPU *cpu) } } *p =3D '\0'; + riscv_isa_string_ext(cpu, &isa_str, maxlen); return isa_str; } =20 --=20 2.35.1 From nobody Tue May 21 09:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650525300485141.2047419477732; Thu, 21 Apr 2022 00:15:00 -0700 (PDT) Received: from localhost ([::1]:54710 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhR1m-00081s-SU for importer@patchew.org; Thu, 21 Apr 2022 03:14:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53918) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQRx-0005Yf-72 for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:37:57 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:13339) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQRu-0007xw-HQ for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:37:56 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 21 Apr 2022 14:37:36 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:08:39 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:37:37 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KkSX04FhYz1SHwl for ; Wed, 20 Apr 2022 23:37:36 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id jhjplSMW3G_O for ; Wed, 20 Apr 2022 23:37:36 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.119]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KkSWx6Pp8z1Rwrw; Wed, 20 Apr 2022 23:37:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1650523074; x=1682059074; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Z0bcwNN6HlsL1bsaGzbPna1G2EFlJ2LfVwXnwKyKZhQ=; b=lENrD0ZKMpPPxFe7ot2Dx5FOBwBZz8rNvy7df4mtyQ46DrC5iS6zlhMW iF23kBgDE+ZoB9d2rldLrnxNRgulpMnkiMWDJc33CGzcX+qo23heSVf2b eZvddaGwYkRBvEPBmJpSzsLB7wsFlkc0HTW5jXJVttDGtvMfV9+m1JdoL 9wiw4KH6j4Gtl4rc7IAgTuXVMl7vk5leLIKSUz9DiPYv+yHcLaX+8yRIg fm02rUEB8/cYxuBedqb3Q5otp2N4iFVA5a3uXBc2duKJw2XrJQM7z0m7t v11PF7+0HfgAJTkOUGLOT0cU0DaT3vB6WH1IBofxPLVZqIKiiyV9YpupM w==; X-IronPort-AV: E=Sophos;i="5.90,278,1643644800"; d="scan'208";a="302639995" IronPort-SDR: 7vY9/uCVer+3/zSnvZCeRvB6DyWaNnyItMi1IIgpRsXIeL32drm7QYMOFCUJzeNPDniutY0tKz WyIVD3ikFQ+5eZjIS8uHU5GALFeQZbEwoDmEiXrbEqemxkga6BrgvWUQY6sWNFsrxY9eMpD7Yo +MdEBwdCq3NojXZLgjeJa6YYOXWHQE6HBV1NH++I4MwE4lRXc44gl60QPxbEnedHROSvv9TAn+ UAg2A1xitCe3n8O8d0AoYDTE9aPIBppAZGhiXDdCypYkmhKmog20yTjSocKnyjOQ4jGc/Oe7A5 Mz2EhbU4de2T/N8AcJApionC IronPort-SDR: FH7MvDARn62zC/iKTrxTuaDlsHAQYoxoturSLEyF1Th9itW2Rioix/6G2x9mk55kdz6iwxDBIl XE3hae/AbT024FCg52067dCTNyhfJJsK2FbOe2U6mGxhkKGiYqB5UbffTuVdLQyAfLBmG2TZo+ 07BVL86r6P7loFkHa04aKG0No7pjY0VlodUY/uzOaba8Opoxt7f2hXR+cHihLvA5UT1O386lMR SH032GqKdVOlcHcwbtRcQJfYiAWQ+ZktEinfV+j6egd6ntMgVsODu1DuzId9KZqjcZ9F1ivJbJ nII= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1650523056; x=1653115057; bh=Z0bcwNN6HlsL1bsaGz bPna1G2EFlJ2LfVwXnwKyKZhQ=; b=XqnKWbg07CtFvXh+dJTA0gmOiAlsBqNDCg DvqoLK4RlBy3KmrJE9lUreqkgFE5Wko8xKJ95Zo88W7FW5jQU55vmTga7zjHUEb8 zDdf0NefQCA1eToIS+Jz3kLq8u2+UfAdYHOHnw6VEVr73vW1rIdUVeNAYU4gj0YX ehFhP3Y4goLynR8FGrMgYzBVqNOlmd3MZMoRoReJ1B12Bb2m9yL4kJdogEFFiwmY IHD3s1xjPDWKdNGgRjhzulvEl17IZk9ueSlM6DP04m3pZKlQWqjt3FOkVsqRHGLy 3lgWsj4oGz+NZFkxCUVO7Y2XTKWHKdPRd9B4qtoY04GYyN4/M5Xw== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Alistair Francis Subject: [PULL 16/31] target/riscv: fix start byte for vmvr.v when vstart != 0 Date: Thu, 21 Apr 2022 16:36:15 +1000 Message-Id: <20220421063630.1033608-17-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650525301411100001 Content-Type: text/plain; charset="utf-8" From: Weiwei Li The spec for vmvr.v says: 'the instructions operate as if EEW=3DSEW, EMUL =3D NREG, effective length evl=3D EMUL * VLEN/SEW.' So the start byte for vstart !=3D 0 should take sew into account Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Acked-by: Alistair Francis Message-Id: <20220330021316.18223-1-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/vector_helper.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index 99f3134aa0..576b14e5a3 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -4890,13 +4890,15 @@ GEN_VEXT_VCOMPRESS_VM(vcompress_vm_d, uint64_t, H8) /* Vector Whole Register Move */ void HELPER(vmvr_v)(void *vd, void *vs2, CPURISCVState *env, uint32_t desc) { - /* EEW =3D 8 */ + /* EEW =3D SEW */ uint32_t maxsz =3D simd_maxsz(desc); - uint32_t i =3D env->vstart; + uint32_t sewb =3D 1 << FIELD_EX64(env->vtype, VTYPE, VSEW); + uint32_t startb =3D env->vstart * sewb; + uint32_t i =3D startb; =20 memcpy((uint8_t *)vd + H1(i), (uint8_t *)vs2 + H1(i), - maxsz - env->vstart); + maxsz - startb); =20 env->vstart =3D 0; } --=20 2.35.1 From nobody Tue May 21 09:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650525637334936.702485836289; Thu, 21 Apr 2022 00:20:37 -0700 (PDT) Received: from localhost ([::1]:35218 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhR7E-00060l-6K for importer@patchew.org; Thu, 21 Apr 2022 03:20:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53920) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQRx-0005Zb-F0 for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:37:57 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:13363) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQRv-0007yk-2A for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:37:57 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 21 Apr 2022 14:37:39 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:08:41 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:37:40 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KkSX30bRzz1Rwrw for ; Wed, 20 Apr 2022 23:37:39 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id LmKVzNjwPfRj for ; Wed, 20 Apr 2022 23:37:38 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.119]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KkSX061yCz1Rvlx; Wed, 20 Apr 2022 23:37:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1650523074; x=1682059074; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=YWQm8OJGwY9DyLYO16rmNKLkbJlmv5Jq1hk2A+TppXg=; b=Kvd9JmsDdgj47s/uUc8MIGvddUgew16KLm0UnrandUitUO8Wd5RlxgxV XjlQzLhHLeVDSyxDgUDB2SWKCvp4MljLFbezuaRPevc2h2ulA0+1PvrL7 LRQdZtEgDxBscYrSYdOLJ9dNmWRHI9Mnw/6ntVUDNpo4OxzghkAhAiN9a dURKdN6XNnGoF5hygJR86TyJqy1ztkZFrF1IMMwjVFp1l1y3h7THdYgQx fBxuQ+eSjYBys4HxTurLhJIpoplyJ+vGM64A9GXDwqPNQEt+p9iCiAMCA qc9jOXou7gp3KAorYXH+ZXwCkHAVKbgARRXJJhmusLxTC7mUjwY6Yy5iO A==; X-IronPort-AV: E=Sophos;i="5.90,278,1643644800"; d="scan'208";a="302639996" IronPort-SDR: CTuYuSa0/3iO17CroMjhRgknGQNf5jNB0NgiwYKTd+VXlyjhIY3Mnrc5hHzFYbJfOh/9gv402K rPMwn7cdp8xs87ODCiOoNYdLFXfJsGDIM1QVsaj/opMGBTK+ayItsvApVf+YjrbfoyX4eHkyPO eFJYHgECqcGrQnzcDkwHfZ7t9hCFKoGm3o2MuGEsvRNR2PSDPHqX3jpQ37cBfTcBYWZ4BLnbar z6OUlDHWi4Pf80BZnnejGiuzwhB4XORZXDaVKm/Gl7oqY+mKe7yx8zKXNHpUnI4hQE8uYzEju/ JsigAWLfjEQcH491KxBTQpuR IronPort-SDR: bxeNAOGKqPY19fWEBsCuuIVm4MAgfGNqRue+ksDBrhR7e4i45ktwiRvr9TYD8fqlNOETfJyQ0U 89gobvfjtX3gMnwwVrhwF5tieRmgvC9IkMULFX/IEOtgP8fTOR10yzv8NvXcd+peImcrWjYkEE XpqmReuvCIH9V/7sWKtJE+UvUfZclfsZJ0crJmE7OcLPZdJQFJJ5wSXlWTtV10CR859yK1XSUO j9Y4fTC+ZjT1pIP//ZMlsQ5oxkpvLmXmJp3uYxZk/ilIOelrzhoYDpnri7hVQSAMJdiMTQVhgJ Wy4= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1650523058; x=1653115059; bh=YWQm8OJGwY9DyLYO16 rmNKLkbJlmv5Jq1hk2A+TppXg=; b=VA4h/Y1PlMly8bIDXZxIERKppLN6DTMr+s W0NteRJuk9meTKZvsQexxnjCVOBGQf6q6C8XZjZoZuC/AUSK4bmp8PTInG2Pxhy3 F5+Eutr/m1CJHktYQ8dci493x0rI0NRgMMhhnaB0AL0Uahw7EgAp1ZZs4EzKOvdt OlHf/YwG43hWEItwzjORdgz5+xOU3cp0fdV9YTVDQ85asVmz1pGUCtq1q1b7WVX9 jAuOxOH/82rcsxv9YajA0zAP+sMpBlXYRIYKdBsghJsYy/SqXdrkWw2RbBFR3Srb fCGj6V76A7nILRK3RRdh41mZEY6Gshax1TGvlvU2PUR9qBDb9uNA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Richard Henderson , Alistair Francis Subject: [PULL 17/31] target/riscv: Use cpu_loop_exit_restore directly from mmu faults Date: Thu, 21 Apr 2022 16:36:16 +1000 Message-Id: <20220421063630.1033608-18-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650525639123100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson The riscv_raise_exception function stores its argument into exception_index and then exits to the main loop. When we have already set exception_index, we can just exit directly. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20220401125948.79292-2-richard.henderson@linaro.org> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 1c60fb2e80..126251d5da 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1150,7 +1150,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hw= addr physaddr, env->badaddr =3D addr; env->two_stage_lookup =3D riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(mmu_idx); - riscv_raise_exception(&cpu->env, cs->exception_index, retaddr); + cpu_loop_exit_restore(cs, retaddr); } =20 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, @@ -1175,7 +1175,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vadd= r addr, env->badaddr =3D addr; env->two_stage_lookup =3D riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(mmu_idx); - riscv_raise_exception(env, cs->exception_index, retaddr); + cpu_loop_exit_restore(cs, retaddr); } =20 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, @@ -1311,7 +1311,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, first_stage_error, riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(mmu_idx)); - riscv_raise_exception(env, cs->exception_index, retaddr); + cpu_loop_exit_restore(cs, retaddr); } =20 return true; --=20 2.35.1 From nobody Tue May 21 09:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650526957326749.6451153109178; Thu, 21 Apr 2022 00:42:37 -0700 (PDT) Received: from localhost ([::1]:36060 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhRSW-0004EJ-2O for importer@patchew.org; Thu, 21 Apr 2022 03:42:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:53966) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQS0-0005dZ-D0 for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:38:00 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:13374) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQRy-0007zd-Mc for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:38:00 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 21 Apr 2022 14:37:42 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:08:45 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:37:43 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KkSX62DK2z1SVp0 for ; Wed, 20 Apr 2022 23:37:42 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id IsZJ3ZYKRorH for ; Wed, 20 Apr 2022 23:37:41 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.119]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KkSX32LcRz1Rvlx; Wed, 20 Apr 2022 23:37:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1650523078; x=1682059078; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=Asrx2POXRJ0pZuD/WMHlGXXuWvs40U2nwecwTv2Oge4=; b=N1VViHK3ZNkyNCSWIuThPqL4yl2Nj5brnpJP3JZ4ZB2JRnjUB8jvSAwR tpkA+DqqbELNwgNgBKT7IQ3mG5vvvDX7fJppE5bFBstIsIgh3emPGkybA CFsBw+qV5LA11GV1X7Isn+woxF4sq4814b7wOADARSwKCE3fPVqtkLVDz auxjdhM4XgESp7GUbgIQ8pVs2KKDfy+2OJSZBmmUJye/jxgVES78Qa+6k WwK1d8+qCwZ6l9hur7MCrHvbkx8VyWgBohYVXkJJHHlbaSw8AKTjfwEtY AFMna1v+KajnV0rxSLNl8ek2BTf5waQihFvMx6MKXlL5eKeSPEkJ2fNS2 A==; X-IronPort-AV: E=Sophos;i="5.90,278,1643644800"; d="scan'208";a="302640000" IronPort-SDR: Bquj1N532X7u/Z5BmO8r21s5aqzHG4I9dufA4zXD3cXEZnRCMDAUlambW9FPXUmqxHYzuO+4yV cvPnA5y7BLHPWybbpsE3ADbaFKXrOBuLAYYzz2vOKZt9/ZTSbxi7zCRMl8md0poYDXrX0nlrLZ XlLrpr6V6637fijBYBgGNy4ae0bUSG1ghWimBBVA+XtZXRcy9OtYKaTrtgmjSuIiOwJ7IasPFk R3XDN57j0aRgRWRID2VCY0QM9nKCvmvagmCgUv2nQF1LKIjXLucH4tIutIEI3E9uD9P2z2PM11 9BQI/Foyn+RNWY6ng/UOn1A5 IronPort-SDR: HivXSFM8/4X2JpxacdOqkwbskhsmeOPoqe4xn9e1NS5cqFKtnEzbl4ZcGQAfoAJprnfXDoVCcY firDAq2XHtGC6IewcVeWJ4vGpdVNESB+oTYfblkZREVlWVKNnu2uHSiR6uU9jsTjnJGouCXgn7 zOqyda7Ff6x+oz0bMZeXQbScYUjv73z6S8pQ41RqluUFI6yu8M3H7nJAUYcSUqhPIA7EW9/NnE 6qt9XGIPUsJc3e9w3i1H/21G+HDR5Ld8CbLoG4xiFkVX7Fl+ODhOQCqLPTWumjDltoShl83LaZ 4oQ= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1650523061; x=1653115062; bh=Asrx2POXRJ0pZuD/WM HlGXXuWvs40U2nwecwTv2Oge4=; b=dDx73NYWhZR8t0U2XAKFFyL3FWrTe4uUlQ BoEGXav/rWPbuRReQrNvYE0iA9vvhMcSJKCBhiHIyf8M0X4PORyN/wetW9pOmGVV WpnHl6YAu0mm052nuG44DdU8h0KGng2xdNP8lTpkUKot15lAk/8tUQHiUfo1XKyv lC/P12kmpIYwRtlpOhJXyDvjdX1sW+LmHCPtkqG7FdxwW8qIjhjoAvK5qEFG6179 9HPygeN7eieYQ/GlehA/dl1cVhJRW93UOaWJP3hLAQ6DREPOS0i2agE3N3ARPosM SnXMlCQawYSpaS/fcxipFG9jwbP0ILFV57PQTVLA9TmOjcP88Z6g== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Ralf Ramsauer , Alistair Francis , Bin Meng , Anup Patel Subject: [PULL 18/31] hw/riscv: virt: Exit if the user provided -bios in combination with KVM Date: Thu, 21 Apr 2022 16:36:17 +1000 Message-Id: <20220421063630.1033608-19-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650526958817100001 Content-Type: text/plain; charset="utf-8" From: Ralf Ramsauer The -bios option is silently ignored if used in combination with -enable-kv= m. The reason is that the machine starts in S-Mode, and the bios typically run= s in M-Mode. Better exit in that case to not confuse the user. Signed-off-by: Ralf Ramsauer Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Anup Patel Message-Id: <20220401121842.2791796-1-ralf.ramsauer@oth-regensburg.de> Signed-off-by: Alistair Francis --- hw/riscv/virt.c | 14 ++++++++++---- 1 file changed, 10 insertions(+), 4 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index da50cbed43..09609c96e8 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1308,12 +1308,18 @@ static void virt_machine_init(MachineState *machine) =20 /* * Only direct boot kernel is currently supported for KVM VM, - * so the "-bios" parameter is ignored and treated like "-bios none" - * when KVM is enabled. + * so the "-bios" parameter is not supported when KVM is enabled. */ if (kvm_enabled()) { - g_free(machine->firmware); - machine->firmware =3D g_strdup("none"); + if (machine->firmware) { + if (strcmp(machine->firmware, "none")) { + error_report("Machine mode firmware is not supported in " + "combination with KVM."); + exit(1); + } + } else { + machine->firmware =3D g_strdup("none"); + } } =20 if (riscv_is_32bit(&s->soc[0])) { --=20 2.35.1 From nobody Tue May 21 09:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650526020205697.1586935543635; Thu, 21 Apr 2022 00:27:00 -0700 (PDT) Received: from localhost ([::1]:44244 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhRDP-0004Jz-29 for importer@patchew.org; Thu, 21 Apr 2022 03:26:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54024) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQSA-0005hv-8L for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:38:11 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:13339) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQS7-0007xw-IB for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:38:09 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 21 Apr 2022 14:37:44 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:08:47 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:37:45 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KkSX84XCTz1Rwrw for ; Wed, 20 Apr 2022 23:37:44 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id KEKi0nHkruMr for ; Wed, 20 Apr 2022 23:37:44 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.119]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KkSX63PjPz1Rvlx; Wed, 20 Apr 2022 23:37:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1650523087; x=1682059087; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iEoKxEagVtDboj6y1cxqsma5Bz1Cu3f9t3vEDTHmk50=; b=QIGhrUWGWl6ZHOtFDnaPkJlvjv1qlefD9YqK8HgpDRNVnNuGvcrotHz6 c7c/zKbFzaKaE5m9bsnKdzDr/COCDsIYMYQ7MBDXJBRYcjsHINBFIN6Y3 rb2ilPymVCVJnKZ8TsZHwxzo5wFQXvTJsLcm8jIQ4J1Fea8ML0owHkR4h LIVoJ2oD17LQI5Ii5Bi3mAaJ1PZM5wkN3hDKwEUeCYCqxSlWiAr0/4PpV 4rJf1rhP9S3G9yvGki8LtYNTWNafKm9V3Id7oiHAmw9wTzR+YK53/V+xG KB2KJdpLMGjPh4ih5LS3QjHN4f2UoxT+dxgVtw+/ZTeoa1BgzJecNpLRY g==; X-IronPort-AV: E=Sophos;i="5.90,278,1643644800"; d="scan'208";a="302640005" IronPort-SDR: EHqDmCofxWj2l2M601AzJ4Fm4m5TLRH/iD5ou9r1Or3dFQc4qwwNKyWEXEzSIbAt1HKl97/EZK hWU34MK5njmN7Qr0LgMY6UXCdEbgvi9LUURJXSqe87ml1OVAXo/g1oz2Y7pMRJVQl09qPXI/84 LqE7uM2Ihmq3c3vm9HnURg1/k/VXZ7DjKEP5tj87QgpxFIJi+wY8OR7sU+5i5CnEMeDrnzv2iY eMkOs1tU71Cv+/fgNkkDKynqvJ4FCnChSMlZTVF469r+kzxk1F4gtv7WCSDt6gT5Y49FNMkzn9 dn/NSSkATDGF7qdsi/pQNE9z IronPort-SDR: ImaWAqrgzywzVByMT/Gi6fWndiX30HxLSyD7uQHOyuIAiepwo2j84g+LNfHXlTZZD4KI1omwgi YGvCiLyMuDJSan+1A4ZoEXlIiJHM6dBLGNiNHQ4ObqEWeUwUaAffQo8la+Tim5ISOal7/9iUUb XeNRtRnqbnzbRc+J4jRe5UTYxZ8UaWQf6y+0D27BJyTe54Jqbe82F8s5bd2Q+g25KwRKZyeHG3 zq0gwimEdkNo2YKy4pn9l0lnzJbL3ttbkn7XzXIQUQnwv7vmQIs6kucL+Mw5roBWwgiFG2eZxv 6Cg= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1650523064; x=1653115065; bh=iEoKxEagVtDboj6y1c xqsma5Bz1Cu3f9t3vEDTHmk50=; b=hLPLOFB3zlX9jDcmT3qWqo7/v7sURkGBnz XuL6Nyl6Iv5o9CEM7N6uajDuQKAgI+lUGouz0meNx6LF2Qfj4ReS+EQxiXZaHqEZ S2zfbjkhVBGTARDMKUi8sZ7tCOli8D6bgpFjq+9PVDRIM1nUurqR/9Up+eQp3/ez zG7K1jYHRPo6DK9xnkFmVdg7UBbf5aE1x6bh/ygi/fsa9LgU5gr0ZJLGK32M+FLZ uKUh4dehBF0Jnyi27nBsHYjOqTApw8SF+jp4QMXnLt/wl8SUMY+3vcQJep4WlYjw DkJM4+mWaKUslCyu4XK0FbFsQUr5m38mHLXZxgW4tfJN0w4rlnxw== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Nicolas Pitre , Alistair Francis Subject: [PULL 19/31] target/riscv/pmp: fix NAPOT range computation overflow Date: Thu, 21 Apr 2022 16:36:18 +1000 Message-Id: <20220421063630.1033608-20-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650526020877100001 Content-Type: text/plain; charset="utf-8" From: Nicolas Pitre There is an overflow with the current code where a pmpaddr value of 0x1fffffff is decoded as sa=3D0 and ea=3D0 whereas it should be sa=3D0 and ea=3D0xffffffff. Fix that by simplifying the computation. There is in fact no need for ctz64() nor special case for -1 to achieve proper results. Signed-off-by: Nicolas Pitre Reviewed-by: Alistair Francis Message-Id: Signed-off-by: Alistair Francis --- target/riscv/pmp.c | 14 +++----------- 1 file changed, 3 insertions(+), 11 deletions(-) diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 81b61bb65c..151da3fa08 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -141,17 +141,9 @@ static void pmp_decode_napot(target_ulong a, target_ul= ong *sa, target_ulong *ea) 0111...1111 2^(XLEN+2)-byte NAPOT range 1111...1111 Reserved */ - if (a =3D=3D -1) { - *sa =3D 0u; - *ea =3D -1; - return; - } else { - target_ulong t1 =3D ctz64(~a); - target_ulong base =3D (a & ~(((target_ulong)1 << t1) - 1)) << 2; - target_ulong range =3D ((target_ulong)1 << (t1 + 3)) - 1; - *sa =3D base; - *ea =3D base + range; - } + a =3D (a << 2) | 0x3; + *sa =3D a & (a + 1); + *ea =3D a | (a + 1); } =20 void pmp_update_rule_addr(CPURISCVState *env, uint32_t pmp_index) --=20 2.35.1 From nobody Tue May 21 09:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650523957754550.0755242565508; Wed, 20 Apr 2022 23:52:37 -0700 (PDT) Received: from localhost ([::1]:54186 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhQg8-0002E2-JY for importer@patchew.org; Thu, 21 Apr 2022 02:52:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54046) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQSB-0005iH-4V for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:38:12 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:13363) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQS7-0007yk-NU for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:38:10 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 21 Apr 2022 14:37:48 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:08:50 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:37:49 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KkSXD123Cz1SVp0 for ; Wed, 20 Apr 2022 23:37:48 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id ykrVPh71Uhbv for ; Wed, 20 Apr 2022 23:37:47 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.119]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KkSX86VmPz1Rvlx; Wed, 20 Apr 2022 23:37:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1650523087; x=1682059087; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=iYb56uk7QkQsKRVbU7X3OT4/rDP+/H7r/KJa/gw5Ij8=; b=RS8AmHpYAz9Et0JjN5Wk1wjg9VoiYzNiTcc5Yc7hGNxOVWb8LW1IkKU7 OHVsRM89mmHxIm4+CWyE+gNQ2dPfdOEr/0p/BPdnjXxyykoyJ21Vv4sWH uQBBLcDycOgZ8ruj5W8QFd2tP0gfrJcg1J+gpjWjLVGNLlj4QFxYFw93a zW1HJb2+CkP9cpKDceFGttpJ/42cq2xWtagWx9ZIjklcottFQf9nfig+x 58bxbZpLdfLjVabQSoyGgzkR0XYeW6SrzwZcIoWSFZsZnyytOFi1g11ac SkJ5NB3sg7nA8QCQIzf2XRymCd00Jq1H21Ly5pKVPJcJo7RqA78xXPRLe Q==; X-IronPort-AV: E=Sophos;i="5.90,278,1643644800"; d="scan'208";a="302640009" IronPort-SDR: 8DJvk4hMx0RdM26UdFgiVNvqY6+Nlqdm71QRY+OTYpNAa4zAyimL9X1jiGIw6x4Edgrwn12SgN /u+O/njSl8eoGOYPPlvuC4ZrcVheWXdAcPmWIvNzGyMlQYMmsusWJ7v5FDOcw4c+8xJmhy0uWm 7Wzhc3lwhokrH3BZlhLHRSc2jo9OKyW9jyEeop4Oi99y1p+2hqXCzVkzHkMJEFyCUzvqYoSij/ BS3WqBOT2XjT8g7ojCfYdAPrZje9WAKkDqWz/ME5TpKzd4bxNv7NUyCiA6wWFLTbTb67Seqsr8 e5MJnnmonYo49dyM0BqJADlX IronPort-SDR: tZD/KNfdz137PxHPYohtbQQMnI7Yh9XH+ab1islJkNwC1+z1v3qWTvHnxgY6CHpTrLwl6Que/1 ceJhww0H+5dctWLmSXvG3HYjl4aO/d6YRylwR22ru5DBKA3s3IjDSc8oYSdbvWem6XPpC2D7V4 2/1mojV7ZI7KQ8lJgzVDMM/lb9WriEtsyyfQy0D2XdMJwyvmPNGXw4v2+3MVYHxniy2UYJqTma 0dYZuocR/GR9tiCze//v87TNSB1ErFQiXS/4S22wTL9zHfaULY3bjfwMRMoSZTAxHy3/XCG9g3 U0E= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1650523067; x=1653115068; bh=iYb56uk7QkQsKRVbU7 X3OT4/rDP+/H7r/KJa/gw5Ij8=; b=sCKALq9SSeeQZ9nghpYhD/NrDfwFPPNaeP sZN2a7+WVm+rk1PxppVfmz8vc3YrGXADRD8gQwzOmG3ALl+fCXLcOrOZBRyHMen/ bfuJlyA8vFpxBLm5ij38XwZhgZcghTDWJdUqRYefFNvTfaslBwlpmkLOKM0KJaOI DcfRrzDh7lz6dDh/hpibA4h4Hoq2XURbWocB126LmpVtpmWkC/8PbFiAZfqarN7v DgUBp5Fdr9b6Qb11wB+I//Pmp0XbSjSmSjZFjdI+L44VbpDBMvnEVwAAft3SlkrQ qrpWajPe62Eq2YGG2ftZsXUfG5h1kni26b6/1GQ8bNtx2ziSIZFg== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Niklas Cassel , Bin Meng , Frank Chang , Alistair Francis Subject: [PULL 20/31] hw/riscv: virt: fix DT property mmu-type when CPU mmu option is disabled Date: Thu, 21 Apr 2022 16:36:19 +1000 Message-Id: <20220421063630.1033608-21-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650523958706100001 Content-Type: text/plain; charset="utf-8" From: Niklas Cassel The device tree property "mmu-type" is currently exported as either "riscv,sv32" or "riscv,sv48". However, the riscv cpu device tree binding [1] has a specific value "riscv,none" for a HART without a MMU. Set the device tree property "mmu-type" to "riscv,none" when the CPU mmu option is disabled using rv32,mmu=3Doff or rv64,mmu=3Doff. [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree= /Documentation/devicetree/bindings/riscv/cpus.yaml?h=3Dv5.17 Signed-off-by: Niklas Cassel Reviewed-by: Bin Meng Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20220414155510.1364147-1-niklas.cassel@wdc.com> Signed-off-by: Alistair Francis --- hw/riscv/virt.c | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 09609c96e8..b49c5361bd 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -230,8 +230,14 @@ static void create_fdt_socket_cpus(RISCVVirtState *s, = int socket, cpu_name =3D g_strdup_printf("/cpus/cpu@%d", s->soc[socket].hartid_base + cpu); qemu_fdt_add_subnode(mc->fdt, cpu_name); - qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", - (is_32_bit) ? "riscv,sv32" : "riscv,sv48"); + if (riscv_feature(&s->soc[socket].harts[cpu].env, + RISCV_FEATURE_MMU)) { + qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", + (is_32_bit) ? "riscv,sv32" : "riscv,sv= 48"); + } else { + qemu_fdt_setprop_string(mc->fdt, cpu_name, "mmu-type", + "riscv,none"); + } name =3D riscv_isa_string(&s->soc[socket].harts[cpu]); qemu_fdt_setprop_string(mc->fdt, cpu_name, "riscv,isa", name); g_free(name); --=20 2.35.1 From nobody Tue May 21 09:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650526474577717.5742490878636; Thu, 21 Apr 2022 00:34:34 -0700 (PDT) Received: from localhost ([::1]:53424 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhRKj-0003cA-FT for importer@patchew.org; Thu, 21 Apr 2022 03:34:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54080) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQSD-0005j3-58 for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:38:15 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:13374) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQSA-0007zd-Ts for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:38:12 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 21 Apr 2022 14:37:50 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:08:53 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:37:51 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KkSXG4hZWz1SHwl for ; Wed, 20 Apr 2022 23:37:50 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id eKGp3ZLfrxDz for ; Wed, 20 Apr 2022 23:37:50 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.119]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KkSXD0gr1z1SVnx; Wed, 20 Apr 2022 23:37:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1650523090; x=1682059090; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cCSvh9NLyfh13yHT8AoxiS9EOLBc9JbgMzZo/YDkN0A=; b=iFZVOQ3T1PduVZ+ZV0+x1sGRGJUJYHicsz+5P4Y5swv9NhHxTc7StuEx koeO5Mh2JOqSulraXwce/NRJnSg+yx5Z7H0ntRtlI7zQ5IeHOmuQLIIdt ESEjue6vQCi672oMEF6Kc/sPQAWUIyfeQqMO8fO/Y4aIwHFbXarleX7nR 57MiKXAJi0dCbh42hQPdQcBAN6/lY35JMlP18LAYS2H/prawruCfrrz2D sBECXPetHtRmSIe2/C+m7LwFH5bWNRHV4vT+sVU+f1khpEv3cJnNSofQd ST9tZBa5O3aXigguA/Sek1v8oZG2rLG70XCAYoK2gVn7x2PodS+b+Z3Tz A==; X-IronPort-AV: E=Sophos;i="5.90,278,1643644800"; d="scan'208";a="302640010" IronPort-SDR: 3+aDraApS6j8GsMrZJ3fSJNCqIFQbIocQeQODcXxL1JTV0rB2/vHON+dykQJujk38JvJ89y+QC vJs+bFLFhy14JOBervZbD6zHEMn+nTfFhsy/eMYNqOvk7XGEfuSME9pY6/xFM2e5GV/8RyWUyv 3q6vWIKDcjOVFyAx4e1tP65kx+7cWebEQRQK7Rb0B3NNoN1pKubZPWJHCelMs5AaPJrJQMQhP6 icO3o6i1WRREkPH4luTzEQfhsbCXNd5vxhrzzN+eNf/7ELCMTiK3QUaG5oxA/bVt6dkcxZlsrA A9JWn11xUxcZTWHb3gxoSLhB IronPort-SDR: wlryxQZ/prJZixdfyqPOTRcXKlblI7e0rMBlG1KkPmPjp9uDxtWW7PSjy4CTXXtkjbPEYljYEk 8DHmMQ1uIlfV8MMwgcFToqZ7aQOmHcbBuWKZVZsyh5Y+OmpSWyroo9oJADpAqGNKrHorjW0Gsd gCXQxxA47YflzwSZwFtmf7PsUGTy7jxSKaCFpMCfyQMSGjOB12QWnxzGDObE7pdUpVJ9i79pin PUaxnbIB/AlTmW3JN0qzOeFsbtTa0Zn2my8pYqXuJ3AwjQ8w+hOFcPmdlGTjXs3AOB0lJFUJix e2o= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1650523070; x=1653115071; bh=cCSvh9NLyfh13yHT8A oxiS9EOLBc9JbgMzZo/YDkN0A=; b=OTEJhLZHFreIO0cBBYN/JzBG74en0oPuJV SLQSdGE7mUwJr1oajadpmrBcy9MsN9MLt/pBpy39hjXs+yRqi1MAE1cf71KXhfvI EEywVKz5C8xR/52LxzdkAp1MCM8S7+2JAeubGUT1e5F3vRlDu2uqBlSE7RgqLQxw UB4OJUSC1KCxiszFL4IFeMvA0iiTZXaz+iSP0TUTmkLbVetIqWZKPKl8AhbIxGth 0K9uF5QUWGEz15LIldGLKU93ijdiz2Cz1VftQhVvWmL7HZjVa4fLdB+EX8xCtsVI aiGFysd5fXa3C08/X4GVnJmQsAJDbXtdwNZDPudo8FZdqZ3eMxYQ== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Frank Chang , Alistair Francis , Jim Shu Subject: [PULL 21/31] hw/intc: Add .impl.[min|max]_access_size declaration in RISC-V ACLINT Date: Thu, 21 Apr 2022 16:36:20 +1000 Message-Id: <20220421063630.1033608-22-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650526475576100001 Content-Type: text/plain; charset="utf-8" From: Frank Chang If device's MemoryRegion doesn't have .impl.[min|max]_access_size declaration, the default access_size_min would be 1 byte and access_size_max would be 4 bytes (see: softmmu/memory.c). This will cause a 64-bit memory access to ACLINT to be splitted into two 32-bit memory accesses. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Reviewed-by: Jim Shu Message-Id: <20220420080901.14655-2-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- hw/intc/riscv_aclint.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index e43b050e92..37e9ace801 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -208,6 +208,10 @@ static const MemoryRegionOps riscv_aclint_mtimer_ops = =3D { .valid =3D { .min_access_size =3D 4, .max_access_size =3D 8 + }, + .impl =3D { + .min_access_size =3D 4, + .max_access_size =3D 8, } }; =20 --=20 2.35.1 From nobody Tue May 21 09:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650524395999640.5173260172194; Wed, 20 Apr 2022 23:59:55 -0700 (PDT) Received: from localhost ([::1]:36160 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhQnC-00017e-Ll for importer@patchew.org; Thu, 21 Apr 2022 02:59:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54130) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQSM-0005py-P1 for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:38:22 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:13339) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQSL-0007xw-0K for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:38:22 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 21 Apr 2022 14:37:53 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:08:56 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:37:54 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KkSXK3XM9z1SHwl for ; Wed, 20 Apr 2022 23:37:53 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id IKIKpvaamRF0 for ; Wed, 20 Apr 2022 23:37:53 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.119]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KkSXG69t4z1Rvlx; Wed, 20 Apr 2022 23:37:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1650523100; x=1682059100; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=8mhuYUPW9ubp8b714MlCocfN5p7aZHrweYlFCZCpOpg=; b=m1Su9TmQAxA4U6mvJPhYoEV9LXgCwHbNYXdX3V2LekBQU7sAdEU5LFsC Ii1Uds+XDOh00BqRsDHYnLhedYK1DqVGPKOViimwZVR/SYT7UxZpD8jAu syEzjWZapXajLedvcfpNS3hkAwJDCacwhFqJSZ0gsjf8npIyqdKttd05U SqVhFEaYWPqteGz8MywVc+11m+SDDKRO42FQk1XhfjcQDEfU167xxzdl6 wyw2BxW/wXavOa5BXIm8V4WRaOJ3TyfxVVkr4R/Z8zFmExANBsiXvk3qa qNwgvqEnRw2Mchw/580HggIqpE+G40/Bir4LHk3q08W28J3M2h4heK7Jb g==; X-IronPort-AV: E=Sophos;i="5.90,278,1643644800"; d="scan'208";a="302640014" IronPort-SDR: 2D1o6X2H35pvOo1PdH59ahoGnlaQ+kJSGNIOxFFsphM/qaS3DEauwUyYg1t6KXZbKE5VXt4S1M 5tWGQTIPdfdlxGbxvIKVlhV1ToZP9pnqq1w4genmrQ5scqGgOTnM4lHCAiL2OIbfTbMT3nOzzY rcD6uzzExv2Gvg0tcwUErQjp4v6xeiLvTS3g+ziWT8TnSGbpHdk19i8jUEctRwMV6rsQ8qqRaw eRIjsXecHSCRxjur9V0wuEpsUzDJfXzOJWy+V52WKejarqIoQpAL6dpVfc+cQvunc3FP5PLCAw pHHGE5dyr+Wfe44MUs7P0Uu/ IronPort-SDR: 3Dw0GP03DHppayA5sDBpIP1VELH7LkDO9pF9r33OUylKt5FwwOdNtUjymjdRzhzgbCwlncVQvk FvaV0Q+y6K8kJBbquutojLo+3yr4KXwG+JcsJIlEB9xZ+jlEfRPG/pmplKWMgx75uKac3LBEuW tleIaJVwO6Hf28WmR3S+mYl7dNs4i7mm/1nqaNHyGS0/p/3hcb0ikAgQopgIptl4tSEoMSKvYc CzPHpVb1ZxnDDYj9YpukQPfUOce45WvKTxQuIFBl2dFS4c4Ypyr2QeiCIjRkL4eowfK4tkVSFQ 6YE= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1650523073; x=1653115074; bh=8mhuYUPW9ubp8b714M lCocfN5p7aZHrweYlFCZCpOpg=; b=G9TIwq1u4JSY/VtTU6PXtHsb1hvoMjg/eK 8PJ1eiQBq7FdqA1/5XTpljZ/pHcWV3xtbehNyVjQD7C4jDkmZLGfgtsyOyzZ+bC0 kiIiEX1QurSYM2+ZjsVECZZizYf/L9QZXB216QftTOFr4lfP9hhoIwvt7yaOU+cE F+iibBHKJU3zPBOXA9YsaZi4wTfQz8avju9lVfqHZ4o41Ahf/kTvcyjt3ty3gOes 1WFofFhwyxYLT2bJMTaRrWpSRUVjUuGKvXIZkZdO1DOISZa4eN340pLjpijCYpe6 OmIXEKXrYjbGFdEoU+f1bXq5Kt5S9SwPXnjn2mq44v9/87fY4QwA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Frank Chang , Alistair Francis , Jim Shu Subject: [PULL 22/31] hw/intc: Support 32/64-bit mtimecmp and mtime accesses in RISC-V ACLINT Date: Thu, 21 Apr 2022 16:36:21 +1000 Message-Id: <20220421063630.1033608-23-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650524396671100001 Content-Type: text/plain; charset="utf-8" From: Frank Chang RISC-V privilege spec defines that: * In RV32, memory-mapped writes to mtimecmp modify only one 32-bit part of the register. * For RV64, naturally aligned 64-bit memory accesses to the mtime and mtimecmp registers are additionally supported and are atomic. It's possible to perform both 32/64-bit read/write accesses to both mtimecmp and mtime registers. Signed-off-by: Frank Chang Reviewed-by: Alistair Francis Reviewed-by: Jim Shu Message-Id: <20220420080901.14655-3-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- hw/intc/riscv_aclint.c | 42 +++++++++++++++++++++++++++--------------- 1 file changed, 27 insertions(+), 15 deletions(-) diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index 37e9ace801..ff082090fe 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -126,9 +126,9 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque, = hwaddr addr, qemu_log_mask(LOG_GUEST_ERROR, "aclint-mtimer: invalid hartid: %zu", hartid); } else if ((addr & 0x7) =3D=3D 0) { - /* timecmp_lo */ + /* timecmp_lo for RV32/RV64 or timecmp for RV64 */ uint64_t timecmp =3D env->timecmp; - return timecmp & 0xFFFFFFFF; + return (size =3D=3D 4) ? (timecmp & 0xFFFFFFFF) : timecmp; } else if ((addr & 0x7) =3D=3D 4) { /* timecmp_hi */ uint64_t timecmp =3D env->timecmp; @@ -139,8 +139,9 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque, = hwaddr addr, return 0; } } else if (addr =3D=3D mtimer->time_base) { - /* time_lo */ - return cpu_riscv_read_rtc(mtimer->timebase_freq) & 0xFFFFFFFF; + /* time_lo for RV32/RV64 or timecmp for RV64 */ + uint64_t rtc =3D cpu_riscv_read_rtc(mtimer->timebase_freq); + return (size =3D=3D 4) ? (rtc & 0xFFFFFFFF) : rtc; } else if (addr =3D=3D mtimer->time_base + 4) { /* time_hi */ return (cpu_riscv_read_rtc(mtimer->timebase_freq) >> 32) & 0xFFFFF= FFF; @@ -167,18 +168,29 @@ static void riscv_aclint_mtimer_write(void *opaque, h= waddr addr, qemu_log_mask(LOG_GUEST_ERROR, "aclint-mtimer: invalid hartid: %zu", hartid); } else if ((addr & 0x7) =3D=3D 0) { - /* timecmp_lo */ - uint64_t timecmp_hi =3D env->timecmp >> 32; - riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hart= id, - timecmp_hi << 32 | (value & 0xFFFFFFFF), - mtimer->timebase_freq); - return; + if (size =3D=3D 4) { + /* timecmp_lo for RV32/RV64 */ + uint64_t timecmp_hi =3D env->timecmp >> 32; + riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), = hartid, + timecmp_hi << 32 | (value & 0xFFFFFFFF), + mtimer->timebase_freq); + } else { + /* timecmp for RV64 */ + riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), = hartid, + value, mtimer->timebase_= freq); + } } else if ((addr & 0x7) =3D=3D 4) { - /* timecmp_hi */ - uint64_t timecmp_lo =3D env->timecmp; - riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), hart= id, - value << 32 | (timecmp_lo & 0xFFFFFFFF), - mtimer->timebase_freq); + if (size =3D=3D 4) { + /* timecmp_hi for RV32/RV64 */ + uint64_t timecmp_lo =3D env->timecmp; + riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), = hartid, + value << 32 | (timecmp_lo & 0xFFFFFFFF), + mtimer->timebase_freq); + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "aclint-mtimer: invalid timecmp_hi write: %0= 8x", + (uint32_t)addr); + } } else { qemu_log_mask(LOG_UNIMP, "aclint-mtimer: invalid timecmp write: %08x", --=20 2.35.1 From nobody Tue May 21 09:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650524358627620.1843393664693; Wed, 20 Apr 2022 23:59:18 -0700 (PDT) Received: from localhost ([::1]:34584 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhQmb-0008Ka-7a for importer@patchew.org; Thu, 21 Apr 2022 02:59:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54164) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQSP-0005ub-4q for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:38:25 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:13363) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQSM-0007yk-WB for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:38:24 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 21 Apr 2022 14:37:58 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:09:00 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:37:58 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KkSXP6m8mz1SHwl for ; Wed, 20 Apr 2022 23:37:57 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id MgdnTKfvl6wV for ; Wed, 20 Apr 2022 23:37:57 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.119]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KkSXK4Nklz1Rvlx; Wed, 20 Apr 2022 23:37:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1650523102; x=1682059102; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=qkBK7YFwpsjTQfxQWj6YxggrEC7ZyzhuamtR0uCtFUM=; b=BE8Tv/Dsr7Z2887n2exuXUce6qh5iq9D222Mvo1TyEWDTgS0NYcC1eW2 3Dvrr/qdoGjJM+umAvD1yFPKUx6LaMmz2xS8VWC36pz9QNGz50VdnIXiy M7VmDnUSXD8vb7+gtQVo1i61mavuSokwsTa8Rt6nfzzxIVsVRtGtRLI9P ZEZdVvJx3mwyFkt8TPjw8taa1gosfXO8H+mlfpy4rYQYVOWCWyoYCnAyz WCvK/ZgQojAJyMc5X6D5+PFkwdGAYkwTvGYFKItzvvMN1sg6XOvfWeCFc 7xilWW2YLug6Zh0ztFKVKKtqulwKQw+r2F9YzNrrAExkBn3QKVD3ucBE+ Q==; X-IronPort-AV: E=Sophos;i="5.90,278,1643644800"; d="scan'208";a="302640017" IronPort-SDR: E8X5fqMU0b8AWc28DGkgDvtOR1wtmyTzYMUqlSqSGZdCm+9MD2/I+09gjtzBTcZrodxy9hYkLx TApMbHL6lLlC3JNzbQYkf8GdX/H9mSb/wZOHx9kBSibhqCs73SFAZuWu/Uu/+PSFYw/ACDZZo0 P0ic+6mYM6VFKzLnsj9XmiVX6XbrCrnDQ13T8ykBoGxidRm2YoEeZ3GO61i/lg3jJ3u9RKSowx QtfLDAEHQYblgIYp31yWc+AEKUisEDIwXMSrxf07b3sOTbf6p1ZsRylWBZnzmsKCXSOzg6VpNP 72aGNrHzk/hbCgf0WmupDqQr IronPort-SDR: JxqFNxM8hF7xFddxBTtl35tCf3Og1v6n296H/B6tD4qwx0LUxRkN4Oq+/qwc5OaXAWHT2sg28n g6kwNxYSsF/bVfSPNz4+9NquoNU4xtA7HGxzf3RGDvLENJ9VVKPKsaedc7lRAZpjUbha7HvYw6 yJFYXtaoM+nmRulBvuklaomwZ9UAvfryJXW/vBAN/ck9oWt8mfnAvndPI/nx6UpPsuy2v78GCu 5xYtJPmL1/5JECm2vhJ/q4quv2W4rHBGSf3cQ+Za6+39+G9uiKRA2/QOYeTWbqtTTTX07KN7KP qMI= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1650523077; x=1653115078; bh=qkBK7YFwpsjTQfxQWj 6YxggrEC7ZyzhuamtR0uCtFUM=; b=AUAJabzcKAVxJqiI3YZtsrqqpTkv42VOLy GYOQgODYIUvdho068MtWP2Q+1A0J+mOGLBVDV0ROeGyXUrtolBMguXLy8eTMO8Eb TjYUZftB3uzTXFlJhj7tNM5cDDHjuk0FLQ6P8LApldugQkasHcKfEAxlzDMGoSC9 73OLd1CU4UEz4FUp1R72gWauBTr+ArMCbmNREk1vNYRK73v4iXXZjUZO5qJJkcPh BZNTixOWpUKdXA8i4xJg0RDtRWbH40s3NyrJjP1jqqQ3EVBpYWdQT2VfOu7N8+Ie lNZrph9xgUGPb7idhrK5pYucIqBSYn7oyxZhNW7fgLQpVHJr5w0w== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Frank Chang , Jim Shu , Alistair Francis Subject: [PULL 23/31] hw/intc: Make RISC-V ACLINT mtime MMIO register writable Date: Thu, 21 Apr 2022 16:36:22 +1000 Message-Id: <20220421063630.1033608-24-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650524360776100001 Content-Type: text/plain; charset="utf-8" From: Frank Chang RISC-V privilege spec defines that mtime is exposed as a memory-mapped machine-mode read-write register. However, as QEMU uses host monotonic timer as timer source, this makes mtime to be read-only in RISC-V ACLINT. This patch makes mtime to be writable by recording the time delta value between the mtime value to be written and the timer value at the time mtime is written. Time delta value is then added back whenever the timer value is retrieved. Signed-off-by: Frank Chang Reviewed-by: Jim Shu Reviewed-by: Alistair Francis Message-Id: <20220420080901.14655-4-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- include/hw/intc/riscv_aclint.h | 1 + target/riscv/cpu.h | 8 ++-- hw/intc/riscv_aclint.c | 71 ++++++++++++++++++++++++---------- target/riscv/cpu_helper.c | 4 +- 4 files changed, 57 insertions(+), 27 deletions(-) diff --git a/include/hw/intc/riscv_aclint.h b/include/hw/intc/riscv_aclint.h index 229bd08d25..26d4048687 100644 --- a/include/hw/intc/riscv_aclint.h +++ b/include/hw/intc/riscv_aclint.h @@ -31,6 +31,7 @@ typedef struct RISCVAclintMTimerState { /*< private >*/ SysBusDevice parent_obj; + uint64_t time_delta; =20 /*< public >*/ MemoryRegion mmio; diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 3f7553c0b5..39a9ff17d3 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -285,8 +285,8 @@ struct CPUArchState { type2_trigger_t type2_trig[TRIGGER_TYPE2_NUM]; =20 /* machine specific rdtime callback */ - uint64_t (*rdtime_fn)(uint32_t); - uint32_t rdtime_fn_arg; + uint64_t (*rdtime_fn)(void *); + void *rdtime_fn_arg; =20 /* machine specific AIA ireg read-modify-write callback */ #define AIA_MAKE_IREG(__isel, __priv, __virt, __vgein, __xlen) \ @@ -496,8 +496,8 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env); int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint64_t interrupts); uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t mask, uint64_t value= ); #define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value = */ -void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), - uint32_t arg); +void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), + void *arg); void riscv_cpu_set_aia_ireg_rmw_fn(CPURISCVState *env, uint32_t priv, int (*rmw_fn)(void *arg, target_ulong reg, diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index ff082090fe..3b3ab548f6 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -38,12 +38,18 @@ typedef struct riscv_aclint_mtimer_callback { int num; } riscv_aclint_mtimer_callback; =20 -static uint64_t cpu_riscv_read_rtc(uint32_t timebase_freq) +static uint64_t cpu_riscv_read_rtc_raw(uint32_t timebase_freq) { return muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), timebase_freq, NANOSECONDS_PER_SECOND); } =20 +static uint64_t cpu_riscv_read_rtc(void *opaque) +{ + RISCVAclintMTimerState *mtimer =3D opaque; + return cpu_riscv_read_rtc_raw(mtimer->timebase_freq) + mtimer->time_de= lta; +} + /* * Called when timecmp is written to update the QEMU timer or immediately * trigger timer interrupt if mtimecmp <=3D current timer value. @@ -51,13 +57,13 @@ static uint64_t cpu_riscv_read_rtc(uint32_t timebase_fr= eq) static void riscv_aclint_mtimer_write_timecmp(RISCVAclintMTimerState *mtim= er, RISCVCPU *cpu, int hartid, - uint64_t value, - uint32_t timebase_freq) + uint64_t value) { + uint32_t timebase_freq =3D mtimer->timebase_freq; uint64_t next; uint64_t diff; =20 - uint64_t rtc_r =3D cpu_riscv_read_rtc(timebase_freq); + uint64_t rtc_r =3D cpu_riscv_read_rtc(mtimer); =20 cpu->env.timecmp =3D value; if (cpu->env.timecmp <=3D rtc_r) { @@ -140,11 +146,11 @@ static uint64_t riscv_aclint_mtimer_read(void *opaque= , hwaddr addr, } } else if (addr =3D=3D mtimer->time_base) { /* time_lo for RV32/RV64 or timecmp for RV64 */ - uint64_t rtc =3D cpu_riscv_read_rtc(mtimer->timebase_freq); + uint64_t rtc =3D cpu_riscv_read_rtc(mtimer); return (size =3D=3D 4) ? (rtc & 0xFFFFFFFF) : rtc; } else if (addr =3D=3D mtimer->time_base + 4) { /* time_hi */ - return (cpu_riscv_read_rtc(mtimer->timebase_freq) >> 32) & 0xFFFFF= FFF; + return (cpu_riscv_read_rtc(mtimer) >> 32) & 0xFFFFFFFF; } =20 qemu_log_mask(LOG_UNIMP, @@ -157,6 +163,7 @@ static void riscv_aclint_mtimer_write(void *opaque, hwa= ddr addr, uint64_t value, unsigned size) { RISCVAclintMTimerState *mtimer =3D opaque; + int i; =20 if (addr >=3D mtimer->timecmp_base && addr < (mtimer->timecmp_base + (mtimer->num_harts << 3))) { @@ -172,20 +179,18 @@ static void riscv_aclint_mtimer_write(void *opaque, h= waddr addr, /* timecmp_lo for RV32/RV64 */ uint64_t timecmp_hi =3D env->timecmp >> 32; riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), = hartid, - timecmp_hi << 32 | (value & 0xFFFFFFFF), - mtimer->timebase_freq); + timecmp_hi << 32 | (value & 0xFFFFFFFF)); } else { /* timecmp for RV64 */ riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), = hartid, - value, mtimer->timebase_= freq); + value); } } else if ((addr & 0x7) =3D=3D 4) { if (size =3D=3D 4) { /* timecmp_hi for RV32/RV64 */ uint64_t timecmp_lo =3D env->timecmp; riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), = hartid, - value << 32 | (timecmp_lo & 0xFFFFFFFF), - mtimer->timebase_freq); + value << 32 | (timecmp_lo & 0xFFFFFFFF)); } else { qemu_log_mask(LOG_GUEST_ERROR, "aclint-mtimer: invalid timecmp_hi write: %0= 8x", @@ -197,15 +202,39 @@ static void riscv_aclint_mtimer_write(void *opaque, h= waddr addr, (uint32_t)addr); } return; - } else if (addr =3D=3D mtimer->time_base) { - /* time_lo */ - qemu_log_mask(LOG_UNIMP, - "aclint-mtimer: time_lo write not implemented"); - return; - } else if (addr =3D=3D mtimer->time_base + 4) { - /* time_hi */ - qemu_log_mask(LOG_UNIMP, - "aclint-mtimer: time_hi write not implemented"); + } else if (addr =3D=3D mtimer->time_base || addr =3D=3D mtimer->time_b= ase + 4) { + uint64_t rtc_r =3D cpu_riscv_read_rtc_raw(mtimer->timebase_freq); + + if (addr =3D=3D mtimer->time_base) { + if (size =3D=3D 4) { + /* time_lo for RV32/RV64 */ + mtimer->time_delta =3D ((rtc_r & ~0xFFFFFFFFULL) | value) = - rtc_r; + } else { + /* time for RV64 */ + mtimer->time_delta =3D value - rtc_r; + } + } else { + if (size =3D=3D 4) { + /* time_hi for RV32/RV64 */ + mtimer->time_delta =3D (value << 32 | (rtc_r & 0xFFFFFFFF)= ) - rtc_r; + } else { + qemu_log_mask(LOG_GUEST_ERROR, + "aclint-mtimer: invalid time_hi write: %08x", + (uint32_t)addr); + return; + } + } + + /* Check if timer interrupt is triggered for each hart. */ + for (i =3D 0; i < mtimer->num_harts; i++) { + CPUState *cpu =3D qemu_get_cpu(mtimer->hartid_base + i); + CPURISCVState *env =3D cpu ? cpu->env_ptr : NULL; + if (!env) { + continue; + } + riscv_aclint_mtimer_write_timecmp(mtimer, RISCV_CPU(cpu), + i, env->timecmp); + } return; } =20 @@ -315,7 +344,7 @@ DeviceState *riscv_aclint_mtimer_create(hwaddr addr, hw= addr size, continue; } if (provide_rdtime) { - riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, timebase_freq= ); + riscv_cpu_set_rdtime_fn(env, cpu_riscv_read_rtc, dev); } =20 cb->s =3D RISCV_ACLINT_MTIMER(dev); diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 126251d5da..e1aa4f2097 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -632,8 +632,8 @@ uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t m= ask, uint64_t value) return old; } =20 -void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(uint32_t), - uint32_t arg) +void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void *), + void *arg) { env->rdtime_fn =3D fn; env->rdtime_fn_arg =3D arg; --=20 2.35.1 From nobody Tue May 21 09:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650527307329301.2795591722436; Thu, 21 Apr 2022 00:48:27 -0700 (PDT) Received: from localhost ([::1]:45688 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhRY8-00028Q-SE for importer@patchew.org; Thu, 21 Apr 2022 03:48:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54166) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQSP-0005us-8b for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:38:25 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:13374) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQSN-0007zd-E2 for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:38:24 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 21 Apr 2022 14:38:01 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:09:03 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:38:02 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KkSXT0r9Yz1SVp1 for ; Wed, 20 Apr 2022 23:38:01 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id Xx6OqRBAC6EI for ; Wed, 20 Apr 2022 23:38:00 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.119]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KkSXQ0V0Xz1SVp2; Wed, 20 Apr 2022 23:37:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1650523103; x=1682059103; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=HZtMfNayAzWb857EUph0gC4EyuX8kVZF+e012B4DRfM=; b=lXRu2IYsKkxbHxFLYj0a5tok062Kil0SOfM+QWC19JdCIEjhHyfifEj0 gHEoqpkSoG96t0GU/UJISd/e7VUUJzormr4qqDAbo9ZrE/Grl03LF5dvZ MWYyUEl92J1flJMVNuFu5DOfTez3SyH/8yTE+ETF5mA3my/QKGvS8Ywit /V35zkQjyKH84gXJhQVNx1E+ikQbUT5BKbrnPwocJPSRurZkDjBot7UEv PFmJ1O3PuOzgbmLluC/mCBb7r3Y9lV6zEKpVRTLmkpuT8lBabSnx8TP6f NKoUJaclakaj+TBgEBclbq5OEjZDphEHWy0fqSpj7DFmGGwafEJuBlZIy A==; X-IronPort-AV: E=Sophos;i="5.90,278,1643644800"; d="scan'208";a="302640018" IronPort-SDR: dhrdXWSZ9hDr2pOPpjZk/E+eapxppyylWBNvlq/AmSn71Wucxxd+/TbJLTmwziSFByMhqQsIzM jFVWxTz8nJKQkY7FwtiL/fOHsmfYNc68Qs95lg8biUGIlXkJbY46H6gwxJQjp+YLkSxOdaJSPJ 95qcrfvWZn0OWfFjkQUMbHptDK44DrFi6zBXPFK4O787R72NzP0Xi3AUmGIGS18yD6VtqDM7hO Ha4W5dvR/BEzr6eE9/hh+PekfPU0vWdficVrqU2TGPY4FB/JYtfcV2ql6pBiFLLbWnOXGomE8/ csGP7YQWLbTJq4aJPqVJAnAW IronPort-SDR: VcUarwsjLB+ekUaZcJS+ik6zK1+MjvXxIZQG/2uRKI6K+DJ7qyBcXM5regBIZT6Z9BOpmbmvEm Gdx9yyJUVFZGZNKbaY3Tp8mcDkZmb+WDY4JOW9978JtH1DC/iumttGmCBl6Izvr5ZF3COnSHWU FC3r9HOaPUAxCqs39BWYbdMSdX2JOYT4rLw6glesG+VDQAj+mBqiUdLFxxrtQ06onhMc2qzqMt GzDe+SYG3+Bpp02yPvZrliMo7voEt8pYEq87SUrts0MHmaoa3OOCvjDrliKSVUWDHpfgc3zUz5 S5g= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1650523080; x=1653115081; bh=HZtMfNayAzWb857EUp h0gC4EyuX8kVZF+e012B4DRfM=; b=UXnpzXh0VUZDbpaMfJSBoyY65DXRgpwyX6 oJDjuJZvAneecyNx0NTLLW7aIljVgHbkGa08d5vWhxopKB4IOrtN9rXMZSRiIM60 wdf5dY/PgCwrz0INqL/u4iJQIB+1h2I5Q51aVKRcXF8EBL99mQXnLucOVVPrbkta YsecC8Mpkb6lew53prNVdq19ItKFdGSTdj/t6RkQ+OUBfHFG6A5nXAW2nebIHrev 26grfp/irIXK0/4fE9GLps7eA7y6no8wGIlueiNK7ZtriiV5qBo2G9QfzwymofRj INctgqaZSnup22v6RCq2uL8UMqXWHV0uhfIskblushdsknstyz9A== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Jim Shu , Frank Chang , Alistair Francis Subject: [PULL 24/31] hw/intc: riscv_aclint: Add reset function of ACLINT devices Date: Thu, 21 Apr 2022 16:36:23 +1000 Message-Id: <20220421063630.1033608-25-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650527308576100001 Content-Type: text/plain; charset="utf-8" From: Jim Shu This commit implements reset function of all ACLINT devices. ACLINT device reset will clear MTIME and MSIP register to 0. Depend on RISC-V ACLINT spec v1.0-rc4: https://github.com/riscv/riscv-aclint/blob/v1.0-rc4/riscv-aclint.adoc Signed-off-by: Jim Shu Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20220420080901.14655-5-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- hw/intc/riscv_aclint.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index 3b3ab548f6..0412edc982 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -293,11 +293,29 @@ static void riscv_aclint_mtimer_realize(DeviceState *= dev, Error **errp) } } =20 +static void riscv_aclint_mtimer_reset_enter(Object *obj, ResetType type) +{ + /* + * According to RISC-V ACLINT spec: + * - On MTIMER device reset, the MTIME register is cleared to zero. + * - On MTIMER device reset, the MTIMECMP registers are in unknown s= tate. + */ + RISCVAclintMTimerState *mtimer =3D RISCV_ACLINT_MTIMER(obj); + + /* + * Clear mtime register by writing to 0 it. + * Pending mtime interrupts will also be cleared at the same time. + */ + riscv_aclint_mtimer_write(mtimer, mtimer->time_base, 0, 8); +} + static void riscv_aclint_mtimer_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); dc->realize =3D riscv_aclint_mtimer_realize; device_class_set_props(dc, riscv_aclint_mtimer_properties); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + rc->phases.enter =3D riscv_aclint_mtimer_reset_enter; } =20 static const TypeInfo riscv_aclint_mtimer_info =3D { @@ -452,11 +470,32 @@ static void riscv_aclint_swi_realize(DeviceState *dev= , Error **errp) } } =20 +static void riscv_aclint_swi_reset_enter(Object *obj, ResetType type) +{ + /* + * According to RISC-V ACLINT spec: + * - On MSWI device reset, each MSIP register is cleared to zero. + * + * p.s. SSWI device reset does nothing since SETSIP register always re= ads 0. + */ + RISCVAclintSwiState *swi =3D RISCV_ACLINT_SWI(obj); + int i; + + if (!swi->sswi) { + for (i =3D 0; i < swi->num_harts; i++) { + /* Clear MSIP registers by lowering software interrupts. */ + qemu_irq_lower(swi->soft_irqs[i]); + } + } +} + static void riscv_aclint_swi_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); dc->realize =3D riscv_aclint_swi_realize; device_class_set_props(dc, riscv_aclint_swi_properties); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + rc->phases.enter =3D riscv_aclint_swi_reset_enter; } =20 static const TypeInfo riscv_aclint_swi_info =3D { --=20 2.35.1 From nobody Tue May 21 09:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650524944631259.27247894450943; Thu, 21 Apr 2022 00:09:04 -0700 (PDT) Received: from localhost ([::1]:44632 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhQw3-00089B-KC for importer@patchew.org; Thu, 21 Apr 2022 03:09:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54208) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQSa-000613-FY for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:38:36 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:13339) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQSX-0007xw-2X for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:38:35 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 21 Apr 2022 14:38:05 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:09:07 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:38:06 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KkSXY1XmSz1SHwl for ; Wed, 20 Apr 2022 23:38:05 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id S_Lp05eJk6JX for ; Wed, 20 Apr 2022 23:38:04 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.119]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KkSXT0Jf0z1SVnx; Wed, 20 Apr 2022 23:38:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1650523112; x=1682059112; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=E7V7bntsiUrBNhbKHQ1ViOvDxpSZHJy1zY6ve2mcyhY=; b=jDYdDv83wJEv6orSfDYWWvV3RbHLoVnN2dVuSy5LhjNyAg1p8H4Y/tC0 L3tKNMuV5YImUyuUr79lKI30H/cBLyWZkwgSnXKHBl9tz/tUsULsjoR0A YKQrE/3QyTnjs40RiUPk9zSqpsuKWqFILTDWLWtPdVLKUSnXTmjppceqT G4qRKIKnsgkgfsEq2BgwteHI5LYqnGoMtJnH+qetL+a4/C7T1TsJkeIxw kPcFMO0ovgo6mBbPsoGeQZ4NPA0Bo5cGzPh3/tIlnRbS7hvFNb+vdr8Qm ICYlDWNYKzvBcJzqi4O9j8GrudAaAfCBA/E1Bz1V/Ll4Ngp3NWf4qttLy Q==; X-IronPort-AV: E=Sophos;i="5.90,278,1643644800"; d="scan'208";a="302640021" IronPort-SDR: fgo49fkD4JvcN4IzBVMISHK+Rev+KEAhVLgBhFu5UP7OKA7GXlMauB+3ObDFrqqXKnWivfx8nm vPB7cyyYyseKZyZw0xGW8hLqTINPHXhy3+B0cZtrasaL+7QCP+AZfj5Mibs5uwpTmr/VJ+zIte uxADUwBS4SdCrNWZpXLwMXPv+lAr62AYo7UmJfqHmkIvjPA5ZI8xQ1aX/EK/SlTA1jihC0RcU8 3EVK0NVaPvnyXh2eNVquOp7EZB/YZJeRxoXQxQERafkWIasR2Z34KTPoneHsnATB6bSma+vBt5 h/Wch0q7/pmO3GSakYDRw8F7 IronPort-SDR: AxhQLsvDiMqh/rs12iAF/PREjIuQL+2tVK+6PQs7wyXuradyaaSSuJBt8dCWbICkMgIsP4Swom WUb7McfoByN3fm0nSKJZO//5J4J/yrjmOkBZVU3qX5sqMeAKl+n2+5nen0qcQV9vh6UmpvPEtT XuVrZyT1yezt+UK21SOrTYH3+KOmhLJfZI7YhU2ttLRIgcreIVZAqaBk4T3+EjHHsYcARli9UH ycjjt49IDKJ+Dn4iwpYvYwyX6LZA0DhKY/eLo2Z0f8rJvpes4lhy1d75bGlB3rvROMcFhPElRk YH8= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1650523084; x=1653115085; bh=E7V7bntsiUrBNhbKHQ 1ViOvDxpSZHJy1zY6ve2mcyhY=; b=h3E9Tf98zi6PsfZ3eWs3Kb6qSTDYbTAag9 dmlkAim+RRi0YsOQA8HQ0ej8fbOpA0Ct6nwZ8ky/Y4k3OQMnEXwv6jTc9Y/zp7QJ BLWqNEB4DLRCyf/SuLJS6secfpW9HfxTn+fx56fRKf2RJw1IP2JbElpWCEMHyELu GkSBIUiohyguGAZd+CzgFKsG0QOfPYEUccLWR1axyMMAVz/0y0puDSArYp124fjP IJBpXSv8OLWUXFdysj4xCbAEvqM6yxV+lAlb3ebG0LyX+bA7bEFhAAB0PfdGsUxh mfjvzhLnVHIusOz9m9pf5tw852/RAbV+bg1MMzbEpgsG/IuAm1eQ== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Bin Meng , Alistair Francis Subject: [PULL 25/31] target/riscv: debug: Implement debug related TCGCPUOps Date: Thu, 21 Apr 2022 16:36:24 +1000 Message-Id: <20220421063630.1033608-26-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650524946438100001 Content-Type: text/plain; charset="utf-8" From: Bin Meng Implement .debug_excp_handler, .debug_check_{breakpoint, watchpoint} TCGCPUOps and hook them into riscv_tcg_ops. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-Id: <20220421003324.1134983-2-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/debug.h | 4 +++ target/riscv/cpu.c | 3 ++ target/riscv/debug.c | 75 ++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 82 insertions(+) diff --git a/target/riscv/debug.h b/target/riscv/debug.h index fbc5f946e2..fb21706e1c 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -105,4 +105,8 @@ void tselect_csr_write(CPURISCVState *env, target_ulong= val); target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index); void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val= ); =20 +void riscv_cpu_debug_excp_handler(CPUState *cs); +bool riscv_cpu_debug_check_breakpoint(CPUState *cs); +bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); + #endif /* RISCV_DEBUG_H */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 94f9434411..8919928f4f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -880,6 +880,9 @@ static const struct TCGCPUOps riscv_tcg_ops =3D { .do_interrupt =3D riscv_cpu_do_interrupt, .do_transaction_failed =3D riscv_cpu_do_transaction_failed, .do_unaligned_access =3D riscv_cpu_do_unaligned_access, + .debug_excp_handler =3D riscv_cpu_debug_excp_handler, + .debug_check_breakpoint =3D riscv_cpu_debug_check_breakpoint, + .debug_check_watchpoint =3D riscv_cpu_debug_check_watchpoint, #endif /* !CONFIG_USER_ONLY */ }; =20 diff --git a/target/riscv/debug.c b/target/riscv/debug.c index c8cec39217..1a9392645e 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -337,3 +337,78 @@ void tdata_csr_write(CPURISCVState *env, int tdata_ind= ex, target_ulong val) =20 return write_func(env, env->trigger_cur, tdata_index, val); } + +void riscv_cpu_debug_excp_handler(CPUState *cs) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + + if (cs->watchpoint_hit) { + if (cs->watchpoint_hit->flags & BP_CPU) { + cs->watchpoint_hit =3D NULL; + riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0); + } + } else { + if (cpu_breakpoint_test(cs, env->pc, BP_CPU)) { + riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0); + } + } +} + +bool riscv_cpu_debug_check_breakpoint(CPUState *cs) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + CPUBreakpoint *bp; + target_ulong ctrl; + target_ulong pc; + int i; + + QTAILQ_FOREACH(bp, &cs->breakpoints, entry) { + for (i =3D 0; i < TRIGGER_TYPE2_NUM; i++) { + ctrl =3D env->type2_trig[i].mcontrol; + pc =3D env->type2_trig[i].maddress; + + if ((ctrl & TYPE2_EXEC) && (bp->pc =3D=3D pc)) { + /* check U/S/M bit against current privilege level */ + if ((ctrl >> 3) & BIT(env->priv)) { + return true; + } + } + } + } + + return false; +} + +bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + target_ulong ctrl; + target_ulong addr; + int flags; + int i; + + for (i =3D 0; i < TRIGGER_TYPE2_NUM; i++) { + ctrl =3D env->type2_trig[i].mcontrol; + addr =3D env->type2_trig[i].maddress; + flags =3D 0; + + if (ctrl & TYPE2_LOAD) { + flags |=3D BP_MEM_READ; + } + if (ctrl & TYPE2_STORE) { + flags |=3D BP_MEM_WRITE; + } + + if ((wp->flags & flags) && (wp->vaddr =3D=3D addr)) { + /* check U/S/M bit against current privilege level */ + if ((ctrl >> 3) & BIT(env->priv)) { + return true; + } + } + } + + return false; +} --=20 2.35.1 From nobody Tue May 21 09:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650527615946239.11293315334262; Thu, 21 Apr 2022 00:53:35 -0700 (PDT) Received: from localhost ([::1]:54550 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhRd8-0000HR-PL for importer@patchew.org; Thu, 21 Apr 2022 03:53:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54218) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQSb-00061k-50 for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:38:38 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:13363) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQSZ-0007yk-Cv for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:38:36 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 21 Apr 2022 14:38:07 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:09:10 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:38:08 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KkSXb4hNpz1SHwl for ; Wed, 20 Apr 2022 23:38:07 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id cUKAHDGtzNvT for ; Wed, 20 Apr 2022 23:38:07 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.119]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KkSXY2npLz1Rvlx; Wed, 20 Apr 2022 23:38:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1650523115; x=1682059115; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=9xVKI1KYX5p2vLhh0U6iF2jzD/ULzCfKpwwLJE4Z56Q=; b=XJ32uMciAidiMayKHDwrY6jyzJ3zXnOER+B5sK8D9/CoBBuTWAi262SZ U8FAYezhkS+R+/oWn53rVtwsYyk/YS7wWz8QaFEIf86oCTSZbk+thEFs9 9Rt83LYYKl49YxQ9mXRLlO1ApvhxWDoRJes3TZS5mMk7YuBSdtaQ9lR3j JcQp5xVowGtuzTmOamiHTzBVUC8VItt/2aVI4UVTy+DGwGsEa9r+IBqVw d+Lue4YVzqbHY9remecI2ISjv5QZcW+lYWsRnStWiNraHAbha4jRbxjoa aYMVwSVaD4/5SrMH6PbX4eFgEbsbmBPmURrgE6Vj87q4sWbZpH2OuFmhA Q==; X-IronPort-AV: E=Sophos;i="5.90,278,1643644800"; d="scan'208";a="302640022" IronPort-SDR: 6Rq28DDd0ciJJgsbW7TBbhurPwqD1cNT5VIwWDYKJM3wEOYA0zcNvuywgLdJAqU38s/abyOtuE OGefKBFekx3CYohdzXvEhf3xRvcMXDZraZluOgU0Lz8AhQSl8MQxolWrN1l5ABTPa6E2ZXrVL5 ZFeYMBZa6D3PSt9ViJ9kNFgcXZjoi8FkgYYPpAJ7kkwTjxuHKiRZPr8OG70zGz7KRJk9NoZFNl jhwaMpoOfS9vDQyfrZ/rbfnM9kKarJrmy/Pa3j84epQWe0TbBHJ7n0nFC3VRqqnjRT5260MkZB GSs3FKM0rqbfb7lwGy7PHQSO IronPort-SDR: cSLGSBRCF7rJIgCxX33iiVhqsYvZYXfqcAn+UAFdrXpvpznyDZoVGEM7hKVtDtql+E7oRxQ5Fq Lh7Hz6TC3xEfmj3rQJ5Ylotkr3VA34VmlYLinIU/sg5LjTaQhutaS/mFokSp4EeWCdOxAzNffr 4K15/y2d6UlR7WUivQVzixrdi8cRxCVQ4jh7lHAlk35fGXskqKIh2hkCba4lcfrpAQEWiTnJnc 1pgwqKGki5lXzkv1DNBV1sslQM2IhwDpjFVx84fyi9Jp8fqyultyu139lNpwocwpjA4rrUkYf6 wWg= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1650523087; x=1653115088; bh=9xVKI1KYX5p2vLhh0U 6iF2jzD/ULzCfKpwwLJE4Z56Q=; b=kF+SpqRIPIj1lalLI5NoaOj/2PiOkD0KUY iWlxIV5yYAe+7V90kiObWyWwjFVf7wDHEHPsZt0Vt5hhuwmXfoM9B+OkUjGRq3SR uzo8nFsH7vsTzzOx12xS5brHlaZPF5ckd42k36zh7UKjqINGsKtntLGuI0QlrrlU T16zlUtLOWM6InSFwQAAn7gJ4GuuSQBmWQ7cR9LF9TdrRatq4TFGilXyUasfxdIy F/QqW15gh+/fXVodT1qqcRxIXY6VP7jH9CBRjpOdPYuM3O9T+Rn6SdQpwBaz9sVZ M1TuWkRs2lQTFfXW9njfbxGqbKAt5J1XIO2eBUs831lDL11u/5wg== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Bin Meng , Alistair Francis Subject: [PULL 26/31] target/riscv: cpu: Add a config option for native debug Date: Thu, 21 Apr 2022 16:36:25 +1000 Message-Id: <20220421063630.1033608-27-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650527616913100001 Content-Type: text/plain; charset="utf-8" From: Bin Meng Add a config option to enable support for native M-mode debug. This is disabled by default and can be enabled with 'debug=3Dtrue'. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-Id: <20220421003324.1134983-3-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 4 +++- target/riscv/cpu.c | 5 +++++ 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 39a9ff17d3..62e53e3653 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -79,7 +79,8 @@ enum { RISCV_FEATURE_PMP, RISCV_FEATURE_EPMP, RISCV_FEATURE_MISA, - RISCV_FEATURE_AIA + RISCV_FEATURE_AIA, + RISCV_FEATURE_DEBUG }; =20 /* Privileged specification version */ @@ -405,6 +406,7 @@ struct RISCVCPUConfig { bool pmp; bool epmp; bool aia; + bool debug; uint64_t resetvec; }; =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8919928f4f..477961b619 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -548,6 +548,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) riscv_set_feature(env, RISCV_FEATURE_AIA); } =20 + if (cpu->cfg.debug) { + riscv_set_feature(env, RISCV_FEATURE_DEBUG); + } + set_resetvec(env, cpu->cfg.resetvec); =20 /* Validate that MISA_MXL is set properly. */ @@ -795,6 +799,7 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), + DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, false), =20 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), --=20 2.35.1 From nobody Tue May 21 09:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650525004592861.6432742701394; Thu, 21 Apr 2022 00:10:04 -0700 (PDT) Received: from localhost ([::1]:46238 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhQx1-0001OA-Hx for importer@patchew.org; Thu, 21 Apr 2022 03:10:03 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54220) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQSb-00061r-L2 for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:38:38 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:13374) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQSZ-0007zd-Je for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:38:37 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 21 Apr 2022 14:38:11 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:09:13 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:38:11 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KkSXf42xfz1SVp0 for ; Wed, 20 Apr 2022 23:38:10 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id P3JXcryivnXl for ; Wed, 20 Apr 2022 23:38:09 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.119]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KkSXb74Qyz1Rvlx; Wed, 20 Apr 2022 23:38:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1650523115; x=1682059115; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3utfC3nNOObrAN6/kxFQxt1dUDahhLFhBZOTeGX9jFY=; b=JIeUslJnX9N/DUg6idmYMUcW4s+aWwnWMOT/y/Q5vO2GB0aQC98UYDJv fnU5bAd9EDChEeKR6GxUEHxUeyvzvfdLdds/NKM+p0WhNWuCPyNrDzJZF /tBhd8jX1mEz2UT1r6G9g2SQby/f0Ig2cIVOxOJqDOjc7RHqAM13gx0S5 CPS1Wghf35HX4z0hdq7LS2s3lY4MXxOIMWz9ZkwtLrLoKTaGd6tZNOlxA Vibr1lF1t6sO/iFHz1wXH1r8FgJ8pIO5clLsvAay8JyaSeMmIZEnsytho oDLRJ/gwYkMwhRGOaHMnQHrWotjXNv/QDTIBvC0KioEL3F+SPNt278em5 g==; X-IronPort-AV: E=Sophos;i="5.90,278,1643644800"; d="scan'208";a="302640028" IronPort-SDR: ZKAdIiWjOaBlGcqagLauCau6jgt8v6wqnW4fA5DZduRQbXynR0vGgFSkseiWjp6ncxZ6Z5v9Ph /vV7hh0aLvpyiwrz/dx+ZXVcx3BJxzrD102gb5CrRG6iy/pN9v2gZ6oWbCwdDVXFi5FxhKdaiP Kpab7BuYGWvDMUntdg8880ghjBmp4rBmRSIL2DHisZR5A05F6dx3s5SaAwAQOtzQWFNCdXOi1L 59kFkmfk/wKwxgyDcGEmWUiTS2GED3Ib/TbMApu53eo+LNUt0rRsiHOXDP7skGL1IcY4vDB/2p CsmUjzmmWjlhQoAvVAbiWzAp IronPort-SDR: +pZmPQ0ZBb9m4dunyuab/BAAqLeLybPizZ8263QkRI9bzkZE06SZ1FxB1MisCwhBuGCyhclBgY J4KEi9WTCc9ONm7kk0ej5e594SQ/0QkV9zEwTi4CcZ+/da+KwuqtOPG/FLlvIJbQEtQzRDzM36 UPJI/p1sL2WQ8MKt23Ipma4bBvchBtyGALXWLFlO4eOu5QREqrGcq6qRmeUiVGaGTPjNuSJ1wP I2f600ShOgabqMOcHyjUXcH+TISNgQzTmaeJFF7K96r88iZq++yoisernOEWjaTC9i69gA1E9e kc4= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1650523089; x=1653115090; bh=3utfC3nNOObrAN6/kx FQxt1dUDahhLFhBZOTeGX9jFY=; b=sg9kadmHnKtiPAx1EwAU0TWB+BIb8jm0Ul eya5CX4fcSdrp/6x/PPNEtwe86S9FaIrFgc/Lh86nYzVIjXjAaqSlU6H7fCFiRzo puvi/QQVjy++DVygJ7Low8i6/ayUBz5XFqKUQWQBmhq2dNHK+xZB26YdS85Hm2fV VBimT+9Sdq6+ocbiUxYgOmZP9A3XQo0mlemITqqi7dGqML79RhrgF8Xv4xrV+Mit 6vc3yqqu/3tNCk4pTWNPjInsQsPE735usBTe533drrSQJJ1m/y9199pG+1ZRxPYb 21/ZDektG8a3sjIcmMnZ4zaAqOA72Pir56TFvLtBchMgBF95wXLQ== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Bin Meng , Alistair Francis Subject: [PULL 27/31] target/riscv: csr: Hook debug CSR read/write Date: Thu, 21 Apr 2022 16:36:26 +1000 Message-Id: <20220421063630.1033608-28-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650525006751100003 Content-Type: text/plain; charset="utf-8" From: Bin Meng This adds debug CSR read/write support to the RISC-V CSR RW table. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-Id: <20220421003324.1134983-4-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/debug.h | 2 ++ target/riscv/cpu.c | 4 ++++ target/riscv/csr.c | 57 ++++++++++++++++++++++++++++++++++++++++++++ target/riscv/debug.c | 27 +++++++++++++++++++++ 4 files changed, 90 insertions(+) diff --git a/target/riscv/debug.h b/target/riscv/debug.h index fb21706e1c..27b9cac6b4 100644 --- a/target/riscv/debug.h +++ b/target/riscv/debug.h @@ -109,4 +109,6 @@ void riscv_cpu_debug_excp_handler(CPUState *cs); bool riscv_cpu_debug_check_breakpoint(CPUState *cs); bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); =20 +void riscv_trigger_init(CPURISCVState *env); + #endif /* RISCV_DEBUG_H */ diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 477961b619..85656cdcc3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -466,6 +466,10 @@ static void riscv_cpu_reset(DeviceState *dev) set_default_nan_mode(1, &env->fp_status); =20 #ifndef CONFIG_USER_ONLY + if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { + riscv_trigger_init(env); + } + if (kvm_enabled()) { kvm_riscv_reset_vcpu(cpu); } diff --git a/target/riscv/csr.c b/target/riscv/csr.c index a09126a011..6ba85e7b5d 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -290,6 +290,15 @@ static RISCVException epmp(CPURISCVState *env, int csr= no) =20 return RISCV_EXCP_ILLEGAL_INST; } + +static RISCVException debug(CPURISCVState *env, int csrno) +{ + if (riscv_feature(env, RISCV_FEATURE_DEBUG)) { + return RISCV_EXCP_NONE; + } + + return RISCV_EXCP_ILLEGAL_INST; +} #endif =20 /* User Floating-Point CSRs */ @@ -2677,6 +2686,48 @@ static RISCVException write_pmpaddr(CPURISCVState *e= nv, int csrno, return RISCV_EXCP_NONE; } =20 +static RISCVException read_tselect(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D tselect_csr_read(env); + return RISCV_EXCP_NONE; +} + +static RISCVException write_tselect(CPURISCVState *env, int csrno, + target_ulong val) +{ + tselect_csr_write(env, val); + return RISCV_EXCP_NONE; +} + +static RISCVException read_tdata(CPURISCVState *env, int csrno, + target_ulong *val) +{ + /* return 0 in tdata1 to end the trigger enumeration */ + if (env->trigger_cur >=3D TRIGGER_NUM && csrno =3D=3D CSR_TDATA1) { + *val =3D 0; + return RISCV_EXCP_NONE; + } + + if (!tdata_available(env, csrno - CSR_TDATA1)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + *val =3D tdata_csr_read(env, csrno - CSR_TDATA1); + return RISCV_EXCP_NONE; +} + +static RISCVException write_tdata(CPURISCVState *env, int csrno, + target_ulong val) +{ + if (!tdata_available(env, csrno - CSR_TDATA1)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + tdata_csr_write(env, csrno - CSR_TDATA1, val); + return RISCV_EXCP_NONE; +} + /* * Functions to access Pointer Masking feature registers * We have to check if current priv lvl could modify @@ -3418,6 +3469,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_PMPADDR14] =3D { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr }, [CSR_PMPADDR15] =3D { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr }, =20 + /* Debug CSRs */ + [CSR_TSELECT] =3D { "tselect", debug, read_tselect, write_tselect }, + [CSR_TDATA1] =3D { "tdata1", debug, read_tdata, write_tdata }, + [CSR_TDATA2] =3D { "tdata2", debug, read_tdata, write_tdata }, + [CSR_TDATA3] =3D { "tdata3", debug, read_tdata, write_tdata }, + /* User Pointer Masking */ [CSR_UMTE] =3D { "umte", pointer_masking, read_umte, write= _umte }, [CSR_UPMMASK] =3D { "upmmask", pointer_masking, read_upmmask, write= _upmmask }, diff --git a/target/riscv/debug.c b/target/riscv/debug.c index 1a9392645e..2f2a51c732 100644 --- a/target/riscv/debug.c +++ b/target/riscv/debug.c @@ -412,3 +412,30 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CP= UWatchpoint *wp) =20 return false; } + +void riscv_trigger_init(CPURISCVState *env) +{ + target_ulong type2 =3D trigger_type(env, TRIGGER_TYPE_AD_MATCH); + int i; + + /* type 2 triggers */ + for (i =3D 0; i < TRIGGER_TYPE2_NUM; i++) { + /* + * type =3D TRIGGER_TYPE_AD_MATCH + * dmode =3D 0 (both debug and M-mode can write tdata) + * maskmax =3D 0 (unimplemented, always 0) + * sizehi =3D 0 (match against any size, RV64 only) + * hit =3D 0 (unimplemented, always 0) + * select =3D 0 (always 0, perform match on address) + * timing =3D 0 (always 0, trigger before instruction) + * sizelo =3D 0 (match against any size) + * action =3D 0 (always 0, raise a breakpoint exception) + * chain =3D 0 (unimplemented, always 0) + * match =3D 0 (always 0, when any compare value equals tdata2) + */ + env->type2_trig[i].mcontrol =3D type2; + env->type2_trig[i].maddress =3D 0; + env->type2_trig[i].bp =3D NULL; + env->type2_trig[i].wp =3D NULL; + } +} --=20 2.35.1 From nobody Tue May 21 09:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650525262001399.1676992338497; Thu, 21 Apr 2022 00:14:22 -0700 (PDT) Received: from localhost ([::1]:53036 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhR1A-0006nr-Qj for importer@patchew.org; Thu, 21 Apr 2022 03:14:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54278) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQSm-0006Cy-G9 for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:38:48 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:13339) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQSk-0007xw-PK for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:38:48 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 21 Apr 2022 14:38:13 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:09:15 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:38:14 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KkSXh73Mzz1Rwrw for ; Wed, 20 Apr 2022 23:38:12 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id XGxpoo9f84KS for ; Wed, 20 Apr 2022 23:38:12 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.119]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KkSXf3wb0z1SVnx; Wed, 20 Apr 2022 23:38:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1650523126; x=1682059126; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=CDXzKpjjddD5WzsgwtbuNALNh5AMoIiu9HJXurmxYAc=; b=Q2p1tkcl50SoO5DNzkIhoQtaDZb3RB8JScM/48AKRbk0leSMBTBfINQC HEmaYzu3vPAk1iOXyhLfpZ6TriMKtrvjZDcjYTnLJXgF6R/2phguPEzb/ xMZHRNKaeH2hA3i32hrHY+6KxkGbwaBQv3hYha0xqG3NSEL2F6w7fc8AJ mHn9mnPKbqg4OK3U1k3+BKvMAFh4yUyPlDKS/CMfM/sHW+IO9up2MQJLZ nTNoxUMOeavVqj5vtHlg4DPyOM6BGxP8iHhK/G2lO38xAOnk2WD+7Mehn 5Eb3izsKtdi3dIuVzZwdcP/f6zjS89phmXWvGVIrnJsub/ih6yQhFJjCk A==; X-IronPort-AV: E=Sophos;i="5.90,278,1643644800"; d="scan'208";a="302640029" IronPort-SDR: 28C4HtaqXlTsKoTT4SDn4M4jk/9l1K4lxjiP290K2XTuX7wLMqs6h2Bdy6Wqyabc/0Z6lRZROn Zh4AzFrSeHj21PXY1f6DCg46/D6j7jNeGxKZss+9S1cdE9PR0XLlCCfclvGhIhwQj6KmmbgKSD Hg4RiDnzCIOHBzkhd/rPGSIzEuJfbtPveW5x0wKcprtpEKFe8wZy1CIXsdo8bS//82faLXuAwo 2aksZycgvIUVRCf3Bkb6HRhIQ54iEFgViCUi2L6hEGE/OvpfNQppP/MHJzDhx+E+kEL34hEx2q LNvhp7FFsDmU37Q3VFf4tn9L IronPort-SDR: lBkQu1bYdw+wfwSSmsfh7k52rdcR2/MHiwwO+LVP/GrBF+nT5g5jEvOcf2Ts3k2bbtQKg4P5OQ kAjEtFINCcJcmy+75L2CUtutscUv6dCu1HajadE+ATVbGCHjLYZhIUb7fthO1LKwaUgj7yX2Su GxtC3I622rHj95K5r2ANE40Hv6Ys5ncdCl4o7VYfvV9BLGTpY0d8YPi12p31GjpcZ4g9/RZZt0 jKBHlZbquUa95tpUxFdNdU7Oab+AHyfNbnrFjmBWkgTgBqf+xSP6EzBBbuh1nSWCmKU6T1uH5E B3M= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1650523092; x=1653115093; bh=CDXzKpjjddD5Wzsgwt buNALNh5AMoIiu9HJXurmxYAc=; b=N0SKqrnNM6UXC+wKfBvIL4O2daqSqxNx7X lUtPrnLOX02pDsn2e+MMPDQABX0Ygn1T6gQtp4AtxXnANftabxyOe9FpYrhi8O7E TsnYtUCrN7K4V3fDBrIL+WaxvZ5q2JRHTA/9eOh3uDchxSgaH4aqspGhmTsbQWhZ xDJEKQtXi24EfxcToR7p2IS3nuSZ15dW9a7Gmq0EtGbxmRHphdmVbqBxOC33Txli pXQoA5I25d22hquv91Kw310uM0Z7N0z+K7P5xrmTxsiVwAgCTEmsZWwWIcyWJkAc 6BTkIrJJ6irLUiP+9pOlahJas+gHHmStYORFiRqGiIn1Oa4Ag0fg== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Bin Meng , Alistair Francis Subject: [PULL 28/31] target/riscv: machine: Add debug state description Date: Thu, 21 Apr 2022 16:36:27 +1000 Message-Id: <20220421063630.1033608-29-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650525265160100001 Content-Type: text/plain; charset="utf-8" From: Bin Meng Add a subsection to machine.c to migrate debug CSR state. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-Id: <20220421003324.1134983-5-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/machine.c | 32 ++++++++++++++++++++++++++++++++ 1 file changed, 32 insertions(+) diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 243f567949..2a437b29a1 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -216,7 +216,38 @@ static const VMStateDescription vmstate_kvmtimer =3D { VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU), VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU), VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool debug_needed(void *opaque) +{ + RISCVCPU *cpu =3D opaque; + CPURISCVState *env =3D &cpu->env; + + return riscv_feature(env, RISCV_FEATURE_DEBUG); +} =20 +static const VMStateDescription vmstate_debug_type2 =3D { + .name =3D "cpu/debug/type2", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_UINTTL(mcontrol, type2_trigger_t), + VMSTATE_UINTTL(maddress, type2_trigger_t), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_debug =3D { + .name =3D "cpu/debug", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D debug_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINTTL(env.trigger_cur, RISCVCPU), + VMSTATE_STRUCT_ARRAY(env.type2_trig, RISCVCPU, TRIGGER_TYPE2_NUM, + 0, vmstate_debug_type2, type2_trigger_t), VMSTATE_END_OF_LIST() } }; @@ -315,6 +346,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { &vmstate_rv128, &vmstate_kvmtimer, &vmstate_envcfg, + &vmstate_debug, NULL } }; --=20 2.35.1 From nobody Tue May 21 09:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650526803622903.2360775575806; Thu, 21 Apr 2022 00:40:03 -0700 (PDT) Received: from localhost ([::1]:33934 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhRQ2-0002VI-El for importer@patchew.org; Thu, 21 Apr 2022 03:40:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54286) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQSn-0006E8-2E for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:38:49 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:13363) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQSl-0007yk-DN for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:38:48 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 21 Apr 2022 14:38:15 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:09:18 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:38:16 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KkSXl4D66z1SVnx for ; Wed, 20 Apr 2022 23:38:15 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id SFocMzxWuBpA for ; Wed, 20 Apr 2022 23:38:15 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.119]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KkSXj1Y36z1Rvlx; Wed, 20 Apr 2022 23:38:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1650523127; x=1682059127; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=AC2dXbVlpogSRQbvLzTUXk+TjhjSi6pCJLR3L19S/+0=; b=WSCNk2OCv1aYC34+M8CZmUKFDru587jigk8LMXm7CqqkWLI3Kj987KEq aR3UVHq7P6ha6CPr+5q48a76EqsqHhCXe5EX8xnhw2nej0T5bCRZtyKt+ iapORXGF1/gb93ww2xvJyuny+zVlu8fSHXezwYDRP5dT92B3y/KYXGa0U 0V0Ug70q+2VKllNJ37LDmQNpmV2zq1MudQQ+ulB+ghEGgCySAJKuyoCv/ Px/zjlGgrfjpJbpzfpD2rPd/M7FtADkLN0zt/0XcdrBEQlCpbrbcCRmvS O42SzYQ8NOTBwHKF4usIBst2tNubl5Ag6H5Op3IlbF0obUkEB9bpqiQwR w==; X-IronPort-AV: E=Sophos;i="5.90,278,1643644800"; d="scan'208";a="302640036" IronPort-SDR: nr8rgC0kb/12YhOlAp+vpRxnZf7mwbDOd7A6TOJgOjhY7m+vlcQF5w/RD72up9cxCxuyAXmSwM 8HpF2LMT5lq24BmUnI1RtgXUNfOKo/oe8h+nEIpJXXc5dpFNv7ePxJhpiijxNywDgp5CWOjmaD edwkoIJAp0/a9IGQHLOrItAZcoXXL9cSuKn9dkujl9nwQg+KLm0mzazuhYwbG3N/1aa0hLljtE wwtOUMlvCjCB4POGSBt/i5Si1fG6VtA6bRJRYVy68/ImtdwDf9GHWWPl9Kfz9/x333vxI8hW98 B+IuhfcxQqpjug6p119BjWbQ IronPort-SDR: 4B2ro0wslMez5TNyhSwria44bCM3h2ikr1mE0l3e3WOSnLhDjsw+ZGn1AL/3GJO+RIbdjibB2j hsdrEpCE8s9bC4Yc4hNXSI5qwPiOIj4F8mE0McTYavjR4TlEi/bDkkYl48qNIYz+/nITSACgEP atuM11HHsE5Wp0bMYuAZuurVL0cs5D5oBLt1pgufhEnl1PL46FZ+C9rFGxlCirmddHhTDvmcsh /UrqWCbwEsEASkraHiv3nb28oOZcJqmuGDzdhDl5W4JLMjogi2HLFgQyoJ6CUURjdFdop0LdVq ow4= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1650523095; x=1653115096; bh=AC2dXbVlpogSRQbvLz TUXk+TjhjSi6pCJLR3L19S/+0=; b=OBcgkrZ3g0e1Ql2adoGwgTk6imgooLQ94G 2xKgd0jrBX3JAgfs0xLPYqgrrQVRNqAmu0ygUprF1hSHoGQChe2BkOX65DAc/zKA bicP3/UxenqmyfvUMfYm3Ac6hWSXXZwOr3NZx9q0hPUXD/bEQVhtdlFQejLSv5BR FID3SIQv+aAknCPA8ca+HiATJhsXMACpb70ry4QkPHfiFaGxGrrovF2mZPxNmbcJ 7E08bGGSx437EaUfOq5IBn/wUgaTXr7nLFyJzwbYdljjWbP1inuZaCVy1yOvZeFU Nd6fSuhSiPfuOZHcIZpmRNfS9w9771udwNhPrLnhkGtFFFaXq78w== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Bin Meng , Alistair Francis Subject: [PULL 29/31] target/riscv: cpu: Enable native debug feature Date: Thu, 21 Apr 2022 16:36:28 +1000 Message-Id: <20220421063630.1033608-30-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650526804070100001 Content-Type: text/plain; charset="utf-8" From: Bin Meng Turn on native debug feature by default for all CPUs. Signed-off-by: Bin Meng Reviewed-by: Alistair Francis Message-Id: <20220421003324.1134983-6-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 85656cdcc3..0c774056c5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -803,7 +803,7 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false), DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), - DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, false), + DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), =20 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), --=20 2.35.1 From nobody Tue May 21 09:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650527902047507.40210770249143; Thu, 21 Apr 2022 00:58:22 -0700 (PDT) Received: from localhost ([::1]:35246 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhRhk-0006VP-I3 for importer@patchew.org; Thu, 21 Apr 2022 03:58:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54290) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQSn-0006GL-P5 for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:38:49 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:13374) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQSl-0007zd-U9 for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:38:49 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 21 Apr 2022 14:38:18 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:09:21 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:38:19 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KkSXp4rw4z1SHwl for ; Wed, 20 Apr 2022 23:38:18 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id DFjMYOXCGbyl for ; Wed, 20 Apr 2022 23:38:18 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.119]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KkSXl6FXTz1Rvlx; Wed, 20 Apr 2022 23:38:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1650523127; x=1682059127; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=cCYAGxJFqppmK8zI89wVAdS5sE6lTAbaaFWAXrir5wU=; b=hgStYdUoM5G5DUFyisrhwT2+JoBmi6ems5UTjl6jWwJeNKwB74vo0WYH OpvddK7BY+TYidDM0jVL0kGOfPnJIfPRG4PU/NRs4l09p7Vg5XS5aAwsI 6NJuLiPsGiaRnVy/BLcpOti7TRLbXPSCkMWX0A+YoTAQ+cO2KKNF1zASd tkb2y6zcwoOTIeS7g7J3mAEfIZQzbXGNY4iRuew1Kw7IrLRbn5et3RejB uNQqOKb9y901olp8UGOiwP4nIcYT1asG9e7FjfO7QL4wHcYFQRC8tKSmR cNwgObsiRdjITNWg9+CZCPrMapcAVvRDqmiMc6rNQG2gJ7fG6bWAecqBr w==; X-IronPort-AV: E=Sophos;i="5.90,278,1643644800"; d="scan'208";a="302640039" IronPort-SDR: NozpPdcQc+QYy8yrUk2lzVWNRhSYjm0Kta8JF5yXoEiwd+bksQ68DeOhR+hholm7t5UXcmSxSC hncJneHL39gr5MYjRgNAWQWAJ9v4TJ0/i8HhmAGtXvNVnRzXrb4Y8eo3Bg/yhWKo/T7BeJYVeT OWFIhiYRZ0k+nYDSSVkVssA/RymhgIxjI4gHyBFkRH/hKPujEz9yrf54fZmwXu29KFQnf9Vg62 TvXyCnkd6zpQhuguKGtSyJiWFmikDN2YwZrTDQCR7HYjXKTfMkKlhEqDJMvK3i6ZWZRcKf60N4 Oww4iGZ216AEHhWxWruswYAz IronPort-SDR: MUzLh4NKc+QJ5J8DVUsaqXi2z54IuezxVd05a0DY6J98S+AbPBlZBrs5hP0QFXjesFey+CDX7i ixysO4nJ9Xj2Hi/AZzYWZ5sCsFpdhyTzZobWCL72FoJd4k9op1kvM+4W1HFaMMF9tTAGrXaWcL /i4mAdzUKeZIPmXP9WvhcbEVjEjdUO0iNkjwI4BE3XjvwyxKTXh3v3bY8zF9VjIdh5h4mt9Eic F1uVAokpniXjfOfcdP9kSLNszjljIirP4z2FBlvQiybbj7/Ahv6XgIpb9NZH6bVSB27FJFRO+X 7LU= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1650523098; x=1653115099; bh=cCYAGxJFqppmK8zI89 wVAdS5sE6lTAbaaFWAXrir5wU=; b=Ro5R5MOL1Q+NAYwRtXIfI68GwmiXzDF5uM v7M5rcjzxfxovfosMuTEY4CpBYBmNNtJ7jeSd6v6GjA1KF7yipEIy2N/T8h4YVU+ Y1Rzf/g/GtxLr8nyxoP+3e2sb8bXheSdGEEezyyb3e0MloXz35nivVoO6U2eFPGl WdPv9Jsb8bo2pQ4QMomQPKr8V78FgmY+jdE1UW2eTn5z1Wif3ffWFU0roaT+NQmL 3hbQVlc5wCwzVqX48ITyKct8CGnaZWJ+lWHOJbbQwQEE/ETrAmyUuc2cIkFACphu LvmzCHrTXvesy7pbvKgIBRN8I8i7inQJtIlU1t9mvzLPHKKOEK6w== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Bin Meng , Richard Henderson , Alistair Francis Subject: [PULL 30/31] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() Date: Thu, 21 Apr 2022 16:36:29 +1000 Message-Id: <20220421063630.1033608-31-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650527903815100001 Content-Type: text/plain; charset="utf-8" From: Bin Meng This is now used by RISC-V as well. Update the comments. Signed-off-by: Bin Meng Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20220421003324.1134983-7-bmeng.cn@gmail.com> Signed-off-by: Alistair Francis --- include/hw/core/tcg-cpu-ops.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index e13898553a..f98671ff32 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -90,6 +90,7 @@ struct TCGCPUOps { /** * @debug_check_watchpoint: return true if the architectural * watchpoint whose address has matched should really fire, used by ARM + * and RISC-V */ bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp); =20 --=20 2.35.1 From nobody Tue May 21 09:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650525597959204.2790945848127; Thu, 21 Apr 2022 00:19:57 -0700 (PDT) Received: from localhost ([::1]:33356 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhR6X-0004fV-G1 for importer@patchew.org; Thu, 21 Apr 2022 03:19:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:54318) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQT0-0006Ve-LS for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:39:06 -0400 Received: from esa2.hgst.iphmx.com ([68.232.143.124]:13339) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhQSw-0007xw-PI for qemu-devel@nongnu.org; Thu, 21 Apr 2022 02:39:00 -0400 Received: from uls-op-cesaip01.wdc.com (HELO uls-op-cesaep01.wdc.com) ([199.255.45.14]) by ob1.hgst.iphmx.com with ESMTP; 21 Apr 2022 14:38:22 +0800 Received: from uls-op-cesaip01.wdc.com ([10.248.3.36]) by uls-op-cesaep01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:09:24 -0700 Received: from usg-ed-osssrv.wdc.com ([10.3.10.180]) by uls-op-cesaip01.wdc.com with ESMTP/TLS/ECDHE-RSA-AES128-GCM-SHA256; 20 Apr 2022 23:38:22 -0700 Received: from usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTP id 4KkSXs4hjYz1SVp0 for ; Wed, 20 Apr 2022 23:38:21 -0700 (PDT) Received: from usg-ed-osssrv.wdc.com ([127.0.0.1]) by usg-ed-osssrv.wdc.com (usg-ed-osssrv.wdc.com [127.0.0.1]) (amavisd-new, port 10026) with ESMTP id e4fL1wSjwABt for ; Wed, 20 Apr 2022 23:38:21 -0700 (PDT) Received: from toolbox.wdc.com (unknown [10.225.165.119]) by usg-ed-osssrv.wdc.com (Postfix) with ESMTPSA id 4KkSXq0Z9Qz1Rvlx; Wed, 20 Apr 2022 23:38:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=simple/simple; d=wdc.com; i=@wdc.com; q=dns/txt; s=dkim.wdc.com; t=1650523138; x=1682059138; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=XsRVPpzc9qGQj9ZSOUzc3fWN20bwbvrPR37zlV2IJ5Y=; b=X1Cr2cP7DaQUL6V4ig3iPYjC+AVaWoIhMLF+irwergKR8CZkR4Hs2nJC RQ0b3FGe0dfHOEe/esvBETIjIcPNGcyT0z6983Yk1xBIhAJt/wYPos6n9 9bs8zd+9scYWP5FWBoxq4VswWVQWoiEj7jVwH1a55Zhvs5LF0bFOlCC1p mBCeKVslm0nxDJlR8UTVh0sYXHGom9sTHv8OsYSGnY416QCSAHgiMjz66 CC96emMSXYzbo1zrVAkoOoSSUdccNoDU0UCvkEAak3BRX0kxlQKn4o/wI om4UQNMLUj4BlwywQdfPDSC0tGWGFQw63DQL1luoYiS81V6FFgC5rK8rh w==; X-IronPort-AV: E=Sophos;i="5.90,278,1643644800"; d="scan'208";a="302640050" IronPort-SDR: uyo4q2v7WSQwsYd36Tk0hbPUQ94kjGdSApz9JJEZcuLD10yKlSGQiu3P6sxGoQ5ZkzlRCyV/3z eCpotBUUgN002iUSejQl85oIQa9mEN+11YNDPVwBO3E88fVUse5vx9M+ZUSDiZN9lmgxf/MwnK oGpEF5IMDqE2xCGJzGDFLfI95vCtzahBPoYuCdmdU6GX8A7ppSJcqfogcnoIZwXe6yzJKe+ZTy 9CbkRDQzSMjkC3xZltGFsp2/SHzEkw3u5wfCHh7ZfkYGgCUegjJv/A7CWrzRmh51e6IPJfeezg aQb/P6k7n7MXHqomR0nY5X9o IronPort-SDR: UOs6jC/qj1M4xZ3R3pvQVXUF/VDyYRYijD41JJ29zi12Bgo3gey31WWbaqgS21Dd02nAEEVaNx 7PPSsNVTjH8ivFk02nrXkCoQ1CMsX5dXeU/Q/qRWs5ADkBdFOL0YhReAPKM07hxVYaSd3sUCdH AWpdCQmXMTtTwo8EDH264ad+Wg4ykj6IqGh1+nU5jDsr0NoedqxZSzUVqFh61iReTTaXoJID1N b5CifNNi2mVMNXT1vu/++A0YANzqZnky3gEfR6jxYUBYzDISZ/tUugd73DZNBH8mB4FXBTJgPK m34= WDCIronportException: Internal Authentication-Results: usg-ed-osssrv.wdc.com (amavisd-new); dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1650523101; x=1653115102; bh=XsRVPpzc9qGQj9ZSOU zc3fWN20bwbvrPR37zlV2IJ5Y=; b=NvZTajpsNKo2y/CT/OZaFdjHoqz1r/a2Xs rMzJdYgBJFPgJ/O/iD17XJ9M7gz9JyW7irhuLcSZWv+gkIgvNURue5d/URQiDNci 3pUm8IfWbH/QljHBttbqZC3Az7pu08xjRkqhZYQVjo5K077Pz/r+fnKeG02v56a4 u8412AbKQSk3WYpWsHE19Rc/vCo03hWKGhJn8/y/326YLwaPnx509SB5XdBpJJkl 1TIzGlTyfRNdi1sgRFZh8qEuDg825UOrYo+fUmyIFWFIVlQdgeiZc5RSf++I3ts4 x0OTG83lITzlbPkWWl+1uTjV4wQJ2/rtnJuZ8E68V+3YXQ0Pv+IQ== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Dylan Jhong , Alistair Francis Subject: [PULL 31/31] hw/riscv: boot: Support 64bit fdt address. Date: Thu, 21 Apr 2022 16:36:30 +1000 Message-Id: <20220421063630.1033608-32-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> References: <20220421063630.1033608-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=10363b772=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650525599032100001 Content-Type: text/plain; charset="utf-8" From: Dylan Jhong The current riscv_load_fdt() forces fdt_load_addr to be placed at a dram ad= dress within 3GB, but not all platforms have dram_base within 3GB. This patch adds an exception for dram base not within 3GB, which will place fdt at dram_end align 16MB. riscv_setup_rom_reset_vec() also needs to be modified Signed-off-by: Dylan Jhong Reviewed-by: Alistair Francis Message-Id: <20220419115945.37945-1-dylan@andestech.com> Signed-off-by: Alistair Francis --- include/hw/riscv/boot.h | 4 ++-- hw/riscv/boot.c | 12 +++++++----- 2 files changed, 9 insertions(+), 7 deletions(-) diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index d937c5c224..d2db29721a 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -46,12 +46,12 @@ target_ulong riscv_load_kernel(const char *kernel_filen= ame, symbol_fn_t sym_cb); hwaddr riscv_load_initrd(const char *filename, uint64_t mem_size, uint64_t kernel_entry, hwaddr *start); -uint32_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); +uint64_t riscv_load_fdt(hwaddr dram_start, uint64_t dram_size, void *fdt); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState = *harts, hwaddr saddr, hwaddr rom_base, hwaddr rom_size, uint64_t kernel_entry, - uint32_t fdt_load_addr, void *fdt); + uint64_t fdt_load_addr, void *fdt); void riscv_rom_copy_firmware_info(MachineState *machine, hwaddr rom_base, hwaddr rom_size, uint32_t reset_vec_size, diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 0f179d3601..57a41df8e9 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -212,9 +212,9 @@ hwaddr riscv_load_initrd(const char *filename, uint64_t= mem_size, return *start + size; } =20 -uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) +uint64_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_size, void *fdt) { - uint32_t temp, fdt_addr; + uint64_t temp, fdt_addr; hwaddr dram_end =3D dram_base + mem_size; int ret, fdtsize =3D fdt_totalsize(fdt); =20 @@ -229,7 +229,7 @@ uint32_t riscv_load_fdt(hwaddr dram_base, uint64_t mem_= size, void *fdt) * Thus, put it at an 16MB aligned address that less than fdt size fro= m the * end of dram or 3GB whichever is lesser. */ - temp =3D MIN(dram_end, 3072 * MiB); + temp =3D (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_e= nd; fdt_addr =3D QEMU_ALIGN_DOWN(temp - fdtsize, 16 * MiB); =20 ret =3D fdt_pack(fdt); @@ -285,13 +285,15 @@ void riscv_setup_rom_reset_vec(MachineState *machine,= RISCVHartArrayState *harts hwaddr start_addr, hwaddr rom_base, hwaddr rom_size, uint64_t kernel_entry, - uint32_t fdt_load_addr, void *fdt) + uint64_t fdt_load_addr, void *fdt) { int i; uint32_t start_addr_hi32 =3D 0x00000000; + uint32_t fdt_load_addr_hi32 =3D 0x00000000; =20 if (!riscv_is_32bit(harts)) { start_addr_hi32 =3D start_addr >> 32; + fdt_load_addr_hi32 =3D fdt_load_addr >> 32; } /* reset vector */ uint32_t reset_vec[10] =3D { @@ -304,7 +306,7 @@ void riscv_setup_rom_reset_vec(MachineState *machine, R= ISCVHartArrayState *harts start_addr, /* start: .dword */ start_addr_hi32, fdt_load_addr, /* fdt_laddr: .dword */ - 0x00000000, + fdt_load_addr_hi32, /* fw_dyn: */ }; if (riscv_is_32bit(harts)) { --=20 2.35.1