From nobody Mon May 20 22:52:43 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=quicinc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650505450846826.2410586429569; Wed, 20 Apr 2022 18:44:10 -0700 (PDT) Received: from localhost ([::1]:44878 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nhLrd-0001Mz-1J for importer@patchew.org; Wed, 20 Apr 2022 21:44:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44556) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nhLqT-0007ro-Vw for qemu-devel@nongnu.org; Wed, 20 Apr 2022 21:42:58 -0400 Received: from alexa-out.qualcomm.com ([129.46.98.28]:40087) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1nhLqR-0000lQ-Qr for qemu-devel@nongnu.org; Wed, 20 Apr 2022 21:42:57 -0400 Received: from ironmsg08-lv.qualcomm.com ([10.47.202.152]) by alexa-out.qualcomm.com with ESMTP; 20 Apr 2022 18:42:52 -0700 Received: from hu-tsimpson-lv.qualcomm.com (HELO hu-devc-lv-u18-c.qualcomm.com) ([10.47.235.220]) by ironmsg08-lv.qualcomm.com with ESMTP; 20 Apr 2022 18:42:52 -0700 Received: by hu-devc-lv-u18-c.qualcomm.com (Postfix, from userid 47164) id 42B65500582; Wed, 20 Apr 2022 18:42:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1650505375; x=1682041375; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=wnJyMXznj/NY6S7udslUPpj6o4RnH2MZKcgpGtQSUlg=; b=MRrswZBrpxJe2qeq1xeeGfRbtQedmutBF6MbHyMteAXByNp9zqOlCeX/ ZfXYTg6aldSNpMHUGdHt3XOOQk0EOFMkjsAR6/TgbLrFRLjZdLsliz7m2 pWtXUXgU4dXkh62dW3duyMkRsZGHpJb4jL9xKbsWtTW2PRCsJUL/e9Adv g=; X-QCInternal: smtphost From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [PATCH] Hexagon (target/hexagon) make VyV operands use a unique temp Date: Wed, 20 Apr 2022 18:42:40 -0700 Message-Id: <20220421014243.7834-2-tsimpson@quicinc.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220421014243.7834-1-tsimpson@quicinc.com> References: <20220421014243.7834-1-tsimpson@quicinc.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=129.46.98.28; envelope-from=tsimpson@qualcomm.com; helo=alexa-out.qualcomm.com X-Spam_score_int: -17 X-Spam_score: -1.8 X-Spam_bar: - X-Spam_report: (-1.8 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, bcain@quicinc.com, richard.henderson@linaro.org, f4bug@amsat.org, tsimpson@quicinc.com, mlambert@quicinc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1650505452078100001 VyV operand is only used in the vshuff and vdeal instructions. These instructions write to both VyV and VxV operands. In the case where both operands are the same register, we need a separate location for VyV. We use the existing vtmp field in CPUHexagonState. Test case added in tests/tcg/hexagon/hvx_misc.c Signed-off-by: Taylor Simpson --- tests/tcg/hexagon/hvx_misc.c | 45 +++++++++++++++++++++++++++++++++ target/hexagon/gen_tcg_funcs.py | 9 +++---- 2 files changed, 49 insertions(+), 5 deletions(-) diff --git a/tests/tcg/hexagon/hvx_misc.c b/tests/tcg/hexagon/hvx_misc.c index b896f5897e..6e2c9ab3cd 100644 --- a/tests/tcg/hexagon/hvx_misc.c +++ b/tests/tcg/hexagon/hvx_misc.c @@ -498,6 +498,49 @@ static void test_vsubuwsat_dv(void) check_output_w(__LINE__, 2); } =20 +static void test_vshuff(void) +{ + /* Test that vshuff works when the two operands are the same register = */ + const uint32_t splat =3D 0x089be55c; + const uint32_t shuff =3D 0x454fa926; + MMVector v0, v1; + + memset(expect, 0x12, sizeof(MMVector)); + memset(output, 0x34, sizeof(MMVector)); + + asm volatile("v25 =3D vsplat(%0)\n\t" + "vshuff(v25, v25, %1)\n\t" + "vmem(%2 + #0) =3D v25\n\t" + : /* no outputs */ + : "r"(splat), "r"(shuff), "r"(output) + : "v25", "memory"); + + /* + * The semantics of Hexagon are the operands are pass-by-value, so cre= ate + * two copies of the vsplat result. + */ + for (int i =3D 0; i < MAX_VEC_SIZE_BYTES / 4; i++) { + v0.uw[i] =3D splat; + v1.uw[i] =3D splat; + } + /* Do the vshuff operation */ + for (int offset =3D 1; offset < MAX_VEC_SIZE_BYTES; offset <<=3D 1) { + if (shuff & offset) { + for (int k =3D 0; k < MAX_VEC_SIZE_BYTES; k++) { + if (!(k & offset)) { + uint8_t tmp =3D v0.ub[k]; + v0.ub[k] =3D v1.ub[k + offset]; + v1.ub[k + offset] =3D tmp; + } + } + } + } + /* Put the result in the expect buffer for verification */ + expect[0] =3D v1; + + check_output_b(__LINE__, 1); +} + int main() { init_buffers(); @@ -533,6 +576,8 @@ int main() test_vadduwsat(); test_vsubuwsat_dv(); =20 + test_vshuff(); + puts(err ? "FAIL" : "PASS"); return err ? 1 : 0; } diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs= .py index 1fd9de95d5..d72c689ad7 100755 --- a/target/hexagon/gen_tcg_funcs.py +++ b/target/hexagon/gen_tcg_funcs.py @@ -1,7 +1,7 @@ #!/usr/bin/env python3 =20 ## -## Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Res= erved. +## Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Res= erved. ## ## This program is free software; you can redistribute it and/or modify ## it under the terms of the GNU General Public License as published by @@ -164,7 +164,9 @@ def genptr_decl(f, tag, regtype, regid, regno): (regtype, regid, regno)) f.write(" const intptr_t %s%sV_off =3D\n" % \ (regtype, regid)) - if (hex_common.is_tmp_result(tag)): + if (regid =3D=3D "y"): + f.write(" offsetof(CPUHexagonState, vtmp);\n") + elif (hex_common.is_tmp_result(tag)): f.write(" ctx_tmp_vreg_off(ctx, %s%sN, 1, true);\n"= % \ (regtype, regid)) else: @@ -379,9 +381,6 @@ def genptr_src_read(f, tag, regtype, regid): f.write(" vreg_src_off(ctx, %s%sN),\n" % \ (regtype, regid)) f.write(" sizeof(MMVector), sizeof(MMVector));\n") - if (not hex_common.skip_qemu_helper(tag)): - f.write(" tcg_gen_addi_ptr(%s%sV, cpu_env, %s%sV_off);\= n" % \ - (regtype, regid, regtype, regid)) else: print("Bad register parse: ", regtype, regid) elif (regtype =3D=3D "Q"): --=20 2.17.1