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bh=v9gcesQuRAnYJLvpa9UYbtJvIgLxSU+QixBcnMmffeY=; b=Pje+rWcjgrZdGbtaDTA81hM+DB/RXD5aJvXfcAvJjF+zuUKmP+5ISr0OkKvaf983dX5iwZ WAt5FUcvvw70VuDfmmslupl4MKz9Nfkj3RlBgdslus96fRqrYIS0XhuOdGxqbw+aFPb7EF 6SSWatm9Vi5xhHxg/Bwr5sWNRvPjSK4= X-MC-Unique: JuvemWmVPYabAtYpbbprNg-1 From: Vitaly Kuznetsov To: qemu-devel@nongnu.org, Paolo Bonzini Subject: [PATCH v3 1/5] i386: Use hv_build_cpuid_leaf() for HV_CPUID_NESTED_FEATURES Date: Tue, 19 Apr 2022 16:47:59 +0200 Message-Id: <20220419144803.1698337-2-vkuznets@redhat.com> In-Reply-To: <20220419144803.1698337-1-vkuznets@redhat.com> References: <20220419144803.1698337-1-vkuznets@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.11.54.2 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=vkuznets@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; 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In fact, there are also feature (e.g. Enlightened MSR-Bitmap) bits there. In preparation to adding these features, move HV_CPUID_NESTED_FEATURES leaf handling to hv_build_cpuid_leaf() and drop now-unneeded 'hyperv_nested'. No functional change intended. Signed-off-by: Vitaly Kuznetsov --- target/i386/cpu.h | 1 - target/i386/kvm/kvm.c | 23 +++++++++++++++-------- 2 files changed, 15 insertions(+), 9 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 982c5323537c..73dc387c52f5 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1770,7 +1770,6 @@ struct ArchCPU { uint32_t hyperv_vendor_id[3]; uint32_t hyperv_interface_id[4]; uint32_t hyperv_limits[3]; - uint32_t hyperv_nested[4]; bool hyperv_enforce_cpuid; uint32_t hyperv_ver_id_build; uint16_t hyperv_ver_id_major; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 9cf8e036698d..ff79994faa87 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -834,6 +834,8 @@ static bool tsc_is_stable_and_known(CPUX86State *env) || env->user_tsc_khz; } =20 +#define DEFAULT_EVMCS_VERSION ((1 << 8) | 1) + static struct { const char *desc; struct { @@ -1241,6 +1243,13 @@ static uint32_t hv_build_cpuid_leaf(CPUState *cs, ui= nt32_t func, int reg) } } =20 + /* HV_CPUID_NESTED_FEATURES.EAX also encodes the supported eVMCS range= */ + if (func =3D=3D HV_CPUID_NESTED_FEATURES && reg =3D=3D R_EAX) { + if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) { + r |=3D DEFAULT_EVMCS_VERSION; + } + } + return r; } =20 @@ -1370,11 +1379,13 @@ static int hyperv_fill_cpuids(CPUState *cs, X86CPU *cpu =3D X86_CPU(cs); struct kvm_cpuid_entry2 *c; uint32_t cpuid_i =3D 0; + uint32_t nested_eax =3D + hv_build_cpuid_leaf(cs, HV_CPUID_NESTED_FEATURES, R_EAX); =20 c =3D &cpuid_ent[cpuid_i++]; c->function =3D HV_CPUID_VENDOR_AND_MAX_FUNCTIONS; - c->eax =3D hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS) ? - HV_CPUID_NESTED_FEATURES : HV_CPUID_IMPLEMENT_LIMITS; + c->eax =3D nested_eax ? HV_CPUID_NESTED_FEATURES : + HV_CPUID_IMPLEMENT_LIMITS; c->ebx =3D cpu->hyperv_vendor_id[0]; c->ecx =3D cpu->hyperv_vendor_id[1]; c->edx =3D cpu->hyperv_vendor_id[2]; @@ -1438,7 +1449,7 @@ static int hyperv_fill_cpuids(CPUState *cs, c->ecx =3D cpu->hyperv_limits[1]; c->edx =3D cpu->hyperv_limits[2]; =20 - if (hyperv_feat_enabled(cpu, HYPERV_FEAT_EVMCS)) { + if (nested_eax) { uint32_t function; =20 /* Create zeroed 0x40000006..0x40000009 leaves */ @@ -1450,7 +1461,7 @@ static int hyperv_fill_cpuids(CPUState *cs, =20 c =3D &cpuid_ent[cpuid_i++]; c->function =3D HV_CPUID_NESTED_FEATURES; - c->eax =3D cpu->hyperv_nested[0]; + c->eax =3D nested_eax; } =20 return cpuid_i; @@ -1472,8 +1483,6 @@ static bool evmcs_version_supported(uint16_t evmcs_ve= rsion, (max_version <=3D max_supported_version); } =20 -#define DEFAULT_EVMCS_VERSION ((1 << 8) | 1) - static int hyperv_init_vcpu(X86CPU *cpu) { CPUState *cs =3D CPU(cpu); @@ -1577,8 +1586,6 @@ static int hyperv_init_vcpu(X86CPU *cpu) supported_evmcs_version >> 8); return -ENOTSUP; } - - cpu->hyperv_nested[0] =3D evmcs_version; } =20 if (cpu->hyperv_enforce_cpuid) { --=20 2.35.1 From nobody Wed May 1 23:01:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1650382385; cv=none; d=zohomail.com; s=zohoarc; b=FVONO8ObFI+KDoXHI7R7mih/2BLDxlXH4CnkzxkLiNk45SCcgbIUjCKIqNzVWi5G9wOX9/Fi62b0mnNraZ+IskNKG429EMziM76ThLnpCs/o97VaIFpaT4PzJvDFqc6DZYulurICNAv6TP0o8ERoTkOQWbrXRCvAwZyzgWFNZxA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650382385; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=uLuffatAT8VSGsl2+sdu35TWMeCNnPWh8yPZZ6BNRf4=; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1650379688; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=uLuffatAT8VSGsl2+sdu35TWMeCNnPWh8yPZZ6BNRf4=; b=Dd7ufM5eTYsJiW6RRX88TvvTyNly2boEwiOlWWlHxpetpSuEjfO0/fiiSbx02FiV0V/C5j o8ArBN6VZ/wb8qM4pWZIsrfIYIz8ULmY3ZFikC6muK3Z9MR/YhRSap52B2p37qAdCMXRjr GdvJlp9vYr2KMgthd2jd5FGlFFQY9pM= X-MC-Unique: l3ezPl0zPHyXgmeG57Hb7w-1 From: Vitaly Kuznetsov To: qemu-devel@nongnu.org, Paolo Bonzini Subject: [PATCH v3 2/5] i386: Hyper-V Enlightened MSR bitmap feature Date: Tue, 19 Apr 2022 16:48:00 +0200 Message-Id: <20220419144803.1698337-3-vkuznets@redhat.com> In-Reply-To: <20220419144803.1698337-1-vkuznets@redhat.com> References: <20220419144803.1698337-1-vkuznets@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.11.54.2 Authentication-Results: relay.mimecast.com; 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charset="utf-8" The newly introduced enlightenment allow L0 (KVM) and L1 (Hyper-V) hypervisors to collaborate to avoid unnecessary updates to L2 MSR-Bitmap upon vmexits. Signed-off-by: Vitaly Kuznetsov --- docs/hyperv.txt | 10 ++++++++++ target/i386/cpu.c | 2 ++ target/i386/cpu.h | 1 + target/i386/kvm/hyperv-proto.h | 5 +++++ target/i386/kvm/kvm.c | 7 +++++++ 5 files changed, 25 insertions(+) diff --git a/docs/hyperv.txt b/docs/hyperv.txt index 0417c183a3b0..08429124a634 100644 --- a/docs/hyperv.txt +++ b/docs/hyperv.txt @@ -225,6 +225,16 @@ default (WS2016). Note: hv-version-id-* are not enlightenments and thus don't enable Hyper-V identification when specified without any other enlightenments. =20 +3.21. hv-emsr-bitmap +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +The enlightenment is nested specific, it targets Hyper-V on KVM guests. Wh= en +enabled, it allows L0 (KVM) and L1 (Hyper-V) hypervisors to collaborate to +avoid unnecessary updates to L2 MSR-Bitmap upon vmexits. While the protoco= l is +supported for both VMX (Intel) and SVM (AMD), the VMX implementation requi= res +Enlightened VMCS ('hv-evmcs') feature to also be enabled. + +Recommended: hv-evmcs (Intel) + 4. Supplementary features =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index cb6b5467d067..3f053919685f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6925,6 +6925,8 @@ static Property x86_cpu_properties[] =3D { HYPERV_FEAT_STIMER_DIRECT, 0), DEFINE_PROP_BIT64("hv-avic", X86CPU, hyperv_features, HYPERV_FEAT_AVIC, 0), + DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, + HYPERV_FEAT_MSR_BITMAP, 0), DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 73dc387c52f5..9615c330315f 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1084,6 +1084,7 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWo= rd w, #define HYPERV_FEAT_IPI 13 #define HYPERV_FEAT_STIMER_DIRECT 14 #define HYPERV_FEAT_AVIC 15 +#define HYPERV_FEAT_MSR_BITMAP 16 =20 #ifndef HYPERV_SPINLOCK_NEVER_NOTIFY #define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF diff --git a/target/i386/kvm/hyperv-proto.h b/target/i386/kvm/hyperv-proto.h index 89f81afda7c6..38e25468122d 100644 --- a/target/i386/kvm/hyperv-proto.h +++ b/target/i386/kvm/hyperv-proto.h @@ -72,6 +72,11 @@ #define HV_ENLIGHTENED_VMCS_RECOMMENDED (1u << 14) #define HV_NO_NONARCH_CORESHARING (1u << 18) =20 +/* + * HV_CPUID_NESTED_FEATURES.EAX bits + */ +#define HV_NESTED_MSR_BITMAP (1u << 19) + /* * Basic virtualized MSRs */ diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index ff79994faa87..4059b46b9449 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -966,6 +966,13 @@ static struct { .bits =3D HV_DEPRECATING_AEOI_RECOMMENDED} } }, + [HYPERV_FEAT_MSR_BITMAP] =3D { + .desc =3D "enlightened MSR-Bitmap (hv-emsr-bitmap)", + .flags =3D { + {.func =3D HV_CPUID_NESTED_FEATURES, .reg =3D R_EAX, + .bits =3D HV_NESTED_MSR_BITMAP} + } + }, }; =20 static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max, --=20 2.35.1 From nobody Wed May 1 23:01:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1650381867; cv=none; d=zohomail.com; s=zohoarc; b=OSulwnkCA0QhSYEvHsyTeg5DIzCdAo1O1wCPuLozPfERa8kst2IEGD6QpJdUmx4vE0Bqq3FrlgNg8Uu56r3FzUcuZcQktKxy1k3JoLT2fvz9F4toNqv5vV8Q25f1vaoBDuDHQVIDzU2JSAQTG16FfN/0P11o0fgYd7OoGK/Vn1E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650381867; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=O9LxI8wSPcSxMN2hG1Nb98gXP7vWvKN8OKpCZy9CAPk=; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1650379691; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=O9LxI8wSPcSxMN2hG1Nb98gXP7vWvKN8OKpCZy9CAPk=; b=iUcd7P3kJ9BJyEkC+KSaW/HpX0j+5sg69HnyOMgdMfw2wR9aOG9WAlms+hVhkuD0cevWl2 Hhj6otq7OZIcHs5tqyS09r1jni2zSziLFfKjmmq4B0uYXoEBilKTaQNaQ65OQTXjvJQTp5 18Phb3uUkItdVah/rrhVs/NA2PTAgtk= X-MC-Unique: 1r5h7uRhMoStOPbJaBBxoQ-1 From: Vitaly Kuznetsov To: qemu-devel@nongnu.org, Paolo Bonzini Subject: [PATCH v3 3/5] i386: Hyper-V XMM fast hypercall input feature Date: Tue, 19 Apr 2022 16:48:01 +0200 Message-Id: <20220419144803.1698337-4-vkuznets@redhat.com> In-Reply-To: <20220419144803.1698337-1-vkuznets@redhat.com> References: <20220419144803.1698337-1-vkuznets@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.11.54.2 Authentication-Results: relay.mimecast.com; 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charset="utf-8" Hyper-V specification allows to pass parameters for certain hypercalls using XMM registers ("XMM Fast Hypercall Input"). When the feature is in use, it allows for faster hypercalls processing as KVM can avoid reading guest's memory. KVM supports the feature since v5.14. Rename HV_HYPERCALL_{PARAMS_XMM_AVAILABLE -> XMM_INPUT_AVAILABLE} to comply with KVM. Signed-off-by: Vitaly Kuznetsov --- docs/hyperv.txt | 6 ++++++ target/i386/cpu.c | 2 ++ target/i386/cpu.h | 1 + target/i386/kvm/hyperv-proto.h | 2 +- target/i386/kvm/kvm.c | 7 +++++++ 5 files changed, 17 insertions(+), 1 deletion(-) diff --git a/docs/hyperv.txt b/docs/hyperv.txt index 08429124a634..857268d37d61 100644 --- a/docs/hyperv.txt +++ b/docs/hyperv.txt @@ -235,6 +235,12 @@ Enlightened VMCS ('hv-evmcs') feature to also be enabl= ed. =20 Recommended: hv-evmcs (Intel) =20 +3.22. hv-xmm-input +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Hyper-V specification allows to pass parameters for certain hypercalls usi= ng XMM +registers ("XMM Fast Hypercall Input"). When the feature is in use, it all= ows +for faster hypercalls processing as KVM can avoid reading guest's memory. + 4. Supplementary features =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 3f053919685f..c4be8ffe7988 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6927,6 +6927,8 @@ static Property x86_cpu_properties[] =3D { HYPERV_FEAT_AVIC, 0), DEFINE_PROP_BIT64("hv-emsr-bitmap", X86CPU, hyperv_features, HYPERV_FEAT_MSR_BITMAP, 0), + DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, + HYPERV_FEAT_XMM_INPUT, 0), DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9615c330315f..ea561e18f934 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1085,6 +1085,7 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWo= rd w, #define HYPERV_FEAT_STIMER_DIRECT 14 #define HYPERV_FEAT_AVIC 15 #define HYPERV_FEAT_MSR_BITMAP 16 +#define HYPERV_FEAT_XMM_INPUT 17 =20 #ifndef HYPERV_SPINLOCK_NEVER_NOTIFY #define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF diff --git a/target/i386/kvm/hyperv-proto.h b/target/i386/kvm/hyperv-proto.h index 38e25468122d..74d91adb7a16 100644 --- a/target/i386/kvm/hyperv-proto.h +++ b/target/i386/kvm/hyperv-proto.h @@ -51,7 +51,7 @@ #define HV_GUEST_DEBUGGING_AVAILABLE (1u << 1) #define HV_PERF_MONITOR_AVAILABLE (1u << 2) #define HV_CPU_DYNAMIC_PARTITIONING_AVAILABLE (1u << 3) -#define HV_HYPERCALL_PARAMS_XMM_AVAILABLE (1u << 4) +#define HV_HYPERCALL_XMM_INPUT_AVAILABLE (1u << 4) #define HV_GUEST_IDLE_STATE_AVAILABLE (1u << 5) #define HV_FREQUENCY_MSRS_AVAILABLE (1u << 8) #define HV_GUEST_CRASH_MSR_AVAILABLE (1u << 10) diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 4059b46b9449..7f752ef4376a 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -973,6 +973,13 @@ static struct { .bits =3D HV_NESTED_MSR_BITMAP} } }, + [HYPERV_FEAT_XMM_INPUT] =3D { + .desc =3D "XMM fast hypercall input (hv-xmm-input)", + .flags =3D { + {.func =3D HV_CPUID_FEATURES, .reg =3D R_EDX, + .bits =3D HV_HYPERCALL_XMM_INPUT_AVAILABLE} + } + }, }; =20 static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max, --=20 2.35.1 From nobody Wed May 1 23:01:14 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=redhat.com ARC-Seal: i=1; a=rsa-sha256; t=1650382489; cv=none; d=zohomail.com; s=zohoarc; b=ka/QT4LV9UA7naJ3YK+x+fXMBZxZz1+bzu8/zZ12s1cP5V1ifEUjbR+UABBR1KEm+BzAJfzSdpc1QP/ly0qw8TGRtwOJgBf9yDaHreuG7Z0+YqL6O5lh8Bj5uKhSNIehmCVE3CSR8c2+IJrBWg4WwHLUoGXHQjhWEcCJuDDfOL4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650382489; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=XMy6K4m6kgkexhxmXxfUl/IiZbgc4Y0yOJ1aLOT88Pk=; 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a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1650379694; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=XMy6K4m6kgkexhxmXxfUl/IiZbgc4Y0yOJ1aLOT88Pk=; b=ExrLtyBN5A5cQyC3UE6mdp7Qi+5YXfyljw5mPSgJytKzCOK1z8dsrZjhliGz5VSSFEnTty ta+kkKamRbushWRKb+TG15Nj7YlN3tTOLSu/I59NBHyQL6wIB2kiQwFJZEyTdr5+OOpwRm SjTGPgysdX1bx5liwLyMDZHsmBX+710= X-MC-Unique: XY8ntmuEPVuEE6_NUwZUew-1 From: Vitaly Kuznetsov To: qemu-devel@nongnu.org, Paolo Bonzini Subject: [PATCH v3 4/5] i386: Hyper-V Support extended GVA ranges for TLB flush hypercalls Date: Tue, 19 Apr 2022 16:48:02 +0200 Message-Id: <20220419144803.1698337-5-vkuznets@redhat.com> In-Reply-To: <20220419144803.1698337-1-vkuznets@redhat.com> References: <20220419144803.1698337-1-vkuznets@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.84 on 10.11.54.2 Authentication-Results: relay.mimecast.com; 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charset="utf-8" KVM kind of supported "extended GVA ranges" (up to 4095 additional GFNs per hypercall) since the implementation of Hyper-V PV TLB flush feature (Linux-4.18) as regardless of the request, full TLB flush was always performed. "Extended GVA ranges for TLB flush hypercalls" feature bit wasn't exposed then. Now, as KVM gains support for fine-grained TLB flush handling, exposing this feature starts making sense. Signed-off-by: Vitaly Kuznetsov --- docs/hyperv.txt | 7 +++++++ target/i386/cpu.c | 2 ++ target/i386/cpu.h | 1 + target/i386/kvm/hyperv-proto.h | 1 + target/i386/kvm/kvm.c | 8 ++++++++ 5 files changed, 19 insertions(+) diff --git a/docs/hyperv.txt b/docs/hyperv.txt index 857268d37d61..acc411eb84cf 100644 --- a/docs/hyperv.txt +++ b/docs/hyperv.txt @@ -241,6 +241,13 @@ Hyper-V specification allows to pass parameters for ce= rtain hypercalls using XMM registers ("XMM Fast Hypercall Input"). When the feature is in use, it all= ows for faster hypercalls processing as KVM can avoid reading guest's memory. =20 +3.23. hv-tlbflush-ext +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D +Allow for extended GVA ranges to be passed to Hyper-V TLB flush hypercalls +(HvFlushVirtualAddressList/HvFlushVirtualAddressListEx). + +Requires: hv-tlbflush + 4. Supplementary features =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index c4be8ffe7988..f80db9a403bd 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6929,6 +6929,8 @@ static Property x86_cpu_properties[] =3D { HYPERV_FEAT_MSR_BITMAP, 0), DEFINE_PROP_BIT64("hv-xmm-input", X86CPU, hyperv_features, HYPERV_FEAT_XMM_INPUT, 0), + DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, + HYPERV_FEAT_TLBFLUSH_EXT, 0), DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), diff --git a/target/i386/cpu.h b/target/i386/cpu.h index ea561e18f934..ec96b0e7a4cb 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1086,6 +1086,7 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWo= rd w, #define HYPERV_FEAT_AVIC 15 #define HYPERV_FEAT_MSR_BITMAP 16 #define HYPERV_FEAT_XMM_INPUT 17 +#define HYPERV_FEAT_TLBFLUSH_EXT 18 =20 #ifndef HYPERV_SPINLOCK_NEVER_NOTIFY #define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF diff --git a/target/i386/kvm/hyperv-proto.h b/target/i386/kvm/hyperv-proto.h index 74d91adb7a16..b3f42ab92051 100644 --- a/target/i386/kvm/hyperv-proto.h +++ b/target/i386/kvm/hyperv-proto.h @@ -55,6 +55,7 @@ #define HV_GUEST_IDLE_STATE_AVAILABLE (1u << 5) #define HV_FREQUENCY_MSRS_AVAILABLE (1u << 8) #define HV_GUEST_CRASH_MSR_AVAILABLE (1u << 10) +#define HV_EXT_GVA_RANGES_FLUSH_AVAILABLE (1u << 14) #define HV_STIMER_DIRECT_MODE_AVAILABLE (1u << 19) =20 /* diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 7f752ef4376a..8a71de07f3c7 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -980,6 +980,14 @@ static struct { .bits =3D HV_HYPERCALL_XMM_INPUT_AVAILABLE} } }, + [HYPERV_FEAT_TLBFLUSH_EXT] =3D { + .desc =3D "Extended gva ranges for TLB flush hypercalls (hv-tlbflu= sh-ext)", + .flags =3D { + {.func =3D HV_CPUID_FEATURES, .reg =3D R_EDX, + .bits =3D HV_EXT_GVA_RANGES_FLUSH_AVAILABLE} + }, + .dependencies =3D BIT(HYPERV_FEAT_TLBFLUSH) + }, }; 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charset="utf-8" Hyper-V TLFS allows for L0 and L1 hypervisors to collaborate on L2's TLB flush hypercalls handling. With the correct setup, L2's TLB flush hypercalls can be handled by L0 directly, without the need to exit to L1. Signed-off-by: Vitaly Kuznetsov --- docs/hyperv.txt | 11 +++++++++++ target/i386/cpu.c | 2 ++ target/i386/cpu.h | 1 + target/i386/kvm/hyperv-proto.h | 1 + target/i386/kvm/kvm.c | 8 ++++++++ 5 files changed, 23 insertions(+) diff --git a/docs/hyperv.txt b/docs/hyperv.txt index acc411eb84cf..9553e5c03c6b 100644 --- a/docs/hyperv.txt +++ b/docs/hyperv.txt @@ -248,6 +248,17 @@ Allow for extended GVA ranges to be passed to Hyper-V = TLB flush hypercalls =20 Requires: hv-tlbflush =20 +3.24. hv-tlbflush-direct +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D +The enlightenment is nested specific, it targets Hyper-V on KVM guests. Wh= en +enabled, it allows L0 (KVM) to directly handle TLB flush hypercalls from L2 +guest without the need to exit to L1 (Hyper-V) hypervisor. While the featu= re is +supported for both VMX (Intel) and SVM (AMD), the VMX implementation requi= res +Enlightened VMCS ('hv-evmcs') feature to also be enabled. + +Requires: hv-vapic +Recommended: hv-evmcs (Intel) + 4. Supplementary features =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f80db9a403bd..e8bbaf24d38d 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6931,6 +6931,8 @@ static Property x86_cpu_properties[] =3D { HYPERV_FEAT_XMM_INPUT, 0), DEFINE_PROP_BIT64("hv-tlbflush-ext", X86CPU, hyperv_features, HYPERV_FEAT_TLBFLUSH_EXT, 0), + DEFINE_PROP_BIT64("hv-tlbflush-direct", X86CPU, hyperv_features, + HYPERV_FEAT_TLBFLUSH_DIRECT, 0), DEFINE_PROP_ON_OFF_AUTO("hv-no-nonarch-coresharing", X86CPU, hyperv_no_nonarch_cs, ON_OFF_AUTO_OFF), DEFINE_PROP_BOOL("hv-passthrough", X86CPU, hyperv_passthrough, false), diff --git a/target/i386/cpu.h b/target/i386/cpu.h index ec96b0e7a4cb..2d17d52c00c1 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1087,6 +1087,7 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWo= rd w, #define HYPERV_FEAT_MSR_BITMAP 16 #define HYPERV_FEAT_XMM_INPUT 17 #define HYPERV_FEAT_TLBFLUSH_EXT 18 +#define HYPERV_FEAT_TLBFLUSH_DIRECT 19 =20 #ifndef HYPERV_SPINLOCK_NEVER_NOTIFY #define HYPERV_SPINLOCK_NEVER_NOTIFY 0xFFFFFFFF diff --git a/target/i386/kvm/hyperv-proto.h b/target/i386/kvm/hyperv-proto.h index b3f42ab92051..28d7759770e1 100644 --- a/target/i386/kvm/hyperv-proto.h +++ b/target/i386/kvm/hyperv-proto.h @@ -76,6 +76,7 @@ /* * HV_CPUID_NESTED_FEATURES.EAX bits */ +#define HV_NESTED_DIRECT_FLUSH (1u << 17) #define HV_NESTED_MSR_BITMAP (1u << 19) =20 /* diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 8a71de07f3c7..e966ab467b74 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -988,6 +988,14 @@ static struct { }, .dependencies =3D BIT(HYPERV_FEAT_TLBFLUSH) }, + [HYPERV_FEAT_TLBFLUSH_DIRECT] =3D { + .desc =3D "direct TLB flush (hv-tlbflush-direct)", + .flags =3D { + {.func =3D HV_CPUID_NESTED_FEATURES, .reg =3D R_EAX, + .bits =3D HV_NESTED_DIRECT_FLUSH} + }, + .dependencies =3D BIT(HYPERV_FEAT_VAPIC) + }, }; =20 static struct kvm_cpuid2 *try_get_hv_cpuid(CPUState *cs, int max, --=20 2.35.1