From nobody Tue Oct 14 14:09:10 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650218006; cv=none; d=zohomail.com; s=zohoarc; b=iqLS1AcNamZ1Cftt8gvl7QAzm47eh+2K1teea3NzliJx5wEOfmSmdM1JGcR0L9EEXxJI6oUpQ66arFfRQ78tT3n33+OrMukYZWg0ATEnf2YMZGfqzP9h/aIByArtKJrH+QPppyYY21o2Dh3884sMyGwxHes/3icN5MIFbJpDkiU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650218006; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4B9pthiRLfIf40OZcpcAQf7C9gNufiID5iESdzNE71c=; b=e5ON3VcVRnfnlOKJZdRz5M+KNTk/uO1OQ6v8a9yHaNszfgXsec41OuCPUpOwtb87bKGBlN9kTLSl9VMlbAsMTwiNx37fXEFpsNpjkjVK6VbdjwdPXOTf0vtAfs9mBzKA3RWtH7x/KHCvx3nksgt9/Hmdn/xRUZKAeqYfJcuH4dk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165021800605116.056387505481666; Sun, 17 Apr 2022 10:53:26 -0700 (PDT) Received: from localhost ([::1]:42624 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng95R-0003DJ-1h for importer@patchew.org; Sun, 17 Apr 2022 13:53:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47812) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng8wx-0000fI-J0 for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:41 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:40532) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng8wu-0003GR-Ku for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:37 -0400 Received: by mail-pj1-x102a.google.com with SMTP id md20-20020a17090b23d400b001cb70ef790dso15505987pjb.5 for ; Sun, 17 Apr 2022 10:44:35 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4B9pthiRLfIf40OZcpcAQf7C9gNufiID5iESdzNE71c=; b=VJE4sumENvnXSWQR9VW72B1CEU54og69sdChfbuItGbFzvfIOztws4fgfB1zp4r4nQ XI+74VB7pbvHnvY8uJed8/jkGhoc60Cf9SDU78fbLT/sTmrt0Pep0oBsE/kq4T8MK/BK 5PSbxELnwExO1ZrXwK+IhQhR77hk49TZJ+71la3YzVclPnfgwSu2ZQIvIOJlOFMwc4ii Ie6lN77wz3MVkLWmasezY7Fwp6bjbegJ7apvIPPNL+ikj9OPowiGVNr2DfZSIUNzUPoM Ar3VSGdgNelzCAp5KxnAXwFw6bMMk7YznGqGqBn+lGqNKtpPvXtC9Y4br30BFhs8AYPz 2nmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4B9pthiRLfIf40OZcpcAQf7C9gNufiID5iESdzNE71c=; b=2vgD8uF5exH0Z3icXeL8fpFLjFHpzPLaAPMRDeS3fT58SorEgXScqkqtQWd7VsYSfN TKpj7Qno8t+aqyjXFvWfdxWcDZHB0/I3pIqcjgKcPi1phI5nlfSZ14TDmEkEjYpQuhDG MRK7TYlcw/95J9Q/8AgWsAQehQhDCpwpIjMVcyCuRRf+ZpLkb5g2CyvryuJCGRIQi76E ZwAJGhx4hJ+UICPTl6690TG0SGgUNtYFOIkktCKh8axroaluIs6IFXekogpt/h9PRe+D +EbgT3G4aS1ZtDFDHbqY5zhBKkyaPiGf9gucWl8IV2pRJZn0/E2jWkaLV6WoXQ5Rb9An UQtA== X-Gm-Message-State: AOAM531BBuoDRRNSuDVBJB1w5GnkphHdmMGKo/ys+TFwkQNZB9qyLQvy 2JiyDQTkaYx61QIo0lHn3izTbkEWddXBrw== X-Google-Smtp-Source: ABdhPJwll9/1ewGDKdNFt+N7xobpYeHRiL+vadJvaGY9EN2977zUdDrME9kFStRtQu1yCXFomdo6sQ== X-Received: by 2002:a17:90a:634b:b0:1ca:6c7e:7952 with SMTP id v11-20020a17090a634b00b001ca6c7e7952mr14230125pjs.54.1650217474868; Sun, 17 Apr 2022 10:44:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 06/60] target/arm: Change CPUArchState.aarch64 to bool Date: Sun, 17 Apr 2022 10:43:32 -0700 Message-Id: <20220417174426.711829-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650218007011100002 Content-Type: text/plain; charset="utf-8" Bool is a more appropriate type for this value. Adjust the assignments to use true/false. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 2 +- target/arm/cpu.c | 2 +- target/arm/helper-a64.c | 4 ++-- target/arm/helper.c | 2 +- target/arm/hvf/hvf.c | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9ae9c935a2..a61a52e2f6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -258,7 +258,7 @@ typedef struct CPUArchState { * all other bits are stored in their correct places in env->pstate */ uint32_t pstate; - uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.n= RW */ + bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nR= W */ =20 /* Cached TBFLAGS state. See below for which bits are included. */ CPUARMTBFlags hflags; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5d4ca7a227..30e0d16ad4 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -189,7 +189,7 @@ static void arm_cpu_reset(DeviceState *dev) =20 if (arm_feature(env, ARM_FEATURE_AARCH64)) { /* 64 bit CPUs always start in 64 bit mode */ - env->aarch64 =3D 1; + env->aarch64 =3D true; #if defined(CONFIG_USER_ONLY) env->pstate =3D PSTATE_MODE_EL0t; /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 7cf953b1e6..77a8502b6b 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -952,7 +952,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_= t new_pc) qemu_mutex_unlock_iothread(); =20 if (!return_to_aa64) { - env->aarch64 =3D 0; + env->aarch64 =3D false; /* We do a raw CPSR write because aarch64_sync_64_to_32() * will sort the register banks out for us, and we've already * caught all the bad-mode cases in el_from_spsr(). @@ -975,7 +975,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_= t new_pc) } else { int tbii; =20 - env->aarch64 =3D 1; + env->aarch64 =3D true; spsr &=3D aarch64_pstate_valid_mask(&env_archcpu(env)->isar); pstate_write(env, spsr); if (!arm_singlestep_active(env)) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 7d14650615..47fe790854 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10182,7 +10182,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *= cs) } =20 pstate_write(env, PSTATE_DAIF | new_mode); - env->aarch64 =3D 1; + env->aarch64 =3D true; aarch64_restore_sp(env, new_el); helper_rebuild_hflags_a64(env, new_el); =20 diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 8c34f86792..11176ef252 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -565,7 +565,7 @@ int hvf_arch_init_vcpu(CPUState *cpu) hv_return_t ret; int i; =20 - env->aarch64 =3D 1; + env->aarch64 =3D true; asm volatile("mrs %0, cntfrq_el0" : "=3Dr"(arm_cpu->gt_cntfrq_hz)); =20 /* Allocate enough space for our sysreg sync */ --=20 2.25.1