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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id e14-20020aa78c4e000000b00506475da4cesm9372055pfd.49.2022.04.17.10.48.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:48:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tg97pAzl6c8fQ/INZXGM16Pyz/AbXSyAlqpVeNxoRMU=; b=RmAFVP8t2BZ3/Cg/otdBUbyo2kR5iHJiQLLbA32jJOgbJMLGq0QPxuo6ScgdFDwm8X TFoNDttTlTZaZvI0A8lmlUXWkvCZf03Aa/H/ECYj4LtL1fHt9ATZsum5ZlgokTyBWg1s IFxIyDXnuTHG2zwsEqTc4wYuwt2Lnk/qbPNGgNuSMrzkApgfUlljzN+Cd8dSGdWAYbXP mzcMY+yDD81PjJiczZkTw77b6tl1KDJLp9+dK0ASfjODoDNWmJiGQQP1vGeS1MqEx/CD IERE4/2L3dLudWVTe1Oemdi2mGDYh3nQkJw2ykj9wVdg/WeUEZgAtMvpj5Ft8Bzo+c4F y5Tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tg97pAzl6c8fQ/INZXGM16Pyz/AbXSyAlqpVeNxoRMU=; b=0rJkKPNV29EfrGQt+tFg5c9eId6VLEx7ysAybf7f9ny5zW4KMRipH4vMsxnxRVQ7r6 Ck6juPwSQRG3/GmnGMegjOnxOAUASxkXpTCKgWb+3DQenqmJl8fC7sVQPx/Yh/s8aqGH o72Z3MFdjheRbknOk+h/7WD3yxe1tjuKhBecHpKy9GNiHL5yGSBibkDGF28s6eew8cY9 4sqbPTY3ZFeT2ztKBvBUD/gr6AuR5i8YrF9fYvN2FsF4KBhnd9kNKqMmweEH68ht2svZ yio6odCAKDDTTzysAzNPy2Yf6MUA6g2d1ZRC6TG5lDr1i1CkHRVLVBLWiTPhs5N+ZuAw rnRQ== X-Gm-Message-State: AOAM531T3JfXf9FQVhzFMzA3ARJb231uce8a4FjsWxoeOeKzuX0wOKum 2Uw/YDx8Et4+ZSPrIqJ2/UOTAMXfA+W/9Q== X-Google-Smtp-Source: ABdhPJxDnJP8VWBasPNLMtUuJjvrJQj6kTq4bf/fNrGgkZMH6NPReNofbv+UKRiR/CMCDLBbypN7mg== X-Received: by 2002:a17:90b:1e49:b0:1d2:9d82:8bb1 with SMTP id pi9-20020a17090b1e4900b001d29d828bb1mr1224747pjb.226.1650217698502; Sun, 17 Apr 2022 10:48:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 56/60] target/arm: Enable FEAT_CSV2_2 for -cpu max Date: Sun, 17 Apr 2022 10:44:22 -0700 Message-Id: <20220417174426.711829-57-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650220629831100003 Content-Type: text/plain; charset="utf-8" There is no branch prediction in TCG, therefore there is no need to actually include the context number into the predictor. Therefore all we need to do is add the state for SCXTNUM_ELx. Signed-off-by: Richard Henderson --- v2: Update emulation.rst; clear CSV2_FRAC; use decimal; tidy access_scxtnum. v3: Rely on EL3-no-EL2 squashing during registration. --- docs/system/arm/emulation.rst | 3 ++ target/arm/cpu.h | 16 +++++++++ target/arm/cpu64.c | 3 +- target/arm/helper.c | 66 ++++++++++++++++++++++++++++++++++- 4 files changed, 86 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 91fb06c579..aebe3be1ba 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -12,6 +12,9 @@ the following architecture extensions: - FEAT_BF16 (AArch64 BFloat16 instructions) - FEAT_BTI (Branch Target Identification) - FEAT_CSV2 (Cache speculation variant 2) +- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) +- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) +- FEAT_CSV2_2 (Cache speculation variant 2, version 2) - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) - FEAT_Debugv8p2 (Debug changes for v8.2) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b90b6d91bd..a7582da7c2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -687,6 +687,8 @@ typedef struct CPUArchState { ARMPACKey apdb; ARMPACKey apga; } keys; + + uint64_t scxtnum_el[4]; #endif =20 #if defined(CONFIG_USER_ONLY) @@ -1210,6 +1212,7 @@ void pmu_init(ARMCPU *cpu); #define SCTLR_WXN (1U << 19) #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ +#define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ @@ -4021,6 +4024,19 @@ static inline bool isar_feature_aa64_dit(const ARMIS= ARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) !=3D 0; } =20 +static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) +{ + int key =3D FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); + if (key >=3D 2) { + return true; /* FEAT_CSV2_2 */ + } + if (key =3D=3D 1) { + key =3D FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); + return key >=3D 2; /* FEAT_CSV2_1p2 */ + } + return false; +} + static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) !=3D 0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index b62656f3c3..6ccbcb857d 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -748,7 +748,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ - t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ cpu->isar.id_aa64pfr0 =3D t; =20 t =3D cpu->isar.id_aa64pfr1; @@ -760,6 +760,7 @@ static void aarch64_max_initfn(Object *obj) * we do for EL2 with the virtualization=3Don property. */ t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ + t =3D FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ cpu->isar.id_aa64pfr1 =3D t; =20 t =3D cpu->isar.id_aa64mmfr0; diff --git a/target/arm/helper.c b/target/arm/helper.c index 7e4178c594..22728b9fbf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1771,6 +1771,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_mte, cpu)) { valid_mask |=3D SCR_ATA; } + if (cpu_isar_feature(aa64_scxtnum, cpu)) { + valid_mask |=3D SCR_ENSCXT; + } } else { valid_mask &=3D ~(SCR_RW | SCR_ST); if (cpu_isar_feature(aa32_ras, cpu)) { @@ -5149,6 +5152,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t v= alue, uint64_t valid_mask) if (cpu_isar_feature(aa64_mte, cpu)) { valid_mask |=3D HCR_ATA | HCR_DCT | HCR_TID5; } + if (cpu_isar_feature(aa64_scxtnum, cpu)) { + valid_mask |=3D HCR_ENSCXT; + } } =20 /* Clear RES0 bits. */ @@ -5798,6 +5804,10 @@ static void define_arm_vh_e2h_redirects_aliases(ARMC= PU *cpu) { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0), "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte }, =20 + { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7), + "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12", + isar_feature_aa64_scxtnum }, + /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ }; @@ -7233,7 +7243,57 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = =3D { }, }; =20 -#endif +static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo = *ri, + bool isread) +{ + int el =3D arm_current_el(env); + + if (el =3D=3D 0) { + uint64_t hcr =3D arm_hcr_el2_eff(env); + if ((hcr & (HCR_TGE | HCR_E2H)) !=3D (HCR_TGE | HCR_E2H)) { + if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) { + if (hcr & HCR_TGE) { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_TRAP; + } + if (arm_is_el2_enabled(env) && !(hcr & HCR_ENSCXT)) { + return CP_ACCESS_TRAP_EL2; + } + goto no_sctlr_el2; + } + } + if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) { + return CP_ACCESS_TRAP_EL2; + } + no_sctlr_el2: + if (el < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_ENSCXT)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo scxtnum_reginfo[] =3D { + { .name =3D "SCXTNUM_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, + .access =3D PL0_RW, .accessfn =3D access_scxtnum, + .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[0]) }, + { .name =3D "SCXTNUM_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, + .access =3D PL1_RW, .accessfn =3D access_scxtnum, + .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[1]) }, + { .name =3D "SCXTNUM_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, + .access =3D PL2_RW, .accessfn =3D access_scxtnum, + .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[2]) }, + { .name =3D "SCXTNUM_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, + .access =3D PL3_RW, + .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[3]) }, +}; +#endif /* TARGET_AARCH64 */ =20 static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo = *ri, bool isread) @@ -8372,6 +8432,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, mte_tco_ro_reginfo); define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); } + + if (cpu_isar_feature(aa64_scxtnum, cpu)) { + define_arm_cp_regs(cpu, scxtnum_reginfo); + } #endif =20 if (cpu_isar_feature(any_predinv, cpu)) { --=20 2.25.1