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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aDgvjaxwViELgB4ykiyMAgIgM6sZRWkjwRFfHxxhnR0=; b=q+10ZK4QziaY93HK4YRlUUL5E30RQARthfc6o4zouS9fSYBBEM1Cmf9bcC6LbhWJI+ P2MBwBI5kjOhkGR2faHETErquGN/Tu5b6pvpfju1I8Malon3SCrW5y5vHWZF97n+dPPl BlDzPP89Lh1xQy62Klv0m1umntPrV/DO3GM+JVqnJ3dR2zzRspyQVSRz11g6S5AsQAT5 HU8/GdHjArTwVfD0YDRIdPnQe3I3rgyYr/wTGoQGaTXV3WvC8umqzkRMHry64wnSgSD9 nweyMu79SxtGMPem61MWoNIAJv3nX0g/84ktjiPoHapK5wIHW/F7xUTZWKmZSqWm+yvW tsrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aDgvjaxwViELgB4ykiyMAgIgM6sZRWkjwRFfHxxhnR0=; b=zrxeKQyulkScvvSDgcGqVH4f5NXCLMjIftkXAO08vPWR7ut8UhJypau8bzUwavU1T4 igmYhpDSbvm7KiORdLv+/Tjp158WlEJaq082Ar7rY59C2W9bMTlW25+8roWePnGCzE+n kP1Cg9cSwUgFJmq7zDsR7sNeh3H672At3O794HlvDWe1hAHhlekWIFNqqwsLyfX/ougJ vxZXXWsHp0RFLuYjX6Fzkaxo+qQ/lyffp7RgahTSva9lGESe+Fu2k3wv5rehMaXSdN1t Q9G2z976kfLuOwTMpeJO5dwabiJPth+kD9YaggvSGwlUbsjM0zt35Jf4Sre2iBO8L61t jr+A== X-Gm-Message-State: AOAM532NlmIcvrUElREEQ1kkNcR2mQ8cW7FYf3IcXIPkQ4gBztb1Hho+ kNmZEiQqxTZhwP9+nJa/EGtwgtm7OS0ZTQ== X-Google-Smtp-Source: ABdhPJzRt8n4xHzQVVryvU7AVDL19Es9oEomVRJqNVLLi/Xzdl/dSjXsX6NiYya0fhadXqKdCz+UIQ== X-Received: by 2002:a17:902:cece:b0:158:d875:e6d6 with SMTP id d14-20020a170902cece00b00158d875e6d6mr7354133plg.165.1650217498102; Sun, 17 Apr 2022 10:44:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 33/60] target/arm: Store cpregs key in the hash table directly Date: Sun, 17 Apr 2022 10:43:59 -0700 Message-Id: <20220417174426.711829-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650218952765100001 Content-Type: text/plain; charset="utf-8" Cast the uint32_t key into a gpointer directly, which allows us to avoid allocating storage for each key. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 4 ++-- target/arm/gdbstub.c | 2 +- target/arm/helper.c | 45 ++++++++++++++++++++------------------------ 3 files changed, 23 insertions(+), 28 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 92fc75b2bf..af13b34697 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1080,8 +1080,8 @@ static void arm_cpu_initfn(Object *obj) ARMCPU *cpu =3D ARM_CPU(obj); =20 cpu_set_cpustate_pointers(cpu); - cpu->cp_regs =3D g_hash_table_new_full(g_int_hash, g_int_equal, - g_free, cpreg_hashtable_data_dest= roy); + cpu->cp_regs =3D g_hash_table_new_full(g_direct_hash, g_direct_equal, + NULL, cpreg_hashtable_data_destro= y); =20 QLIST_INIT(&cpu->pre_el_change_hooks); QLIST_INIT(&cpu->el_change_hooks); diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index f01a126108..f5b35cd55f 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -273,7 +273,7 @@ static void arm_gen_one_xml_sysreg_tag(GString *s, Dyna= micGDBXMLInfo *dyn_xml, static void arm_register_sysreg_for_xml(gpointer key, gpointer value, gpointer p) { - uint32_t ri_key =3D *(uint32_t *)key; + uint32_t ri_key =3D (uintptr_t)key; ARMCPRegInfo *ri =3D value; RegisterSysregXmlParam *param =3D (RegisterSysregXmlParam *)p; GString *s =3D param->s; diff --git a/target/arm/helper.c b/target/arm/helper.c index aee195400b..db9e75a42d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -215,11 +215,8 @@ bool write_list_to_cpustate(ARMCPU *cpu) static void add_cpreg_to_list(gpointer key, gpointer opaque) { ARMCPU *cpu =3D opaque; - uint64_t regidx; - const ARMCPRegInfo *ri; - - regidx =3D *(uint32_t *)key; - ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); + uint32_t regidx =3D (uintptr_t)key; + const ARMCPRegInfo *ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); =20 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { cpu->cpreg_indexes[cpu->cpreg_array_len] =3D cpreg_to_kvm_id(regid= x); @@ -231,11 +228,9 @@ static void add_cpreg_to_list(gpointer key, gpointer o= paque) static void count_cpreg(gpointer key, gpointer opaque) { ARMCPU *cpu =3D opaque; - uint64_t regidx; const ARMCPRegInfo *ri; =20 - regidx =3D *(uint32_t *)key; - ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); + ri =3D g_hash_table_lookup(cpu->cp_regs, key); =20 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { cpu->cpreg_array_len++; @@ -244,8 +239,8 @@ static void count_cpreg(gpointer key, gpointer opaque) =20 static gint cpreg_key_compare(gconstpointer a, gconstpointer b) { - uint64_t aidx =3D cpreg_to_kvm_id(*(uint32_t *)a); - uint64_t bidx =3D cpreg_to_kvm_id(*(uint32_t *)b); + uint64_t aidx =3D cpreg_to_kvm_id((uintptr_t)a); + uint64_t bidx =3D cpreg_to_kvm_id((uintptr_t)b); =20 if (aidx > bidx) { return 1; @@ -5915,16 +5910,17 @@ static void define_arm_vh_e2h_redirects_aliases(ARM= CPU *cpu) =20 for (i =3D 0; i < ARRAY_SIZE(aliases); i++) { const struct E2HAlias *a =3D &aliases[i]; - ARMCPRegInfo *src_reg, *dst_reg, *new_reg; - uint32_t *new_key; + const ARMCPRegInfo *dst_reg; + ARMCPRegInfo *src_reg; + ARMCPRegInfo *new_reg; bool ok; =20 if (a->feature && !a->feature(&cpu->isar)) { continue; } =20 - src_reg =3D g_hash_table_lookup(cpu->cp_regs, &a->src_key); - dst_reg =3D g_hash_table_lookup(cpu->cp_regs, &a->dst_key); + src_reg =3D (ARMCPRegInfo *)get_arm_cp_reginfo(cpu->cp_regs, a->sr= c_key); + dst_reg =3D get_arm_cp_reginfo(cpu->cp_regs, a->dst_key); g_assert(src_reg !=3D NULL); g_assert(dst_reg !=3D NULL); =20 @@ -5937,7 +5933,6 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCP= U *cpu) =20 /* Create alias before redirection so we dup the right data. */ new_reg =3D g_memdup(src_reg, sizeof(ARMCPRegInfo)); - new_key =3D g_memdup(&a->new_key, sizeof(uint32_t)); =20 new_reg->name =3D a->new_name; new_reg->type |=3D ARM_CP_ALIAS; @@ -5956,10 +5951,11 @@ static void define_arm_vh_e2h_redirects_aliases(ARM= CPU *cpu) =20 #undef E =20 - ok =3D g_hash_table_insert(cpu->cp_regs, new_key, new_reg); + ok =3D g_hash_table_insert(cpu->cp_regs, + (gpointer)(uintptr_t)a->new_key, new_reg); g_assert(ok); =20 - src_reg->opaque =3D dst_reg; + src_reg->opaque =3D (void *)dst_reg; src_reg->orig_readfn =3D src_reg->readfn ?: raw_read; src_reg->orig_writefn =3D src_reg->writefn ?: raw_write; if (!src_reg->raw_readfn) { @@ -8522,7 +8518,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, /* Private utility function for define_one_arm_cp_reg_with_opaque(): * add a single reginfo struct to the hash table. */ - uint32_t *key =3D g_new(uint32_t, 1); + uint32_t key; ARMCPRegInfo *r2 =3D g_memdup(r, sizeof(ARMCPRegInfo)); int is64 =3D (r->type & ARM_CP_64BIT) ? 1 : 0; int ns =3D (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; @@ -8589,10 +8585,10 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con= st ARMCPRegInfo *r, if (r->cp =3D=3D 0 || r->state =3D=3D ARM_CP_STATE_BOTH) { r2->cp =3D CP_REG_ARM64_SYSREG_CP; } - *key =3D ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, - r2->opc0, opc1, opc2); + key =3D ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, + r2->opc0, opc1, opc2); } else { - *key =3D ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); + key =3D ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); } if (opaque) { r2->opaque =3D opaque; @@ -8634,8 +8630,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, * requested. */ if (!(r->type & ARM_CP_OVERRIDE)) { - ARMCPRegInfo *oldreg; - oldreg =3D g_hash_table_lookup(cpu->cp_regs, key); + const ARMCPRegInfo *oldreg =3D get_arm_cp_reginfo(cpu->cp_regs, ke= y); if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { fprintf(stderr, "Register redefined: cp=3D%d %d bit " "crn=3D%d crm=3D%d opc1=3D%d opc2=3D%d, " @@ -8645,7 +8640,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, g_assert_not_reached(); } } - g_hash_table_insert(cpu->cp_regs, key, r2); + g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2); } =20 =20 @@ -8875,7 +8870,7 @@ void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, = size_t regs_len, =20 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encode= d_cp) { - return g_hash_table_lookup(cpregs, &encoded_cp); + return g_hash_table_lookup(cpregs, (gpointer)(uintptr_t)encoded_cp); } =20 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, --=20 2.25.1