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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=TnTEItSGWycbpaAmp+hDaYT95wtDnOp1XDNT2WSNp3w=; b=E6Yq7Evf4C609rZ+2CIrPoceBE6G0loh0WZDqzcpW+M+S5jZQlgAu8P+9bJclkVmeW 2P7w4GLy/J9hHfie+DwTts7cb6w6DP5v3x/Dgse4HwT78iKzzmOyXkRgDHuH1TqQg/m2 HEz5VaFnMxCM5YcdgvwV7RxS9kRuK9Io+Xiu5MrRYYdNpY8Aje84cN3C9jUtce/TwLMi YH5RPauvCvXZ8FbX0wTqcO0bsTI6O/y84x0+ZcieUQ7iQVYSB7yKfSdoxV+nHs9D2QHV CpsUx+jOjI05ykwfaLnECbqysWqdBFqb3Srt1wECZCI9zp2/Ph1sxB5vRCgwDo7e9IFo OUzw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=TnTEItSGWycbpaAmp+hDaYT95wtDnOp1XDNT2WSNp3w=; b=cbAy4aZa2K+lSsgzA3v0uDM5qKLFoxJl6m91VqvPiDE3/i8g+1ywfRxHM0YywjWLlN P69SS8b2PlaQrvqai5hVVdaCSNJVdc9YF/w2MG5myxWuLxxOalvCa5bupHrftlEmVZay 96MUMMlWzj+bk7ZdJGJ/kHss0NfJRELSkUpd2UdT/6W+JuAlQ4Ql9TFsesU5pr4HNFu5 ggS3Ka6iVqtHfkw+4NJhUtlyO+GjpaY5XAXo32DWoq00mdevKcWf/0KqLdVAJDidVcw7 HWRsyyHjaDtEaqfwMnUzorywV9g/PK1Z2qVBKkK3wHvNCRFSKbYhBzTCdGbgzruikQz2 3HqQ== X-Gm-Message-State: AOAM530po5g6Kz9MwUWalfrNPzncO8O+hb8qGF40GUtaUpdMO3zFPaHY svsXuTmTtWHu/XBlzw8wA61nLU5cUDSTMQ== X-Google-Smtp-Source: ABdhPJzSfiuO3MY4Br/5ROAMmgK3Nsoa6TwiRnA34FOIKg6xcWXn5FEBuQ558h9Qb/hJP3UUD/b39g== X-Received: by 2002:a17:90b:804:b0:1cb:be2d:e28f with SMTP id bk4-20020a17090b080400b001cbbe2de28fmr8942645pjb.21.1650217470376; Sun, 17 Apr 2022 10:44:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 01/60] tcg: Add tcg_constant_ptr Date: Sun, 17 Apr 2022 10:43:27 -0700 Message-Id: <20220417174426.711829-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650217814260100001 Content-Type: text/plain; charset="utf-8" Similar to tcg_const_ptr, defer to tcg_constant_{i32,i64}. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- include/tcg/tcg.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 73869fd9d0..cd6eaae410 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -1054,9 +1054,11 @@ TCGv_vec tcg_constant_vec_matching(TCGv_vec match, u= nsigned vece, int64_t val); #if UINTPTR_MAX =3D=3D UINT32_MAX # define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i32((intptr_t)(x))) # define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i32((intptr_t)= (x))) +# define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i32((intptr_t)(x)= )) #else # define tcg_const_ptr(x) ((TCGv_ptr)tcg_const_i64((intptr_t)(x))) # define tcg_const_local_ptr(x) ((TCGv_ptr)tcg_const_local_i64((intptr_t)= (x))) +# define tcg_constant_ptr(x) ((TCGv_ptr)tcg_constant_i64((intptr_t)(x)= )) #endif =20 TCGLabel *gen_new_label(void); --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650217957520127.35004120176598; Sun, 17 Apr 2022 10:52:37 -0700 (PDT) Received: from localhost ([::1]:40318 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng94e-0001dd-41 for importer@patchew.org; Sun, 17 Apr 2022 13:52:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47638) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng8ws-0000dj-24 for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:35 -0400 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:41513) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng8wq-0003E5-Jb for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:33 -0400 Received: by mail-pg1-x532.google.com with SMTP id t13so14959232pgn.8 for ; Sun, 17 Apr 2022 10:44:32 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KMJqWCFFQ/5jg8W4iYwme8tmF7Vde2zNGH6ujSmTVXA=; b=E/DaA9JzIYarK2hn6C1lG8rNsmjSrAw+ocrr0LWL51dOfsELU+1qvo5RgJIot+fiuj KHYJtb1F6HI4u4ovM0HqOpymS0h8wIAo5Rbrvm2X5p75VSAC6u/1Ondk9ZSV5ktdF90N UzZxhIN7fnvViDvRsHMtvM+p8g1Iej1WCErU2dAZdhrSnYJWJR8skVmWRAhwFbxp2sJr dEWCyN807QKZFm+l1GUeruZL8Nat1I1rmMqSfo1wDoiF/vtLuwjZAzeTRIuipAOZydCK znrQ/aP8t+tb1qZCBVeVCGAg1dhfpw/kbntQcJUHZBhBQqJpl2R2tkSUOZUY8ut1fmZR Md3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KMJqWCFFQ/5jg8W4iYwme8tmF7Vde2zNGH6ujSmTVXA=; b=nLQmAmxBIbwRZYfTdO5Gq24rF9ZDpzZgcQympj31VjTy7KkguEODhOS7gKykMTGMRF wrHFP1qgUA7v3MpfOjoYMaPDf3b0HLjUuvrTGMu6pWCzoXeiFBVl+/gu2gGPVwPWivOp GLLSCiPcbsShKqbocCO7E+jylhDrzIo/yX1HFvJKqLGn6zLusvuBo4ib909zxXPHsVus r2yJai1KBNa95DPqMda6KdbnS1n18O7+lqCydqIQbkU7EkHZGLRNQpaCoyWQYF5XtFoE 97nQ+Zp4dfjeO5uG2BDLLHlPb/0DodjhCy0q4p+uR38vYCwqhOFGdeUDR4nBsBl+Wh+q +PDg== X-Gm-Message-State: AOAM532Fel/Q2goYOPlZOuhftQzTeBgAUKaoP0K0RwxHelCH+Oqgp5ap 4ERQ9Wl8gVRam/VMiTZpEBhpEihMfsiVMQ== X-Google-Smtp-Source: ABdhPJyfkKBhRT6aaEmWdpfz+SMxEptRvIyoZ+IBaC8lZIVFlxXv9wwLL+UjhaR04EY25w4gisD4Sg== X-Received: by 2002:a05:6a00:2148:b0:4fa:92f2:bae3 with SMTP id o8-20020a056a00214800b004fa92f2bae3mr8391283pfk.69.1650217471292; Sun, 17 Apr 2022 10:44:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 02/60] target/arm: Update ISAR fields for ARMv8.8 Date: Sun, 17 Apr 2022 10:43:28 -0700 Message-Id: <20220417174426.711829-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1650217958783100001 Content-Type: text/plain; charset="utf-8" Update isar fields per ARM DDI0487 H.a. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- v2: Add ID_AA64DFR0.HPMN0 --- target/arm/cpu.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 23879de5fa..9a29a4a215 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1933,6 +1933,7 @@ FIELD(ID_MMFR4, CCIDX, 24, 4) FIELD(ID_MMFR4, EVT, 28, 4) =20 FIELD(ID_MMFR5, ETS, 0, 4) +FIELD(ID_MMFR5, NTLBPA, 4, 4) =20 FIELD(ID_PFR0, STATE0, 0, 4) FIELD(ID_PFR0, STATE1, 4, 4) @@ -1985,6 +1986,16 @@ FIELD(ID_AA64ISAR1, SPECRES, 40, 4) FIELD(ID_AA64ISAR1, BF16, 44, 4) FIELD(ID_AA64ISAR1, DGH, 48, 4) FIELD(ID_AA64ISAR1, I8MM, 52, 4) +FIELD(ID_AA64ISAR1, XS, 56, 4) +FIELD(ID_AA64ISAR1, LS64, 60, 4) + +FIELD(ID_AA64ISAR2, WFXT, 0, 4) +FIELD(ID_AA64ISAR2, RPRES, 4, 4) +FIELD(ID_AA64ISAR2, GPA3, 8, 4) +FIELD(ID_AA64ISAR2, APA3, 12, 4) +FIELD(ID_AA64ISAR2, MOPS, 16, 4) +FIELD(ID_AA64ISAR2, BC, 20, 4) +FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) =20 FIELD(ID_AA64PFR0, EL0, 0, 4) FIELD(ID_AA64PFR0, EL1, 4, 4) @@ -2007,6 +2018,10 @@ FIELD(ID_AA64PFR1, SSBS, 4, 4) FIELD(ID_AA64PFR1, MTE, 8, 4) FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) +FIELD(ID_AA64PFR1, SME, 24, 4) +FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) +FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) +FIELD(ID_AA64PFR1, NMI, 36, 4) =20 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) @@ -2033,6 +2048,11 @@ FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) FIELD(ID_AA64MMFR1, XNX, 28, 4) FIELD(ID_AA64MMFR1, TWED, 32, 4) FIELD(ID_AA64MMFR1, ETS, 36, 4) +FIELD(ID_AA64MMFR1, HCX, 40, 4) +FIELD(ID_AA64MMFR1, AFP, 44, 4) +FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) +FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) +FIELD(ID_AA64MMFR1, CMOW, 56, 4) =20 FIELD(ID_AA64MMFR2, CNP, 0, 4) FIELD(ID_AA64MMFR2, UAO, 4, 4) @@ -2059,7 +2079,10 @@ FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) FIELD(ID_AA64DFR0, PMSVER, 32, 4) FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) +FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) FIELD(ID_AA64DFR0, MTPMU, 48, 4) +FIELD(ID_AA64DFR0, BRBE, 52, 4) +FIELD(ID_AA64DFR0, HPMN0, 60, 4) =20 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) FIELD(ID_AA64ZFR0, AES, 4, 4) @@ -2081,6 +2104,7 @@ FIELD(ID_DFR0, PERFMON, 24, 4) FIELD(ID_DFR0, TRACEFILT, 28, 4) =20 FIELD(ID_DFR1, MTPMU, 0, 4) +FIELD(ID_DFR1, HPMN0, 4, 4) =20 FIELD(DBGDIDR, SE_IMP, 12, 1) FIELD(DBGDIDR, NSUHD_IMP, 14, 1) --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650217747; cv=none; d=zohomail.com; s=zohoarc; b=OBW47tt7RiOhibTfgZ+/nAkYCsEKnlO2g2CBotXlZsB8CAyjRFRTT9HL8JV0ool8VGXbFmX1PcKNspdgB1lzyWmbZWa89TXtEQegYoK2Xjtd+yjRLDbBwXlrqF1T7EH3Nt17IBMYIo5f9RSl0s3HIbhiOQcorjHJMWfpYB0/MD8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650217747; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ctao6OM4nQH5DOtD+RHJ8jgaq6PvH+d/+VQiChfQs3Y=; b=BM2Ch3RSBnjh1MT6FddzLtyr/0LI/uJzC+GoLiKhcf7AjquUp03KhbGJvwSYevHfXSdrMlcQVsesflrO7wqyU98A+j/x490FezT801/o4aMBtlxCaeZ8gCb6Kz0gyMh0zH97GmuXC8Yr/Z/72KqOjTBFHmwJaOjbkVLGQVRRnLQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650217747759808.298711629632; Sun, 17 Apr 2022 10:49:07 -0700 (PDT) Received: from localhost ([::1]:59590 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng91F-0003wU-RF for importer@patchew.org; Sun, 17 Apr 2022 13:49:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47682) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng8wt-0000dn-7N for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:35 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]:38743) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng8wr-0003FC-I5 for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:34 -0400 Received: by mail-pj1-x1032.google.com with SMTP id s14-20020a17090a880e00b001caaf6d3dd1so15524693pjn.3 for ; Sun, 17 Apr 2022 10:44:33 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ctao6OM4nQH5DOtD+RHJ8jgaq6PvH+d/+VQiChfQs3Y=; b=lPQNaZrQHa0wXcZD1iwewNJ4tDzIuJ8474HPRZrXy6sg1jWo2CKRLueZPtSHYBTPRm yX865H9BIQnUIvQKPo8N2qWllwYQd2YA64+bM+Dfg1qEKGdH7x+JX/2zca4M658Gc2tu EMj6yZrUDai1QQq9iqjatgkBFNADbJwUheVk5abunrEU6w80OUZkQzYdYMbbkYgXA2Ex mzLB4Ugbab7FRIO1McRcuNE5IEfxhCM3bmKJ6Ahqct0/Hf48yP5X88KbtPM8KElA7BxT +TwI7qyijSUb0S+OQDOjQKoYoPDl0P0zXrFZWGvE+9FDaaw0Tsm0HHIz7DX2tfO7Sr6s iQhA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ctao6OM4nQH5DOtD+RHJ8jgaq6PvH+d/+VQiChfQs3Y=; b=n2ylR4WwDu9T+1PIKEI+yNmpu/wtZRJge3zIU0NyJBh+pKbOhpvgxFdlSEaweV1q7v U2ejIy86gTtw3NIy9I9Im6R2tQ3aMOHfyPprDSJ5KGP+Xv7U+PHuM9TewCU74fULLqfk kdn1EuvOUUt0d2dFvl/jUfn9uUiYj92lsd3FsbbsJQmupKSQ7eSPjTEbNskJnKzt5tO5 OadKYvMws2mElGuYxITPudk844uEj0itZfwv5Fio/ZfCkYRh0rFYVOHbrlQbJ1TaBhQ5 Tp7DKlVzSu5CeRB4cCdRrqY6y27AmOUGqxfqSAIKeAoU8VOBfa2jQwFYPZJFdCl0ynGk +p1Q== X-Gm-Message-State: AOAM532V48LRWow+PnGCWrDS/9wfPVYTIJIaDDeui+JO423oCrmvX7jM y7gDhaJAMfZxOmdweBnOI01mjiiHFVf7Zg== X-Google-Smtp-Source: ABdhPJzZRZcsNlwG3xHoI9WV0KYVhpikFi8jLrpEEy91Hrz765UwRX1qXfA+pKbFSeBABUJvUbn7+A== X-Received: by 2002:a17:90b:4d01:b0:1d0:f39f:6073 with SMTP id mw1-20020a17090b4d0100b001d0f39f6073mr9068144pjb.175.1650217472216; Sun, 17 Apr 2022 10:44:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 03/60] target/arm: Update SCR_EL3 bits to ARMv8.8 Date: Sun, 17 Apr 2022 10:43:29 -0700 Message-Id: <20220417174426.711829-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650217748460100001 Content-Type: text/plain; charset="utf-8" Update SCR_EL3 fields per ARM DDI0487 H.a. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9a29a4a215..f843c62c83 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1544,6 +1544,18 @@ static inline void xpsr_write(CPUARMState *env, uint= 32_t val, uint32_t mask) #define SCR_FIEN (1U << 21) #define SCR_ENSCXT (1U << 25) #define SCR_ATA (1U << 26) +#define SCR_FGTEN (1U << 27) +#define SCR_ECVEN (1U << 28) +#define SCR_TWEDEN (1U << 29) +#define SCR_TWEDEL MAKE_64BIT_MASK(30, 4) +#define SCR_TME (1ULL << 34) +#define SCR_AMVOFFEN (1ULL << 35) +#define SCR_ENAS0 (1ULL << 36) +#define SCR_ADEN (1ULL << 37) +#define SCR_HXEN (1ULL << 38) +#define SCR_TRNDR (1ULL << 40) +#define SCR_ENTP2 (1ULL << 41) +#define SCR_GPF (1ULL << 48) =20 #define HSTR_TTEE (1 << 16) #define HSTR_TJDBX (1 << 17) --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650218007; cv=none; d=zohomail.com; s=zohoarc; b=LdwiEflyN4DRErCvkWPqdCO5DbO8oN3ee9jnLFofGGjJM4GMHvU00S2yA2nP6jWDC8ecTcAHVMa3Vrt4vsWL1UG9DJIxVmRVVM8k8SQJeEYfDbMwe9jwZcQlJNzB7RcO3jPmI87jdwHgja1EE2u7BCFufEpOBSJt//TUhD3nmys= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650218007; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vxLFgR2+O/yEO8CWTOhGko5rMSYgERGzbB2hOUZT2qw=; b=UDbcF1bDkpnhwew+9JSbtgFmW3FcQBddBuGyhT13VrfLpkqiZKYgnRiTfMmKDz5KvxT5XSgRLwTOSj9zi+lNNfaiSnf6xmHC5D7x1mATojvaRDrPbvpjvgUyN9zFJOYeAzlAy5WZ+emYIe414QvQv+GrQyDqyAoiljvBUWiT5FU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650218007453205.89980929201715; Sun, 17 Apr 2022 10:53:27 -0700 (PDT) Received: from localhost ([::1]:42650 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng95S-0003ET-2X for importer@patchew.org; Sun, 17 Apr 2022 13:53:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47724) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng8wu-0000eP-70 for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:39 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:38745) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng8ws-0003Fj-Lt for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:35 -0400 Received: by mail-pj1-x1034.google.com with SMTP id s14-20020a17090a880e00b001caaf6d3dd1so15524710pjn.3 for ; Sun, 17 Apr 2022 10:44:33 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vxLFgR2+O/yEO8CWTOhGko5rMSYgERGzbB2hOUZT2qw=; b=DI2wNBxyNTHyxEmGRPu3vdwxS/laH9SsS+E2H6qdbjNXas4N9p99jvRv0GaJaJMqCJ 8n9osSuqzQnMuH91TtrbZq2/+hLJlBmd4ipexGdLwxPbLBIBnNBdiauOefPJcMMIAvYO 0u7+JqGV1Mm982Pmkw7gwVSXHMH1/DqKX953whZfxpSgwKUxSWlsWpMkjEDn7RdlqYaZ FBtarDC8e0BMwHf9v6vl4u56sZlHMfWszW1wFhAToFYV+GaEkIyrAEZKLOJJaRKjZ/ZP kK4MekSXaa1PNUtNp6wDSWdiGubCJ04KU4Chqe0OgbVO6/NZupWo4Ixzl6FIAbQKtuE7 P+Jg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vxLFgR2+O/yEO8CWTOhGko5rMSYgERGzbB2hOUZT2qw=; b=przrJ8xm+WJ28cmcU1MhwLzmyEg4agtcSsQCHcsDnvP8EqUDdX6tfVeHzBT9rOUsCZ iY/GIcOF0+gW3j4oRwdv265wbmuyVL2r1ItbfzxgNSsdjl7IqH0Yj7uzOpF7NDEX9OHd he+uaDpfXHNLC+5rhiHWGyvdgYgq9FYh7TxcHk7ncjLJeUil1WuWgqKPR3nsHCnX98PV BmbJgsd46M8yESB5GBEYf2IC+gi/7NbSr4eL/JIYcTFkAfUbM50q6Q2jPSYGsT4SWzVG ptDZRZQymlL6PDWEZ7EJi8k+C8OwgLfk3MAciz5UM+/keDuDlKIoPW6kEuArfnWiZZZW OPDQ== X-Gm-Message-State: AOAM530XTCo1q9FVDg0q5HYQR5OnakFpAJVCuFpHwJeExQXLC2N6kFX2 opmm5xbv7ZWKAJLN6OlhS0w8HDNZjMBP4w== X-Google-Smtp-Source: ABdhPJxvniTuUuh/Utr9BFNaoR+rydMo7iN3wi7zFARoTUekHeWlvKy1bi70PjLsjMsXRDK2zxsJMA== X-Received: by 2002:a17:90b:1a81:b0:1d2:63f5:e24e with SMTP id ng1-20020a17090b1a8100b001d263f5e24emr7088951pjb.124.1650217473013; Sun, 17 Apr 2022 10:44:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 04/60] target/arm: Update SCTLR bits to ARMv9.2 Date: Sun, 17 Apr 2022 10:43:30 -0700 Message-Id: <20220417174426.711829-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650218009000100005 Content-Type: text/plain; charset="utf-8" Update SCTLR_ELx fields per ARM DDI0487 H.a. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index f843c62c83..9ae9c935a2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1232,6 +1232,20 @@ void pmu_init(ARMCPU *cpu); #define SCTLR_ATA0 (1ULL << 42) /* v8.5-MemTag */ #define SCTLR_ATA (1ULL << 43) /* v8.5-MemTag */ #define SCTLR_DSSBS_64 (1ULL << 44) /* v8.5, AArch64 only */ +#define SCTLR_TWEDEn (1ULL << 45) /* FEAT_TWED */ +#define SCTLR_TWEDEL MAKE_64_MASK(46, 4) /* FEAT_TWED */ +#define SCTLR_TMT0 (1ULL << 50) /* FEAT_TME */ +#define SCTLR_TMT (1ULL << 51) /* FEAT_TME */ +#define SCTLR_TME0 (1ULL << 52) /* FEAT_TME */ +#define SCTLR_TME (1ULL << 53) /* FEAT_TME */ +#define SCTLR_EnASR (1ULL << 54) /* FEAT_LS64_V */ +#define SCTLR_EnAS0 (1ULL << 55) /* FEAT_LS64_ACCDATA */ +#define SCTLR_EnALS (1ULL << 56) /* FEAT_LS64 */ +#define SCTLR_EPAN (1ULL << 57) /* FEAT_PAN3 */ +#define SCTLR_EnTP2 (1ULL << 60) /* FEAT_SME */ +#define SCTLR_NMI (1ULL << 61) /* FEAT_NMI */ +#define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ +#define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ =20 #define CPTR_TCPAC (1U << 31) #define CPTR_TTA (1U << 20) --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650218249; cv=none; d=zohomail.com; s=zohoarc; b=L32uTuFfazCIa0qrE3lhmmsZkcnbxSq7mb0V5rgBMBcQ7jJM239KTJXd8D3EaCQU537Pnf7Ke7Dlza9gVFOMutwYX9Jq9SawuSayawgH5o3eTon2hNVCpsvCO8M3032BpHq31kAjTvuuTMKJ0ksrOPt+3G8eu/ex/uHYY3lk+b0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650218249; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QU3oeydO4deqKs71AOrHq4mL0RBHni0rDESBhTtVtZg=; b=GEqpQXBiK1hiBtjkpduqy7RZLvLn11TUHT02dNw4Uf+dHYtPimdwUx0AMIzSt4znzTWlMtCjyHAH9SrwXpgudGXbYy+tq1HXvbfPmNfbpKlxKEdlXpdx9BPmFyopp1Eu/pwvshlNnXkh01Fz4VxbBHSyEvhYmPjRpEvYjd7qqbk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650218249738417.52354231976244; Sun, 17 Apr 2022 10:57:29 -0700 (PDT) Received: from localhost ([::1]:51476 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng99M-0000pK-He for importer@patchew.org; Sun, 17 Apr 2022 13:57:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47744) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng8wu-0000eW-SZ for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:39 -0400 Received: from mail-pg1-x52c.google.com ([2607:f8b0:4864:20::52c]:44579) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng8wt-0003G1-7n for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:36 -0400 Received: by mail-pg1-x52c.google.com with SMTP id j71so1443550pge.11 for ; Sun, 17 Apr 2022 10:44:34 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QU3oeydO4deqKs71AOrHq4mL0RBHni0rDESBhTtVtZg=; b=QuHfkcAa45CVHNhWIt5J9EguM6s0DglhM2qCMAOia+jzJ5jEmbq/eZgmSZMXu+9Jcz evGbGUhTefzInCOFnHboL4DEIFTv1RUGO3o1lG+l5SYB29R2ikvOifJxIZuUbnq65sad PPxeIJKD0T19WIEoi6axKLrZS8cGM3JIYZ8QcfpFJYVoUTBTtoEjCWLHJAgyP5Hm5gFj li8G0ND1j/RVNoREFGSURvmPCFxuO4wUp08jOO7qLz2lFvB7F3Uli7KBdj8+8IzdFeze e929xuBSZAWfFrjvf15McWULdX/kfJWrVy5qUKXQiY39vxAn7Lfig0wczP5JEApAErX0 SK6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QU3oeydO4deqKs71AOrHq4mL0RBHni0rDESBhTtVtZg=; b=yPITRyyGRwpA26lHidiSuvsgk/X1O3X7nzaQMXSnN/zNK0s4DG+IPoKfRwtImSwie7 Gs4A3YKbtUBXr0mEYkha7g4w4yPTewbBPgRiM+GyfYtAMuycamqvQ2At5xGnZWkNztRp sTR90MdRYaUkqLhCGhbwDacoowftOtVw9soJmm4kroyEfm0KI/Ux0sBl8x8spAF8Ncf8 rmufcVy9T2arASZzxcQFeJs4glX6gpc8uciMUOiCBtUXnldXfmBCTitGRQnV7Z560KA0 v0hUckEM/0oFug6jnEP1t9bwZMapCPlFbf62tkQeoZLy6A4wea3FL/UUPqxvo3YEqatv nlmg== X-Gm-Message-State: AOAM532coOkSYYD+AoaHoyFAC/rnxYWaTpJTqkv7l9UtGif3/VXRgvwR uYlf59Az398YD79Mu9uogM32WQZHxcnzBQ== X-Google-Smtp-Source: ABdhPJyIUrhaNGX913yNF2s9iULMRmpnYJ34k60apYo3YK88J0WprPqzTLMQPNiRrwMA16BXajJHGA== X-Received: by 2002:a05:6a00:997:b0:506:1e25:435e with SMTP id u23-20020a056a00099700b005061e25435emr8268538pfg.9.1650217473977; Sun, 17 Apr 2022 10:44:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 05/60] target/arm: Change DisasContext.aarch64 to bool Date: Sun, 17 Apr 2022 10:43:31 -0700 Message-Id: <20220417174426.711829-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650218250183100001 Content-Type: text/plain; charset="utf-8" Bool is a more appropriate type for this value. Move the member down in the struct to keep the bool type members together and remove a hole. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/translate.h | 2 +- target/arm/translate-a64.c | 2 +- target/arm/translate.c | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 3a0db801d3..8b7dd1a4c0 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -59,12 +59,12 @@ typedef struct DisasContext { * so that top level loop can generate correct syndrome information. */ uint32_t svc_imm; - int aarch64; int current_el; /* Debug target exception level for single-step exceptions */ int debug_target_el; GHashTable *cp_regs; uint64_t features; /* CPU features bits */ + bool aarch64; /* Because unallocated encodings generate different exception syndrome * information from traps due to FP being disabled, we can't do a sing= le * "is fp access disabled" check at a high level in the decode tree. diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9333d7be41..4dad23db48 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14664,7 +14664,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, dc->isar =3D &arm_cpu->isar; dc->condjmp =3D 0; =20 - dc->aarch64 =3D 1; + dc->aarch64 =3D true; /* If we are coming from secure EL0 in a system with a 32-bit EL3, then * there is no secure EL1, so we route exceptions to EL3. */ diff --git a/target/arm/translate.c b/target/arm/translate.c index bf2196b9e2..480e58f49e 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9334,7 +9334,7 @@ static void arm_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) dc->isar =3D &cpu->isar; dc->condjmp =3D 0; =20 - dc->aarch64 =3D 0; + dc->aarch64 =3D false; /* If we are coming from secure EL0 in a system with a 32-bit EL3, then * there is no secure EL1, so we route exceptions to EL3. */ --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650218006; cv=none; d=zohomail.com; s=zohoarc; b=iqLS1AcNamZ1Cftt8gvl7QAzm47eh+2K1teea3NzliJx5wEOfmSmdM1JGcR0L9EEXxJI6oUpQ66arFfRQ78tT3n33+OrMukYZWg0ATEnf2YMZGfqzP9h/aIByArtKJrH+QPppyYY21o2Dh3884sMyGwxHes/3icN5MIFbJpDkiU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650218006; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4B9pthiRLfIf40OZcpcAQf7C9gNufiID5iESdzNE71c=; b=e5ON3VcVRnfnlOKJZdRz5M+KNTk/uO1OQ6v8a9yHaNszfgXsec41OuCPUpOwtb87bKGBlN9kTLSl9VMlbAsMTwiNx37fXEFpsNpjkjVK6VbdjwdPXOTf0vtAfs9mBzKA3RWtH7x/KHCvx3nksgt9/Hmdn/xRUZKAeqYfJcuH4dk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165021800605116.056387505481666; Sun, 17 Apr 2022 10:53:26 -0700 (PDT) Received: from localhost ([::1]:42624 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng95R-0003DJ-1h for importer@patchew.org; Sun, 17 Apr 2022 13:53:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47812) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng8wx-0000fI-J0 for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:41 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:40532) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng8wu-0003GR-Ku for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:37 -0400 Received: by mail-pj1-x102a.google.com with SMTP id md20-20020a17090b23d400b001cb70ef790dso15505987pjb.5 for ; Sun, 17 Apr 2022 10:44:35 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4B9pthiRLfIf40OZcpcAQf7C9gNufiID5iESdzNE71c=; b=VJE4sumENvnXSWQR9VW72B1CEU54og69sdChfbuItGbFzvfIOztws4fgfB1zp4r4nQ XI+74VB7pbvHnvY8uJed8/jkGhoc60Cf9SDU78fbLT/sTmrt0Pep0oBsE/kq4T8MK/BK 5PSbxELnwExO1ZrXwK+IhQhR77hk49TZJ+71la3YzVclPnfgwSu2ZQIvIOJlOFMwc4ii Ie6lN77wz3MVkLWmasezY7Fwp6bjbegJ7apvIPPNL+ikj9OPowiGVNr2DfZSIUNzUPoM Ar3VSGdgNelzCAp5KxnAXwFw6bMMk7YznGqGqBn+lGqNKtpPvXtC9Y4br30BFhs8AYPz 2nmQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4B9pthiRLfIf40OZcpcAQf7C9gNufiID5iESdzNE71c=; b=2vgD8uF5exH0Z3icXeL8fpFLjFHpzPLaAPMRDeS3fT58SorEgXScqkqtQWd7VsYSfN TKpj7Qno8t+aqyjXFvWfdxWcDZHB0/I3pIqcjgKcPi1phI5nlfSZ14TDmEkEjYpQuhDG MRK7TYlcw/95J9Q/8AgWsAQehQhDCpwpIjMVcyCuRRf+ZpLkb5g2CyvryuJCGRIQi76E ZwAJGhx4hJ+UICPTl6690TG0SGgUNtYFOIkktCKh8axroaluIs6IFXekogpt/h9PRe+D +EbgT3G4aS1ZtDFDHbqY5zhBKkyaPiGf9gucWl8IV2pRJZn0/E2jWkaLV6WoXQ5Rb9An UQtA== X-Gm-Message-State: AOAM531BBuoDRRNSuDVBJB1w5GnkphHdmMGKo/ys+TFwkQNZB9qyLQvy 2JiyDQTkaYx61QIo0lHn3izTbkEWddXBrw== X-Google-Smtp-Source: ABdhPJwll9/1ewGDKdNFt+N7xobpYeHRiL+vadJvaGY9EN2977zUdDrME9kFStRtQu1yCXFomdo6sQ== X-Received: by 2002:a17:90a:634b:b0:1ca:6c7e:7952 with SMTP id v11-20020a17090a634b00b001ca6c7e7952mr14230125pjs.54.1650217474868; Sun, 17 Apr 2022 10:44:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 06/60] target/arm: Change CPUArchState.aarch64 to bool Date: Sun, 17 Apr 2022 10:43:32 -0700 Message-Id: <20220417174426.711829-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650218007011100002 Content-Type: text/plain; charset="utf-8" Bool is a more appropriate type for this value. Adjust the assignments to use true/false. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e --- target/arm/cpu.h | 2 +- target/arm/cpu.c | 2 +- target/arm/helper-a64.c | 4 ++-- target/arm/helper.c | 2 +- target/arm/hvf/hvf.c | 2 +- 5 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9ae9c935a2..a61a52e2f6 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -258,7 +258,7 @@ typedef struct CPUArchState { * all other bits are stored in their correct places in env->pstate */ uint32_t pstate; - uint32_t aarch64; /* 1 if CPU is in aarch64 state; inverse of PSTATE.n= RW */ + bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nR= W */ =20 /* Cached TBFLAGS state. See below for which bits are included. */ CPUARMTBFlags hflags; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5d4ca7a227..30e0d16ad4 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -189,7 +189,7 @@ static void arm_cpu_reset(DeviceState *dev) =20 if (arm_feature(env, ARM_FEATURE_AARCH64)) { /* 64 bit CPUs always start in 64 bit mode */ - env->aarch64 =3D 1; + env->aarch64 =3D true; #if defined(CONFIG_USER_ONLY) env->pstate =3D PSTATE_MODE_EL0t; /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */ diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 7cf953b1e6..77a8502b6b 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -952,7 +952,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_= t new_pc) qemu_mutex_unlock_iothread(); =20 if (!return_to_aa64) { - env->aarch64 =3D 0; + env->aarch64 =3D false; /* We do a raw CPSR write because aarch64_sync_64_to_32() * will sort the register banks out for us, and we've already * caught all the bad-mode cases in el_from_spsr(). @@ -975,7 +975,7 @@ void HELPER(exception_return)(CPUARMState *env, uint64_= t new_pc) } else { int tbii; =20 - env->aarch64 =3D 1; + env->aarch64 =3D true; spsr &=3D aarch64_pstate_valid_mask(&env_archcpu(env)->isar); pstate_write(env, spsr); if (!arm_singlestep_active(env)) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 7d14650615..47fe790854 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10182,7 +10182,7 @@ static void arm_cpu_do_interrupt_aarch64(CPUState *= cs) } =20 pstate_write(env, PSTATE_DAIF | new_mode); - env->aarch64 =3D 1; + env->aarch64 =3D true; aarch64_restore_sp(env, new_el); helper_rebuild_hflags_a64(env, new_el); =20 diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 8c34f86792..11176ef252 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -565,7 +565,7 @@ int hvf_arch_init_vcpu(CPUState *cpu) hv_return_t ret; int i; =20 - env->aarch64 =3D 1; + env->aarch64 =3D true; asm volatile("mrs %0, cntfrq_el0" : "=3Dr"(arm_cpu->gt_cntfrq_hz)); =20 /* Allocate enough space for our sysreg sync */ --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650217813; cv=none; d=zohomail.com; s=zohoarc; b=VaH9nfXFijJMrSbZ39eTJhLllcvqgG7d/6SlGSgaNZUptjqzWt/sn919khsfRCn3l5+6Tpo3nTnLsjaZAZGQooX3xvs+TK9WKnXYZP531fkeQYAd82RUzEKdGIGhtDJP8Hpq+ONOYdh1qqQsty5ylYxDBFILNAd45wjDaIHJkIg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650217813; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=VFtB/E7djXDPURXg40lhRvaf5WnkYYoUZ27VyitKWXw=; b=hQmzkTQi+msXdZRLcKIcRVnMGvcthx4yepqcL6wRPG7qR1eVGbqi3gt8mX7AcQpsKEDlElqnLAvug4Fqxv+GpZHnRdsEH/b0X884GOQzxyF8KTU+mqZygf/S6oVDJEWIBIU2/eAVFT7SMkbHn6Mv3jAw/mSFoN/U1c9goP2ulWY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650217813408392.84882962713823; Sun, 17 Apr 2022 10:50:13 -0700 (PDT) Received: from localhost ([::1]:34048 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng92K-0005r8-EP for importer@patchew.org; Sun, 17 Apr 2022 13:50:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47816) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng8wx-0000fK-Kg for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:41 -0400 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:44654) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng8wv-0003Gs-2H for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:38 -0400 Received: by mail-pj1-x102c.google.com with SMTP id u5-20020a17090a6a8500b001d0b95031ebso5272257pjj.3 for ; Sun, 17 Apr 2022 10:44:36 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VFtB/E7djXDPURXg40lhRvaf5WnkYYoUZ27VyitKWXw=; b=BiNO/Tsd5nN/K0y5UIKpidCYPek4TbeIB8m1MQZe9XMma39xFN2au6Vu3xS3MgjYiA aFuhzEWNFoh+jH501BEzLj+moRqLSG21PZAmpaItbrEWLbHORUsf5jJx9fRCObdtCvq8 AOGwC1pQEzRVFsS7fyDQXPRBcqqOCqQP7mvXiqgztW+1I4UuZl0mfWm6fdZwZH54N1wZ YY1UdaD55HP9sIbvwugNJUX5hfYXic/YFjGCIE1aEispWSD0d288zMo6am70kIzVcBI5 X/hLQZAufGsxDf4+XY9up7PVuUeyupHHRFdgK+pH8fd9yk2KJOHbWuy+1z5FK+3FoNrs 4gqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VFtB/E7djXDPURXg40lhRvaf5WnkYYoUZ27VyitKWXw=; b=ORd/gmMWNFvjA59/PSRBmA9bZbW4qpibNhu/rBGfAgp7Ak/VnC3lPVKGsGtjva6zA6 xnUKHyg2vGOHUDPFOojqz25Iv5y2FOo9Xiz8qeiyvHmEBfmV8tR1MwsjoCTJ3DnXwkgg a+n3F61QIEMeFS2T+TgWJytToPFaoQRT11mMA5ndRX2MtFWCQewL5X7JFv9rFeoLtvfZ ZexJ4+bulwypBIWWG5wmAUH+SPYipQpsfPCPtITqF9199MqWkM3PwKBsSmbWlZRNxzD1 8wJjt9JNCUeMLKNV2KcHAN3z7qn4d2XOEq0Ga0dyUgWTsICSqV/kOw7NyH7GLVu46H7u CboA== X-Gm-Message-State: AOAM530/Gh4+q6rO2xk0lZESNk1M0x1sW6K0kBaCxxcoujSr8LQ+XzNF nFdAsLVhvw0F3peUa1lrP8RO1UiAiRxGLg== X-Google-Smtp-Source: ABdhPJwviKhxBqWh8q83DmT9sI4b6YBl+zVaAVLaFlzhKplJuNlwiNzhkC2rsMxdpf5oFqo0xd8TQg== X-Received: by 2002:a17:90b:218d:b0:1d0:90f5:4064 with SMTP id ku13-20020a17090b218d00b001d090f54064mr9222138pjb.95.1650217475781; Sun, 17 Apr 2022 10:44:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 07/60] target/arm: Extend store_cpu_offset to take field size Date: Sun, 17 Apr 2022 10:43:33 -0700 Message-Id: <20220417174426.711829-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650217814266100002 Content-Type: text/plain; charset="utf-8" Currently we assume all fields are 32-bit. Prepare for fields of a single byte, using sizeof. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell --- target/arm/translate-a32.h | 13 +++++-------- target/arm/translate.c | 21 ++++++++++++++++++++- 2 files changed, 25 insertions(+), 9 deletions(-) diff --git a/target/arm/translate-a32.h b/target/arm/translate-a32.h index 5be4b9b834..f593740a88 100644 --- a/target/arm/translate-a32.h +++ b/target/arm/translate-a32.h @@ -61,17 +61,14 @@ static inline TCGv_i32 load_cpu_offset(int offset) =20 #define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name)) =20 -static inline void store_cpu_offset(TCGv_i32 var, int offset) -{ - tcg_gen_st_i32(var, cpu_env, offset); - tcg_temp_free_i32(var); -} +void store_cpu_offset(TCGv_i32 var, int offset, int size); =20 -#define store_cpu_field(var, name) \ - store_cpu_offset(var, offsetof(CPUARMState, name)) +#define store_cpu_field(var, name) \ + store_cpu_offset(var, offsetof(CPUARMState, name), \ + sizeof(((CPUARMState *)NULL)->name)) =20 #define store_cpu_field_constant(val, name) \ - tcg_gen_st_i32(tcg_constant_i32(val), cpu_env, offsetof(CPUARMState, n= ame)) + store_cpu_field(tcg_constant_i32(val), name) =20 /* Create a new temporary and set it to the value of a CPU register. */ static inline TCGv_i32 load_reg(DisasContext *s, int reg) diff --git a/target/arm/translate.c b/target/arm/translate.c index 480e58f49e..c745b7fc91 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -180,6 +180,25 @@ typedef enum ISSInfo { ISSIs16Bit =3D (1 << 8), } ISSInfo; =20 +/* + * Store var into env + offset to a member with size bytes. + * Free var after use. + */ +void store_cpu_offset(TCGv_i32 var, int offset, int size) +{ + switch (size) { + case 1: + tcg_gen_st8_i32(var, cpu_env, offset); + break; + case 4: + tcg_gen_st_i32(var, cpu_env, offset); + break; + default: + g_assert_not_reached(); + } + tcg_temp_free_i32(var); +} + /* Save the syndrome information for a Data Abort */ static void disas_set_da_iss(DisasContext *s, MemOp memop, ISSInfo issinfo) { @@ -4852,7 +4871,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, tcg_temp_free_i32(tmp); } else { TCGv_i32 tmp =3D load_reg(s, rt); - store_cpu_offset(tmp, ri->fieldoffset); + store_cpu_offset(tmp, ri->fieldoffset, 4); } } } --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650218290; cv=none; d=zohomail.com; s=zohoarc; b=TsUnZHGsa4qM4QFU3I6IdlsNJN7q74o/dBjbuW8S1gLBD0YCLhlTXM/S+6Fy8rY+PbzzoPXRBJCnRBIUTKjUcEsHrRrNo2oyT2AySM5nNj6XhxPOJWdvAGhS8R1hgyFmt2OinDaYDiXsx273REBIT9+DrZOLhvJkXiAE6MzKIT0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650218290; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RxLRcUMRXZIX8VeQpjedlgnjJfO7UvkrNmgRZi4O4+0=; b=cxtlp/Tkp9GmjVQRtscuQVsT6JOvioIya5aDa8jPg0QRQRJz5u00lqbWbgVXWyCfhofTYphUqgV33KSXQLpBlaIMtMb2ZAWLuNMGGr5aSFMzWT7tx5u78MyptgvE3txJHDIohA/Bo58XetrCvEFTc/Xu9cY0DPE38UuvurH+ql8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650218290509747.1816790704042; Sun, 17 Apr 2022 10:58:10 -0700 (PDT) Received: from localhost ([::1]:52652 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9A1-0001bB-Ek for importer@patchew.org; Sun, 17 Apr 2022 13:58:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47860) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng8wy-0000fU-Qj for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:41 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]:44583) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng8wv-0003H9-Sl for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:40 -0400 Received: by mail-pg1-x530.google.com with SMTP id j71so1443664pge.11 for ; Sun, 17 Apr 2022 10:44:37 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RxLRcUMRXZIX8VeQpjedlgnjJfO7UvkrNmgRZi4O4+0=; b=KdLM8h1JGtzeZuX9glkjRthvPMUmMwW7CNEQ/sKHmk5U8L+Lptw5Cj5sJvm/W0qu6Y 1aQIDVX487Smbz7Tqsw/pP7DR4DmpUh4cvKjVuXnB9TWKHf3iQnK65l14jjz4yljw59B RF1ySx5Gb3CLSsWlepjHm0JeiezwKG7brMkVw1TuawQMvI2GoqEOm4pJKLpjuCbnGbg9 hXHKQNxfxSAJgr7AjVn1jMncJK1hFKLIMktb4ZtuIPfppky6hwDFivDupaEglnz44f5c RXCYzPzhN+brwePv6ln/I1dLX/8Fn4LEGJ4GWODZ/PTOvHHvhX0bZA7k0Zcfb0b6yT18 35TA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RxLRcUMRXZIX8VeQpjedlgnjJfO7UvkrNmgRZi4O4+0=; b=4oZ9pkXMJjlehQ1HTsbVckC6mdrZr0tx86zmKQPsIdCVHGWhpRpv5PIg0Ko7SoTwbM ++axaJ+cfnU+b7nCz+oPI247pit2muvb4U1m104puFyzZNiZTqw4ORQ/Rjg4xFOBnNJl clDW61TsbooUfvm5orhM/dFmAYx1WZhCOt6u4R13RMUpSULjefaywgdeDStDYkA5NKG0 XdqLt2AariWWj0FioeLaGKBc6bHyZKCa1eITIlVxkAC/BGakivKxcarrGQlQFt0s/3Hh t4LGjsDqf0HW3ybRfho5PQPgmwYHkwnk+MaM8aCAHbMSenX2y4MO6Bos38GXW6YRxQ86 FCxQ== X-Gm-Message-State: AOAM5320eNbb5p7KjtXXWpe5riVbabuN7XtuTSr6TTmbT8AmziUV7My0 IHedV/5tPMuDfHQgHL6P6bgfrmsGrt7IAg== X-Google-Smtp-Source: ABdhPJwVhj1ZYuQygR/efqLh80XvFEaPDxzU7OvdsZGapHWLZcCuABZt+X84fqo/E2pW/7W0zcT+Ew== X-Received: by 2002:aa7:920b:0:b0:505:66a5:3029 with SMTP id 11-20020aa7920b000000b0050566a53029mr8313795pfo.40.1650217476615; Sun, 17 Apr 2022 10:44:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 08/60] target/arm: Change DisasContext.thumb to bool Date: Sun, 17 Apr 2022 10:43:34 -0700 Message-Id: <20220417174426.711829-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650218292157100003 Content-Type: text/plain; charset="utf-8" Bool is a more appropriate type for this value. Move the member down in the struct to keep the bool type members together and remove a hole. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell --- target/arm/translate.h | 2 +- target/arm/translate-a64.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 8b7dd1a4c0..050d80f6f9 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -30,7 +30,6 @@ typedef struct DisasContext { bool eci_handled; /* TCG op to rewind to if this turns out to be an invalid ECI state */ TCGOp *insn_eci_rewind; - int thumb; int sctlr_b; MemOp be_data; #if !defined(CONFIG_USER_ONLY) @@ -65,6 +64,7 @@ typedef struct DisasContext { GHashTable *cp_regs; uint64_t features; /* CPU features bits */ bool aarch64; + bool thumb; /* Because unallocated encodings generate different exception syndrome * information from traps due to FP being disabled, we can't do a sing= le * "is fp access disabled" check at a high level in the decode tree. diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 4dad23db48..be7283b966 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -14670,7 +14670,7 @@ static void aarch64_tr_init_disas_context(DisasCont= extBase *dcbase, */ dc->secure_routed_to_el3 =3D arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3); - dc->thumb =3D 0; + dc->thumb =3D false; dc->sctlr_b =3D 0; dc->be_data =3D EX_TBFLAG_ANY(tb_flags, BE_DATA) ? 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=28ulwBk/DdHKOhHfzeHCOUU8iGC2wvWNCEyLXBlgf/g=; b=JAj8bIiAgO5uzz4Oe7l6bjlADn4o1Vg69i2QGlT6tTEESbK2OvQj0MnybKY8D2Cueu 1ZwlHh3eDqwI3DmWLxOCZODdIknmUVWVaCJ0J8CVER5YBmY3OU2W6pZxCj3x74+Ha0sr vsNYCAHIUrZradqz33jQEAdKI2001/xqhGJ/MVnd3Wq3CDGt81iI+25K9fnRU7FYRMFB lY/PL7cJO6jyrgYTAXqHfctZpiBdNNp+VyQf9FEsGpXnJsFA1gGYpTDR0ELQ6nnuwhNe dNW9Pt2tY8g4XXPN5OlaEQ1SUCeTytlvf8TbLp47OyXgpt6ChGWv3TjOPtOCiSEFr9Ot G97w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=28ulwBk/DdHKOhHfzeHCOUU8iGC2wvWNCEyLXBlgf/g=; b=BNMOZMknVYIz4s2XFUQ3A/SqQn2OmRSfDXLEMh9DfAFN33PHkzegQKkv42kprBR4aS diFCSWxoLHi1gI3zHHNfgZgtMLlEZLQ0vvwhS/I09kq+8Xoap+5ctlb6WyiW3FXQc9gk BOc01oa9yrvjgySw4/tHsCx18Sc6+Vn6711TPUIKrXdFJaWjHLZSNYYbOV4uuSCbzNnK 9z4z/YvgJocCMTePDtJprIFJxf1y8w1ylc9ZvLkMHlT1i/gF54MZ/2l8aKOHBBbMtdpA 8UpFodqNeb9rAFUY53SEYJwdEuaQgeuxYliYb3woKjk8mlRDlaO77h5HBBaoqxjYm/uK 0t6w== X-Gm-Message-State: AOAM53121C8Ke55OwRwf4LmY9d5LKyry5soYf99WvA4SkB7XwprRt5jp xNoEiQV9or5faJkt5OBhNCDeZ92xfFhlLg== X-Google-Smtp-Source: ABdhPJwXPF47FuVlVKGf2CpbPZmCHTt3kiBHIeaAb3nVEjpawCc6tWQ5rKIh5sx2pXBXSjOWEJh/Kg== X-Received: by 2002:a17:90a:5902:b0:1cb:a0eb:8f8c with SMTP id k2-20020a17090a590200b001cba0eb8f8cmr8955487pji.17.1650217477378; Sun, 17 Apr 2022 10:44:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 09/60] target/arm: Change CPUArchState.thumb to bool Date: Sun, 17 Apr 2022 10:43:35 -0700 Message-Id: <20220417174426.711829-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650218007006100001 Content-Type: text/plain; charset="utf-8" Bool is a more appropriate type for this value. Adjust the assignments to use true/false. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 2 +- linux-user/arm/cpu_loop.c | 2 +- target/arm/cpu.c | 2 +- target/arm/m_helper.c | 6 +++--- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a61a52e2f6..4eb378ede2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -259,6 +259,7 @@ typedef struct CPUArchState { */ uint32_t pstate; bool aarch64; /* True if CPU is in aarch64 state; inverse of PSTATE.nR= W */ + bool thumb; /* True if CPU is in thumb mode; cpsr[5] */ =20 /* Cached TBFLAGS state. See below for which bits are included. */ CPUARMTBFlags hflags; @@ -285,7 +286,6 @@ typedef struct CPUArchState { uint32_t ZF; /* Z set if zero. */ uint32_t QF; /* 0 or 1 */ uint32_t GE; /* cpsr[19:16] */ - uint32_t thumb; /* cpsr[5]. 0 =3D arm mode, 1 =3D thumb mode. */ uint32_t condexec_bits; /* IT bits. cpsr[15:10,26:25]. */ uint32_t btype; /* BTI branch type. spsr[11:10]. */ uint64_t daif; /* exception masks, in the bits they are in PSTATE */ diff --git a/linux-user/arm/cpu_loop.c b/linux-user/arm/cpu_loop.c index aae375d617..2979109f92 100644 --- a/linux-user/arm/cpu_loop.c +++ b/linux-user/arm/cpu_loop.c @@ -231,7 +231,7 @@ do_kernel_trap(CPUARMState *env) /* Jump back to the caller. */ addr =3D env->regs[14]; if (addr & 1) { - env->thumb =3D 1; + env->thumb =3D true; addr &=3D ~1; } env->regs[15] =3D addr; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 30e0d16ad4..561f180067 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -51,7 +51,7 @@ static void arm_cpu_set_pc(CPUState *cs, vaddr value) =20 if (is_a64(env)) { env->pc =3D value; - env->thumb =3D 0; + env->thumb =3D false; } else { env->regs[15] =3D value & ~1; env->thumb =3D value & 1; diff --git a/target/arm/m_helper.c b/target/arm/m_helper.c index b7a0fe0114..a740c3e160 100644 --- a/target/arm/m_helper.c +++ b/target/arm/m_helper.c @@ -564,7 +564,7 @@ void HELPER(v7m_bxns)(CPUARMState *env, uint32_t dest) env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_SFPA_MASK; } switch_v7m_security_state(env, dest & 1); - env->thumb =3D 1; + env->thumb =3D true; env->regs[15] =3D dest & ~1; arm_rebuild_hflags(env); } @@ -590,7 +590,7 @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) * except that the low bit doesn't indicate Thumb/not. */ env->regs[14] =3D nextinst; - env->thumb =3D 1; + env->thumb =3D true; env->regs[15] =3D dest & ~1; return; } @@ -626,7 +626,7 @@ void HELPER(v7m_blxns)(CPUARMState *env, uint32_t dest) } env->v7m.control[M_REG_S] &=3D ~R_V7M_CONTROL_SFPA_MASK; switch_v7m_security_state(env, 0); - env->thumb =3D 1; + env->thumb =3D true; env->regs[15] =3D dest; arm_rebuild_hflags(env); } --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650218658; cv=none; d=zohomail.com; s=zohoarc; b=c3mq7GnT3TjEkCy3UAhASA3eXBzmPZG8OcEQIBk/TsJnEvDYS0cXHXlZYQQR0Beh2ZRY8yUA6Q3xQyF6m7NJZTijc5bEaF6rfG/p00uQMn+1gcMtffk8FkbpZTlvFTJC8gPSXAztOyEFqnpka7Z8OPp12yjYkW30HzgiZcAbfmw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650218658; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vIjgH0QxYeAMP4DzJu3i3Y0UtqyUSNTOLfLjsYFO5vU=; b=LFCBjI/LGPBfRFqtGlOWFnPoFeiT3FxD1mTVuhGEQ67D1JVpM5ofEQHq0GqzZJXtG+MLWXN5tnhcLIqk18wR0ePU2oZp6sRFiHtxRkLQdZBtFv6oIdM0bvLuZSupQyCXex2TR8IS8zSbsYqu8vlu0s3eXjGy/pVTeLsALSiBRY0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650218658839220.22598283232162; Sun, 17 Apr 2022 11:04:18 -0700 (PDT) Received: from localhost ([::1]:41544 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9Fx-0004iL-PE for importer@patchew.org; Sun, 17 Apr 2022 14:04:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47926) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng8x0-0000fb-AS for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:43 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]:33601) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng8wx-0003Hb-IO for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:42 -0400 Received: by mail-pg1-x534.google.com with SMTP id k14so14986489pga.0 for ; Sun, 17 Apr 2022 10:44:39 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vIjgH0QxYeAMP4DzJu3i3Y0UtqyUSNTOLfLjsYFO5vU=; b=PDXnRxqpB6Ja5X6pHmUS58KPdyU9sgvY3ljJ1wuYioD3iMjqxhl1US2Siw/MnLHRmm KDWsbWAByfc0AtQ2C1aieJm4zbxOClH7c6OOt2y8hBoeuNI0AlJT/MJEn8NEJFcBBfYB ao0RyFRr/Tp/D12Gw1gAw51lT/yp25XR4606YZEPIGyqoW01/vRbTW5JF2PywahmTWy5 J4WKLJ1XfO6g5nR1YCgSllkqelxOc+f/5xBnc1e1RBLHICicd0oyHooWbfI+COkEDmyX mfhDYthyZ8dYoZmEEHM/HOnYha9srcbSTxv5tRCM6PP+BS91cz7u9OhO+jtZcxEUl280 NJjw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vIjgH0QxYeAMP4DzJu3i3Y0UtqyUSNTOLfLjsYFO5vU=; b=k2eDWJM8M6UHwvqZTclmRKPqOQ+viX2RmHSF+RUwB4QmrFODSarlsqeFoLOs0Itjd9 dMTMnfLaWpHF4jWHLW4S4WqYFyYKXzvc7zNFoaQiCsPjdoLF1xEzzood9SK2mmXRtJkV GCVqUvz/TD2FVsLzxQ6GRadb3cRVoHBGkdR0XBwco6LYLGy1U4AjNW0fY1rFk86ZwtP4 yi96sT0GjKplDEwZSEMzWtdo3GMGjCNKa3V4cVS8njogtHBJpMl+In7LnHgPD6XfVdCy faRlFaP2IdOyoH+tYVU87sSbKP4GW0rtJcqFUfdt5/ICYTqRweRoK8MrpzVDQ2GKY8G/ dWdw== X-Gm-Message-State: AOAM5302+/e2mD5OOw8hNGbaLv/830O9/QJtdDuonu3Y+KAwgilpzaFW CpCiKepUBJkjf3SCJzgBD3UbgPdLTDg5sw== X-Google-Smtp-Source: ABdhPJyUrP1Buc94SOsJh37YYwb2NT31te6I54Ssx353atCZr66Wt70n3K1wgtbc9Ahyl4JgQeOwDA== X-Received: by 2002:a63:4f43:0:b0:39d:96ff:838c with SMTP id p3-20020a634f43000000b0039d96ff838cmr6937937pgl.115.1650217478256; Sun, 17 Apr 2022 10:44:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 10/60] target/arm: Remove fpexc32_access Date: Sun, 17 Apr 2022 10:43:36 -0700 Message-Id: <20220417174426.711829-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650218659593100001 Content-Type: text/plain; charset="utf-8" This function is incorrect in that it does not properly consider CPTR_EL2.FPEN. We've already got another mechanism for raising an FPU access trap: ARM_CP_FPU, so use that instead. Remove CP_ACCESS_TRAP_FP_EL{2,3}, which becomes unused. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 5 ----- target/arm/helper.c | 17 ++--------------- target/arm/op_helper.c | 13 ------------- 3 files changed, 2 insertions(+), 33 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 4eb378ede2..e7f669d0a9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2806,11 +2806,6 @@ typedef enum CPAccessResult { /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ CP_ACCESS_TRAP_UNCATEGORIZED_EL2 =3D 5, CP_ACCESS_TRAP_UNCATEGORIZED_EL3 =3D 6, - /* Access fails and results in an exception syndrome for an FP access, - * trapped directly to EL2 or EL3 - */ - CP_ACCESS_TRAP_FP_EL2 =3D 7, - CP_ACCESS_TRAP_FP_EL3 =3D 8, } CPAccessResult; =20 /* Access functions for coprocessor registers. These cannot fail and diff --git a/target/arm/helper.c b/target/arm/helper.c index 47fe790854..60d9233b7e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4785,18 +4785,6 @@ static void sctlr_write(CPUARMState *env, const ARMC= PRegInfo *ri, } } =20 -static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo = *ri, - bool isread) -{ - if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) =3D=3D 2)= { - return CP_ACCESS_TRAP_FP_EL2; - } - if (env->cp15.cptr_el[3] & CPTR_TFP) { - return CP_ACCESS_TRAP_FP_EL3; - } - return CP_ACCESS_OK; -} - static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -5098,9 +5086,8 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .access =3D PL1_RW, .readfn =3D spsel_read, .writefn =3D spsel_write= }, { .name =3D "FPEXC32_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 3, .opc2 =3D 0, - .type =3D ARM_CP_ALIAS, - .fieldoffset =3D offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]), - .access =3D PL2_RW, .accessfn =3D fpexc32_access }, + .access =3D PL2_RW, .type =3D ARM_CP_ALIAS | ARM_CP_FPU, + .fieldoffset =3D offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) }, { .name =3D "DACR32_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 3, .crm =3D 0, .opc2 =3D 0, .access =3D PL2_RW, .resetvalue =3D 0, diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 70b42b55fd..2b87e8808b 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -691,19 +691,6 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, voi= d *rip, uint32_t syndrome, target_el =3D 3; syndrome =3D syn_uncategorized(); break; - case CP_ACCESS_TRAP_FP_EL2: - target_el =3D 2; - /* Since we are an implementation that takes exceptions on a trapp= ed - * conditional insn only if the insn has passed its condition code - * check, we take the IMPDEF choice to always report CV=3D1 COND= =3D0xe - * (which is also the required value for AArch64 traps). - */ - syndrome =3D syn_fp_access_trap(1, 0xe, false); - break; - case CP_ACCESS_TRAP_FP_EL3: - target_el =3D 3; - syndrome =3D syn_fp_access_trap(1, 0xe, false); - break; default: g_assert_not_reached(); } --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650218503; cv=none; d=zohomail.com; s=zohoarc; b=KEP/t1DjWLQsCbXRLuYEKwlgDW53JDNTRYpEPtPlcSq4/FIUakqMLuW6TwxRDVHWeBOJKGxv3oWXwIR/9Z4Si50mFSJpgYsmyL+MaiUhOXFOGrHJ5EdfEyRRqFWtEL6FvjIFML8aACpoeAyP6drvNymqlu+3bRGHsAvOWPjijqo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650218503; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=MiWeWkecp06NuqnvJcQe+4MeVb3lXXDHi5qwkM/XVaM=; b=MladSijRutnP/CQp6azgQRLlV8L3tMEDwWxOmYFIZPHZSqDxZw4lf49AnauAPOjDbh1qk+5LFs1L9w1ni7oqGCEbiada3rrTbaOVbhcA4AlZtWLWpL7idj+nMFEsd2aKPNnJznsiy1n2h/l41l8+fL4y4AoNrACGXCMANwdnoUA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16502185039311015.3702557067919; Sun, 17 Apr 2022 11:01:43 -0700 (PDT) Received: from localhost ([::1]:33054 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9DS-0007S3-JQ for importer@patchew.org; Sun, 17 Apr 2022 14:01:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47918) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng8x0-0000fY-4I for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:43 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]:33603) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng8wy-0003Hx-D6 for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:41 -0400 Received: by mail-pg1-x536.google.com with SMTP id k14so14986518pga.0 for ; Sun, 17 Apr 2022 10:44:40 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MiWeWkecp06NuqnvJcQe+4MeVb3lXXDHi5qwkM/XVaM=; b=B20sxyvpNez0Dj4y1gXoZcPlKJOklmmL98rVxx52/lIffU2syKDPNWTYTn1V5eNvoI 1BvR+zNmREQIXGN8NHFFPGhVSMW9A22KtqBcbPWvJtM6O2KqhgBTNwEFXQEDDlKbzQu0 3YmA8XB6I1Oxydq4f7zBJynmBUyCu1QIT+nh2eAyLuwBGPiL+GDuqljuYrjfruf6AbIO NQovIcO7noSyD6t61CDTie0lWOogauqxNaNJgFjBWUn1u1tD3hiuQsSYVEePLU9OZOVs sXgnKnK9J29WNXVaoLU7vwsMxF7WfFuqO/e6mwIP+DoHdpM5q6l269EUXgaEtlYNrhnO baBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MiWeWkecp06NuqnvJcQe+4MeVb3lXXDHi5qwkM/XVaM=; b=SSzQKzkAQGaHwo1GL/JO+xKx6EEPOx09FfD5CpoxlrFmac/r0sri62+fj5bGEZAyAK 6JiTKT6w1BNfVBanDXBanORowHzyQnURPDJbFpU3TklVbSTai38NpATTpd6a5mRoOLwU yLudje99QCe1nitEYoaMaC7xWF6+VV/CTt6niJJR9zdo/sBoIaV3qQLYtP+yPl/1hFMp T4bM30V1Vala9pzivmtdzsUYm7rpsOqwItQwthH+JKmGO7L1CQpxy5nwM2T7C/HFtFR9 qfb99MWjdv/FU2AN7vbwrCla54eOk/NJ8FRw8Cfl0NaHrR3L5yLZhooNqE/xxnu2UMfC pwFw== X-Gm-Message-State: AOAM531RxCK955e5NFsDepswrixNeLtAqyazTH6Ndy9pKuYkM1XFJ1ua JmHnNHvEi214iy0NvMCOowZ2aOGsAcl5ow== X-Google-Smtp-Source: ABdhPJyLFLMB1a5HTg6RqbJO0EtSNNPNlxQ+N2I8Vu++v6jJZpe/BIgKLGey3QwowejW/5esTPcv8Q== X-Received: by 2002:aa7:9ad8:0:b0:50a:49e1:164c with SMTP id x24-20020aa79ad8000000b0050a49e1164cmr8354515pfp.8.1650217479056; Sun, 17 Apr 2022 10:44:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 11/60] target/arm: Split out set_btype_raw Date: Sun, 17 Apr 2022 10:43:37 -0700 Message-Id: <20220417174426.711829-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650218505139100002 Content-Type: text/plain; charset="utf-8" Common code for reset_btype and set_btype. Use tcg_constant_i32. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-a64.c | 25 ++++++++++++------------- 1 file changed, 12 insertions(+), 13 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index be7283b966..a85ca380a9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -128,29 +128,28 @@ static int get_a64_user_mem_index(DisasContext *s) return arm_to_core_mmu_idx(useridx); } =20 -static void reset_btype(DisasContext *s) +static void set_btype_raw(int val) { - if (s->btype !=3D 0) { - TCGv_i32 zero =3D tcg_const_i32(0); - tcg_gen_st_i32(zero, cpu_env, offsetof(CPUARMState, btype)); - tcg_temp_free_i32(zero); - s->btype =3D 0; - } + tcg_gen_st_i32(tcg_constant_i32(val), cpu_env, + offsetof(CPUARMState, btype)); } =20 static void set_btype(DisasContext *s, int val) { - TCGv_i32 tcg_val; - /* BTYPE is a 2-bit field, and 0 should be done with reset_btype. */ tcg_debug_assert(val >=3D 1 && val <=3D 3); - - tcg_val =3D tcg_const_i32(val); - tcg_gen_st_i32(tcg_val, cpu_env, offsetof(CPUARMState, btype)); - tcg_temp_free_i32(tcg_val); + set_btype_raw(val); s->btype =3D -1; } =20 +static void reset_btype(DisasContext *s) +{ + if (s->btype !=3D 0) { + set_btype_raw(0); + s->btype =3D 0; + } +} + void gen_a64_set_pc_im(uint64_t val) { tcg_gen_movi_i64(cpu_pc, val); --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650218290; cv=none; d=zohomail.com; s=zohoarc; b=M3bvSbzebElW/EdINpP50yxp4qQaxWUgsT/tfDpWznvXRIbbqKscP4BjtJgSQAGDQ9HwaQeJn+yr5YhyHmlnYL1a53lL8Ur4+leAUOceI0m93sKy8XTrqn5dSKyZDQBzrWECBZCB0dguopbGqnWplg8W6qAGNFt+21FElavN2Og= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650218290; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vG6RbvXKJEF7LRvBZL+ritf7+gssSLdu8vjdxGvJ4Ws=; b=K6gbNFiSrNk6guNvKTY5xu7mVKxEfxhhTEX6Q64JfCBjtjzgli9Qmz0Oi22po2ui7OfdWCtxnFI5Ts/tUKA6e5gHNIe+oFUdRvQRFNmSXFGe+1mVWSvPYFcjQI1Uoe//tlJOZ/JFepiAbpv3lfun52XlIDQEkFM6kmncxb1yHGg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650218290057273.3262412189599; Sun, 17 Apr 2022 10:58:10 -0700 (PDT) Received: from localhost ([::1]:52548 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9A0-0001Wr-Mm for importer@patchew.org; Sun, 17 Apr 2022 13:58:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48034) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng8x3-0000h8-C0 for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:45 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:41960) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng8wz-0003IG-50 for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:43 -0400 Received: by mail-pl1-x62f.google.com with SMTP id s14so10738174plk.8 for ; Sun, 17 Apr 2022 10:44:40 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vG6RbvXKJEF7LRvBZL+ritf7+gssSLdu8vjdxGvJ4Ws=; b=H47D5x6Shn7fQGf+4FEQc6oC2xBpiuTUjJSGhhQf7fGGK/ZGJuURsYLJOwvB/YM6W/ 4KrGqKbGS5DyGW4XFoYZLL7WkebZauxspjQQ6+LoMUalKOf0isUx5xhGlB1TYGcmXazB uA0pjFk+IJYaEm9t1wAgTEEKj9zsnRKcfeL/zQHm4/C0IaLMR9lRfO8e02UeAWz17E7J 3dOlnqUduqenGWONIp3hNVIkndOg1msT4Zil+7gW8aL4vL95y08/7aBipM/7Rt1ooaJD V5f1x0ljqVWMw9DM7GlqNTzHVvjffw7JrvtttwrsqqgGXsYRwddNUW94xIBVqJ5kfrBw p6aw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vG6RbvXKJEF7LRvBZL+ritf7+gssSLdu8vjdxGvJ4Ws=; b=r2VE+5uCnChaoS2gcEgI3HKQMO+uLP76yiG139mJNpFMiSSfHveP5P5oUjwMRrGNIi S03QDo2cuXV1bl4ulXx3CqbgOemBlL9r0Unv3H4HmkhMW7PRrjaBOxauSyyGeQ9pV2wr L44sIOrDNfCqdAq2eHNnQvFg/qKCtyZevPVrP4vjghyhHjLXfTcqop0Hg9O9V2vd1w2x tDivRvEfOBkgqoYg53YAwoZNSeK2IDQ6yo90KIxPPIuoE1bqAqQZBhH4GjKnzfjb00Zz AoEosf3E+sVpO2vfKm0A/zcisb0iNh1qfClYP+Iv7MMs4HICzcD/GBfVZbxhwcQOzmoX zHfw== X-Gm-Message-State: AOAM533yqdas3Z2iqEg53lg21S9uKPsyatS30ohmtNK41SSO8Q1o4G/o nQD/yIQeKYa7ElM5bk0ed/o+Vu/fg+GAJw== X-Google-Smtp-Source: ABdhPJwY2sIhSlxHP632cvTztUmEqt5dw7twamz93m/NpNRWt/GbS7nOr+7hL56CvdmMpVwVpq7T8w== X-Received: by 2002:a17:90a:4bc2:b0:1b8:cdd3:53e2 with SMTP id u2-20020a17090a4bc200b001b8cdd353e2mr14253075pjl.219.1650217479905; Sun, 17 Apr 2022 10:44:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 12/60] target/arm: Split out gen_rebuild_hflags Date: Sun, 17 Apr 2022 10:43:38 -0700 Message-Id: <20220417174426.711829-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650218292175100005 Content-Type: text/plain; charset="utf-8" For aa32, the function has a parameter to use the new el. For aa64, that never happens. Use tcg_constant_i32 while we're at it. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-a64.c | 21 +++++++++----------- target/arm/translate.c | 40 +++++++++++++++++++++++--------------- 2 files changed, 33 insertions(+), 28 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a85ca380a9..a00a882145 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -341,6 +341,11 @@ static void a64_free_cc(DisasCompare64 *c64) tcg_temp_free_i64(c64->value); } =20 +static void gen_rebuild_hflags(DisasContext *s) +{ + gen_helper_rebuild_hflags_a64(cpu_env, tcg_constant_i32(s->current_el)= ); +} + static void gen_exception_internal(int excp) { TCGv_i32 tcg_excp =3D tcg_const_i32(excp); @@ -1667,9 +1672,7 @@ static void handle_msr_i(DisasContext *s, uint32_t in= sn, } else { clear_pstate_bits(PSTATE_UAO); } - t1 =3D tcg_const_i32(s->current_el); - gen_helper_rebuild_hflags_a64(cpu_env, t1); - tcg_temp_free_i32(t1); + gen_rebuild_hflags(s); break; =20 case 0x04: /* PAN */ @@ -1681,9 +1684,7 @@ static void handle_msr_i(DisasContext *s, uint32_t in= sn, } else { clear_pstate_bits(PSTATE_PAN); } - t1 =3D tcg_const_i32(s->current_el); - gen_helper_rebuild_hflags_a64(cpu_env, t1); - tcg_temp_free_i32(t1); + gen_rebuild_hflags(s); break; =20 case 0x05: /* SPSel */ @@ -1741,9 +1742,7 @@ static void handle_msr_i(DisasContext *s, uint32_t in= sn, } else { clear_pstate_bits(PSTATE_TCO); } - t1 =3D tcg_const_i32(s->current_el); - gen_helper_rebuild_hflags_a64(cpu_env, t1); - tcg_temp_free_i32(t1); + gen_rebuild_hflags(s); /* Many factors, including TCO, go into MTE_ACTIVE. */ s->base.is_jmp =3D DISAS_UPDATE_NOCHAIN; } else if (dc_isar_feature(aa64_mte_insn_reg, s)) { @@ -1990,9 +1989,7 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, * A write to any coprocessor regiser that ends a TB * must rebuild the hflags for the next TB. */ - TCGv_i32 tcg_el =3D tcg_const_i32(s->current_el); - gen_helper_rebuild_hflags_a64(cpu_env, tcg_el); - tcg_temp_free_i32(tcg_el); + gen_rebuild_hflags(s); /* * We default to ending the TB on a coprocessor register write, * but allow this to be suppressed by the register definition diff --git a/target/arm/translate.c b/target/arm/translate.c index c745b7fc91..6b293f8279 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -351,6 +351,26 @@ void gen_set_cpsr(TCGv_i32 var, uint32_t mask) tcg_temp_free_i32(tmp_mask); } =20 +static void gen_rebuild_hflags(DisasContext *s, bool new_el) +{ + bool m_profile =3D arm_dc_feature(s, ARM_FEATURE_M); + + if (new_el) { + if (m_profile) { + gen_helper_rebuild_hflags_m32_newel(cpu_env); + } else { + gen_helper_rebuild_hflags_a32_newel(cpu_env); + } + } else { + TCGv_i32 tcg_el =3D tcg_constant_i32(s->current_el); + if (m_profile) { + gen_helper_rebuild_hflags_m32(cpu_env, tcg_el); + } else { + gen_helper_rebuild_hflags_a32(cpu_env, tcg_el); + } + } +} + static void gen_exception_internal(int excp) { TCGv_i32 tcg_excp =3D tcg_const_i32(excp); @@ -4885,17 +4905,7 @@ static void do_coproc_insn(DisasContext *s, int cpnu= m, int is64, * A write to any coprocessor register that ends a TB * must rebuild the hflags for the next TB. */ - TCGv_i32 tcg_el =3D tcg_const_i32(s->current_el); - if (arm_dc_feature(s, ARM_FEATURE_M)) { - gen_helper_rebuild_hflags_m32(cpu_env, tcg_el); - } else { - if (ri->type & ARM_CP_NEWEL) { - gen_helper_rebuild_hflags_a32_newel(cpu_env); - } else { - gen_helper_rebuild_hflags_a32(cpu_env, tcg_el); - } - } - tcg_temp_free_i32(tcg_el); + gen_rebuild_hflags(s, ri->type & ARM_CP_NEWEL); /* * We default to ending the TB on a coprocessor register write, * but allow this to be suppressed by the register definition @@ -6445,7 +6455,7 @@ static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v7= m *a) tcg_temp_free_i32(addr); tcg_temp_free_i32(reg); /* If we wrote to CONTROL, the EL might have changed */ - gen_helper_rebuild_hflags_m32_newel(cpu_env); + gen_rebuild_hflags(s, true); gen_lookup_tb(s); return true; } @@ -8897,7 +8907,7 @@ static bool trans_CPS(DisasContext *s, arg_CPS *a) =20 static bool trans_CPS_v7m(DisasContext *s, arg_CPS_v7m *a) { - TCGv_i32 tmp, addr, el; + TCGv_i32 tmp, addr; =20 if (!arm_dc_feature(s, ARM_FEATURE_M)) { return false; @@ -8920,9 +8930,7 @@ static bool trans_CPS_v7m(DisasContext *s, arg_CPS_v7= m *a) gen_helper_v7m_msr(cpu_env, addr, tmp); tcg_temp_free_i32(addr); } - el =3D tcg_const_i32(s->current_el); - gen_helper_rebuild_hflags_m32(cpu_env, el); - tcg_temp_free_i32(el); + gen_rebuild_hflags(s, false); tcg_temp_free_i32(tmp); gen_lookup_tb(s); return true; --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650218662; cv=none; d=zohomail.com; s=zohoarc; b=k/4m5hVwmFPGq5d2pmL3HfUDxNE17sD0PacA78+28ZFeaiTmkv7V11187lSg5n+42/6pVgmMWffs8+ES6Zv7R0m105SRJOXU1xc96kyiiytg/2XF56UidwqlERlgkNzJ1oZtqTcjIp9dJqFASaQXpeJ0HcOq0TceaIcK0uDXQcE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650218662; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Li7BpUg3HRfrUiGI4ar3otSrrJFn7ZOtj1NESYHRNXk=; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Li7BpUg3HRfrUiGI4ar3otSrrJFn7ZOtj1NESYHRNXk=; b=wXkVsXk5mbXDOQhf8gRMZUr3/Uw8KLt/6fH5EYTix9axQgBvxjezExqvNA7ZeA0Bq1 5geKiPueFELq9a0QkzRZ5Du08vnbr1AM61rBM8do6ooWz7woR3KUyVzQkArmy+Vk7gsK bxlxMkmJGNaZG1qViykgTJuemgMz0z0SyIttZECcDYX82PbXQNsNYOQF/QDiCU+fdhmT OIuR5h+3yJ/FFJo1KjOh0Jc1fhCFG3d7fHsqbH17UjJ8+gQLgOyNOj/tF91Fl3vc8cCi FbcmSA+ZuOg0fQA86cj5oa9e986wtCeFibYOvQkEHKhDxqCnlEKgT6UdA7wxOwCSalaV 5O/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Li7BpUg3HRfrUiGI4ar3otSrrJFn7ZOtj1NESYHRNXk=; b=5S/j9rcBVubDV94x6jqwuULbP+j+KJAvpAxISQ8KY0GlkZ9QVG7ykuUrrQeN4WYYUy 9mzQzKr1njg7yNcT21/nvOETODj5u3KS2mL7UjnZG+ghxz1R8FDSDNzBPGfJ81/8dMfO oBPmDPgeFwLJFN0T3yik4mMibQqQID0Zj4vMFayYC82FzWkJkRGcMOjPStgTm4uL3TGq 67nzWTIz+a9hvgg6lHbP4QdFJTkJYG/MuLcJ5jeic9lUMpv3vG57uyYrEgHYyWq+qbuz hukYgXpasclJVEvXW4PT7crgcuSpXSv3c27u4L16npKYBEB9VvkQUHck4BOaPcJwTu2/ VKQA== X-Gm-Message-State: AOAM532JrHdekOgidnfQHysCG6Er9Kjow7IvUki6124hTHXLUmh6IqYh a/JJAf3VMkusSwcXL5GRf/BopoeIbzPbZw== X-Google-Smtp-Source: ABdhPJz5mv3rOp/wyGPfvnioVQ6wgJVl1jgFCUvVWOkQlRctf27iS2clnCU9wltwA5tw2JkV/lSaqw== X-Received: by 2002:a17:90a:cc6:b0:1d2:9a04:d29e with SMTP id 6-20020a17090a0cc600b001d29a04d29emr1463017pjt.136.1650217480899; Sun, 17 Apr 2022 10:44:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 13/60] target/arm: Use tcg_constant in translate-a64.c Date: Sun, 17 Apr 2022 10:43:39 -0700 Message-Id: <20220417174426.711829-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650218663718100001 Content-Type: text/plain; charset="utf-8" Use tcg_constant_{i32,i64,ptr} as appropriate throughout, which means we get to remove lots of tcg_temp_free_*. Drop variables in many cases, passing the constant directly to another function. Signed-off-by: Richard Henderson --- target/arm/translate-a64.c | 302 +++++++++++-------------------------- 1 file changed, 90 insertions(+), 212 deletions(-) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a00a882145..3867910ed4 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -240,14 +240,10 @@ static void gen_address_with_allocation_tag0(TCGv_i64= dst, TCGv_i64 src) static void gen_probe_access(DisasContext *s, TCGv_i64 ptr, MMUAccessType acc, int log2_size) { - TCGv_i32 t_acc =3D tcg_const_i32(acc); - TCGv_i32 t_idx =3D tcg_const_i32(get_mem_index(s)); - TCGv_i32 t_size =3D tcg_const_i32(1 << log2_size); - - gen_helper_probe_access(cpu_env, ptr, t_acc, t_idx, t_size); - tcg_temp_free_i32(t_acc); - tcg_temp_free_i32(t_idx); - tcg_temp_free_i32(t_size); + gen_helper_probe_access(cpu_env, ptr, + tcg_constant_i32(acc), + tcg_constant_i32(get_mem_index(s)), + tcg_constant_i32(1 << log2_size)); } =20 /* @@ -262,7 +258,6 @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s, = TCGv_i64 addr, int core_idx) { if (tag_checked && s->mte_active[is_unpriv]) { - TCGv_i32 tcg_desc; TCGv_i64 ret; int desc =3D 0; =20 @@ -271,11 +266,9 @@ static TCGv_i64 gen_mte_check1_mmuidx(DisasContext *s,= TCGv_i64 addr, desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); desc =3D FIELD_DP32(desc, MTEDESC, WRITE, is_write); desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, (1 << log2_size) - 1); - tcg_desc =3D tcg_const_i32(desc); =20 ret =3D new_tmp_a64(s); - gen_helper_mte_check(ret, cpu_env, tcg_desc, addr); - tcg_temp_free_i32(tcg_desc); + gen_helper_mte_check(ret, cpu_env, tcg_constant_i32(desc), addr); =20 return ret; } @@ -296,7 +289,6 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr,= bool is_write, bool tag_checked, int size) { if (tag_checked && s->mte_active[0]) { - TCGv_i32 tcg_desc; TCGv_i64 ret; int desc =3D 0; =20 @@ -305,11 +297,9 @@ TCGv_i64 gen_mte_checkN(DisasContext *s, TCGv_i64 addr= , bool is_write, desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); desc =3D FIELD_DP32(desc, MTEDESC, WRITE, is_write); desc =3D FIELD_DP32(desc, MTEDESC, SIZEM1, size - 1); - tcg_desc =3D tcg_const_i32(desc); =20 ret =3D new_tmp_a64(s); - gen_helper_mte_check(ret, cpu_env, tcg_desc, addr); - tcg_temp_free_i32(tcg_desc); + gen_helper_mte_check(ret, cpu_env, tcg_constant_i32(desc), addr); =20 return ret; } @@ -348,11 +338,8 @@ static void gen_rebuild_hflags(DisasContext *s) =20 static void gen_exception_internal(int excp) { - TCGv_i32 tcg_excp =3D tcg_const_i32(excp); - assert(excp_is_internal(excp)); - gen_helper_exception_internal(cpu_env, tcg_excp); - tcg_temp_free_i32(tcg_excp); + gen_helper_exception_internal(cpu_env, tcg_constant_i32(excp)); } =20 static void gen_exception_internal_insn(DisasContext *s, uint64_t pc, int = excp) @@ -364,12 +351,8 @@ static void gen_exception_internal_insn(DisasContext *= s, uint64_t pc, int excp) =20 static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syndrome) { - TCGv_i32 tcg_syn; - gen_a64_set_pc_im(s->pc_curr); - tcg_syn =3D tcg_const_i32(syndrome); - gen_helper_exception_bkpt_insn(cpu_env, tcg_syn); - tcg_temp_free_i32(tcg_syn); + gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syndrome)); s->base.is_jmp =3D DISAS_NORETURN; } =20 @@ -831,15 +814,15 @@ static void gen_adc(int sf, TCGv_i64 dest, TCGv_i64 t= 0, TCGv_i64 t1) static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i64 t0, TCGv_i64 t1) { if (sf) { - TCGv_i64 result, cf_64, vf_64, tmp; - result =3D tcg_temp_new_i64(); - cf_64 =3D tcg_temp_new_i64(); - vf_64 =3D tcg_temp_new_i64(); - tmp =3D tcg_const_i64(0); + TCGv_i64 result =3D tcg_temp_new_i64(); + TCGv_i64 cf_64 =3D tcg_temp_new_i64(); + TCGv_i64 vf_64 =3D tcg_temp_new_i64(); + TCGv_i64 tmp =3D tcg_temp_new_i64(); + TCGv_i64 zero =3D tcg_constant_i64(0); =20 tcg_gen_extu_i32_i64(cf_64, cpu_CF); - tcg_gen_add2_i64(result, cf_64, t0, tmp, cf_64, tmp); - tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, tmp); + tcg_gen_add2_i64(result, cf_64, t0, zero, cf_64, zero); + tcg_gen_add2_i64(result, cf_64, result, cf_64, t1, zero); tcg_gen_extrl_i64_i32(cpu_CF, cf_64); gen_set_NZ64(result); =20 @@ -855,15 +838,15 @@ static void gen_adc_CC(int sf, TCGv_i64 dest, TCGv_i6= 4 t0, TCGv_i64 t1) tcg_temp_free_i64(cf_64); tcg_temp_free_i64(result); } else { - TCGv_i32 t0_32, t1_32, tmp; - t0_32 =3D tcg_temp_new_i32(); - t1_32 =3D tcg_temp_new_i32(); - tmp =3D tcg_const_i32(0); + TCGv_i32 t0_32 =3D tcg_temp_new_i32(); + TCGv_i32 t1_32 =3D tcg_temp_new_i32(); + TCGv_i32 tmp =3D tcg_temp_new_i32(); + TCGv_i32 zero =3D tcg_constant_i32(0); =20 tcg_gen_extrl_i64_i32(t0_32, t0); tcg_gen_extrl_i64_i32(t1_32, t1); - tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, tmp, cpu_CF, tmp); - tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, tmp); + tcg_gen_add2_i32(cpu_NF, cpu_CF, t0_32, zero, cpu_CF, zero); + tcg_gen_add2_i32(cpu_NF, cpu_CF, cpu_NF, cpu_CF, t1_32, zero); =20 tcg_gen_mov_i32(cpu_ZF, cpu_NF); tcg_gen_xor_i32(cpu_VF, cpu_NF, t0_32); @@ -1632,7 +1615,6 @@ static void gen_axflag(void) static void handle_msr_i(DisasContext *s, uint32_t insn, unsigned int op1, unsigned int op2, unsigned int = crm) { - TCGv_i32 t1; int op =3D op1 << 3 | op2; =20 /* End the TB by default, chaining is ok. */ @@ -1691,9 +1673,7 @@ static void handle_msr_i(DisasContext *s, uint32_t in= sn, if (s->current_el =3D=3D 0) { goto do_unallocated; } - t1 =3D tcg_const_i32(crm & PSTATE_SP); - gen_helper_msr_i_spsel(cpu_env, t1); - tcg_temp_free_i32(t1); + gen_helper_msr_i_spsel(cpu_env, tcg_constant_i32(crm & PSTATE_SP)); break; =20 case 0x19: /* SSBS */ @@ -1721,15 +1701,11 @@ static void handle_msr_i(DisasContext *s, uint32_t = insn, break; =20 case 0x1e: /* DAIFSet */ - t1 =3D tcg_const_i32(crm); - gen_helper_msr_i_daifset(cpu_env, t1); - tcg_temp_free_i32(t1); + gen_helper_msr_i_daifset(cpu_env, tcg_constant_i32(crm)); break; =20 case 0x1f: /* DAIFClear */ - t1 =3D tcg_const_i32(crm); - gen_helper_msr_i_daifclear(cpu_env, t1); - tcg_temp_free_i32(t1); + gen_helper_msr_i_daifclear(cpu_env, tcg_constant_i32(crm)); /* For DAIFClear, exit the cpu loop to re-evaluate pending IRQs. = */ s->base.is_jmp =3D DISAS_UPDATE_EXIT; break; @@ -1842,19 +1818,14 @@ static void handle_sys(DisasContext *s, uint32_t in= sn, bool isread, /* Emit code to perform further access permissions checks at * runtime; this may result in an exception. */ - TCGv_ptr tmpptr; - TCGv_i32 tcg_syn, tcg_isread; uint32_t syndrome; =20 - gen_a64_set_pc_im(s->pc_curr); - tmpptr =3D tcg_const_ptr(ri); syndrome =3D syn_aa64_sysregtrap(op0, op1, op2, crn, crm, rt, isre= ad); - tcg_syn =3D tcg_const_i32(syndrome); - tcg_isread =3D tcg_const_i32(isread); - gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn, tcg_isrea= d); - tcg_temp_free_ptr(tmpptr); - tcg_temp_free_i32(tcg_syn); - tcg_temp_free_i32(tcg_isread); + gen_a64_set_pc_im(s->pc_curr); + gen_helper_access_check_cp_reg(cpu_env, + tcg_constant_ptr(ri), + tcg_constant_i32(syndrome), + tcg_constant_i32(isread)); } else if (ri->type & ARM_CP_RAISES_EXC) { /* * The readfn or writefn might raise an exception; @@ -1885,17 +1856,15 @@ static void handle_sys(DisasContext *s, uint32_t in= sn, bool isread, case ARM_CP_DC_ZVA: /* Writes clear the aligned block of memory which rt points into. = */ if (s->mte_active[0]) { - TCGv_i32 t_desc; int desc =3D 0; =20 desc =3D FIELD_DP32(desc, MTEDESC, MIDX, get_mem_index(s)); desc =3D FIELD_DP32(desc, MTEDESC, TBI, s->tbid); desc =3D FIELD_DP32(desc, MTEDESC, TCMA, s->tcma); - t_desc =3D tcg_const_i32(desc); =20 tcg_rt =3D new_tmp_a64(s); - gen_helper_mte_check_zva(tcg_rt, cpu_env, t_desc, cpu_reg(s, r= t)); - tcg_temp_free_i32(t_desc); + gen_helper_mte_check_zva(tcg_rt, cpu_env, + tcg_constant_i32(desc), cpu_reg(s, rt= )); } else { tcg_rt =3D clean_data_tbi(s, cpu_reg(s, rt)); } @@ -1959,10 +1928,7 @@ static void handle_sys(DisasContext *s, uint32_t ins= n, bool isread, if (ri->type & ARM_CP_CONST) { tcg_gen_movi_i64(tcg_rt, ri->resetvalue); } else if (ri->readfn) { - TCGv_ptr tmpptr; - tmpptr =3D tcg_const_ptr(ri); - gen_helper_get_cp_reg64(tcg_rt, cpu_env, tmpptr); - tcg_temp_free_ptr(tmpptr); + gen_helper_get_cp_reg64(tcg_rt, cpu_env, tcg_constant_ptr(ri)); } else { tcg_gen_ld_i64(tcg_rt, cpu_env, ri->fieldoffset); } @@ -1971,10 +1937,7 @@ static void handle_sys(DisasContext *s, uint32_t ins= n, bool isread, /* If not forbidden by access permissions, treat as WI */ return; } else if (ri->writefn) { - TCGv_ptr tmpptr; - tmpptr =3D tcg_const_ptr(ri); - gen_helper_set_cp_reg64(cpu_env, tmpptr, tcg_rt); - tcg_temp_free_ptr(tmpptr); + gen_helper_set_cp_reg64(cpu_env, tcg_constant_ptr(ri), tcg_rt); } else { tcg_gen_st_i64(tcg_rt, cpu_env, ri->fieldoffset); } @@ -2052,7 +2015,6 @@ static void disas_exc(DisasContext *s, uint32_t insn) int opc =3D extract32(insn, 21, 3); int op2_ll =3D extract32(insn, 0, 5); int imm16 =3D extract32(insn, 5, 16); - TCGv_i32 tmp; =20 switch (opc) { case 0: @@ -2087,9 +2049,7 @@ static void disas_exc(DisasContext *s, uint32_t insn) break; } gen_a64_set_pc_im(s->pc_curr); - tmp =3D tcg_const_i32(syn_aa64_smc(imm16)); - gen_helper_pre_smc(cpu_env, tmp); - tcg_temp_free_i32(tmp); + gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa64_smc(imm1= 6))); gen_ss_advance(s); gen_exception_insn(s, s->base.pc_next, EXCP_SMC, syn_aa64_smc(imm16), 3); @@ -2563,7 +2523,7 @@ static void gen_compare_and_swap_pair(DisasContext *s= , int rs, int rt, tcg_temp_free_i64(cmp); } else if (tb_cflags(s->base.tb) & CF_PARALLEL) { if (HAVE_CMPXCHG128) { - TCGv_i32 tcg_rs =3D tcg_const_i32(rs); + TCGv_i32 tcg_rs =3D tcg_constant_i32(rs); if (s->be_data =3D=3D MO_LE) { gen_helper_casp_le_parallel(cpu_env, tcg_rs, clean_addr, t1, t2); @@ -2571,7 +2531,6 @@ static void gen_compare_and_swap_pair(DisasContext *s= , int rs, int rt, gen_helper_casp_be_parallel(cpu_env, tcg_rs, clean_addr, t1, t2); } - tcg_temp_free_i32(tcg_rs); } else { gen_helper_exit_atomic(cpu_env); s->base.is_jmp =3D DISAS_NORETURN; @@ -2582,7 +2541,7 @@ static void gen_compare_and_swap_pair(DisasContext *s= , int rs, int rt, TCGv_i64 a2 =3D tcg_temp_new_i64(); TCGv_i64 c1 =3D tcg_temp_new_i64(); TCGv_i64 c2 =3D tcg_temp_new_i64(); - TCGv_i64 zero =3D tcg_const_i64(0); + TCGv_i64 zero =3D tcg_constant_i64(0); =20 /* Load the two words, in memory order. */ tcg_gen_qemu_ld_i64(d1, clean_addr, memidx, @@ -2603,7 +2562,6 @@ static void gen_compare_and_swap_pair(DisasContext *s= , int rs, int rt, tcg_temp_free_i64(a2); tcg_temp_free_i64(c1); tcg_temp_free_i64(c2); - tcg_temp_free_i64(zero); =20 /* Write back the data from memory to Rs. */ tcg_gen_mov_i64(s1, d1); @@ -2820,7 +2778,7 @@ static void disas_ld_lit(DisasContext *s, uint32_t in= sn) =20 tcg_rt =3D cpu_reg(s, rt); =20 - clean_addr =3D tcg_const_i64(s->pc_curr + imm); + clean_addr =3D tcg_constant_i64(s->pc_curr + imm); if (is_vector) { do_fp_ld(s, rt, clean_addr, size); } else { @@ -2830,7 +2788,6 @@ static void disas_ld_lit(DisasContext *s, uint32_t in= sn) do_gpr_ld(s, tcg_rt, clean_addr, size + is_signed * MO_SIGN, false, true, rt, iss_sf, false); } - tcg_temp_free_i64(clean_addr); } =20 /* @@ -3736,7 +3693,7 @@ static void disas_ldst_multiple_struct(DisasContext *= s, uint32_t insn) mop =3D endian | size | align; =20 elements =3D (is_q ? 16 : 8) >> size; - tcg_ebytes =3D tcg_const_i64(1 << size); + tcg_ebytes =3D tcg_constant_i64(1 << size); for (r =3D 0; r < rpt; r++) { int e; for (e =3D 0; e < elements; e++) { @@ -3752,7 +3709,6 @@ static void disas_ldst_multiple_struct(DisasContext *= s, uint32_t insn) } } } - tcg_temp_free_i64(tcg_ebytes); =20 if (!is_store) { /* For non-quad operations, setting a slice of the low @@ -3882,7 +3838,7 @@ static void disas_ldst_single_struct(DisasContext *s,= uint32_t insn) total); mop =3D finalize_memop(s, scale); =20 - tcg_ebytes =3D tcg_const_i64(1 << scale); + tcg_ebytes =3D tcg_constant_i64(1 << scale); for (xs =3D 0; xs < selem; xs++) { if (replicate) { /* Load and replicate to all elements */ @@ -3904,7 +3860,6 @@ static void disas_ldst_single_struct(DisasContext *s,= uint32_t insn) tcg_gen_add_i64(clean_addr, clean_addr, tcg_ebytes); rt =3D (rt + 1) % 32; } - tcg_temp_free_i64(tcg_ebytes); =20 if (is_postidx) { if (rm =3D=3D 31) { @@ -4095,7 +4050,7 @@ static void disas_ldst_tag(DisasContext *s, uint32_t = insn) =20 if (is_zero) { TCGv_i64 clean_addr =3D clean_data_tbi(s, addr); - TCGv_i64 tcg_zero =3D tcg_const_i64(0); + TCGv_i64 tcg_zero =3D tcg_constant_i64(0); int mem_index =3D get_mem_index(s); int i, n =3D (1 + is_pair) << LOG2_TAG_GRANULE; =20 @@ -4105,7 +4060,6 @@ static void disas_ldst_tag(DisasContext *s, uint32_t = insn) tcg_gen_addi_i64(clean_addr, clean_addr, 8); tcg_gen_qemu_st_i64(tcg_zero, clean_addr, mem_index, MO_UQ); } - tcg_temp_free_i64(tcg_zero); } =20 if (index !=3D 0) { @@ -4224,13 +4178,12 @@ static void disas_add_sub_imm(DisasContext *s, uint= 32_t insn) tcg_gen_addi_i64(tcg_result, tcg_rn, imm); } } else { - TCGv_i64 tcg_imm =3D tcg_const_i64(imm); + TCGv_i64 tcg_imm =3D tcg_constant_i64(imm); if (sub_op) { gen_sub_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); } else { gen_add_CC(is_64bit, tcg_result, tcg_rn, tcg_imm); } - tcg_temp_free_i64(tcg_imm); } =20 if (is_64bit) { @@ -4278,12 +4231,9 @@ static void disas_add_sub_imm_with_tags(DisasContext= *s, uint32_t insn) tcg_rd =3D cpu_reg_sp(s, rd); =20 if (s->ata) { - TCGv_i32 offset =3D tcg_const_i32(imm); - TCGv_i32 tag_offset =3D tcg_const_i32(uimm4); - - gen_helper_addsubg(tcg_rd, cpu_env, tcg_rn, offset, tag_offset); - tcg_temp_free_i32(tag_offset); - tcg_temp_free_i32(offset); + gen_helper_addsubg(tcg_rd, cpu_env, tcg_rn, + tcg_constant_i32(imm), + tcg_constant_i32(uimm4)); } else { tcg_gen_addi_i64(tcg_rd, tcg_rn, imm); gen_address_with_allocation_tag0(tcg_rd, tcg_rd); @@ -4469,7 +4419,6 @@ static void disas_movw_imm(DisasContext *s, uint32_t = insn) int opc =3D extract32(insn, 29, 2); int pos =3D extract32(insn, 21, 2) << 4; TCGv_i64 tcg_rd =3D cpu_reg(s, rd); - TCGv_i64 tcg_imm; =20 if (!sf && (pos >=3D 32)) { unallocated_encoding(s); @@ -4489,9 +4438,7 @@ static void disas_movw_imm(DisasContext *s, uint32_t = insn) tcg_gen_movi_i64(tcg_rd, imm); break; case 3: /* MOVK */ - tcg_imm =3D tcg_const_i64(imm); - tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_imm, pos, 16); - tcg_temp_free_i64(tcg_imm); + tcg_gen_deposit_i64(tcg_rd, tcg_rd, tcg_constant_i64(imm), pos, 16= ); if (!sf) { tcg_gen_ext32u_i64(tcg_rd, tcg_rd); } @@ -4731,11 +4678,7 @@ static void shift_reg_imm(TCGv_i64 dst, TCGv_i64 src= , int sf, if (shift_i =3D=3D 0) { tcg_gen_mov_i64(dst, src); } else { - TCGv_i64 shift_const; - - shift_const =3D tcg_const_i64(shift_i); - shift_reg(dst, src, sf, shift_type, shift_const); - tcg_temp_free_i64(shift_const); + shift_reg(dst, src, sf, shift_type, tcg_constant_i64(shift_i)); } } =20 @@ -5312,7 +5255,7 @@ static void disas_cond_select(DisasContext *s, uint32= _t insn) tcg_rd =3D cpu_reg(s, rd); =20 a64_test_cc(&c, cond); - zero =3D tcg_const_i64(0); + zero =3D tcg_constant_i64(0); =20 if (rn =3D=3D 31 && rm =3D=3D 31 && (else_inc ^ else_inv)) { /* CSET & CSETM. */ @@ -5333,7 +5276,6 @@ static void disas_cond_select(DisasContext *s, uint32= _t insn) tcg_gen_movcond_i64(c.cond, tcg_rd, c.value, zero, t_true, t_false= ); } =20 - tcg_temp_free_i64(zero); a64_free_cc(&c); =20 if (!sf) { @@ -5430,7 +5372,7 @@ static void handle_rev16(DisasContext *s, unsigned in= t sf, TCGv_i64 tcg_rd =3D cpu_reg(s, rd); TCGv_i64 tcg_tmp =3D tcg_temp_new_i64(); TCGv_i64 tcg_rn =3D read_cpu_reg(s, rn, sf); - TCGv_i64 mask =3D tcg_const_i64(sf ? 0x00ff00ff00ff00ffull : 0x00ff00f= f); + TCGv_i64 mask =3D tcg_constant_i64(sf ? 0x00ff00ff00ff00ffull : 0x00ff= 00ff); =20 tcg_gen_shri_i64(tcg_tmp, tcg_rn, 8); tcg_gen_and_i64(tcg_rd, tcg_rn, mask); @@ -5438,7 +5380,6 @@ static void handle_rev16(DisasContext *s, unsigned in= t sf, tcg_gen_shli_i64(tcg_rd, tcg_rd, 8); tcg_gen_or_i64(tcg_rd, tcg_rd, tcg_tmp); =20 - tcg_temp_free_i64(mask); tcg_temp_free_i64(tcg_tmp); } =20 @@ -5721,15 +5662,13 @@ static void handle_crc32(DisasContext *s, } =20 tcg_acc =3D cpu_reg(s, rn); - tcg_bytes =3D tcg_const_i32(1 << sz); + tcg_bytes =3D tcg_constant_i32(1 << sz); =20 if (crc32c) { gen_helper_crc32c_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes); } else { gen_helper_crc32_64(cpu_reg(s, rd), tcg_acc, tcg_val, tcg_bytes); } - - tcg_temp_free_i32(tcg_bytes); } =20 /* Data-processing (2 source) @@ -5795,15 +5734,13 @@ static void disas_data_proc_2src(DisasContext *s, u= int32_t insn) if (sf =3D=3D 0 || !dc_isar_feature(aa64_mte_insn_reg, s)) { goto do_unallocated; } else { - TCGv_i64 t1 =3D tcg_const_i64(1); - TCGv_i64 t2 =3D tcg_temp_new_i64(); + TCGv_i64 t =3D tcg_temp_new_i64(); =20 - tcg_gen_extract_i64(t2, cpu_reg_sp(s, rn), 56, 4); - tcg_gen_shl_i64(t1, t1, t2); - tcg_gen_or_i64(cpu_reg(s, rd), cpu_reg(s, rm), t1); + tcg_gen_extract_i64(t, cpu_reg_sp(s, rn), 56, 4); + tcg_gen_shl_i64(t, tcg_constant_i64(1), t); + tcg_gen_or_i64(cpu_reg(s, rd), cpu_reg(s, rm), t); =20 - tcg_temp_free_i64(t1); - tcg_temp_free_i64(t2); + tcg_temp_free_i64(t); } break; case 8: /* LSLV */ @@ -5938,7 +5875,7 @@ static void handle_fp_compare(DisasContext *s, int si= ze, =20 tcg_vn =3D read_fp_dreg(s, rn); if (cmp_with_zero) { - tcg_vm =3D tcg_const_i64(0); + tcg_vm =3D tcg_constant_i64(0); } else { tcg_vm =3D read_fp_dreg(s, rm); } @@ -6048,7 +5985,6 @@ static void disas_fp_compare(DisasContext *s, uint32_= t insn) static void disas_fp_ccomp(DisasContext *s, uint32_t insn) { unsigned int mos, type, rm, cond, rn, op, nzcv; - TCGv_i64 tcg_flags; TCGLabel *label_continue =3D NULL; int size; =20 @@ -6092,9 +6028,7 @@ static void disas_fp_ccomp(DisasContext *s, uint32_t = insn) label_continue =3D gen_new_label(); arm_gen_test_cc(cond, label_match); /* nomatch: */ - tcg_flags =3D tcg_const_i64(nzcv << 28); - gen_set_nzcv(tcg_flags); - tcg_temp_free_i64(tcg_flags); + gen_set_nzcv(tcg_constant_i64(nzcv << 28)); tcg_gen_br(label_continue); gen_set_label(label_match); } @@ -6115,7 +6049,7 @@ static void disas_fp_ccomp(DisasContext *s, uint32_t = insn) static void disas_fp_csel(DisasContext *s, uint32_t insn) { unsigned int mos, type, rm, cond, rn, rd; - TCGv_i64 t_true, t_false, t_zero; + TCGv_i64 t_true, t_false; DisasCompare64 c; MemOp sz; =20 @@ -6160,10 +6094,8 @@ static void disas_fp_csel(DisasContext *s, uint32_t = insn) read_vec_element(s, t_false, rm, 0, sz); =20 a64_test_cc(&c, cond); - t_zero =3D tcg_const_i64(0); - tcg_gen_movcond_i64(c.cond, t_true, c.value, t_zero, t_true, t_false); - tcg_temp_free_i64(t_zero); - tcg_temp_free_i64(t_false); + tcg_gen_movcond_i64(c.cond, t_true, c.value, tcg_constant_i64(0), + t_true, t_false); a64_free_cc(&c); =20 /* Note that sregs & hregs write back zeros to the high bits, @@ -6944,7 +6876,6 @@ static void disas_fp_imm(DisasContext *s, uint32_t in= sn) int type =3D extract32(insn, 22, 2); int mos =3D extract32(insn, 29, 3); uint64_t imm; - TCGv_i64 tcg_res; MemOp sz; =20 if (mos || imm5) { @@ -6975,10 +6906,7 @@ static void disas_fp_imm(DisasContext *s, uint32_t i= nsn) } =20 imm =3D vfp_expand_imm(sz, imm8); - - tcg_res =3D tcg_const_i64(imm); - write_fp_dreg(s, rd, tcg_res); - tcg_temp_free_i64(tcg_res); + write_fp_dreg(s, rd, tcg_constant_i64(imm)); } =20 /* Handle floating point <=3D> fixed point conversions. Note that we can @@ -6996,7 +6924,7 @@ static void handle_fpfpcvt(DisasContext *s, int rd, i= nt rn, int opcode, =20 tcg_fpstatus =3D fpstatus_ptr(type =3D=3D 3 ? FPST_FPCR_F16 : FPST_FPC= R); =20 - tcg_shift =3D tcg_const_i32(64 - scale); + tcg_shift =3D tcg_constant_i32(64 - scale); =20 if (itof) { TCGv_i64 tcg_int =3D cpu_reg(s, rn); @@ -7155,7 +7083,6 @@ static void handle_fpfpcvt(DisasContext *s, int rd, i= nt rn, int opcode, } =20 tcg_temp_free_ptr(tcg_fpstatus); - tcg_temp_free_i32(tcg_shift); } =20 /* Floating point <-> fixed point conversions @@ -8426,7 +8353,7 @@ static void handle_shri_with_rndacc(TCGv_i64 tcg_res,= TCGv_i64 tcg_src, /* Deal with the rounding step */ if (round) { if (extended_result) { - TCGv_i64 tcg_zero =3D tcg_const_i64(0); + TCGv_i64 tcg_zero =3D tcg_constant_i64(0); if (!is_u) { /* take care of sign extending tcg_res */ tcg_gen_sari_i64(tcg_src_hi, tcg_src, 63); @@ -8438,7 +8365,6 @@ static void handle_shri_with_rndacc(TCGv_i64 tcg_res,= TCGv_i64 tcg_src, tcg_src, tcg_zero, tcg_rnd, tcg_zero); } - tcg_temp_free_i64(tcg_zero); } else { tcg_gen_add_i64(tcg_src, tcg_src, tcg_rnd); } @@ -8524,8 +8450,7 @@ static void handle_scalar_simd_shri(DisasContext *s, } =20 if (round) { - uint64_t round_const =3D 1ULL << (shift - 1); - tcg_round =3D tcg_const_i64(round_const); + tcg_round =3D tcg_constant_i64(1ULL << (shift - 1)); } else { tcg_round =3D NULL; } @@ -8551,9 +8476,6 @@ static void handle_scalar_simd_shri(DisasContext *s, =20 tcg_temp_free_i64(tcg_rn); tcg_temp_free_i64(tcg_rd); - if (round) { - tcg_temp_free_i64(tcg_round); - } } =20 /* SHL/SLI - Scalar shift left */ @@ -8651,8 +8573,7 @@ static void handle_vec_simd_sqshrn(DisasContext *s, b= ool is_scalar, bool is_q, tcg_final =3D tcg_const_i64(0); =20 if (round) { - uint64_t round_const =3D 1ULL << (shift - 1); - tcg_round =3D tcg_const_i64(round_const); + tcg_round =3D tcg_constant_i64(1ULL << (shift - 1)); } else { tcg_round =3D NULL; } @@ -8672,9 +8593,6 @@ static void handle_vec_simd_sqshrn(DisasContext *s, b= ool is_scalar, bool is_q, write_vec_element(s, tcg_final, rd, 1, MO_64); } =20 - if (round) { - tcg_temp_free_i64(tcg_round); - } tcg_temp_free_i64(tcg_rn); tcg_temp_free_i64(tcg_rd); tcg_temp_free_i32(tcg_rd_narrowed); @@ -8726,7 +8644,7 @@ static void handle_simd_qshl(DisasContext *s, bool sc= alar, bool is_q, } =20 if (size =3D=3D 3) { - TCGv_i64 tcg_shift =3D tcg_const_i64(shift); + TCGv_i64 tcg_shift =3D tcg_constant_i64(shift); static NeonGenTwo64OpEnvFn * const fns[2][2] =3D { { gen_helper_neon_qshl_s64, gen_helper_neon_qshlu_s64 }, { NULL, gen_helper_neon_qshl_u64 }, @@ -8743,10 +8661,9 @@ static void handle_simd_qshl(DisasContext *s, bool s= calar, bool is_q, =20 tcg_temp_free_i64(tcg_op); } - tcg_temp_free_i64(tcg_shift); clear_vec_high(s, is_q, rd); } else { - TCGv_i32 tcg_shift =3D tcg_const_i32(shift); + TCGv_i32 tcg_shift =3D tcg_constant_i32(shift); static NeonGenTwoOpEnvFn * const fns[2][2][3] =3D { { { gen_helper_neon_qshl_s8, @@ -8791,7 +8708,6 @@ static void handle_simd_qshl(DisasContext *s, bool sc= alar, bool is_q, =20 tcg_temp_free_i32(tcg_op); } - tcg_temp_free_i32(tcg_shift); =20 if (!scalar) { clear_vec_high(s, is_q, rd); @@ -8811,7 +8727,7 @@ static void handle_simd_intfp_conv(DisasContext *s, i= nt rd, int rn, int pass; =20 if (fracbits || size =3D=3D MO_64) { - tcg_shift =3D tcg_const_i32(fracbits); + tcg_shift =3D tcg_constant_i32(fracbits); } =20 if (size =3D=3D MO_64) { @@ -8896,9 +8812,6 @@ static void handle_simd_intfp_conv(DisasContext *s, i= nt rd, int rn, } =20 tcg_temp_free_ptr(tcg_fpst); - if (tcg_shift) { - tcg_temp_free_i32(tcg_shift); - } =20 clear_vec_high(s, elements << size =3D=3D 16, rd); } @@ -8988,7 +8901,7 @@ static void handle_simd_shift_fpint_conv(DisasContext= *s, bool is_scalar, tcg_fpstatus =3D fpstatus_ptr(size =3D=3D MO_16 ? FPST_FPCR_F16 : FPST= _FPCR); gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); fracbits =3D (16 << size) - immhb; - tcg_shift =3D tcg_const_i32(fracbits); + tcg_shift =3D tcg_constant_i32(fracbits); =20 if (size =3D=3D MO_64) { int maxpass =3D is_scalar ? 1 : 2; @@ -9046,7 +8959,6 @@ static void handle_simd_shift_fpint_conv(DisasContext= *s, bool is_scalar, } } =20 - tcg_temp_free_i32(tcg_shift); gen_helper_set_rmode(tcg_rmode, tcg_rmode, tcg_fpstatus); tcg_temp_free_ptr(tcg_fpstatus); tcg_temp_free_i32(tcg_rmode); @@ -9918,23 +9830,15 @@ static void handle_2misc_64(DisasContext *s, int op= code, bool u, case 0x1c: /* FCVTAS */ case 0x3a: /* FCVTPS */ case 0x3b: /* FCVTZS */ - { - TCGv_i32 tcg_shift =3D tcg_const_i32(0); - gen_helper_vfp_tosqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); - tcg_temp_free_i32(tcg_shift); + gen_helper_vfp_tosqd(tcg_rd, tcg_rn, tcg_constant_i32(0), tcg_fpst= atus); break; - } case 0x5a: /* FCVTNU */ case 0x5b: /* FCVTMU */ case 0x5c: /* FCVTAU */ case 0x7a: /* FCVTPU */ case 0x7b: /* FCVTZU */ - { - TCGv_i32 tcg_shift =3D tcg_const_i32(0); - gen_helper_vfp_touqd(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); - tcg_temp_free_i32(tcg_shift); + gen_helper_vfp_touqd(tcg_rd, tcg_rn, tcg_constant_i32(0), tcg_fpst= atus); break; - } case 0x18: /* FRINTN */ case 0x19: /* FRINTM */ case 0x38: /* FRINTP */ @@ -9974,7 +9878,7 @@ static void handle_2misc_fcmp_zero(DisasContext *s, i= nt opcode, =20 if (is_double) { TCGv_i64 tcg_op =3D tcg_temp_new_i64(); - TCGv_i64 tcg_zero =3D tcg_const_i64(0); + TCGv_i64 tcg_zero =3D tcg_constant_i64(0); TCGv_i64 tcg_res =3D tcg_temp_new_i64(); NeonGenTwoDoubleOpFn *genfn; bool swap =3D false; @@ -10010,13 +9914,12 @@ static void handle_2misc_fcmp_zero(DisasContext *s= , int opcode, write_vec_element(s, tcg_res, rd, pass, MO_64); } tcg_temp_free_i64(tcg_res); - tcg_temp_free_i64(tcg_zero); tcg_temp_free_i64(tcg_op); =20 clear_vec_high(s, !is_scalar, rd); } else { TCGv_i32 tcg_op =3D tcg_temp_new_i32(); - TCGv_i32 tcg_zero =3D tcg_const_i32(0); + TCGv_i32 tcg_zero =3D tcg_constant_i32(0); TCGv_i32 tcg_res =3D tcg_temp_new_i32(); NeonGenTwoSingleOpFn *genfn; bool swap =3D false; @@ -10085,7 +9988,6 @@ static void handle_2misc_fcmp_zero(DisasContext *s, = int opcode, } } tcg_temp_free_i32(tcg_res); - tcg_temp_free_i32(tcg_zero); tcg_temp_free_i32(tcg_op); if (!is_scalar) { clear_vec_high(s, is_q, rd); @@ -10186,7 +10088,7 @@ static void handle_2misc_narrow(DisasContext *s, bo= ol scalar, int passes =3D scalar ? 1 : 2; =20 if (scalar) { - tcg_res[1] =3D tcg_const_i32(0); + tcg_res[1] =3D tcg_constant_i32(0); } =20 for (pass =3D 0; pass < passes; pass++) { @@ -10364,9 +10266,7 @@ static void handle_2misc_satacc(DisasContext *s, bo= ol is_scalar, bool is_u, } =20 if (is_scalar) { - TCGv_i64 tcg_zero =3D tcg_const_i64(0); - write_vec_element(s, tcg_zero, rd, 0, MO_64); - tcg_temp_free_i64(tcg_zero); + write_vec_element(s, tcg_constant_i64(0), rd, 0, MO_64); } write_vec_element_i32(s, tcg_rd, rd, pass, MO_32); } @@ -10549,23 +10449,17 @@ static void disas_simd_scalar_two_reg_misc(DisasC= ontext *s, uint32_t insn) case 0x1c: /* FCVTAS */ case 0x3a: /* FCVTPS */ case 0x3b: /* FCVTZS */ - { - TCGv_i32 tcg_shift =3D tcg_const_i32(0); - gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); - tcg_temp_free_i32(tcg_shift); + gen_helper_vfp_tosls(tcg_rd, tcg_rn, tcg_constant_i32(0), + tcg_fpstatus); break; - } case 0x5a: /* FCVTNU */ case 0x5b: /* FCVTMU */ case 0x5c: /* FCVTAU */ case 0x7a: /* FCVTPU */ case 0x7b: /* FCVTZU */ - { - TCGv_i32 tcg_shift =3D tcg_const_i32(0); - gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_shift, tcg_fpstatus); - tcg_temp_free_i32(tcg_shift); + gen_helper_vfp_touls(tcg_rd, tcg_rn, tcg_constant_i32(0), + tcg_fpstatus); break; - } default: g_assert_not_reached(); } @@ -10737,8 +10631,7 @@ static void handle_vec_simd_shrn(DisasContext *s, b= ool is_q, read_vec_element(s, tcg_final, rd, is_q ? 1 : 0, MO_64); =20 if (round) { - uint64_t round_const =3D 1ULL << (shift - 1); - tcg_round =3D tcg_const_i64(round_const); + tcg_round =3D tcg_constant_i64(1ULL << (shift - 1)); } else { tcg_round =3D NULL; } @@ -10756,9 +10649,6 @@ static void handle_vec_simd_shrn(DisasContext *s, b= ool is_q, } else { write_vec_element(s, tcg_final, rd, 1, MO_64); } - if (round) { - tcg_temp_free_i64(tcg_round); - } tcg_temp_free_i64(tcg_rn); tcg_temp_free_i64(tcg_rd); tcg_temp_free_i64(tcg_final); @@ -12462,7 +12352,7 @@ static void handle_2misc_pairwise(DisasContext *s, = int opcode, bool u, } } if (!is_q) { - tcg_res[1] =3D tcg_const_i64(0); + tcg_res[1] =3D tcg_constant_i64(0); } for (pass =3D 0; pass < 2; pass++) { write_vec_element(s, tcg_res[pass], rd, pass, MO_64); @@ -12895,25 +12785,17 @@ static void disas_simd_two_reg_misc(DisasContext = *s, uint32_t insn) case 0x1c: /* FCVTAS */ case 0x3a: /* FCVTPS */ case 0x3b: /* FCVTZS */ - { - TCGv_i32 tcg_shift =3D tcg_const_i32(0); gen_helper_vfp_tosls(tcg_res, tcg_op, - tcg_shift, tcg_fpstatus); - tcg_temp_free_i32(tcg_shift); + tcg_constant_i32(0), tcg_fpstatus= ); break; - } case 0x5a: /* FCVTNU */ case 0x5b: /* FCVTMU */ case 0x5c: /* FCVTAU */ case 0x7a: /* FCVTPU */ case 0x7b: /* FCVTZU */ - { - TCGv_i32 tcg_shift =3D tcg_const_i32(0); gen_helper_vfp_touls(tcg_res, tcg_op, - tcg_shift, tcg_fpstatus); - tcg_temp_free_i32(tcg_shift); + tcg_constant_i32(0), tcg_fpstatus= ); break; - } case 0x18: /* FRINTN */ case 0x19: /* FRINTM */ case 0x38: /* FRINTP */ @@ -14011,7 +13893,7 @@ static void disas_simd_indexed(DisasContext *s, uin= t32_t insn) } =20 if (is_scalar) { - tcg_res[1] =3D tcg_const_i64(0); + tcg_res[1] =3D tcg_constant_i64(0); } =20 for (pass =3D 0; pass < 2; pass++) { @@ -14415,7 +14297,7 @@ static void disas_crypto_four_reg(DisasContext *s, = uint32_t insn) tcg_op2 =3D tcg_temp_new_i32(); tcg_op3 =3D tcg_temp_new_i32(); tcg_res =3D tcg_temp_new_i32(); - tcg_zero =3D tcg_const_i32(0); + tcg_zero =3D tcg_constant_i32(0); =20 read_vec_element_i32(s, tcg_op1, rn, 3, MO_32); read_vec_element_i32(s, tcg_op2, rm, 3, MO_32); @@ -14435,7 +14317,6 @@ static void disas_crypto_four_reg(DisasContext *s, = uint32_t insn) tcg_temp_free_i32(tcg_op2); tcg_temp_free_i32(tcg_op3); tcg_temp_free_i32(tcg_res); - tcg_temp_free_i32(tcg_zero); } } =20 @@ -14943,22 +14824,19 @@ static void aarch64_tr_tb_stop(DisasContextBase *= dcbase, CPUState *cpu) gen_helper_yield(cpu_env); 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cn62Jvoq3Pb11WwsFWhBF5m4nITQmzUChokYzJD1Jq4=; b=eReMNyweJi6MfDh6wje3xHRDFoafz6DelGZ7BTElJiwX1MEN+afQ6vd1k0/ygxxcmH I1s06huv/JT0z+TtstYbh0GX1xX8NPOxDh5Eo6hE1u8oIp5wefixtEH0K1VGpVHQEsjD 2U0LBaFsy9Ud6KIkhsuvStq1om78hlq/HGk8RQQ93GluZ4JlzUTOvB01T0SVuia7mzZV wMT7SaAaww5UE8V4FW0kLJU0Vga4gDiSxo2+8uACq5je6JTPsRCTAOSzT/BCabSDdD9g zIL+et9OUkR26jvckhb1UsV1Mg6qhfTJJs5fg4Llk3HUWHiNz38TDvOMw08lxbo2r+d5 yXSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cn62Jvoq3Pb11WwsFWhBF5m4nITQmzUChokYzJD1Jq4=; b=a4lZ76YK4CkbMMehU7wgK+i1IgNtmfwgA72R86nvWzlaykSW8rPeXX5FW0U2W5Kxtw dWkGtzfm46WbC4qFWSCj6AO7AebFktTK1VultlDdhgN4MVsnbeKRWpD4UHeVetd1xgI9 GAVGItKjtOZzRWVqZsET36YWtoQM0r/Y87g+gLN+liqWYxA0sIMam7wCRWqhpXRyMjcu NyBVo3moGj13fxHd0pLtidBV6iG4DG8F0LV4g1JO8aRjcEODxKCTxSrM1E1ZCbo6OFof iR3mtliPRwoaxR5z9rbNYAEA3Nwwrs61Mh1v9Yg+zjGyquQktN3Hfok+4ZluND3lX/Is iXfQ== X-Gm-Message-State: AOAM531caEK2tKWtNkPAzuJb+RZCMKdVbca3MiD7yL9QX2aYfoo/iD9V yCAC+ARVLnnrFs9gHCLV1KaWudPcIBXlyA== X-Google-Smtp-Source: ABdhPJxesFE84CbAwHsk14MoGwdH69oHqJNQ34VgzOp7G6kkrkChdGeiEuMU//LRXA0ia8VvoSYRFQ== X-Received: by 2002:a05:6a00:b94:b0:50a:5ff2:bb2a with SMTP id g20-20020a056a000b9400b0050a5ff2bb2amr5172146pfj.56.1650217481745; Sun, 17 Apr 2022 10:44:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 14/60] target/arm: Simplify GEN_SHIFT in translate.c Date: Sun, 17 Apr 2022 10:43:40 -0700 Message-Id: <20220417174426.711829-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650218292170100004 Content-Type: text/plain; charset="utf-8" Instead of computing tmp1 =3D shift & 0xff; dest =3D (tmp1 > 0x1f ? 0 : value) << (tmp1 & 0x1f) use tmpd =3D value << (shift & 0x1f); dest =3D shift & 0xe ? 0 : tmpd; which has a flatter dependency tree. Use tcg_constant_i32 while we're at it. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 18 ++++++++---------- 1 file changed, 8 insertions(+), 10 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 6b293f8279..57631c9fa1 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -552,16 +552,14 @@ static void gen_sbc_CC(TCGv_i32 dest, TCGv_i32 t0, TC= Gv_i32 t1) #define GEN_SHIFT(name) \ static void gen_##name(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) \ { \ - TCGv_i32 tmp1, tmp2, tmp3; \ - tmp1 =3D tcg_temp_new_i32(); \ - tcg_gen_andi_i32(tmp1, t1, 0xff); \ - tmp2 =3D tcg_const_i32(0); \ - tmp3 =3D tcg_const_i32(0x1f); \ - tcg_gen_movcond_i32(TCG_COND_GTU, tmp2, tmp1, tmp3, tmp2, t0); \ - tcg_temp_free_i32(tmp3); \ - tcg_gen_andi_i32(tmp1, tmp1, 0x1f); \ - tcg_gen_##name##_i32(dest, tmp2, tmp1); \ - tcg_temp_free_i32(tmp2); \ + TCGv_i32 tmpd =3D tcg_temp_new_i32(); \ + TCGv_i32 tmp1 =3D tcg_temp_new_i32(); \ + TCGv_i32 zero =3D tcg_constant_i32(0); \ + tcg_gen_andi_i32(tmp1, t1, 0x1f); \ + tcg_gen_##name##_i32(tmpd, t0, tmp1); \ + tcg_gen_andi_i32(tmp1, t1, 0xe0); \ + tcg_gen_movcond_i32(TCG_COND_NE, dest, tmp1, zero, zero, tmpd); \ + tcg_temp_free_i32(tmpd); \ tcg_temp_free_i32(tmp1); \ } GEN_SHIFT(shl) --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650218835; cv=none; d=zohomail.com; s=zohoarc; b=DGVBIzolxc/Pa8ruPszmCema+W5k3Ik5TQczqQt3ZWIkDoT4QxrjwRyeZRIv799Ai+tdghscgoIbVyypvqy/RL2YZgTviUGI/Jvzydu9hf8SYgeL/BrXP1hqBAUtppXVcKfjXf902Q9zDq4cbmsqUbslEGnRbTuG8zHfvdcqFqU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650218835; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=z284YO2l+zNv3weW3jS6RSJVzTJCNg6AbcZ1VqRFtfo=; b=nmIGukjthlYGbjNd5hfsuoO++P7s5yNpiwOCkfXoWOfG8DLSpRUHrHMCkdVqIZgPth4KaNQ27jii8pkIiYo1ZzDOXuHRbQJ60HmmMnxneKDG37AMYE3OFx3f0YRBZHazNiidmYWSJ7TKxSesp6T/6x9XDfOpmvxGqDxJzxfOgKc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650218835350408.6338918096453; Sun, 17 Apr 2022 11:07:15 -0700 (PDT) Received: from localhost ([::1]:52412 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9Io-0003ZT-9D for importer@patchew.org; Sun, 17 Apr 2022 14:07:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48112) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng8x5-0000j2-BW for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:48 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:40610) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng8x3-0003JU-35 for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:46 -0400 Received: by mail-pl1-x633.google.com with SMTP id t12so10738699pll.7 for ; Sun, 17 Apr 2022 10:44:43 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=z284YO2l+zNv3weW3jS6RSJVzTJCNg6AbcZ1VqRFtfo=; b=xEMyygvUXN6bfDFI+qFB8xYg7Yc899cQXWUScaoDeYT+iLdPSDz52Sgrww4GTluvJx 8kjEMBDub64QOMrG/1QjBZtH7ttYlfPbveFMpYMjxp2HwoMtfUWjbSVtamU3J2WZKWkv epZNeylcWT88FK2bANnV8JAoCtp5vnLKXm2K7ha7NQsR2JexI+MOkjvaM9shDgaxSrbp ytLWELUpKTVHbJl+bhVRhYFb0oOpkrg9brLBeTmMRcQOjP3xz7iNfO4QWhBVoD8fSFlx NUC6L/j8h7a7Li+1TqPUaEi2p+9jUbInQiPWIFk1LSF64jFtY0VXzQ0parAv4K6wn8Gy Wydg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=z284YO2l+zNv3weW3jS6RSJVzTJCNg6AbcZ1VqRFtfo=; b=IG0V78/EqV4koKODyaY2cvyPPJJyufkUe55Yo/8hxcM9T7/Nz37kjyuXTNYeXT0Svs X3NZC89cYko8a4HiDtKVU96x80Yrr5PDVBfciwXEHWA9q12PMVeHT6tRZBSJjqMKFMsl 2yHM2gFxldbilvdonmHaIfUKpoi1Ub65huZcITXzgIvRfj32Vy0wvHNvyw/W6jk+/AJX B0oQwkFbxxc2iMICSQ/jxPXoG9AEDKMFi4ctyw5/s3No4VhA8DGB3xAELjidzzaaITJo O1CaUWtxp0zjo6Q1jeHnXqSE2t3TtWUf1WXwMmZbSBBQb1R6PlHBKke9c+uZS7jjwid6 aNAQ== X-Gm-Message-State: AOAM530RUp4xH/Tltm2JQg/vltcmdOF6d/lyqXbxBrx/HsVSBoonNW2S Pwl7h6Xn6MGnngPqfvEQm9xSwxiTFnqO4Q== X-Google-Smtp-Source: ABdhPJwNKYMilrCWo9J20O/bOdm2tkcEqHpSLsBkDtKTbvUfoOeDPGZaIZZPD2lDoZ4cqbQf+sl41g== X-Received: by 2002:a17:902:ce0f:b0:156:5a4:926c with SMTP id k15-20020a170902ce0f00b0015605a4926cmr7557717plg.3.1650217482752; Sun, 17 Apr 2022 10:44:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 15/60] target/arm: Simplify gen_sar Date: Sun, 17 Apr 2022 10:43:41 -0700 Message-Id: <20220417174426.711829-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650218836310100001 Content-Type: text/plain; charset="utf-8" Use tcg_gen_umin_i32 instead of tcg_gen_movcond_i32. Use tcg_constant_i32 while we're at it. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 57631c9fa1..8d6534f9a5 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -568,12 +568,10 @@ GEN_SHIFT(shr) =20 static void gen_sar(TCGv_i32 dest, TCGv_i32 t0, TCGv_i32 t1) { - TCGv_i32 tmp1, tmp2; - tmp1 =3D tcg_temp_new_i32(); + TCGv_i32 tmp1 =3D tcg_temp_new_i32(); + tcg_gen_andi_i32(tmp1, t1, 0xff); - tmp2 =3D tcg_const_i32(0x1f); - tcg_gen_movcond_i32(TCG_COND_GTU, tmp1, tmp1, tmp2, tmp2, tmp1); - tcg_temp_free_i32(tmp2); + tcg_gen_umin_i32(tmp1, tmp1, tcg_constant_i32(31)); tcg_gen_sar_i32(dest, t0, tmp1); tcg_temp_free_i32(tmp1); } --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650218502; cv=none; d=zohomail.com; s=zohoarc; b=SPDn8/mlO4awlIHPVpe+lHaQtk0KVP+HnZcmaNkBRxESnuzCbi8G8pMEcxfRzYJJT7lBjpIzHTyJmX/fmePmqM84percqSLu+FQPFUXkZc1M1uzkB0L4ez2HzCVLeIAODHqEm+9fE8GJ0syLuuS0MkjZ+iucQzWveiGOdDjk2AU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650218502; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=T+qbueQADK/vfjH9sg1vNkUW9Au5lmMPxG4EP03Vc/s=; b=bJpPD5n3BljdRhvjSOre7ELQxPpUwe13f9j4s/NGav/oFfZSY+0nu0/bBgfClMrBa17Vuhl9UPZXQS30670n4pQQY/lcmVFlBndu87lPjO0uqF1HSBlEg3v4H/33Y7TtJdvuaFFUOkeyvSc898OBn6v4xXe8/C0wpcLW3ttwUKA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650218502913215.90384796377384; Sun, 17 Apr 2022 11:01:42 -0700 (PDT) Received: from localhost ([::1]:33024 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9DR-0007Qn-KQ for importer@patchew.org; Sun, 17 Apr 2022 14:01:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48098) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng8x5-0000iq-7g for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:48 -0400 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:43921) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng8x3-0003Jm-3E for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:46 -0400 Received: by mail-pg1-x532.google.com with SMTP id u2so14950417pgq.10 for ; Sun, 17 Apr 2022 10:44:44 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=T+qbueQADK/vfjH9sg1vNkUW9Au5lmMPxG4EP03Vc/s=; b=aySD4yBwds8m94r8eX+fNpZnJzukavDjz6GWEEYQXcYuhW+SoTf11yPk9b9FSLiRvQ /dQMLgqdOKfTCSyYfG8lWeS3HNNyZH6WiBiFBElJrP3xx1ttzlWfGvNxv7ke2dFCWwMy lEcoZ5auKUOCfGKLqw5Y1akblshYbXERu95YWjXYXvWftvuWQboERDOLvLB3/R09h/rg LNo2O17hMSrvV06vy7OYmCl2yKSdFcujSkET3q/XodSs0nQe4b+VmEZJLky+xgWDmBK+ jV/On1JngCVBw9VBqGYDrTuoRYDhxNJNqgnHcv3TQyNT6tUQIZFyoOruIagcYiSZFSG4 LiwA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=T+qbueQADK/vfjH9sg1vNkUW9Au5lmMPxG4EP03Vc/s=; b=0MXRHiUMoTlHyz8mAmOtu9YRI9sh0R5otays0b85mPjWBEpPFkaKCtNhG/jm+LBPoN 9n1hVj88TtF1SPaUR3gnzKBbo2NUAc4Oduu/VlgV8xlHN99evBRFc/NP2hXH+9ZOWB0r ChxmtbaoW92XakWiLSxE7GZ1VNGJTQQbv5dK9SlDzNQOweE4RBpq8kysvMixxzcXOUxF MNy29FFf3quIYphhdtelsEJL+Vk8gB8z+WI3C+p92GR81XNxA2kYQ5kEawk3UmxKxmLv 166TagvDwn4PWgonubbDuJ6//Nk44Y1k+z5dC+eoTzemADtm9t7uGl2fsbx69xT2J7N9 CVHg== X-Gm-Message-State: AOAM531waYB1GAqgiRJm6Q6jJJSZaaYnoh16YYIxXUJGxTCuTYsNdTAm 6TwnSbuPydMqX6Ch5quxYeiksoJtds3jvA== X-Google-Smtp-Source: ABdhPJyXbKumEIxSSCiJhSEJuYaRat8z7052DZeENRXcqnH118urX2K01Y8AzrhOWKaKTwvrLT9U5A== X-Received: by 2002:a05:6a00:b46:b0:508:2d0f:9f83 with SMTP id p6-20020a056a000b4600b005082d0f9f83mr8308075pfo.80.1650217483604; Sun, 17 Apr 2022 10:44:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 16/60] target/arm: Simplify aa32 DISAS_WFI Date: Sun, 17 Apr 2022 10:43:42 -0700 Message-Id: <20220417174426.711829-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650218505112100001 Content-Type: text/plain; charset="utf-8" The length of the previous insn may be computed from the difference of start and end addresses. Use tcg_constant_i32 while we're at it. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index 8d6534f9a5..e1c1dbc563 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -9870,18 +9870,14 @@ static void arm_tr_tb_stop(DisasContextBase *dcbase= , CPUState *cpu) /* nothing more to generate */ break; case DISAS_WFI: - { - TCGv_i32 tmp =3D tcg_const_i32((dc->thumb && - !(dc->insn & (1U << 31))) ? 2 : = 4); - - gen_helper_wfi(cpu_env, tmp); - tcg_temp_free_i32(tmp); - /* The helper doesn't necessarily throw an exception, but we + gen_helper_wfi(cpu_env, + tcg_constant_i32(dc->base.pc_next - dc->pc_curr= )); + /* + * The helper doesn't necessarily throw an exception, but we * must go back to the main loop to check for interrupts anywa= y. */ tcg_gen_exit_tb(NULL, 0); break; - } case DISAS_WFE: gen_helper_wfe(cpu_env); break; --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650218830; cv=none; d=zohomail.com; s=zohoarc; b=X+Br3BaoWinGyPEBdpfZbcnUwmoQ47q62R+HuJWXBS4LevBPeLZTHMEFM/ttBwGv+QGB4XhkNp7f1vT7w288qGwcxB0592zBFcp9mAbLyZih34y6T3by9t0FPaD5sep2kN35X/Vw2cu1oAC0G7FcgjE+oO3KM4sWThtsFSB40wk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650218830; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=V6Sw+Kw5igCtY28372OR+Z/+OWydY+yQWED9kzgh3iA=; b=T66yUjPS/qGRc/a9g+iWhQHoL1EShnuVxOA2seNpc84DUHELg8IWyICLTjJy4/I6Tl3qwSmX8eldF5+ROYBPeT+9RSLs5zqbhd0uaQ5ezo45dgK1RrQZQAHs4q10L+Gi8rAgyJdkw6c7hcqlY/DNSMBJ8KpZ6RBJBrPiskW2lro= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650218830066127.8011101608223; Sun, 17 Apr 2022 11:07:10 -0700 (PDT) Received: from localhost ([::1]:51748 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9Ii-00038M-SN for importer@patchew.org; Sun, 17 Apr 2022 14:07:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48178) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng8x8-0000lJ-7v for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:50 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:34705) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng8x5-0003K2-0M for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:49 -0400 Received: by mail-pl1-x62d.google.com with SMTP id n8so10761683plh.1 for ; Sun, 17 Apr 2022 10:44:45 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=V6Sw+Kw5igCtY28372OR+Z/+OWydY+yQWED9kzgh3iA=; b=Ey0JDQNbjHLk3vCelOf+nsPiPr1X4Q774SH7IbCBjGOJpB9b9Z8WeU66zTP8ASijMh L7lBixAJDdeIeBB8ngRrAPVWV+RVbe0KfifDy0ChsgECkAcPersgABvIoaiu5e7n5r/+ id1PJyKJetdNkStzJ0EyBOhSJIwi45GiRnyKBBNqPPgdvX+JqKiN748Oh3tLmC6U//my 2VenqN3NVaqXaly8Cs/a+jHiJ1H4PPXztvv5VGenRtCd0/zzE+HTD4VlHMYeKizE7UNc 1vFPBLH+9piDvToOcwdGBitHvSt2gGY69GJqbLZRNOZ29RbkA9xXIvZLPvaKWZw3aDXj XGbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=V6Sw+Kw5igCtY28372OR+Z/+OWydY+yQWED9kzgh3iA=; b=qQxjUcHi3DTLjD7Yz95/vLcA64xST1ae26fg29M7bPMkrGl+VxyvejCKo5rCwGGi72 Uv+c3CuXtGdT5XJnOrk3JXefq3PqJCeodrUVz1+8I084Nb8tL3tr25hdkgSN8DjZlUbY rx2faeGDlpggi44n+3ax2jFWJCUIVonS2bmxI0HFPgf7W8pl52a6wxrn6lTrXu0tNn1A 0eXd3A5jJTablVvqVgQTC7LyJEvTM3AB8MnRfm+UPJiwrfOBpsIa/4HIMpUA7p8fWyL1 lOHIVS+HYU/NgHmY8JwUsOPGc23kHzMrUfE7QXf3zyjNEaFVH4wGPhS2oQJwjMfeesQj IjiA== X-Gm-Message-State: AOAM53095a0E+vm4kIbB8f5VHLJHvindvirawvT7149SV4dr7Und3bZG y3sL8shGZWMW9qOwc/8Xplcj4wuBrUjGrw== X-Google-Smtp-Source: ABdhPJyQaFE+gmBgyD2elBtuKGuwcetuFL6FJNIQ4Yetru/uFY7JqNcoXIY9bV4j/4QebC+hxa1XLw== X-Received: by 2002:a17:902:ec8c:b0:154:2e86:dd51 with SMTP id x12-20020a170902ec8c00b001542e86dd51mr7629487plg.99.1650217484624; Sun, 17 Apr 2022 10:44:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 17/60] target/arm: Use tcg_constant in translate.c Date: Sun, 17 Apr 2022 10:43:43 -0700 Message-Id: <20220417174426.711829-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650218830355100001 Content-Type: text/plain; charset="utf-8" Use tcg_constant_{i32,i64,ptr} as appropriate throughout, which means we get to remove lots of tcg_temp_free_*. Drop variables in many cases, passing the constant directly to another function. Signed-off-by: Richard Henderson --- target/arm/translate.c | 250 ++++++++++++++--------------------------- 1 file changed, 84 insertions(+), 166 deletions(-) diff --git a/target/arm/translate.c b/target/arm/translate.c index e1c1dbc563..5cb4b3da33 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -346,9 +346,7 @@ static void store_sp_checked(DisasContext *s, TCGv_i32 = var) =20 void gen_set_cpsr(TCGv_i32 var, uint32_t mask) { - TCGv_i32 tmp_mask =3D tcg_const_i32(mask); - gen_helper_cpsr_write(cpu_env, var, tmp_mask); - tcg_temp_free_i32(tmp_mask); + gen_helper_cpsr_write(cpu_env, var, tcg_constant_i32(mask)); } =20 static void gen_rebuild_hflags(DisasContext *s, bool new_el) @@ -373,11 +371,8 @@ static void gen_rebuild_hflags(DisasContext *s, bool n= ew_el) =20 static void gen_exception_internal(int excp) { - TCGv_i32 tcg_excp =3D tcg_const_i32(excp); - assert(excp_is_internal(excp)); - gen_helper_exception_internal(cpu_env, tcg_excp); - tcg_temp_free_i32(tcg_excp); + gen_helper_exception_internal(cpu_env, tcg_constant_i32(excp)); } =20 static void gen_singlestep_exception(DisasContext *s) @@ -1078,12 +1073,8 @@ static inline void gen_smc(DisasContext *s) /* As with HVC, we may take an exception either before or after * the insn executes. */ - TCGv_i32 tmp; - gen_set_pc_im(s, s->pc_curr); - tmp =3D tcg_const_i32(syn_aa32_smc()); - gen_helper_pre_smc(cpu_env, tmp); - tcg_temp_free_i32(tmp); + gen_helper_pre_smc(cpu_env, tcg_constant_i32(syn_aa32_smc())); gen_set_pc_im(s, s->base.pc_next); s->base.is_jmp =3D DISAS_SMC; } @@ -1111,13 +1102,9 @@ void gen_exception_insn(DisasContext *s, uint64_t pc= , int excp, =20 static void gen_exception_bkpt_insn(DisasContext *s, uint32_t syn) { - TCGv_i32 tcg_syn; - gen_set_condexec(s); gen_set_pc_im(s, s->pc_curr); - tcg_syn =3D tcg_const_i32(syn); - gen_helper_exception_bkpt_insn(cpu_env, tcg_syn); - tcg_temp_free_i32(tcg_syn); + gen_helper_exception_bkpt_insn(cpu_env, tcg_constant_i32(syn)); s->base.is_jmp =3D DISAS_NORETURN; } =20 @@ -1131,16 +1118,11 @@ void unallocated_encoding(DisasContext *s) static void gen_exception_el(DisasContext *s, int excp, uint32_t syn, TCGv_i32 tcg_el) { - TCGv_i32 tcg_excp; - TCGv_i32 tcg_syn; - gen_set_condexec(s); gen_set_pc_im(s, s->pc_curr); - tcg_excp =3D tcg_const_i32(excp); - tcg_syn =3D tcg_const_i32(syn); - gen_helper_exception_with_syndrome(cpu_env, tcg_excp, tcg_syn, tcg_el); - tcg_temp_free_i32(tcg_syn); - tcg_temp_free_i32(tcg_excp); + gen_helper_exception_with_syndrome(cpu_env, + tcg_constant_i32(excp), + tcg_constant_i32(syn), tcg_el); s->base.is_jmp =3D DISAS_NORETURN; } =20 @@ -1863,24 +1845,21 @@ static int disas_iwmmxt_insn(DisasContext *s, uint3= 2_t insn) gen_op_iwmmxt_movq_M0_wRn(wrd); switch ((insn >> 6) & 3) { case 0: - tmp2 =3D tcg_const_i32(0xff); - tmp3 =3D tcg_const_i32((insn & 7) << 3); + tmp2 =3D tcg_constant_i32(0xff); + tmp3 =3D tcg_constant_i32((insn & 7) << 3); break; case 1: - tmp2 =3D tcg_const_i32(0xffff); - tmp3 =3D tcg_const_i32((insn & 3) << 4); + tmp2 =3D tcg_constant_i32(0xffff); + tmp3 =3D tcg_constant_i32((insn & 3) << 4); break; case 2: - tmp2 =3D tcg_const_i32(0xffffffff); - tmp3 =3D tcg_const_i32((insn & 1) << 5); + tmp2 =3D tcg_constant_i32(0xffffffff); + tmp3 =3D tcg_constant_i32((insn & 1) << 5); break; default: - tmp2 =3D NULL; - tmp3 =3D NULL; + g_assert_not_reached(); } gen_helper_iwmmxt_insr(cpu_M0, cpu_M0, tmp, tmp2, tmp3); - tcg_temp_free_i32(tmp3); - tcg_temp_free_i32(tmp2); tcg_temp_free_i32(tmp); gen_op_iwmmxt_movq_wRn_M0(wrd); gen_op_iwmmxt_set_mup(); @@ -2336,10 +2315,9 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32= _t insn) rd0 =3D (insn >> 16) & 0xf; rd1 =3D (insn >> 0) & 0xf; gen_op_iwmmxt_movq_M0_wRn(rd0); - tmp =3D tcg_const_i32((insn >> 20) & 3); iwmmxt_load_reg(cpu_V1, rd1); - gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, tmp); - tcg_temp_free_i32(tmp); + gen_helper_iwmmxt_align(cpu_M0, cpu_M0, cpu_V1, + tcg_constant_i32((insn >> 20) & 3)); gen_op_iwmmxt_movq_wRn_M0(wrd); gen_op_iwmmxt_set_mup(); break; @@ -2393,9 +2371,8 @@ static int disas_iwmmxt_insn(DisasContext *s, uint32_= t insn) wrd =3D (insn >> 12) & 0xf; rd0 =3D (insn >> 16) & 0xf; gen_op_iwmmxt_movq_M0_wRn(rd0); - tmp =3D tcg_const_i32(((insn >> 16) & 0xf0) | (insn & 0x0f)); + tmp =3D tcg_constant_i32(((insn >> 16) & 0xf0) | (insn & 0x0f)); gen_helper_iwmmxt_shufh(cpu_M0, cpu_env, cpu_M0, tmp); - tcg_temp_free_i32(tmp); gen_op_iwmmxt_movq_wRn_M0(wrd); gen_op_iwmmxt_set_mup(); gen_op_iwmmxt_set_cup(); @@ -2868,7 +2845,7 @@ static bool msr_banked_access_decode(DisasContext *s,= int r, int sysm, int rn, tcg_gen_sextract_i32(tcg_el, tcg_el, ctz32(SCR_EEL2), 1); tcg_gen_addi_i32(tcg_el, tcg_el, 3); } else { - tcg_el =3D tcg_const_i32(3); + tcg_el =3D tcg_constant_i32(3); } =20 gen_exception_el(s, EXCP_UDEF, syn_uncategorized(), tcg_el); @@ -2903,7 +2880,7 @@ undef: =20 static void gen_msr_banked(DisasContext *s, int r, int sysm, int rn) { - TCGv_i32 tcg_reg, tcg_tgtmode, tcg_regno; + TCGv_i32 tcg_reg; int tgtmode =3D 0, regno =3D 0; =20 if (!msr_banked_access_decode(s, r, sysm, rn, &tgtmode, ®no)) { @@ -2914,18 +2891,16 @@ static void gen_msr_banked(DisasContext *s, int r, = int sysm, int rn) gen_set_condexec(s); gen_set_pc_im(s, s->pc_curr); tcg_reg =3D load_reg(s, rn); - tcg_tgtmode =3D tcg_const_i32(tgtmode); - tcg_regno =3D tcg_const_i32(regno); - gen_helper_msr_banked(cpu_env, tcg_reg, tcg_tgtmode, tcg_regno); - tcg_temp_free_i32(tcg_tgtmode); - tcg_temp_free_i32(tcg_regno); + gen_helper_msr_banked(cpu_env, tcg_reg, + tcg_constant_i32(tgtmode), + tcg_constant_i32(regno)); tcg_temp_free_i32(tcg_reg); s->base.is_jmp =3D DISAS_UPDATE_EXIT; } =20 static void gen_mrs_banked(DisasContext *s, int r, int sysm, int rn) { - TCGv_i32 tcg_reg, tcg_tgtmode, tcg_regno; + TCGv_i32 tcg_reg; int tgtmode =3D 0, regno =3D 0; =20 if (!msr_banked_access_decode(s, r, sysm, rn, &tgtmode, ®no)) { @@ -2936,11 +2911,9 @@ static void gen_mrs_banked(DisasContext *s, int r, i= nt sysm, int rn) gen_set_condexec(s); gen_set_pc_im(s, s->pc_curr); tcg_reg =3D tcg_temp_new_i32(); - tcg_tgtmode =3D tcg_const_i32(tgtmode); - tcg_regno =3D tcg_const_i32(regno); - gen_helper_mrs_banked(tcg_reg, cpu_env, tcg_tgtmode, tcg_regno); - tcg_temp_free_i32(tcg_tgtmode); - tcg_temp_free_i32(tcg_regno); + gen_helper_mrs_banked(tcg_reg, cpu_env, + tcg_constant_i32(tgtmode), + tcg_constant_i32(regno)); store_reg(s, rn, tcg_reg); s->base.is_jmp =3D DISAS_UPDATE_EXIT; } @@ -3023,9 +2996,8 @@ void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_= ofs, uint32_t rn_ofs, } \ static void gen_##NAME##0_vec(unsigned vece, TCGv_vec d, TCGv_vec a) \ { \ - TCGv_vec zero =3D tcg_const_zeros_vec_matching(d); \ + TCGv_vec zero =3D tcg_constant_vec_matching(d, vece, 0); \ tcg_gen_cmp_vec(COND, vece, d, a, zero); \ - tcg_temp_free_vec(zero); \ } \ void gen_gvec_##NAME##0(unsigned vece, uint32_t d, uint32_t m, \ uint32_t opr_sz, uint32_t max_sz) \ @@ -4015,8 +3987,8 @@ void gen_ushl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i3= 2 shift) TCGv_i32 rval =3D tcg_temp_new_i32(); TCGv_i32 lsh =3D tcg_temp_new_i32(); TCGv_i32 rsh =3D tcg_temp_new_i32(); - TCGv_i32 zero =3D tcg_const_i32(0); - TCGv_i32 max =3D tcg_const_i32(32); + TCGv_i32 zero =3D tcg_constant_i32(0); + TCGv_i32 max =3D tcg_constant_i32(32); =20 /* * Rely on the TCG guarantee that out of range shifts produce @@ -4034,8 +4006,6 @@ void gen_ushl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i3= 2 shift) tcg_temp_free_i32(rval); tcg_temp_free_i32(lsh); tcg_temp_free_i32(rsh); - tcg_temp_free_i32(zero); - tcg_temp_free_i32(max); } =20 void gen_ushl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift) @@ -4044,8 +4014,8 @@ void gen_ushl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i6= 4 shift) TCGv_i64 rval =3D tcg_temp_new_i64(); TCGv_i64 lsh =3D tcg_temp_new_i64(); TCGv_i64 rsh =3D tcg_temp_new_i64(); - TCGv_i64 zero =3D tcg_const_i64(0); - TCGv_i64 max =3D tcg_const_i64(64); + TCGv_i64 zero =3D tcg_constant_i64(0); + TCGv_i64 max =3D tcg_constant_i64(64); =20 /* * Rely on the TCG guarantee that out of range shifts produce @@ -4063,8 +4033,6 @@ void gen_ushl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i6= 4 shift) tcg_temp_free_i64(rval); tcg_temp_free_i64(lsh); tcg_temp_free_i64(rsh); - tcg_temp_free_i64(zero); - tcg_temp_free_i64(max); } =20 static void gen_ushl_vec(unsigned vece, TCGv_vec dst, @@ -4159,8 +4127,8 @@ void gen_sshl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i3= 2 shift) TCGv_i32 rval =3D tcg_temp_new_i32(); TCGv_i32 lsh =3D tcg_temp_new_i32(); TCGv_i32 rsh =3D tcg_temp_new_i32(); - TCGv_i32 zero =3D tcg_const_i32(0); - TCGv_i32 max =3D tcg_const_i32(31); + TCGv_i32 zero =3D tcg_constant_i32(0); + TCGv_i32 max =3D tcg_constant_i32(31); =20 /* * Rely on the TCG guarantee that out of range shifts produce @@ -4179,8 +4147,6 @@ void gen_sshl_i32(TCGv_i32 dst, TCGv_i32 src, TCGv_i3= 2 shift) tcg_temp_free_i32(rval); tcg_temp_free_i32(lsh); tcg_temp_free_i32(rsh); - tcg_temp_free_i32(zero); - tcg_temp_free_i32(max); } =20 void gen_sshl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i64 shift) @@ -4189,8 +4155,8 @@ void gen_sshl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i6= 4 shift) TCGv_i64 rval =3D tcg_temp_new_i64(); TCGv_i64 lsh =3D tcg_temp_new_i64(); TCGv_i64 rsh =3D tcg_temp_new_i64(); - TCGv_i64 zero =3D tcg_const_i64(0); - TCGv_i64 max =3D tcg_const_i64(63); + TCGv_i64 zero =3D tcg_constant_i64(0); + TCGv_i64 max =3D tcg_constant_i64(63); =20 /* * Rely on the TCG guarantee that out of range shifts produce @@ -4209,8 +4175,6 @@ void gen_sshl_i64(TCGv_i64 dst, TCGv_i64 src, TCGv_i6= 4 shift) tcg_temp_free_i64(rval); tcg_temp_free_i64(lsh); tcg_temp_free_i64(rsh); - tcg_temp_free_i64(zero); - tcg_temp_free_i64(max); } =20 static void gen_sshl_vec(unsigned vece, TCGv_vec dst, @@ -4725,8 +4689,6 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, * Note that on XScale all cp0..c13 registers do an access che= ck * call in order to handle c15_cpar. */ - TCGv_ptr tmpptr; - TCGv_i32 tcg_syn, tcg_isread; uint32_t syndrome; =20 /* Note that since we are an implementation which takes an @@ -4769,14 +4731,10 @@ static void do_coproc_insn(DisasContext *s, int cpn= um, int is64, =20 gen_set_condexec(s); gen_set_pc_im(s, s->pc_curr); - tmpptr =3D tcg_const_ptr(ri); - tcg_syn =3D tcg_const_i32(syndrome); - tcg_isread =3D tcg_const_i32(isread); - gen_helper_access_check_cp_reg(cpu_env, tmpptr, tcg_syn, - tcg_isread); - tcg_temp_free_ptr(tmpptr); - tcg_temp_free_i32(tcg_syn); - tcg_temp_free_i32(tcg_isread); + gen_helper_access_check_cp_reg(cpu_env, + tcg_constant_ptr(ri), + tcg_constant_i32(syndrome), + tcg_constant_i32(isread)); } else if (ri->type & ARM_CP_RAISES_EXC) { /* * The readfn or writefn might raise an exception; @@ -4812,13 +4770,11 @@ static void do_coproc_insn(DisasContext *s, int cpn= um, int is64, TCGv_i64 tmp64; TCGv_i32 tmp; if (ri->type & ARM_CP_CONST) { - tmp64 =3D tcg_const_i64(ri->resetvalue); + tmp64 =3D tcg_constant_i64(ri->resetvalue); } else if (ri->readfn) { - TCGv_ptr tmpptr; tmp64 =3D tcg_temp_new_i64(); - tmpptr =3D tcg_const_ptr(ri); - gen_helper_get_cp_reg64(tmp64, cpu_env, tmpptr); - tcg_temp_free_ptr(tmpptr); + gen_helper_get_cp_reg64(tmp64, cpu_env, + tcg_constant_ptr(ri)); } else { tmp64 =3D tcg_temp_new_i64(); tcg_gen_ld_i64(tmp64, cpu_env, ri->fieldoffset); @@ -4833,13 +4789,10 @@ static void do_coproc_insn(DisasContext *s, int cpn= um, int is64, } else { TCGv_i32 tmp; if (ri->type & ARM_CP_CONST) { - tmp =3D tcg_const_i32(ri->resetvalue); + tmp =3D tcg_constant_i32(ri->resetvalue); } else if (ri->readfn) { - TCGv_ptr tmpptr; tmp =3D tcg_temp_new_i32(); - tmpptr =3D tcg_const_ptr(ri); - gen_helper_get_cp_reg(tmp, cpu_env, tmpptr); - tcg_temp_free_ptr(tmpptr); + gen_helper_get_cp_reg(tmp, cpu_env, tcg_constant_ptr(r= i)); } else { tmp =3D load_cpu_offset(ri->fieldoffset); } @@ -4869,24 +4822,18 @@ static void do_coproc_insn(DisasContext *s, int cpn= um, int is64, tcg_temp_free_i32(tmplo); tcg_temp_free_i32(tmphi); if (ri->writefn) { - TCGv_ptr tmpptr =3D tcg_const_ptr(ri); - gen_helper_set_cp_reg64(cpu_env, tmpptr, tmp64); - tcg_temp_free_ptr(tmpptr); + gen_helper_set_cp_reg64(cpu_env, tcg_constant_ptr(ri), + tmp64); } else { tcg_gen_st_i64(tmp64, cpu_env, ri->fieldoffset); } tcg_temp_free_i64(tmp64); } else { + TCGv_i32 tmp =3D load_reg(s, rt); if (ri->writefn) { - TCGv_i32 tmp; - TCGv_ptr tmpptr; - tmp =3D load_reg(s, rt); - tmpptr =3D tcg_const_ptr(ri); - gen_helper_set_cp_reg(cpu_env, tmpptr, tmp); - tcg_temp_free_ptr(tmpptr); + gen_helper_set_cp_reg(cpu_env, tcg_constant_ptr(ri), t= mp); tcg_temp_free_i32(tmp); } else { - TCGv_i32 tmp =3D load_reg(s, rt); store_cpu_offset(tmp, ri->fieldoffset, 4); } } @@ -5190,12 +5137,10 @@ static void gen_srs(DisasContext *s, } =20 addr =3D tcg_temp_new_i32(); - tmp =3D tcg_const_i32(mode); /* get_r13_banked() will raise an exception if called from System mode= */ gen_set_condexec(s); gen_set_pc_im(s, s->pc_curr); - gen_helper_get_r13_banked(addr, cpu_env, tmp); - tcg_temp_free_i32(tmp); + gen_helper_get_r13_banked(addr, cpu_env, tcg_constant_i32(mode)); switch (amode) { case 0: /* DA */ offset =3D -4; @@ -5238,9 +5183,7 @@ static void gen_srs(DisasContext *s, abort(); } tcg_gen_addi_i32(addr, addr, offset); - tmp =3D tcg_const_i32(mode); - gen_helper_set_r13_banked(cpu_env, tmp, addr); - tcg_temp_free_i32(tmp); + gen_helper_set_r13_banked(cpu_env, tcg_constant_i32(mode), addr); } tcg_temp_free_i32(addr); s->base.is_jmp =3D DISAS_UPDATE_EXIT; @@ -5552,23 +5495,21 @@ static bool op_s_rri_rot(DisasContext *s, arg_s_rri= _rot *a, void (*gen)(TCGv_i32, TCGv_i32, TCGv_i32), int logic_cc, StoreRegKind kind) { - TCGv_i32 tmp1, tmp2; + TCGv_i32 tmp; uint32_t imm; =20 imm =3D ror32(a->imm, a->rot); if (logic_cc && a->rot) { tcg_gen_movi_i32(cpu_CF, imm >> 31); } - tmp2 =3D tcg_const_i32(imm); - tmp1 =3D load_reg(s, a->rn); + tmp =3D load_reg(s, a->rn); =20 - gen(tmp1, tmp1, tmp2); - tcg_temp_free_i32(tmp2); + gen(tmp, tmp, tcg_constant_i32(imm)); =20 if (logic_cc) { - gen_logic_CC(tmp1); + gen_logic_CC(tmp); } - return store_reg_kind(s, a->rd, tmp1, kind); + return store_reg_kind(s, a->rd, tmp, kind); } =20 static bool op_s_rxi_rot(DisasContext *s, arg_s_rri_rot *a, @@ -5582,9 +5523,10 @@ static bool op_s_rxi_rot(DisasContext *s, arg_s_rri_= rot *a, if (logic_cc && a->rot) { tcg_gen_movi_i32(cpu_CF, imm >> 31); } - tmp =3D tcg_const_i32(imm); =20 - gen(tmp, tmp); + tmp =3D tcg_temp_new_i32(); + gen(tmp, tcg_constant_i32(imm)); + if (logic_cc) { gen_logic_CC(tmp); } @@ -5710,14 +5652,11 @@ static bool trans_ADR(DisasContext *s, arg_ri *a) =20 static bool trans_MOVW(DisasContext *s, arg_MOVW *a) { - TCGv_i32 tmp; - if (!ENABLE_ARCH_6T2) { return false; } =20 - tmp =3D tcg_const_i32(a->imm); - store_reg(s, a->rd, tmp); + store_reg(s, a->rd, tcg_constant_i32(a->imm)); return true; } =20 @@ -6088,14 +6027,13 @@ static bool trans_UMAAL(DisasContext *s, arg_UMAAL = *a) t0 =3D load_reg(s, a->rm); t1 =3D load_reg(s, a->rn); tcg_gen_mulu2_i32(t0, t1, t0, t1); - zero =3D tcg_const_i32(0); + zero =3D tcg_constant_i32(0); t2 =3D load_reg(s, a->ra); tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero); tcg_temp_free_i32(t2); t2 =3D load_reg(s, a->rd); tcg_gen_add2_i32(t0, t1, t0, t1, t2, zero); tcg_temp_free_i32(t2); - tcg_temp_free_i32(zero); store_reg(s, a->ra, t0); store_reg(s, a->rd, t1); return true; @@ -6342,14 +6280,13 @@ static bool op_crc32(DisasContext *s, arg_rrr *a, b= ool c, MemOp sz) default: g_assert_not_reached(); } - t3 =3D tcg_const_i32(1 << sz); + t3 =3D tcg_constant_i32(1 << sz); if (c) { gen_helper_crc32c(t1, t1, t2, t3); } else { gen_helper_crc32(t1, t1, t2, t3); } tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); store_reg(s, a->rd, t1); return true; } @@ -6432,8 +6369,8 @@ static bool trans_MRS_v7m(DisasContext *s, arg_MRS_v7= m *a) if (!arm_dc_feature(s, ARM_FEATURE_M)) { return false; } - tmp =3D tcg_const_i32(a->sysm); - gen_helper_v7m_mrs(tmp, cpu_env, tmp); + tmp =3D tcg_temp_new_i32(); + gen_helper_v7m_mrs(tmp, cpu_env, tcg_constant_i32(a->sysm)); store_reg(s, a->rd, tmp); return true; } @@ -6445,10 +6382,9 @@ static bool trans_MSR_v7m(DisasContext *s, arg_MSR_v= 7m *a) if (!arm_dc_feature(s, ARM_FEATURE_M)) { return false; } - addr =3D tcg_const_i32((a->mask << 10) | a->sysm); + addr =3D tcg_constant_i32((a->mask << 10) | a->sysm); reg =3D load_reg(s, a->rn); gen_helper_v7m_msr(cpu_env, addr, reg); - tcg_temp_free_i32(addr); tcg_temp_free_i32(reg); /* If we wrote to CONTROL, the EL might have changed */ gen_rebuild_hflags(s, true); @@ -6660,8 +6596,8 @@ static bool trans_TT(DisasContext *s, arg_TT *a) } =20 addr =3D load_reg(s, a->rn); - tmp =3D tcg_const_i32((a->A << 1) | a->T); - gen_helper_v7m_tt(tmp, cpu_env, addr, tmp); + tmp =3D tcg_temp_new_i32(); + gen_helper_v7m_tt(tmp, cpu_env, addr, tcg_constant_i32((a->A << 1) | a= ->T)); tcg_temp_free_i32(addr); store_reg(s, a->rd, tmp); return true; @@ -7628,7 +7564,7 @@ static bool trans_PKH(DisasContext *s, arg_PKH *a) static bool op_sat(DisasContext *s, arg_sat *a, void (*gen)(TCGv_i32, TCGv_env, TCGv_i32, TCGv_i32)) { - TCGv_i32 tmp, satimm; + TCGv_i32 tmp; int shift =3D a->imm; =20 if (!ENABLE_ARCH_6) { @@ -7642,9 +7578,7 @@ static bool op_sat(DisasContext *s, arg_sat *a, tcg_gen_shli_i32(tmp, tmp, shift); } =20 - satimm =3D tcg_const_i32(a->satimm); - gen(tmp, cpu_env, tmp, satimm); - tcg_temp_free_i32(satimm); + gen(tmp, cpu_env, tmp, tcg_constant_i32(a->satimm)); =20 store_reg(s, a->rd, tmp); return true; @@ -7979,9 +7913,7 @@ static bool op_smmla(DisasContext *s, arg_rrrr *a, bo= ol round, bool sub) * a non-zero multiplicand lowpart, and the correct result * lowpart for rounding. */ - TCGv_i32 zero =3D tcg_const_i32(0); - tcg_gen_sub2_i32(t2, t1, zero, t3, t2, t1); - tcg_temp_free_i32(zero); + tcg_gen_sub2_i32(t2, t1, tcg_constant_i32(0), t3, t2, t1); } else { tcg_gen_add_i32(t1, t1, t3); } @@ -8118,7 +8050,7 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a= , int min_n) { int i, j, n, list, mem_idx; bool user =3D a->u; - TCGv_i32 addr, tmp, tmp2; + TCGv_i32 addr, tmp; =20 if (user) { /* STM (user) */ @@ -8148,9 +8080,7 @@ static bool op_stm(DisasContext *s, arg_ldst_block *a= , int min_n) =20 if (user && i !=3D 15) { tmp =3D tcg_temp_new_i32(); - tmp2 =3D tcg_const_i32(i); - gen_helper_get_user_reg(tmp, cpu_env, tmp2); - tcg_temp_free_i32(tmp2); + gen_helper_get_user_reg(tmp, cpu_env, tcg_constant_i32(i)); } else { tmp =3D load_reg(s, i); } @@ -8191,7 +8121,7 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a= , int min_n) bool loaded_base; bool user =3D a->u; bool exc_return =3D false; - TCGv_i32 addr, tmp, tmp2, loaded_var; + TCGv_i32 addr, tmp, loaded_var; =20 if (user) { /* LDM (user), LDM (exception return) */ @@ -8234,9 +8164,7 @@ static bool do_ldm(DisasContext *s, arg_ldst_block *a= , int min_n) tmp =3D tcg_temp_new_i32(); gen_aa32_ld_i32(s, tmp, addr, mem_idx, MO_UL | MO_ALIGN); if (user) { - tmp2 =3D tcg_const_i32(i); - gen_helper_set_user_reg(cpu_env, tmp2, tmp); - tcg_temp_free_i32(tmp2); + gen_helper_set_user_reg(cpu_env, tcg_constant_i32(i), tmp); tcg_temp_free_i32(tmp); } else if (i =3D=3D a->rn) { loaded_var =3D tmp; @@ -8329,7 +8257,7 @@ static bool trans_CLRM(DisasContext *s, arg_CLRM *a) =20 s->eci_handled =3D true; =20 - zero =3D tcg_const_i32(0); + zero =3D tcg_constant_i32(0); for (i =3D 0; i < 15; i++) { if (extract32(a->list, i, 1)) { /* Clear R[i] */ @@ -8341,11 +8269,8 @@ static bool trans_CLRM(DisasContext *s, arg_CLRM *a) * Clear APSR (by calling the MSR helper with the same argument * as for "MSR APSR_nzcvqg, Rn": mask =3D 0b1100, SYSM=3D0) */ - TCGv_i32 maskreg =3D tcg_const_i32(0xc << 8); - gen_helper_v7m_msr(cpu_env, maskreg, zero); - tcg_temp_free_i32(maskreg); + gen_helper_v7m_msr(cpu_env, tcg_constant_i32(0xc00), zero); } - tcg_temp_free_i32(zero); clear_eci_state(s); return true; } @@ -8488,8 +8413,7 @@ static bool trans_DLS(DisasContext *s, arg_DLS *a) store_reg(s, 14, tmp); if (a->size !=3D 4) { /* DLSTP: set FPSCR.LTPSIZE */ - tmp =3D tcg_const_i32(a->size); - store_cpu_field(tmp, v7m.ltpsize); + store_cpu_field(tcg_constant_i32(a->size), v7m.ltpsize); s->base.is_jmp =3D DISAS_UPDATE_NOCHAIN; } return true; @@ -8554,8 +8478,7 @@ static bool trans_WLS(DisasContext *s, arg_WLS *a) */ bool ok =3D vfp_access_check(s); assert(ok); - tmp =3D tcg_const_i32(a->size); - store_cpu_field(tmp, v7m.ltpsize); + store_cpu_field(tcg_constant_i32(a->size), v7m.ltpsize); /* * LTPSIZE updated, but MVE_NO_PRED will always be the same thing = (0) * when we take this upcoming exit from this TB, so gen_jmp_tb() i= s OK. @@ -8681,8 +8604,7 @@ static bool trans_LE(DisasContext *s, arg_LE *a) gen_set_label(loopend); if (a->tp) { /* Exits from tail-pred loops must reset LTPSIZE to 4 */ - tmp =3D tcg_const_i32(4); - store_cpu_field(tmp, v7m.ltpsize); + store_cpu_field(tcg_constant_i32(4), v7m.ltpsize); } /* End TB, continuing to following insn */ gen_jmp_tb(s, s->base.pc_next, 1); @@ -8913,21 +8835,18 @@ static bool trans_CPS_v7m(DisasContext *s, arg_CPS_= v7m *a) return true; } =20 - tmp =3D tcg_const_i32(a->im); + tmp =3D tcg_constant_i32(a->im); /* FAULTMASK */ if (a->F) { - addr =3D tcg_const_i32(19); + addr =3D tcg_constant_i32(19); gen_helper_v7m_msr(cpu_env, addr, tmp); - tcg_temp_free_i32(addr); } /* PRIMASK */ if (a->I) { - addr =3D tcg_const_i32(16); + addr =3D tcg_constant_i32(16); gen_helper_v7m_msr(cpu_env, addr, tmp); - tcg_temp_free_i32(addr); } gen_rebuild_hflags(s, false); - tcg_temp_free_i32(tmp); gen_lookup_tb(s); return true; } @@ -9063,13 +8982,14 @@ static bool trans_CSEL(DisasContext *s, arg_CSEL *a) } =20 /* In this insn input reg fields of 0b1111 mean "zero", not "PC" */ + zero =3D tcg_constant_i32(0); if (a->rn =3D=3D 15) { - rn =3D tcg_const_i32(0); + rn =3D zero; } else { rn =3D load_reg(s, a->rn); } if (a->rm =3D=3D 15) { - rm =3D tcg_const_i32(0); + rm =3D zero; } else { rm =3D load_reg(s, a->rm); } @@ -9091,10 +9011,8 @@ static bool trans_CSEL(DisasContext *s, arg_CSEL *a) } =20 arm_test_cc(&c, a->fcond); - zero =3D tcg_const_i32(0); tcg_gen_movcond_i32(c.cond, rn, c.value, zero, rn, rm); arm_free_cc(&c); - tcg_temp_free_i32(zero); =20 store_reg(s, a->rd, rn); tcg_temp_free_i32(rm); --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650218529; cv=none; d=zohomail.com; s=zohoarc; b=jo1rXYvURafngie8LbQsdvXIPcAmTLnG4eHBty3nA04t7sUkfGXHFY8ttGnLObad+lDnav0pCzK0RwTKjwUko13NEI3iuVM2wvitMKOTZyE8RdYeFJOfbaa5DRIKmp8aWY30uPNu9LT8xxe+Gg0ApWxGgLA5ryMIbn8YKTqZTDs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=IAIkA9WY+ynIkbE8B6qs1qYR9g0d4GyKrWJIQLT3oZA=; b=O8+5AEenqKsSi/tqs2XN7GmHHAC0qCtuR9TYGKlfMLI9yLN2JRLEIYJyfFXaU8mnNb 4ONd5YwXui4ZbYee1FtQduBcVKHwqd4Kc4hZGyw5uSk5rXPvy2FvmQBA86coUjRRJJW/ 2ZuRmqhtx6ICwWKJcq8fp+9kEn3b5jWOHXbgwe1Ix/IxzK1sE2Taofdf2JKPRhsRHnP7 XxSUJhEQ+jUZr3Vw8b1GPwx49nYOVvw86B8qBkLOVAZ97sCOlKcLU5W1wFLaQUYoy/Y4 9RTActJcGEz16EMZrFKesN+pNoJ+yK/ZxOgd3s5rw03VvgNazjUljL3rA9I+T16liqlI W8fA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IAIkA9WY+ynIkbE8B6qs1qYR9g0d4GyKrWJIQLT3oZA=; b=WtRIE7assqB5VUgLLcAiiEjFaYAYz1wCHeq0G2HQ5HkfB+bfvmLtKdKeE58qrs8wWM XYxpbsKAfqZ/FGByf5RwNd1qAA55iX09brS7RAiLAGkd95+Aq6r+wisYZit/f+aXQ1DK bc35TJRw9tzLA74VeQeQhJPwSZgz+Eiit260KJdjQba6yRIhBIK9s2Q72J/kxiimWjBs VAh386+V/7tRbAsjknV6KdxVlz4ik7i2iYZrYXTXXQSx+QNlB8wJhaPWlaUxNolErqp8 aY53eNTVJ8Kf+Rw9VjMLAg+h4mcjMjyRkLjfu77klGQRZAwLHa2BB86AT6MHR6GLUvWe +mWA== X-Gm-Message-State: AOAM530C1JDodRVcmxX2kMx+jK8saKkw6j7il5MXV7Ft/ikP2s0I5PSj DBAFFesGSjUyX0ELScRG41sGfK8SM9580w== X-Google-Smtp-Source: ABdhPJyO+MMSQjuSGhPsqjdmDG+SnHKk8eqHWv8TYT5OVFqjVrlq/M+8KVvw/rQBlKQpJ461QUjVmg== X-Received: by 2002:a63:5115:0:b0:39c:d48d:1b87 with SMTP id f21-20020a635115000000b0039cd48d1b87mr7299197pgb.107.1650217485735; Sun, 17 Apr 2022 10:44:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 18/60] target/arm: Use tcg_constant in translate-m-nocp.c Date: Sun, 17 Apr 2022 10:43:44 -0700 Message-Id: <20220417174426.711829-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650218531038100003 Content-Type: text/plain; charset="utf-8" Use tcg_constant_{i32,i64} as appropriate throughout. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-m-nocp.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/target/arm/translate-m-nocp.c b/target/arm/translate-m-nocp.c index d9e144e8eb..27363a7b4e 100644 --- a/target/arm/translate-m-nocp.c +++ b/target/arm/translate-m-nocp.c @@ -173,7 +173,7 @@ static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM = *a) } =20 /* Zero the Sregs from btmreg to topreg inclusive. */ - zero =3D tcg_const_i64(0); + zero =3D tcg_constant_i64(0); if (btmreg & 1) { write_neon_element64(zero, btmreg >> 1, 1, MO_32); btmreg++; @@ -187,8 +187,7 @@ static bool trans_VSCCLRM(DisasContext *s, arg_VSCCLRM = *a) } assert(btmreg =3D=3D topreg + 1); if (dc_isar_feature(aa32_mve, s)) { - TCGv_i32 z32 =3D tcg_const_i32(0); - store_cpu_field(z32, v7m.vpr); + store_cpu_field(tcg_constant_i32(0), v7m.vpr); } =20 clear_eci_state(s); @@ -512,7 +511,7 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int r= egno, } case ARM_VFP_FPCXT_NS: { - TCGv_i32 control, sfpa, fpscr, fpdscr, zero; + TCGv_i32 control, sfpa, fpscr, fpdscr; TCGLabel *lab_active =3D gen_new_label(); =20 lookup_tb =3D true; @@ -552,10 +551,9 @@ static bool gen_M_fp_sysreg_read(DisasContext *s, int = regno, storefn(s, opaque, tmp, true); /* If SFPA is zero then set FPSCR from FPDSCR_NS */ fpdscr =3D load_cpu_field(v7m.fpdscr[M_REG_NS]); - zero =3D tcg_const_i32(0); - tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, zero, fpdscr, fpscr); + tcg_gen_movcond_i32(TCG_COND_EQ, fpscr, sfpa, tcg_constant_i32(0), + fpdscr, fpscr); gen_helper_vfp_set_fpscr(cpu_env, fpscr); - tcg_temp_free_i32(zero); tcg_temp_free_i32(sfpa); tcg_temp_free_i32(fpdscr); tcg_temp_free_i32(fpscr); --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650219047; cv=none; d=zohomail.com; s=zohoarc; b=Cyyw0S9Cc+uA8lNdwT5uYUU7INwQrCiRg55+bmonCjFVJ+WpFErxka2d0GyzI7wzbL/zgfh2D0nptBaC/3Hcn+zhz4zpJ37jA8xBXYlwE2dzDV+E5tyHpwk8/p+ATttfJkkxt23oQ2gJuSnHiT7Tzv/mVNSRvVD/af6FIHox5rw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650219047; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=R9t04A2fMNf/j0rLfzwp96zli6WbNRwThiKfiyjip1Q=; b=AdBosfspJ7NgdglfrJeK1LQgHYBz9G9uzF4aGkq7YfVjTVsEVlM9q2y4zkDpDXk3CDkEJj0H12/7mpl7NlNI7uhdVdMy6E4HVzYItaGGC2i9NTql7h+J270b0RJ69/zLEry1oLK9Gu4jJX/f6DqgVF26eVxWW9RZAQ2vlPYsWys= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650219047180514.2307881283277; Sun, 17 Apr 2022 11:10:47 -0700 (PDT) Received: from localhost ([::1]:34136 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9MD-0001lp-Po for importer@patchew.org; Sun, 17 Apr 2022 14:10:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48232) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng8x9-0000mH-BB for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:51 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:45720) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng8x6-0003Ka-CI for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:51 -0400 Received: by mail-pj1-x1034.google.com with SMTP id n33-20020a17090a5aa400b001d28f5ee3f9so732945pji.4 for ; Sun, 17 Apr 2022 10:44:47 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=R9t04A2fMNf/j0rLfzwp96zli6WbNRwThiKfiyjip1Q=; b=pjAgOhvO4E7QNWcocOq2KdCapxIekgveVEVmm43mVJpFBMAHBGZN1h1sQvkYsyLnrl c02SULDFsXOIs8MhWk6ox0xfVJz/kd2o82q11AwSLnKzn4SLGuJEpsEL7XctQ7Ltthn0 a9kSwsXW2SgMjn2n0rX5odm50rfDmbZNAvbliIliQEqm3g2MLbksvsrb+JtVmBWreR3g EWxzKnNXH77XfghkB+HSXz4QTibUgqdM1mNe1MnE1do5UvSK1LsaR5powSbqwrowFNrG Q6Wr8/1TgrBu+9oJTgovR5k6sjMAjrmzV2rBd9r507km9GGSRyofEUdyOlwuWT3gljRy bDvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=R9t04A2fMNf/j0rLfzwp96zli6WbNRwThiKfiyjip1Q=; b=TWPtYMwfrxy2K0MaIixPFL2A7oYJXEQY6L3UF/uWhZ/LEyWQDccr52KU9SLrwOmBwI Dn42zOmrQcetHp1MeBiUMFkYMFxuGD8HRnBr8oBUA3zbybBIRnxSuBpsZsHRhIfQ4t4N 5e5FGztRzFommijenkGWtpjQNDEvFua/qGZHKG4vxJKw0A8Y2FQc1AxNiUxW/3gEotV1 rNthUG6xGxv6D4EeKttkZKOeRPMyiNRs8ZxmJ9ODK6yEdry+NrRG3U5CndES70yOscRZ w49lKQqu29gOL9c1KbIEibdohPcZQa32veLxRhoKxvcynAzhHgtSZNXDpn5RoCw6Vl+j lXcw== X-Gm-Message-State: AOAM5302yRRpqqINpZNtEilOzzQCjOZQ8TCZr+S7ysfPd7v2Lv04KVrW O+xQG7WKQTM/DXehC9xMbiDIYFLQGELzIg== X-Google-Smtp-Source: ABdhPJxkLL8oqm8nGGC4gLBM5OtTv7rWRJKxY4HqrFhdd6minrT7sMj+9L3OK3+HEW5CXUop0+WuXg== X-Received: by 2002:a17:90b:4f45:b0:1d2:21e5:905d with SMTP id pj5-20020a17090b4f4500b001d221e5905dmr8047847pjb.18.1650217486584; Sun, 17 Apr 2022 10:44:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 19/60] target/arm: Use tcg_constant in translate-neon.c Date: Sun, 17 Apr 2022 10:43:45 -0700 Message-Id: <20220417174426.711829-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650219049151100001 Content-Type: text/plain; charset="utf-8" Use tcg_constant_{i32,i64} as appropriate throughout. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-neon.c | 21 +++++++-------------- 1 file changed, 7 insertions(+), 14 deletions(-) diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c index 384604c009..2e4d1ec87d 100644 --- a/target/arm/translate-neon.c +++ b/target/arm/translate-neon.c @@ -447,7 +447,7 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_V= LDST_multiple *a) int mmu_idx =3D get_mem_index(s); int size =3D a->size; TCGv_i64 tmp64; - TCGv_i32 addr, tmp; + TCGv_i32 addr; =20 if (!arm_dc_feature(s, ARM_FEATURE_NEON)) { return false; @@ -513,7 +513,6 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_V= LDST_multiple *a) =20 tmp64 =3D tcg_temp_new_i64(); addr =3D tcg_temp_new_i32(); - tmp =3D tcg_const_i32(1 << size); load_reg_var(s, addr, a->rn); =20 mop =3D endian | size | align; @@ -530,7 +529,7 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_V= LDST_multiple *a) neon_load_element64(tmp64, tt, n, size); gen_aa32_st_internal_i64(s, tmp64, addr, mmu_idx, mop); } - tcg_gen_add_i32(addr, addr, tmp); + tcg_gen_addi_i32(addr, addr, 1 << size); =20 /* Subsequent memory operations inherit alignment */ mop &=3D ~MO_AMASK; @@ -538,7 +537,6 @@ static bool trans_VLDST_multiple(DisasContext *s, arg_V= LDST_multiple *a) } } tcg_temp_free_i32(addr); - tcg_temp_free_i32(tmp); tcg_temp_free_i64(tmp64); =20 gen_neon_ldst_base_update(s, a->rm, a->rn, nregs * interleave * 8); @@ -1348,7 +1346,7 @@ static bool do_2shift_env_64(DisasContext *s, arg_2re= g_shift *a, * To avoid excessive duplication of ops we implement shift * by immediate using the variable shift operations. */ - constimm =3D tcg_const_i64(dup_const(a->size, a->shift)); + constimm =3D tcg_constant_i64(dup_const(a->size, a->shift)); =20 for (pass =3D 0; pass < a->q + 1; pass++) { TCGv_i64 tmp =3D tcg_temp_new_i64(); @@ -1358,7 +1356,6 @@ static bool do_2shift_env_64(DisasContext *s, arg_2re= g_shift *a, write_neon_element64(tmp, a->vd, pass, MO_64); tcg_temp_free_i64(tmp); } - tcg_temp_free_i64(constimm); return true; } =20 @@ -1394,7 +1391,7 @@ static bool do_2shift_env_32(DisasContext *s, arg_2re= g_shift *a, * To avoid excessive duplication of ops we implement shift * by immediate using the variable shift operations. */ - constimm =3D tcg_const_i32(dup_const(a->size, a->shift)); + constimm =3D tcg_constant_i32(dup_const(a->size, a->shift)); tmp =3D tcg_temp_new_i32(); =20 for (pass =3D 0; pass < (a->q ? 4 : 2); pass++) { @@ -1403,7 +1400,6 @@ static bool do_2shift_env_32(DisasContext *s, arg_2re= g_shift *a, write_neon_element32(tmp, a->vd, pass, MO_32); } tcg_temp_free_i32(tmp); - tcg_temp_free_i32(constimm); return true; } =20 @@ -1457,7 +1453,7 @@ static bool do_2shift_narrow_64(DisasContext *s, arg_= 2reg_shift *a, * This is always a right shift, and the shiftfn is always a * left-shift helper, which thus needs the negated shift count. */ - constimm =3D tcg_const_i64(-a->shift); + constimm =3D tcg_constant_i64(-a->shift); rm1 =3D tcg_temp_new_i64(); rm2 =3D tcg_temp_new_i64(); rd =3D tcg_temp_new_i32(); @@ -1477,7 +1473,6 @@ static bool do_2shift_narrow_64(DisasContext *s, arg_= 2reg_shift *a, tcg_temp_free_i32(rd); tcg_temp_free_i64(rm1); tcg_temp_free_i64(rm2); - tcg_temp_free_i64(constimm); =20 return true; } @@ -1521,7 +1516,7 @@ static bool do_2shift_narrow_32(DisasContext *s, arg_= 2reg_shift *a, /* size =3D=3D 2 */ imm =3D -a->shift; } - constimm =3D tcg_const_i32(imm); + constimm =3D tcg_constant_i32(imm); =20 /* Load all inputs first to avoid potential overwrite */ rm1 =3D tcg_temp_new_i32(); @@ -1546,7 +1541,6 @@ static bool do_2shift_narrow_32(DisasContext *s, arg_= 2reg_shift *a, =20 shiftfn(rm3, rm3, constimm); shiftfn(rm4, rm4, constimm); - tcg_temp_free_i32(constimm); =20 tcg_gen_concat_i32_i64(rtmp, rm3, rm4); tcg_temp_free_i32(rm4); @@ -2911,7 +2905,7 @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a) return true; } =20 - desc =3D tcg_const_i32((a->vn << 2) | a->len); + desc =3D tcg_constant_i32((a->vn << 2) | a->len); def =3D tcg_temp_new_i64(); if (a->op) { read_neon_element64(def, a->vd, 0, MO_64); @@ -2926,7 +2920,6 @@ static bool trans_VTBL(DisasContext *s, arg_VTBL *a) =20 tcg_temp_free_i64(def); tcg_temp_free_i64(val); - tcg_temp_free_i32(desc); return true; } =20 --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650218677; cv=none; d=zohomail.com; s=zohoarc; b=EQsv2TZPiGoEO6X248+Z4PwagDB1P95pYzGhvYHcv+PF2Q7a4DhcvetpnihZDDt7WIIl6sJ+lWeS6cuKnBHK9M/KRiDDfKNX2chCG9ieN3Vyihgn0ShffMGBUAlSjmNWC81OcsAi7UCh11/rsrrhNrLMuYYPx9ma0/HUKhxBnkM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650218677; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rwqJPJ//6TQT5UmISyCch80APlTh3KWpu8wgkVgb10g=; b=CAKKQ39XQRha+t6XzpqCyoLQMPoJmOyTJAtJaCeuqyDTNC/28O8ojFHrkIBv0movZJOzdplDayCVGgrr4XJjKXCTtOOzk8lBM9+Mm44o/cvM4fHAJrXFT/dIokKcrmViHyueKOSHuzTPWJ68LUje844TG+5jyeNV27r4UmCfszw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650218677346104.61607559230754; Sun, 17 Apr 2022 11:04:37 -0700 (PDT) Received: from localhost ([::1]:43098 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9GG-0005k5-9h for importer@patchew.org; Sun, 17 Apr 2022 14:04:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48266) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng8xA-0000pF-Cp for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:52 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]:37669) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng8x6-0003LC-GT for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:52 -0400 Received: by mail-pg1-x534.google.com with SMTP id t184so1964335pgd.4 for ; Sun, 17 Apr 2022 10:44:48 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rwqJPJ//6TQT5UmISyCch80APlTh3KWpu8wgkVgb10g=; b=US1SyCFaW/3LmCuUoc+LgmazZxmkCpZZpzMxB4hNYsFVGlTquh7Y86bMsdauF4M2Rn NOyNH2sVKaP/SOlwj51bXQoLOWoCZ51dT5c6MkDaM3TObSt5dIvFiNwIAzyCFL+CyNlb vd8mze0Rnyiwqlgj+XwW/QYG5s0+Mp9A5jjGpg8He71VgUBOwRvgwFgFjMTmQ+yt85tm gr39fedn+ZCe7ZzOgTVD0P03f4Z69BxEGIUR3ICkbM8br9O5jd73eS3w5OOABxoO0PaE 4Kkp2KOKChRFzEDwdRe+kRh7VAIMtE7D2o+dSrEmdx84J5Sli6/S6V1Y+NK9poyFpn1k kHTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rwqJPJ//6TQT5UmISyCch80APlTh3KWpu8wgkVgb10g=; b=GfKOzkogxgD7I/MoidRH82nc43ftmdLAcYT6qiz8+b2bMmAQUgMUPEQRz7BKBPu7gz tKPycuLKRg6x41DiUdiLHBIj1sHm2EhXaRhyFczXMDH+vgOLD6sLm5+4z410CIQekpqj gVuorPa6rYOkAiti/grbe7X6HyC6sCOGtnT4psNugf9vCklUpWrtehdMvYz3hg54bH+R c0wS2141GrbKF5uyrfDen5YSJgDnaT4Yl7KGa3JK6yxcSUE8KY8KPCZzRCZpElHYMiWi 6uh7327HlB+L/VzC1ekJtK4grgkTg6WOHJ6LrOmfjHchAVWug5oJYdICa0sfnQrSY6St inDA== X-Gm-Message-State: AOAM533Nh/eY0SAQ8oZjWXrHQHMCFcoZUssvIaUJdVvx9iV0Seh0e7Eb AU8Jt592MrLJX6ZgjzCqzjeGilSrkha2Ww== X-Google-Smtp-Source: ABdhPJyvbYO3olKLw0agNwgsM4IbVKO5jG0uEHm4uot1KOh1Dl5NfU62PQjhJhA3WvOPcAj3GPYu4Q== X-Received: by 2002:a63:cf41:0:b0:399:3e74:d249 with SMTP id b1-20020a63cf41000000b003993e74d249mr7096851pgj.475.1650217487304; Sun, 17 Apr 2022 10:44:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 20/60] target/arm: Use smin/smax for do_sat_addsub_32 Date: Sun, 17 Apr 2022 10:43:46 -0700 Message-Id: <20220417174426.711829-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650218677663100001 Content-Type: text/plain; charset="utf-8" The operation we're performing with the movcond is either min/max depending on cond -- simplify. Use tcg_constant_i64 while we're at it. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-sve.c | 9 ++------- 1 file changed, 2 insertions(+), 7 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 2c23459e76..ddc3a8060b 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -1916,8 +1916,6 @@ static bool trans_PNEXT(DisasContext *s, arg_rr_esz *= a) static void do_sat_addsub_32(TCGv_i64 reg, TCGv_i64 val, bool u, bool d) { int64_t ibound; - TCGv_i64 bound; - TCGCond cond; =20 /* Use normal 64-bit arithmetic to detect 32-bit overflow. */ if (u) { @@ -1928,15 +1926,12 @@ static void do_sat_addsub_32(TCGv_i64 reg, TCGv_i64= val, bool u, bool d) if (d) { tcg_gen_sub_i64(reg, reg, val); ibound =3D (u ? 0 : INT32_MIN); - cond =3D TCG_COND_LT; + tcg_gen_smax_i64(reg, reg, tcg_constant_i64(ibound)); } else { tcg_gen_add_i64(reg, reg, val); ibound =3D (u ? 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Dv6HLxT9VFR7Qb8w8wRvblozKpmuKMNmz+opU05p1gI=; b=Kq+7vAAZ63i776g4UPxOicCFbMUY+h8h0SEY4QK26+Jh1l4fxASPV9ypVzdhbU/HC7 mt45O+nk6zmIxC3Eu6viECfDHktq+hZE+Sj5nRwGmLvGkztDF9LKIQB7Ln0L0BA4zq8U OcQft1dUVn3yab+S61Nsk3L79Z/LIXPBSGGFdd9XvlZ0jvlF3ooVTIXofTVMiLKCXurT xPQ8NV1AEFfPpP3nBOgtA/0rGwslE7VqfLvHw5q6zdUa2JotT3PG3Z6REZvGukWK0WF9 nv8FVm6yn6fm/fUfH01usO3Zf57/F4/mWo74ABJ8QDxqhhWtVNNupQXfWxTq4/zdsRkS nP8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Dv6HLxT9VFR7Qb8w8wRvblozKpmuKMNmz+opU05p1gI=; b=IAB7/yHrSAwJ73VyR51/iFUVaPk2fFx7o5ghVAALWT1GmKG9/iY9++AnpJNBrVnhV+ y8ZG0OA+QlyD0yQX0UD+ZyOGQZMlQLKgiH1hv1EFwVTOTTdXagLeqi8OHIZlnMzG7OPy Dg/hocgQeDMJlzLOU5vr1VFpSWppL1+ZT/9xKOwl1jll6nZ2vlgZe9DDekCklMb/8RiM 8OYnrNSpM4O+GYBMHGULgBSOys+GhJNt9HnPkvGAqoq+D/OfFGrTLL3CYwr5HvBGpRGJ JtF7fr8I24h4XOyLhHOFitaPHDleRomftZ90TSnnp8MqgSksm4L3jlCGafdIp0na3RaB a8fg== X-Gm-Message-State: AOAM5311f0nnxak+mLDFXKEj+COlgLV4S2fhFZDaBGWI4oya7pHyMOtt 6SrTrG8CKPYzUt8DbDfHFKkw4XFTCxrCTw== X-Google-Smtp-Source: ABdhPJyHppv/zK4E9hOQsjQmQVNhnob1BEWKrYF0d8g7ndM7ObU9r9U/AXrOBWajW5z+prMhJD5xxA== X-Received: by 2002:a05:6a00:a8b:b0:4cd:6030:4df3 with SMTP id b11-20020a056a000a8b00b004cd60304df3mr8413946pfl.40.1650217488035; Sun, 17 Apr 2022 10:44:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 21/60] target/arm: Use tcg_constant in translate-sve.c Date: Sun, 17 Apr 2022 10:43:47 -0700 Message-Id: <20220417174426.711829-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650219611784100001 Content-Type: text/plain; charset="utf-8" Use tcg_constant_{i32,i64} as appropriate throughout. Signed-off-by: Richard Henderson --- target/arm/translate-sve.c | 198 +++++++++++++------------------------ 1 file changed, 68 insertions(+), 130 deletions(-) diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index ddc3a8060b..5b3478a43a 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -282,13 +282,12 @@ static void do_predtest(DisasContext *s, int dofs, in= t gofs, int words) { TCGv_ptr dptr =3D tcg_temp_new_ptr(); TCGv_ptr gptr =3D tcg_temp_new_ptr(); - TCGv_i32 t; + TCGv_i32 t =3D tcg_temp_new_i32(); =20 tcg_gen_addi_ptr(dptr, cpu_env, dofs); tcg_gen_addi_ptr(gptr, cpu_env, gofs); - t =3D tcg_const_i32(words); =20 - gen_helper_sve_predtest(t, dptr, gptr, t); + gen_helper_sve_predtest(t, dptr, gptr, tcg_constant_i32(words)); tcg_temp_free_ptr(dptr); tcg_temp_free_ptr(gptr); =20 @@ -889,7 +888,7 @@ static bool do_vpz_ool(DisasContext *s, arg_rpr_esz *a, return true; } =20 - desc =3D tcg_const_i32(simd_desc(vsz, vsz, 0)); + desc =3D tcg_constant_i32(simd_desc(vsz, vsz, 0)); temp =3D tcg_temp_new_i64(); t_zn =3D tcg_temp_new_ptr(); t_pg =3D tcg_temp_new_ptr(); @@ -899,7 +898,6 @@ static bool do_vpz_ool(DisasContext *s, arg_rpr_esz *a, fn(temp, t_zn, t_pg, desc); tcg_temp_free_ptr(t_zn); tcg_temp_free_ptr(t_pg); - tcg_temp_free_i32(desc); =20 write_fp_dreg(s, a->rd, temp); tcg_temp_free_i64(temp); @@ -1236,7 +1234,7 @@ static void do_index(DisasContext *s, int esz, int rd, TCGv_i64 start, TCGv_i64 incr) { unsigned vsz =3D vec_full_reg_size(s); - TCGv_i32 desc =3D tcg_const_i32(simd_desc(vsz, vsz, 0)); + TCGv_i32 desc =3D tcg_constant_i32(simd_desc(vsz, vsz, 0)); TCGv_ptr t_zd =3D tcg_temp_new_ptr(); =20 tcg_gen_addi_ptr(t_zd, cpu_env, vec_full_reg_offset(s, rd)); @@ -1260,17 +1258,14 @@ static void do_index(DisasContext *s, int esz, int = rd, tcg_temp_free_i32(i32); } tcg_temp_free_ptr(t_zd); - tcg_temp_free_i32(desc); } =20 static bool trans_INDEX_ii(DisasContext *s, arg_INDEX_ii *a) { if (sve_access_check(s)) { - TCGv_i64 start =3D tcg_const_i64(a->imm1); - TCGv_i64 incr =3D tcg_const_i64(a->imm2); + TCGv_i64 start =3D tcg_constant_i64(a->imm1); + TCGv_i64 incr =3D tcg_constant_i64(a->imm2); do_index(s, a->esz, a->rd, start, incr); - tcg_temp_free_i64(start); - tcg_temp_free_i64(incr); } return true; } @@ -1278,10 +1273,9 @@ static bool trans_INDEX_ii(DisasContext *s, arg_INDE= X_ii *a) static bool trans_INDEX_ir(DisasContext *s, arg_INDEX_ir *a) { if (sve_access_check(s)) { - TCGv_i64 start =3D tcg_const_i64(a->imm); + TCGv_i64 start =3D tcg_constant_i64(a->imm); TCGv_i64 incr =3D cpu_reg(s, a->rm); do_index(s, a->esz, a->rd, start, incr); - tcg_temp_free_i64(start); } return true; } @@ -1290,9 +1284,8 @@ static bool trans_INDEX_ri(DisasContext *s, arg_INDEX= _ri *a) { if (sve_access_check(s)) { TCGv_i64 start =3D cpu_reg(s, a->rn); - TCGv_i64 incr =3D tcg_const_i64(a->imm); + TCGv_i64 incr =3D tcg_constant_i64(a->imm); do_index(s, a->esz, a->rd, start, incr); - tcg_temp_free_i64(incr); } return true; } @@ -1884,9 +1877,9 @@ static bool do_pfirst_pnext(DisasContext *s, arg_rr_e= sz *a, =20 tcg_gen_addi_ptr(t_pd, cpu_env, pred_full_reg_offset(s, a->rd)); tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->rn)); - t =3D tcg_const_i32(desc); + t =3D tcg_temp_new_i32(); =20 - gen_fn(t, t_pd, t_pg, t); + gen_fn(t, t_pd, t_pg, tcg_constant_i32(desc)); tcg_temp_free_ptr(t_pd); tcg_temp_free_ptr(t_pg); =20 @@ -1993,7 +1986,7 @@ static void do_sat_addsub_vec(DisasContext *s, int es= z, int rd, int rn, nptr =3D tcg_temp_new_ptr(); tcg_gen_addi_ptr(dptr, cpu_env, vec_full_reg_offset(s, rd)); tcg_gen_addi_ptr(nptr, cpu_env, vec_full_reg_offset(s, rn)); - desc =3D tcg_const_i32(simd_desc(vsz, vsz, 0)); + desc =3D tcg_constant_i32(simd_desc(vsz, vsz, 0)); =20 switch (esz) { case MO_8: @@ -2062,7 +2055,6 @@ static void do_sat_addsub_vec(DisasContext *s, int es= z, int rd, int rn, =20 tcg_temp_free_ptr(dptr); tcg_temp_free_ptr(nptr); - tcg_temp_free_i32(desc); } =20 static bool trans_CNT_r(DisasContext *s, arg_CNT_r *a) @@ -2107,9 +2099,7 @@ static bool trans_SINCDEC_r_32(DisasContext *s, arg_i= ncdec_cnt *a) tcg_gen_ext32s_i64(reg, reg); } } else { - TCGv_i64 t =3D tcg_const_i64(inc); - do_sat_addsub_32(reg, t, a->u, a->d); - tcg_temp_free_i64(t); + do_sat_addsub_32(reg, tcg_constant_i64(inc), a->u, a->d); } return true; } @@ -2126,9 +2116,7 @@ static bool trans_SINCDEC_r_64(DisasContext *s, arg_i= ncdec_cnt *a) TCGv_i64 reg =3D cpu_reg(s, a->rd); =20 if (inc !=3D 0) { - TCGv_i64 t =3D tcg_const_i64(inc); - do_sat_addsub_64(reg, t, a->u, a->d); - tcg_temp_free_i64(t); + do_sat_addsub_64(reg, tcg_constant_i64(inc), a->u, a->d); } return true; } @@ -2145,11 +2133,10 @@ static bool trans_INCDEC_v(DisasContext *s, arg_inc= dec2_cnt *a) =20 if (inc !=3D 0) { if (sve_access_check(s)) { - TCGv_i64 t =3D tcg_const_i64(a->d ? -inc : inc); tcg_gen_gvec_adds(a->esz, vec_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), - t, fullsz, fullsz); - tcg_temp_free_i64(t); + tcg_constant_i64(a->d ? -inc : inc), + fullsz, fullsz); } } else { do_mov_z(s, a->rd, a->rn); @@ -2169,9 +2156,8 @@ static bool trans_SINCDEC_v(DisasContext *s, arg_incd= ec2_cnt *a) =20 if (inc !=3D 0) { if (sve_access_check(s)) { - TCGv_i64 t =3D tcg_const_i64(inc); - do_sat_addsub_vec(s, a->esz, a->rd, a->rn, t, a->u, a->d); - tcg_temp_free_i64(t); + do_sat_addsub_vec(s, a->esz, a->rd, a->rn, + tcg_constant_i64(inc), a->u, a->d); } } else { do_mov_z(s, a->rd, a->rn); @@ -2244,7 +2230,7 @@ static void do_cpy_m(DisasContext *s, int esz, int rd= , int rn, int pg, gen_helper_sve_cpy_m_s, gen_helper_sve_cpy_m_d, }; unsigned vsz =3D vec_full_reg_size(s); - TCGv_i32 desc =3D tcg_const_i32(simd_desc(vsz, vsz, 0)); + TCGv_i32 desc =3D tcg_constant_i32(simd_desc(vsz, vsz, 0)); TCGv_ptr t_zd =3D tcg_temp_new_ptr(); TCGv_ptr t_zn =3D tcg_temp_new_ptr(); TCGv_ptr t_pg =3D tcg_temp_new_ptr(); @@ -2258,7 +2244,6 @@ static void do_cpy_m(DisasContext *s, int esz, int rd= , int rn, int pg, tcg_temp_free_ptr(t_zd); tcg_temp_free_ptr(t_zn); tcg_temp_free_ptr(t_pg); - tcg_temp_free_i32(desc); } =20 static bool trans_FCPY(DisasContext *s, arg_FCPY *a) @@ -2269,9 +2254,7 @@ static bool trans_FCPY(DisasContext *s, arg_FCPY *a) if (sve_access_check(s)) { /* Decode the VFP immediate. */ uint64_t imm =3D vfp_expand_imm(a->esz, a->imm); - TCGv_i64 t_imm =3D tcg_const_i64(imm); - do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, t_imm); - tcg_temp_free_i64(t_imm); + do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, tcg_constant_i64(imm)); } return true; } @@ -2282,9 +2265,7 @@ static bool trans_CPY_m_i(DisasContext *s, arg_rpri_e= sz *a) return false; } if (sve_access_check(s)) { - TCGv_i64 t_imm =3D tcg_const_i64(a->imm); - do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, t_imm); - tcg_temp_free_i64(t_imm); + do_cpy_m(s, a->esz, a->rd, a->rn, a->pg, tcg_constant_i64(a->imm)); } return true; } @@ -2301,11 +2282,10 @@ static bool trans_CPY_z_i(DisasContext *s, arg_CPY_= z_i *a) } if (sve_access_check(s)) { unsigned vsz =3D vec_full_reg_size(s); - TCGv_i64 t_imm =3D tcg_const_i64(a->imm); tcg_gen_gvec_2i_ool(vec_full_reg_offset(s, a->rd), pred_full_reg_offset(s, a->pg), - t_imm, vsz, vsz, 0, fns[a->esz]); - tcg_temp_free_i64(t_imm); + tcg_constant_i64(a->imm), + vsz, vsz, 0, fns[a->esz]); } return true; } @@ -2406,7 +2386,7 @@ static void do_insr_i64(DisasContext *s, arg_rrr_esz = *a, TCGv_i64 val) gen_helper_sve_insr_s, gen_helper_sve_insr_d, }; unsigned vsz =3D vec_full_reg_size(s); - TCGv_i32 desc =3D tcg_const_i32(simd_desc(vsz, vsz, 0)); + TCGv_i32 desc =3D tcg_constant_i32(simd_desc(vsz, vsz, 0)); TCGv_ptr t_zd =3D tcg_temp_new_ptr(); TCGv_ptr t_zn =3D tcg_temp_new_ptr(); =20 @@ -2417,7 +2397,6 @@ static void do_insr_i64(DisasContext *s, arg_rrr_esz = *a, TCGv_i64 val) =20 tcg_temp_free_ptr(t_zd); tcg_temp_free_ptr(t_zn); - tcg_temp_free_i32(desc); } =20 static bool trans_INSR_f(DisasContext *s, arg_rrr_esz *a) @@ -2536,7 +2515,6 @@ static bool do_perm_pred3(DisasContext *s, arg_rrr_es= z *a, bool high_odd, TCGv_ptr t_d =3D tcg_temp_new_ptr(); TCGv_ptr t_n =3D tcg_temp_new_ptr(); TCGv_ptr t_m =3D tcg_temp_new_ptr(); - TCGv_i32 t_desc; uint32_t desc =3D 0; =20 desc =3D FIELD_DP32(desc, PREDDESC, OPRSZ, vsz); @@ -2546,14 +2524,12 @@ static bool do_perm_pred3(DisasContext *s, arg_rrr_= esz *a, bool high_odd, tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd)); tcg_gen_addi_ptr(t_n, cpu_env, pred_full_reg_offset(s, a->rn)); tcg_gen_addi_ptr(t_m, cpu_env, pred_full_reg_offset(s, a->rm)); - t_desc =3D tcg_const_i32(desc); =20 - fn(t_d, t_n, t_m, t_desc); + fn(t_d, t_n, t_m, tcg_constant_i32(desc)); =20 tcg_temp_free_ptr(t_d); tcg_temp_free_ptr(t_n); tcg_temp_free_ptr(t_m); - tcg_temp_free_i32(t_desc); return true; } =20 @@ -2567,7 +2543,6 @@ static bool do_perm_pred2(DisasContext *s, arg_rr_esz= *a, bool high_odd, unsigned vsz =3D pred_full_reg_size(s); TCGv_ptr t_d =3D tcg_temp_new_ptr(); TCGv_ptr t_n =3D tcg_temp_new_ptr(); - TCGv_i32 t_desc; uint32_t desc =3D 0; =20 tcg_gen_addi_ptr(t_d, cpu_env, pred_full_reg_offset(s, a->rd)); @@ -2576,11 +2551,9 @@ static bool do_perm_pred2(DisasContext *s, arg_rr_es= z *a, bool high_odd, desc =3D FIELD_DP32(desc, PREDDESC, OPRSZ, vsz); desc =3D FIELD_DP32(desc, PREDDESC, ESZ, a->esz); desc =3D FIELD_DP32(desc, PREDDESC, DATA, high_odd); - t_desc =3D tcg_const_i32(desc); =20 - fn(t_d, t_n, t_desc); + fn(t_d, t_n, tcg_constant_i32(desc)); =20 - tcg_temp_free_i32(t_desc); tcg_temp_free_ptr(t_d); tcg_temp_free_ptr(t_n); return true; @@ -2782,18 +2755,15 @@ static void find_last_active(DisasContext *s, TCGv_= i32 ret, int esz, int pg) * round up, as we do elsewhere, because we need the exact size. */ TCGv_ptr t_p =3D tcg_temp_new_ptr(); - TCGv_i32 t_desc; unsigned desc =3D 0; =20 desc =3D FIELD_DP32(desc, PREDDESC, OPRSZ, pred_full_reg_size(s)); desc =3D FIELD_DP32(desc, PREDDESC, ESZ, esz); =20 tcg_gen_addi_ptr(t_p, cpu_env, pred_full_reg_offset(s, pg)); - t_desc =3D tcg_const_i32(desc); =20 - gen_helper_sve_last_active_element(ret, t_p, t_desc); + gen_helper_sve_last_active_element(ret, t_p, tcg_constant_i32(desc)); =20 - tcg_temp_free_i32(t_desc); tcg_temp_free_ptr(t_p); } =20 @@ -2808,11 +2778,9 @@ static void incr_last_active(DisasContext *s, TCGv_i= 32 last, int esz) if (is_power_of_2(vsz)) { tcg_gen_andi_i32(last, last, vsz - 1); } else { - TCGv_i32 max =3D tcg_const_i32(vsz); - TCGv_i32 zero =3D tcg_const_i32(0); + TCGv_i32 max =3D tcg_constant_i32(vsz); + TCGv_i32 zero =3D tcg_constant_i32(0); tcg_gen_movcond_i32(TCG_COND_GEU, last, last, max, zero, last); - tcg_temp_free_i32(max); - tcg_temp_free_i32(zero); } } =20 @@ -2824,11 +2792,9 @@ static void wrap_last_active(DisasContext *s, TCGv_i= 32 last, int esz) if (is_power_of_2(vsz)) { tcg_gen_andi_i32(last, last, vsz - 1); } else { - TCGv_i32 max =3D tcg_const_i32(vsz - (1 << esz)); - TCGv_i32 zero =3D tcg_const_i32(0); + TCGv_i32 max =3D tcg_constant_i32(vsz - (1 << esz)); + TCGv_i32 zero =3D tcg_constant_i32(0); tcg_gen_movcond_i32(TCG_COND_LT, last, last, zero, max, last); - tcg_temp_free_i32(max); - tcg_temp_free_i32(zero); } } =20 @@ -2945,7 +2911,7 @@ static void do_clast_scalar(DisasContext *s, int esz,= int pg, int rm, bool before, TCGv_i64 reg_val) { TCGv_i32 last =3D tcg_temp_new_i32(); - TCGv_i64 ele, cmp, zero; + TCGv_i64 ele, cmp; =20 find_last_active(s, last, esz, pg); =20 @@ -2965,10 +2931,9 @@ static void do_clast_scalar(DisasContext *s, int esz= , int pg, int rm, ele =3D load_last_active(s, last, rm, esz); tcg_temp_free_i32(last); =20 - zero =3D tcg_const_i64(0); - tcg_gen_movcond_i64(TCG_COND_GE, reg_val, cmp, zero, ele, reg_val); + tcg_gen_movcond_i64(TCG_COND_GE, reg_val, cmp, tcg_constant_i64(0), + ele, reg_val); =20 - tcg_temp_free_i64(zero); tcg_temp_free_i64(cmp); tcg_temp_free_i64(ele); } @@ -3196,7 +3161,7 @@ static bool do_ppzz_flags(DisasContext *s, arg_rprr_e= sz *a, } =20 vsz =3D vec_full_reg_size(s); - t =3D tcg_const_i32(simd_desc(vsz, vsz, 0)); + t =3D tcg_temp_new_i32(); pd =3D tcg_temp_new_ptr(); zn =3D tcg_temp_new_ptr(); zm =3D tcg_temp_new_ptr(); @@ -3207,7 +3172,7 @@ static bool do_ppzz_flags(DisasContext *s, arg_rprr_e= sz *a, tcg_gen_addi_ptr(zm, cpu_env, vec_full_reg_offset(s, a->rm)); tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg)); =20 - gen_fn(t, pd, zn, zm, pg, t); + gen_fn(t, pd, zn, zm, pg, tcg_constant_i32(simd_desc(vsz, vsz, 0))); =20 tcg_temp_free_ptr(pd); tcg_temp_free_ptr(zn); @@ -3281,7 +3246,7 @@ static bool do_ppzi_flags(DisasContext *s, arg_rpri_e= sz *a, } =20 vsz =3D vec_full_reg_size(s); - t =3D tcg_const_i32(simd_desc(vsz, vsz, a->imm)); + t =3D tcg_temp_new_i32(); pd =3D tcg_temp_new_ptr(); zn =3D tcg_temp_new_ptr(); pg =3D tcg_temp_new_ptr(); @@ -3290,7 +3255,7 @@ static bool do_ppzi_flags(DisasContext *s, arg_rpri_e= sz *a, tcg_gen_addi_ptr(zn, cpu_env, vec_full_reg_offset(s, a->rn)); tcg_gen_addi_ptr(pg, cpu_env, pred_full_reg_offset(s, a->pg)); =20 - gen_fn(t, pd, zn, pg, t); + gen_fn(t, pd, zn, pg, tcg_constant_i32(simd_desc(vsz, vsz, a->imm))); =20 tcg_temp_free_ptr(pd); tcg_temp_free_ptr(zn); @@ -3343,7 +3308,8 @@ static bool do_brk3(DisasContext *s, arg_rprr_s *a, TCGv_ptr n =3D tcg_temp_new_ptr(); TCGv_ptr m =3D tcg_temp_new_ptr(); TCGv_ptr g =3D tcg_temp_new_ptr(); - TCGv_i32 t =3D tcg_const_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz)); + TCGv_i32 t =3D tcg_temp_new_i32(); + TCGv_i32 desc =3D tcg_constant_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz)= ); =20 tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd)); tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn)); @@ -3351,10 +3317,10 @@ static bool do_brk3(DisasContext *s, arg_rprr_s *a, tcg_gen_addi_ptr(g, cpu_env, pred_full_reg_offset(s, a->pg)); =20 if (a->s) { - fn_s(t, d, n, m, g, t); + fn_s(t, d, n, m, g, desc); do_pred_flags(t); } else { - fn(d, n, m, g, t); + fn(d, n, m, g, desc); } tcg_temp_free_ptr(d); tcg_temp_free_ptr(n); @@ -3377,17 +3343,18 @@ static bool do_brk2(DisasContext *s, arg_rpr_s *a, TCGv_ptr d =3D tcg_temp_new_ptr(); TCGv_ptr n =3D tcg_temp_new_ptr(); TCGv_ptr g =3D tcg_temp_new_ptr(); - TCGv_i32 t =3D tcg_const_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz)); + TCGv_i32 t =3D tcg_temp_new_i32(); + TCGv_i32 desc =3D tcg_constant_i32(FIELD_DP32(0, PREDDESC, OPRSZ, vsz)= ); =20 tcg_gen_addi_ptr(d, cpu_env, pred_full_reg_offset(s, a->rd)); tcg_gen_addi_ptr(n, cpu_env, pred_full_reg_offset(s, a->rn)); tcg_gen_addi_ptr(g, cpu_env, pred_full_reg_offset(s, a->pg)); =20 if (a->s) { - fn_s(t, d, n, g, t); + fn_s(t, d, n, g, desc); do_pred_flags(t); } else { - fn(d, n, g, t); + fn(d, n, g, desc); } tcg_temp_free_ptr(d); tcg_temp_free_ptr(n); @@ -3461,19 +3428,16 @@ static void do_cntp(DisasContext *s, TCGv_i64 val, = int esz, int pn, int pg) TCGv_ptr t_pn =3D tcg_temp_new_ptr(); TCGv_ptr t_pg =3D tcg_temp_new_ptr(); unsigned desc =3D 0; - TCGv_i32 t_desc; =20 desc =3D FIELD_DP32(desc, PREDDESC, OPRSZ, psz); desc =3D FIELD_DP32(desc, PREDDESC, ESZ, esz); =20 tcg_gen_addi_ptr(t_pn, cpu_env, pred_full_reg_offset(s, pn)); tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); - t_desc =3D tcg_const_i32(desc); =20 - gen_helper_sve_cntp(val, t_pn, t_pg, t_desc); + gen_helper_sve_cntp(val, t_pn, t_pg, tcg_constant_i32(desc)); tcg_temp_free_ptr(t_pn); tcg_temp_free_ptr(t_pg); - tcg_temp_free_i32(t_desc); } } =20 @@ -3588,7 +3552,7 @@ static bool trans_CTERM(DisasContext *s, arg_CTERM *a) static bool trans_WHILE(DisasContext *s, arg_WHILE *a) { TCGv_i64 op0, op1, t0, t1, tmax; - TCGv_i32 t2, t3; + TCGv_i32 t2; TCGv_ptr ptr; unsigned vsz =3D vec_full_reg_size(s); unsigned desc =3D 0; @@ -3644,7 +3608,7 @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a) } } =20 - tmax =3D tcg_const_i64(vsz >> a->esz); + tmax =3D tcg_constant_i64(vsz >> a->esz); if (eq) { /* Equality means one more iteration. */ tcg_gen_addi_i64(t0, t0, 1); @@ -3664,7 +3628,6 @@ static bool trans_WHILE(DisasContext *s, arg_WHILE *a) =20 /* Bound to the maximum. */ tcg_gen_umin_i64(t0, t0, tmax); - tcg_temp_free_i64(tmax); =20 /* Set the count to zero if the condition is false. */ tcg_gen_movi_i64(t1, 0); @@ -3681,28 +3644,26 @@ static bool trans_WHILE(DisasContext *s, arg_WHILE = *a) =20 desc =3D FIELD_DP32(desc, PREDDESC, OPRSZ, vsz / 8); desc =3D FIELD_DP32(desc, PREDDESC, ESZ, a->esz); - t3 =3D tcg_const_i32(desc); =20 ptr =3D tcg_temp_new_ptr(); tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd)); =20 if (a->lt) { - gen_helper_sve_whilel(t2, ptr, t2, t3); + gen_helper_sve_whilel(t2, ptr, t2, tcg_constant_i32(desc)); } else { - gen_helper_sve_whileg(t2, ptr, t2, t3); + gen_helper_sve_whileg(t2, ptr, t2, tcg_constant_i32(desc)); } do_pred_flags(t2); =20 tcg_temp_free_ptr(ptr); tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); return true; } =20 static bool trans_WHILE_ptr(DisasContext *s, arg_WHILE_ptr *a) { TCGv_i64 op0, op1, diff, t1, tmax; - TCGv_i32 t2, t3; + TCGv_i32 t2; TCGv_ptr ptr; unsigned vsz =3D vec_full_reg_size(s); unsigned desc =3D 0; @@ -3717,7 +3678,7 @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WHIL= E_ptr *a) op0 =3D read_cpu_reg(s, a->rn, 1); op1 =3D read_cpu_reg(s, a->rm, 1); =20 - tmax =3D tcg_const_i64(vsz); + tmax =3D tcg_constant_i64(vsz); diff =3D tcg_temp_new_i64(); =20 if (a->rw) { @@ -3743,7 +3704,6 @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WHIL= E_ptr *a) =20 /* Bound to the maximum. */ tcg_gen_umin_i64(diff, diff, tmax); - tcg_temp_free_i64(tmax); =20 /* Since we're bounded, pass as a 32-bit type. */ t2 =3D tcg_temp_new_i32(); @@ -3752,17 +3712,15 @@ static bool trans_WHILE_ptr(DisasContext *s, arg_WH= ILE_ptr *a) =20 desc =3D FIELD_DP32(desc, PREDDESC, OPRSZ, vsz / 8); desc =3D FIELD_DP32(desc, PREDDESC, ESZ, a->esz); - t3 =3D tcg_const_i32(desc); =20 ptr =3D tcg_temp_new_ptr(); tcg_gen_addi_ptr(ptr, cpu_env, pred_full_reg_offset(s, a->rd)); =20 - gen_helper_sve_whilel(t2, ptr, t2, t3); + gen_helper_sve_whilel(t2, ptr, t2, tcg_constant_i32(desc)); do_pred_flags(t2); =20 tcg_temp_free_ptr(ptr); tcg_temp_free_i32(t2); - tcg_temp_free_i32(t3); return true; } =20 @@ -3856,11 +3814,9 @@ static bool trans_SUBR_zzi(DisasContext *s, arg_rri_= esz *a) } if (sve_access_check(s)) { unsigned vsz =3D vec_full_reg_size(s); - TCGv_i64 c =3D tcg_const_i64(a->imm); tcg_gen_gvec_2s(vec_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), - vsz, vsz, c, &op[a->esz]); - tcg_temp_free_i64(c); + vsz, vsz, tcg_constant_i64(a->imm), &op[a->esz]); } return true; } @@ -3881,9 +3837,8 @@ static bool do_zzi_sat(DisasContext *s, arg_rri_esz *= a, bool u, bool d) return false; } if (sve_access_check(s)) { - TCGv_i64 val =3D tcg_const_i64(a->imm); - do_sat_addsub_vec(s, a->esz, a->rd, a->rn, val, u, d); - tcg_temp_free_i64(val); + do_sat_addsub_vec(s, a->esz, a->rd, a->rn, + tcg_constant_i64(a->imm), u, d); } return true; } @@ -3912,12 +3867,9 @@ static bool do_zzi_ool(DisasContext *s, arg_rri_esz = *a, gen_helper_gvec_2i *fn) { if (sve_access_check(s)) { unsigned vsz =3D vec_full_reg_size(s); - TCGv_i64 c =3D tcg_const_i64(a->imm); - tcg_gen_gvec_2i_ool(vec_full_reg_offset(s, a->rd), vec_full_reg_offset(s, a->rn), - c, vsz, vsz, 0, fn); - tcg_temp_free_i64(c); + tcg_constant_i64(a->imm), vsz, vsz, 0, fn); } return true; } @@ -4221,7 +4173,7 @@ static void do_reduce(DisasContext *s, arg_rpr_esz *a, { unsigned vsz =3D vec_full_reg_size(s); unsigned p2vsz =3D pow2ceil(vsz); - TCGv_i32 t_desc =3D tcg_const_i32(simd_desc(vsz, vsz, p2vsz)); + TCGv_i32 t_desc =3D tcg_constant_i32(simd_desc(vsz, vsz, p2vsz)); TCGv_ptr t_zn, t_pg, status; TCGv_i64 temp; =20 @@ -4237,7 +4189,6 @@ static void do_reduce(DisasContext *s, arg_rpr_esz *a, tcg_temp_free_ptr(t_zn); tcg_temp_free_ptr(t_pg); tcg_temp_free_ptr(status); - tcg_temp_free_i32(t_desc); =20 write_fp_dreg(s, a->rd, temp); tcg_temp_free_i64(temp); @@ -4414,11 +4365,10 @@ static bool trans_FADDA(DisasContext *s, arg_rprr_e= sz *a) tcg_gen_addi_ptr(t_rm, cpu_env, vec_full_reg_offset(s, a->rm)); tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg)); t_fpst =3D fpstatus_ptr(a->esz =3D=3D MO_16 ? FPST_FPCR_F16 : FPST_FPC= R); - t_desc =3D tcg_const_i32(simd_desc(vsz, vsz, 0)); + t_desc =3D tcg_constant_i32(simd_desc(vsz, vsz, 0)); =20 fns[a->esz - 1](t_val, t_val, t_rm, t_pg, t_fpst, t_desc); =20 - tcg_temp_free_i32(t_desc); tcg_temp_free_ptr(t_fpst); tcg_temp_free_ptr(t_pg); tcg_temp_free_ptr(t_rm); @@ -4535,10 +4485,9 @@ static void do_fp_scalar(DisasContext *s, int zd, in= t zn, int pg, bool is_fp16, tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); =20 status =3D fpstatus_ptr(is_fp16 ? FPST_FPCR_F16 : FPST_FPCR); - desc =3D tcg_const_i32(simd_desc(vsz, vsz, 0)); + desc =3D tcg_constant_i32(simd_desc(vsz, vsz, 0)); fn(t_zd, t_zn, t_pg, scalar, status, desc); =20 - tcg_temp_free_i32(desc); tcg_temp_free_ptr(status); tcg_temp_free_ptr(t_pg); tcg_temp_free_ptr(t_zn); @@ -4548,9 +4497,8 @@ static void do_fp_scalar(DisasContext *s, int zd, int= zn, int pg, bool is_fp16, static void do_fp_imm(DisasContext *s, arg_rpri_esz *a, uint64_t imm, gen_helper_sve_fp2scalar *fn) { - TCGv_i64 temp =3D tcg_const_i64(imm); - do_fp_scalar(s, a->rd, a->rn, a->pg, a->esz =3D=3D MO_16, temp, fn); - tcg_temp_free_i64(temp); + do_fp_scalar(s, a->rd, a->rn, a->pg, a->esz =3D=3D MO_16, + tcg_constant_i64(imm), fn); } =20 #define DO_FP_IMM(NAME, name, const0, const1) \ @@ -5297,7 +5245,6 @@ static void do_mem_zpa(DisasContext *s, int zt, int p= g, TCGv_i64 addr, { unsigned vsz =3D vec_full_reg_size(s); TCGv_ptr t_pg; - TCGv_i32 t_desc; int desc =3D 0; =20 /* @@ -5319,14 +5266,12 @@ static void do_mem_zpa(DisasContext *s, int zt, int= pg, TCGv_i64 addr, } =20 desc =3D simd_desc(vsz, vsz, zt | desc); - t_desc =3D tcg_const_i32(desc); t_pg =3D tcg_temp_new_ptr(); =20 tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); - fn(cpu_env, t_pg, addr, t_desc); + fn(cpu_env, t_pg, addr, tcg_constant_i32(desc)); =20 tcg_temp_free_ptr(t_pg); - tcg_temp_free_i32(t_desc); } =20 /* Indexed by [mte][be][dtype][nreg] */ @@ -6069,7 +6014,6 @@ static void do_mem_zpz(DisasContext *s, int zt, int p= g, int zm, TCGv_ptr t_zm =3D tcg_temp_new_ptr(); TCGv_ptr t_pg =3D tcg_temp_new_ptr(); TCGv_ptr t_zt =3D tcg_temp_new_ptr(); - TCGv_i32 t_desc; int desc =3D 0; =20 if (s->mte_active[0]) { @@ -6081,17 +6025,15 @@ static void do_mem_zpz(DisasContext *s, int zt, int= pg, int zm, desc <<=3D SVE_MTEDESC_SHIFT; } desc =3D simd_desc(vsz, vsz, desc | scale); - t_desc =3D tcg_const_i32(desc); =20 tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, pg)); tcg_gen_addi_ptr(t_zm, cpu_env, vec_full_reg_offset(s, zm)); tcg_gen_addi_ptr(t_zt, cpu_env, vec_full_reg_offset(s, zt)); - fn(cpu_env, t_zt, t_pg, t_zm, scalar, t_desc); + fn(cpu_env, t_zt, t_pg, t_zm, scalar, tcg_constant_i32(desc)); =20 tcg_temp_free_ptr(t_zt); tcg_temp_free_ptr(t_zm); tcg_temp_free_ptr(t_pg); - tcg_temp_free_i32(t_desc); } =20 /* Indexed by [mte][be][ff][xs][u][msz]. */ @@ -6452,7 +6394,6 @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_z= piz *a) gen_helper_gvec_mem_scatter *fn =3D NULL; bool be =3D s->be_data =3D=3D MO_BE; bool mte =3D s->mte_active[0]; - TCGv_i64 imm; =20 if (a->esz < a->msz || (a->esz =3D=3D a->msz && !a->u)) { return false; @@ -6474,9 +6415,8 @@ static bool trans_LD1_zpiz(DisasContext *s, arg_LD1_z= piz *a) /* Treat LD1_zpiz (zn[x] + imm) the same way as LD1_zprz (rn + zm[x]) * by loading the immediate into the scalar parameter. */ - imm =3D tcg_const_i64(a->imm << a->msz); - do_mem_zpz(s, a->rd, a->pg, a->rn, 0, imm, a->msz, false, fn); - tcg_temp_free_i64(imm); + do_mem_zpz(s, a->rd, a->pg, a->rn, 0, + tcg_constant_i64(a->imm << a->msz), a->msz, false, fn); return true; } =20 @@ -6635,7 +6575,6 @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_z= piz *a) gen_helper_gvec_mem_scatter *fn =3D NULL; bool be =3D s->be_data =3D=3D MO_BE; bool mte =3D s->mte_active[0]; - TCGv_i64 imm; =20 if (a->esz < a->msz) { return false; @@ -6657,9 +6596,8 @@ static bool trans_ST1_zpiz(DisasContext *s, arg_ST1_z= piz *a) /* Treat ST1_zpiz (zn[x] + imm) the same way as ST1_zprz (rn + zm[x]) * by loading the immediate into the scalar parameter. */ - imm =3D tcg_const_i64(a->imm << a->msz); - do_mem_zpz(s, a->rd, a->pg, a->rn, 0, imm, a->msz, true, fn); - tcg_temp_free_i64(imm); + do_mem_zpz(s, a->rd, a->pg, a->rn, 0, + tcg_constant_i64(a->imm << a->msz), a->msz, true, fn); return true; } =20 --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650219083; cv=none; d=zohomail.com; s=zohoarc; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EjDsRVrr40sK4EqnjCDkGgI2/MSKp18+eb6X2mYbvxs=; b=r0V1/2VKGSm5JnKWZq0XEM9IyawtQwL+Qi0+lzvFBfLw6fLdrjJ0ACEA4qgpUfL6qd JMfOT1GeV7xx2GRDwB51YYLSB+KUtUlFeTHPkNNW6SjUy51r1S6ENQcYggTyO5nsIbuu bdraHueUHupFOLDpWvXGilF/2XKv74wZjIXY7dqXfnN+o6dw++qunoR9sU9bixEt6nRF Hyq7Vh86/gMwp0KE+3wUDpzGisOiIBLBEAQa03JH/F8m+yLY1rJEx/VXC/8pNx4Dabyb Fxi+tD+OqWxglrBtoVR7/5hkrhiC8TS3iWKOFUcKeMRq5DoYthHpUkbH8TWZEEKzN+7N P1og== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EjDsRVrr40sK4EqnjCDkGgI2/MSKp18+eb6X2mYbvxs=; b=ndp5e42AKbRjWJ5Z4j8PoTpkZhFbcLnQ4RkmS6j36vmP68OHGyO2iHbfFu7+5UDWVN izgNecEsp0BZC5/E3hxGmmnq8/R4L3nM0ATB+xcs2ypFVfsrWDhyFPJ/YG8MwCK0TRlt rBiukDBDt7nLoElD1L2k3TRMbian+A2QNaze07ISi20Mh942UU2ejoBEwSCzAeXrJwzk jnV/ZqVBY28xNmcpGszrjGUhyJSnSuQJ27yG1ePxPTUPlmzRpmkKlGfIlqkIza96F1px lax4eNHU2S5in69M68tjRHMlY68jHhq39rWxBgZ3Mx3DXdP7dBNAfxmEOiGvrTrH7aJM 35gg== X-Gm-Message-State: AOAM53273Edik43wSa2RX6+ddKM0FXcyX9+w/bdVglwcvXhlwlslqsG9 fB4NGGk5dZdjoTl+MpChfLuvFCsAUOiBXg== X-Google-Smtp-Source: ABdhPJw4rlKo6XCj0zQeRQUXGSKFpU7K7uF8xPMUg54mLI+NbbEpgw+Tl/kE2zSlUTst9wWaHCYeSw== X-Received: by 2002:aa7:8049:0:b0:4fd:bfde:45eb with SMTP id y9-20020aa78049000000b004fdbfde45ebmr8518125pfm.76.1650217488880; Sun, 17 Apr 2022 10:44:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 22/60] target/arm: Use tcg_constant in translate-vfp.c Date: Sun, 17 Apr 2022 10:43:48 -0700 Message-Id: <20220417174426.711829-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650219085281100001 Content-Type: text/plain; charset="utf-8" Use tcg_constant_{i32,i64} as appropriate throughout. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate-vfp.c | 76 ++++++++++++-------------------------- 1 file changed, 23 insertions(+), 53 deletions(-) diff --git a/target/arm/translate-vfp.c b/target/arm/translate-vfp.c index 17f796e32a..32b784b9c8 100644 --- a/target/arm/translate-vfp.c +++ b/target/arm/translate-vfp.c @@ -180,8 +180,7 @@ static void gen_update_fp_context(DisasContext *s) gen_helper_vfp_set_fpscr(cpu_env, fpscr); tcg_temp_free_i32(fpscr); if (dc_isar_feature(aa32_mve, s)) { - TCGv_i32 z32 =3D tcg_const_i32(0); - store_cpu_field(z32, v7m.vpr); + store_cpu_field(tcg_constant_i32(0), v7m.vpr); } /* * We just updated the FPSCR and VPR. Some of this state is cached @@ -317,7 +316,7 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) TCGv_i64 frn, frm, dest; TCGv_i64 tmp, zero, zf, nf, vf; =20 - zero =3D tcg_const_i64(0); + zero =3D tcg_constant_i64(0); =20 frn =3D tcg_temp_new_i64(); frm =3D tcg_temp_new_i64(); @@ -335,27 +334,22 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) vfp_load_reg64(frm, rm); switch (a->cc) { case 0: /* eq: Z */ - tcg_gen_movcond_i64(TCG_COND_EQ, dest, zf, zero, - frn, frm); + tcg_gen_movcond_i64(TCG_COND_EQ, dest, zf, zero, frn, frm); break; case 1: /* vs: V */ - tcg_gen_movcond_i64(TCG_COND_LT, dest, vf, zero, - frn, frm); + tcg_gen_movcond_i64(TCG_COND_LT, dest, vf, zero, frn, frm); break; case 2: /* ge: N =3D=3D V -> N ^ V =3D=3D 0 */ tmp =3D tcg_temp_new_i64(); tcg_gen_xor_i64(tmp, vf, nf); - tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero, - frn, frm); + tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero, frn, frm); tcg_temp_free_i64(tmp); break; case 3: /* gt: !Z && N =3D=3D V */ - tcg_gen_movcond_i64(TCG_COND_NE, dest, zf, zero, - frn, frm); + tcg_gen_movcond_i64(TCG_COND_NE, dest, zf, zero, frn, frm); tmp =3D tcg_temp_new_i64(); tcg_gen_xor_i64(tmp, vf, nf); - tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero, - dest, frm); + tcg_gen_movcond_i64(TCG_COND_GE, dest, tmp, zero, dest, frm); tcg_temp_free_i64(tmp); break; } @@ -367,13 +361,11 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) tcg_temp_free_i64(zf); tcg_temp_free_i64(nf); tcg_temp_free_i64(vf); - - tcg_temp_free_i64(zero); } else { TCGv_i32 frn, frm, dest; TCGv_i32 tmp, zero; =20 - zero =3D tcg_const_i32(0); + zero =3D tcg_constant_i32(0); =20 frn =3D tcg_temp_new_i32(); frm =3D tcg_temp_new_i32(); @@ -382,27 +374,22 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) vfp_load_reg32(frm, rm); switch (a->cc) { case 0: /* eq: Z */ - tcg_gen_movcond_i32(TCG_COND_EQ, dest, cpu_ZF, zero, - frn, frm); + tcg_gen_movcond_i32(TCG_COND_EQ, dest, cpu_ZF, zero, frn, frm); break; case 1: /* vs: V */ - tcg_gen_movcond_i32(TCG_COND_LT, dest, cpu_VF, zero, - frn, frm); + tcg_gen_movcond_i32(TCG_COND_LT, dest, cpu_VF, zero, frn, frm); break; case 2: /* ge: N =3D=3D V -> N ^ V =3D=3D 0 */ tmp =3D tcg_temp_new_i32(); tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF); - tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero, - frn, frm); + tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero, frn, frm); tcg_temp_free_i32(tmp); break; case 3: /* gt: !Z && N =3D=3D V */ - tcg_gen_movcond_i32(TCG_COND_NE, dest, cpu_ZF, zero, - frn, frm); + tcg_gen_movcond_i32(TCG_COND_NE, dest, cpu_ZF, zero, frn, frm); tmp =3D tcg_temp_new_i32(); tcg_gen_xor_i32(tmp, cpu_VF, cpu_NF); - tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero, - dest, frm); + tcg_gen_movcond_i32(TCG_COND_GE, dest, tmp, zero, dest, frm); tcg_temp_free_i32(tmp); break; } @@ -414,8 +401,6 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a) tcg_temp_free_i32(frn); tcg_temp_free_i32(frm); tcg_temp_free_i32(dest); - - tcg_temp_free_i32(zero); } =20 return true; @@ -547,7 +532,7 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) fpst =3D fpstatus_ptr(FPST_FPCR); } =20 - tcg_shift =3D tcg_const_i32(0); + tcg_shift =3D tcg_constant_i32(0); =20 tcg_rmode =3D tcg_const_i32(arm_rmode_to_sf(rounding)); gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); @@ -595,8 +580,6 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a) gen_helper_set_rmode(tcg_rmode, tcg_rmode, fpst); tcg_temp_free_i32(tcg_rmode); =20 - tcg_temp_free_i32(tcg_shift); - tcg_temp_free_ptr(fpst); =20 return true; @@ -850,15 +833,11 @@ static bool trans_VMSR_VMRS(DisasContext *s, arg_VMSR= _VMRS *a) case ARM_VFP_MVFR2: case ARM_VFP_FPSID: if (s->current_el =3D=3D 1) { - TCGv_i32 tcg_reg, tcg_rt; - gen_set_condexec(s); gen_set_pc_im(s, s->pc_curr); - tcg_reg =3D tcg_const_i32(a->reg); - tcg_rt =3D tcg_const_i32(a->rt); - gen_helper_check_hcr_el2_trap(cpu_env, tcg_rt, tcg_reg); - tcg_temp_free_i32(tcg_reg); - tcg_temp_free_i32(tcg_rt); + gen_helper_check_hcr_el2_trap(cpu_env, + tcg_constant_i32(a->rt), + tcg_constant_i32(a->reg)); } /* fall through */ case ARM_VFP_FPEXC: @@ -2388,8 +2367,6 @@ MAKE_VFM_TRANS_FNS(dp) =20 static bool trans_VMOV_imm_hp(DisasContext *s, arg_VMOV_imm_sp *a) { - TCGv_i32 fd; - if (!dc_isar_feature(aa32_fp16_arith, s)) { return false; } @@ -2402,9 +2379,7 @@ static bool trans_VMOV_imm_hp(DisasContext *s, arg_VM= OV_imm_sp *a) return true; } =20 - fd =3D tcg_const_i32(vfp_expand_imm(MO_16, a->imm)); - vfp_store_reg32(fd, a->vd); - tcg_temp_free_i32(fd); + vfp_store_reg32(tcg_constant_i32(vfp_expand_imm(MO_16, a->imm)), a->vd= ); return true; } =20 @@ -2440,7 +2415,7 @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_VM= OV_imm_sp *a) } } =20 - fd =3D tcg_const_i32(vfp_expand_imm(MO_32, a->imm)); + fd =3D tcg_constant_i32(vfp_expand_imm(MO_32, a->imm)); =20 for (;;) { vfp_store_reg32(fd, vd); @@ -2454,7 +2429,6 @@ static bool trans_VMOV_imm_sp(DisasContext *s, arg_VM= OV_imm_sp *a) vd =3D vfp_advance_sreg(vd, delta_d); } =20 - tcg_temp_free_i32(fd); return true; } =20 @@ -2495,7 +2469,7 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VM= OV_imm_dp *a) } } =20 - fd =3D tcg_const_i64(vfp_expand_imm(MO_64, a->imm)); + fd =3D tcg_constant_i64(vfp_expand_imm(MO_64, a->imm)); =20 for (;;) { vfp_store_reg64(fd, vd); @@ -2509,7 +2483,6 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VM= OV_imm_dp *a) vd =3D vfp_advance_dreg(vd, delta_d); } =20 - tcg_temp_free_i64(fd); return true; } =20 @@ -3294,7 +3267,7 @@ static bool trans_VCVT_fix_hp(DisasContext *s, arg_VC= VT_fix_sp *a) vfp_load_reg32(vd, a->vd); =20 fpst =3D fpstatus_ptr(FPST_FPCR_F16); - shift =3D tcg_const_i32(frac_bits); + shift =3D tcg_constant_i32(frac_bits); =20 /* Switch on op:U:sx bits */ switch (a->opc) { @@ -3328,7 +3301,6 @@ static bool trans_VCVT_fix_hp(DisasContext *s, arg_VC= VT_fix_sp *a) =20 vfp_store_reg32(vd, a->vd); tcg_temp_free_i32(vd); - tcg_temp_free_i32(shift); tcg_temp_free_ptr(fpst); return true; } @@ -3353,7 +3325,7 @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VC= VT_fix_sp *a) vfp_load_reg32(vd, a->vd); =20 fpst =3D fpstatus_ptr(FPST_FPCR); - shift =3D tcg_const_i32(frac_bits); + shift =3D tcg_constant_i32(frac_bits); =20 /* Switch on op:U:sx bits */ switch (a->opc) { @@ -3387,7 +3359,6 @@ static bool trans_VCVT_fix_sp(DisasContext *s, arg_VC= VT_fix_sp *a) =20 vfp_store_reg32(vd, a->vd); tcg_temp_free_i32(vd); - tcg_temp_free_i32(shift); tcg_temp_free_ptr(fpst); return true; } @@ -3418,7 +3389,7 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VC= VT_fix_dp *a) vfp_load_reg64(vd, a->vd); =20 fpst =3D fpstatus_ptr(FPST_FPCR); - shift =3D tcg_const_i32(frac_bits); + shift =3D tcg_constant_i32(frac_bits); =20 /* Switch on op:U:sx bits */ switch (a->opc) { @@ -3452,7 +3423,6 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VC= VT_fix_dp *a) =20 vfp_store_reg64(vd, a->vd); tcg_temp_free_i64(vd); - tcg_temp_free_i32(shift); tcg_temp_free_ptr(fpst); return true; } --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650219302; cv=none; d=zohomail.com; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650219304381100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/translate.h | 13 +++---------- 1 file changed, 3 insertions(+), 10 deletions(-) diff --git a/target/arm/translate.h b/target/arm/translate.h index 050d80f6f9..6f0ebdc88e 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -332,16 +332,9 @@ static inline void gen_ss_advance(DisasContext *s) static inline void gen_exception(int excp, uint32_t syndrome, uint32_t target_el) { - TCGv_i32 tcg_excp =3D tcg_const_i32(excp); - TCGv_i32 tcg_syn =3D tcg_const_i32(syndrome); - TCGv_i32 tcg_el =3D tcg_const_i32(target_el); - - gen_helper_exception_with_syndrome(cpu_env, tcg_excp, - tcg_syn, tcg_el); - - tcg_temp_free_i32(tcg_el); - tcg_temp_free_i32(tcg_syn); - tcg_temp_free_i32(tcg_excp); + gen_helper_exception_with_syndrome(cpu_env, tcg_constant_i32(excp), + tcg_constant_i32(syndrome), + tcg_constant_i32(target_el)); } =20 /* Generate an architectural singlestep exception */ --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650219242; cv=none; d=zohomail.com; s=zohoarc; b=fhIqvkolQbtPUnpyKuXM2tLWAcIqqVEhWbSSnnQOC21zCqB2MD/Srj9KRZmYOBpBCRnVOf6wDzt/PGXfQj0LiCjaZ4JYD5Y2zBg8yf8RyGJ83G8OFFXC8eQXGFB4v0qmo2PZdwUT2GpsDvjx/Cz5/FvqB8QAnl68VdPhefwjBoQ= ARC-Message-Signature: i=1; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=v/4nUFEFhPbECEOcrTf7ZSJ5Kp+IM3GRGZb7ARPXAT8=; b=yPJTe1c7sOJCp/e1oT5nef6QSoIo50mecnTYeB9cY9dK55pG+/Vug8eB15kCD27i5z kJwOHzN8bpfsrN5JRC6JDOKGhr22Pt5x0emPb621Xp2xojObvPLcyUqEjQ4vMJsorjMj fherkXS4QHi2QQ8ZARvNkGqoVvHDL/tstXXS99M6OMyF7SLU67NVgRdUJIxoRNmyGhcV o15tohShjtUW0f9Af6NyuV7U+XaQBMfB0hwIbas6d009q6COjvA+2Sfent8zzcNpXugs G5knGw2Geh1S7jnO444blBKvdsl3F+rBgH5dGyn3bMWD8y5LcurCq4HMvFlIh+j0kPPP jC4A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v/4nUFEFhPbECEOcrTf7ZSJ5Kp+IM3GRGZb7ARPXAT8=; b=C8TLxDrXA0t8ba1s208NB7gl7m3kSSghLoj9+Qjkjo9e7w4Dxd3EJk9gisTVg/VZj2 V/wvfN92FwsiQqi2edmXrNfikEghnVavbKJ0/RWkLPL8c7tzidOMfpXP8a+0tGtRHmE4 MEU+9Nv8oysOcQfQ8IuGWWx3wUfGi2mxdGehEkx8ZAdpyg/iiXA21CEQfr62gjW4qtfo bN5ady4628+vfzAtJPJhhaByur+0Wr47zWq3PQ6Vl28pGxNEDQ7584yX1+hDIuYKYxGr 2Fnj4ZZ9IFFUksXtc4cjL4ii/nxrubiOQC/L5bioUJU9TB3bOPtjrW6ln2WPgj6R+APC 0Vkg== X-Gm-Message-State: AOAM531Z0YD66XKbr4pzwRF7bCCLMLuBCei0rm//CGFqtcP946qCVwp+ eiEcsnUDrmXDN3CJoXYOJbyrk1XvdfZ4+w== X-Google-Smtp-Source: ABdhPJyRmUmLfwHm3CjxjNE35jqHzghLXMPg572auEJhKomuP5gWIIyVTgH93RHqGEz0fmaTzPxmhg== X-Received: by 2002:a17:902:70c1:b0:156:16c0:dc7b with SMTP id l1-20020a17090270c100b0015616c0dc7bmr7830230plt.85.1650217490615; Sun, 17 Apr 2022 10:44:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 24/60] target/arm: Split out cpregs.h Date: Sun, 17 Apr 2022 10:43:50 -0700 Message-Id: <20220417174426.711829-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650219244072100001 Content-Type: text/plain; charset="utf-8" Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell --- target/arm/cpregs.h | 413 +++++++++++++++++++++++++++++++++++++ target/arm/cpu.h | 368 --------------------------------- hw/arm/pxa2xx.c | 1 + hw/arm/pxa2xx_pic.c | 1 + hw/intc/arm_gicv3_cpuif.c | 1 + hw/intc/arm_gicv3_kvm.c | 2 + target/arm/cpu.c | 1 + target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 1 + target/arm/gdbstub.c | 3 +- target/arm/helper.c | 1 + target/arm/op_helper.c | 1 + target/arm/translate-a64.c | 4 +- target/arm/translate.c | 3 +- 14 files changed, 427 insertions(+), 374 deletions(-) create mode 100644 target/arm/cpregs.h diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h new file mode 100644 index 0000000000..005aa2d3a5 --- /dev/null +++ b/target/arm/cpregs.h @@ -0,0 +1,413 @@ +/* + * QEMU ARM CP Register access and descriptions + * + * Copyright (c) 2022 Linaro Ltd + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ + +#ifndef TARGET_ARM_CPREGS_H +#define TARGET_ARM_CPREGS_H 1 + +/* + * ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a + * special-behaviour cp reg and bits [11..8] indicate what behaviour + * it has. Otherwise it is a simple cp reg, where CONST indicates that + * TCG can assume the value to be constant (ie load at translate time) + * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END + * indicates that the TB should not be ended after a write to this register + * (the default is that the TB ends after cp writes). OVERRIDE permits + * a register definition to override a previous definition for the + * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the + * old must have the OVERRIDE bit set. + * ALIAS indicates that this register is an alias view of some underlying + * state which is also visible via another register, and that the other + * register is handling migration and reset; registers marked ALIAS will n= ot be + * migrated but may have their state set by syncing of register state from= KVM. + * NO_RAW indicates that this register has no underlying state and does not + * support raw access for state saving/loading; it will not be used for ei= ther + * migration or KVM state synchronization. (Typically this is for "registe= rs" + * which are actually used as instructions for cache maintenance and so on= .) + * IO indicates that this register does I/O and therefore its accesses + * need to be marked with gen_io_start() and also end the TB. In particula= r, + * registers which implement clocks or timers require this. + * RAISES_EXC is for when the read or write hook might raise an exception; + * the generated code will synchronize the CPU state before calling the ho= ok + * so that it is safe for the hook to call raise_exception(). + * NEWEL is for writes to registers that might change the exception + * level - typically on older ARM chips. For those cases we need to + * re-read the new el when recomputing the translation flags. + */ +#define ARM_CP_SPECIAL 0x0001 +#define ARM_CP_CONST 0x0002 +#define ARM_CP_64BIT 0x0004 +#define ARM_CP_SUPPRESS_TB_END 0x0008 +#define ARM_CP_OVERRIDE 0x0010 +#define ARM_CP_ALIAS 0x0020 +#define ARM_CP_IO 0x0040 +#define ARM_CP_NO_RAW 0x0080 +#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) +#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) +#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) +#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) +#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) +#define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600) +#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700) +#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA +#define ARM_CP_FPU 0x1000 +#define ARM_CP_SVE 0x2000 +#define ARM_CP_NO_GDB 0x4000 +#define ARM_CP_RAISES_EXC 0x8000 +#define ARM_CP_NEWEL 0x10000 +/* Used only as a terminator for ARMCPRegInfo lists */ +#define ARM_CP_SENTINEL 0xfffff +/* Mask of only the flag bits in a type field */ +#define ARM_CP_FLAG_MASK 0x1f0ff + +/* + * Valid values for ARMCPRegInfo state field, indicating which of + * the AArch32 and AArch64 execution states this register is visible in. + * If the reginfo doesn't explicitly specify then it is AArch32 only. + * If the reginfo is declared to be visible in both states then a second + * reginfo is synthesised for the AArch32 view of the AArch64 register, + * such that the AArch32 view is the lower 32 bits of the AArch64 one. + * Note that we rely on the values of these enums as we iterate through + * the various states in some places. + */ +enum { + ARM_CP_STATE_AA32 =3D 0, + ARM_CP_STATE_AA64 =3D 1, + ARM_CP_STATE_BOTH =3D 2, +}; + +/* + * ARM CP register secure state flags. These flags identify security state + * attributes for a given CP register entry. + * The existence of both or neither secure and non-secure flags indicates = that + * the register has both a secure and non-secure hash entry. A single one= of + * these flags causes the register to only be hashed for the specified + * security state. + * Although definitions may have any combination of the S/NS bits, each + * registered entry will only have one to identify whether the entry is se= cure + * or non-secure. + */ +enum { + ARM_CP_SECSTATE_S =3D (1 << 0), /* bit[0]: Secure state register */ + ARM_CP_SECSTATE_NS =3D (1 << 1), /* bit[1]: Non-secure state register= */ +}; + +/* + * Return true if cptype is a valid type field. This is used to try to + * catch errors where the sentinel has been accidentally left off the end + * of a list of registers. + */ +static inline bool cptype_valid(int cptype) +{ + return ((cptype & ~ARM_CP_FLAG_MASK) =3D=3D 0) + || ((cptype & ARM_CP_SPECIAL) && + ((cptype & ~ARM_CP_FLAG_MASK) <=3D ARM_LAST_SPECIAL)); +} + +/* + * Access rights: + * We define bits for Read and Write access for what rev C of the v7-AR AR= M ARM + * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and + * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 + * (ie any of the privileged modes in Secure state, or Monitor mode). + * If a register is accessible in one privilege level it's always accessib= le + * in higher privilege levels too. Since "Secure PL1" also follows this ru= le + * (ie anything visible in PL2 is visible in S-PL1, some things are only + * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the + * terminology a little and call this PL3. + * In AArch64 things are somewhat simpler as the PLx bits line up exactly + * with the ELx exception levels. + * + * If access permissions for a register are more complex than can be + * described with these bits, then use a laxer set of restrictions, and + * do the more restrictive/complex check inside a helper function. + */ +#define PL3_R 0x80 +#define PL3_W 0x40 +#define PL2_R (0x20 | PL3_R) +#define PL2_W (0x10 | PL3_W) +#define PL1_R (0x08 | PL2_R) +#define PL1_W (0x04 | PL2_W) +#define PL0_R (0x02 | PL1_R) +#define PL0_W (0x01 | PL1_W) + +/* + * For user-mode some registers are accessible to EL0 via a kernel + * trap-and-emulate ABI. In this case we define the read permissions + * as actually being PL0_R. However some bits of any given register + * may still be masked. + */ +#ifdef CONFIG_USER_ONLY +#define PL0U_R PL0_R +#else +#define PL0U_R PL1_R +#endif + +#define PL3_RW (PL3_R | PL3_W) +#define PL2_RW (PL2_R | PL2_W) +#define PL1_RW (PL1_R | PL1_W) +#define PL0_RW (PL0_R | PL0_W) + +typedef enum CPAccessResult { + /* Access is permitted */ + CP_ACCESS_OK =3D 0, + /* + * Access fails due to a configurable trap or enable which would + * result in a categorized exception syndrome giving information about + * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, + * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or + * PL1 if in EL0, otherwise to the current EL). + */ + CP_ACCESS_TRAP =3D 1, + /* + * Access fails and results in an exception syndrome 0x0 ("uncategoriz= ed"). + * Note that this is not a catch-all case -- the set of cases which may + * result in this failure is specifically defined by the architecture. + */ + CP_ACCESS_TRAP_UNCATEGORIZED =3D 2, + /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ + CP_ACCESS_TRAP_EL2 =3D 3, + CP_ACCESS_TRAP_EL3 =3D 4, + /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ + CP_ACCESS_TRAP_UNCATEGORIZED_EL2 =3D 5, + CP_ACCESS_TRAP_UNCATEGORIZED_EL3 =3D 6, +} CPAccessResult; + +typedef struct ARMCPRegInfo ARMCPRegInfo; + +/* + * Access functions for coprocessor registers. These cannot fail and + * may not raise exceptions. + */ +typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); +typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, + uint64_t value); +/* Access permission check functions for coprocessor registers. */ +typedef CPAccessResult CPAccessFn(CPUARMState *env, + const ARMCPRegInfo *opaque, + bool isread); +/* Hook function for register reset */ +typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); + +#define CP_ANY 0xff + +/* Definition of an ARM coprocessor register */ +struct ARMCPRegInfo { + /* Name of register (useful mainly for debugging, need not be unique) = */ + const char *name; + /* + * Location of register: coprocessor number and (crn,crm,opc1,opc2) + * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a + * 'wildcard' field -- any value of that field in the MRC/MCR insn + * will be decoded to this register. The register read and write + * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 + * used by the program, so it is possible to register a wildcard and + * then behave differently on read/write if necessary. + * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 + * must both be zero. + * For AArch64-visible registers, opc0 is also used. + * Since there are no "coprocessors" in AArch64, cp is purely used as a + * way to distinguish (for KVM's benefit) guest-visible system registe= rs + * from demuxed ones provided to preserve the "no side effects on + * KVM register read/write from QEMU" semantics. cp=3D=3D0x13 is guest + * visible (to match KVM's encoding); cp=3D=3D0 will be converted to + * cp=3D=3D0x13 when the ARMCPRegInfo is registered, for convenience. + */ + uint8_t cp; + uint8_t crn; + uint8_t crm; + uint8_t opc0; + uint8_t opc1; + uint8_t opc2; + /* Execution state in which this register is visible: ARM_CP_STATE_* */ + int state; + /* Register type: ARM_CP_* bits/values */ + int type; + /* Access rights: PL*_[RW] */ + int access; + /* Security state: ARM_CP_SECSTATE_* bits/values */ + int secure; + /* + * The opaque pointer passed to define_arm_cp_regs_with_opaque() when + * this register was defined: can be used to hand data through to the + * register read/write functions, since they are passed the ARMCPRegIn= fo*. + */ + void *opaque; + /* + * Value of this register, if it is ARM_CP_CONST. Otherwise, if + * fieldoffset is non-zero, the reset value of the register. + */ + uint64_t resetvalue; + /* + * Offset of the field in CPUARMState for this register. + * This is not needed if either: + * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs + * 2. both readfn and writefn are specified + */ + ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ + + /* + * Offsets of the secure and non-secure fields in CPUARMState for the + * register if it is banked. These fields are only used during the st= atic + * registration of a register. During hashing the bank associated + * with a given security state is copied to fieldoffset which is used = from + * there on out. + * + * It is expected that register definitions use either fieldoffset or + * bank_fieldoffsets in the definition but not both. It is also expec= ted + * that both bank offsets are set when defining a banked register. Th= is + * use indicates that a register is banked. + */ + ptrdiff_t bank_fieldoffsets[2]; + + /* + * Function for making any access checks for this register in addition= to + * those specified by the 'access' permissions bits. If NULL, no extra + * checks required. The access check is performed at runtime, not at + * translate time. + */ + CPAccessFn *accessfn; + /* + * Function for handling reads of this register. If NULL, then reads + * will be done by loading from the offset into CPUARMState specified + * by fieldoffset. + */ + CPReadFn *readfn; + /* + * Function for handling writes of this register. If NULL, then writes + * will be done by writing to the offset into CPUARMState specified + * by fieldoffset. + */ + CPWriteFn *writefn; + /* + * Function for doing a "raw" read; used when we need to copy + * coprocessor state to the kernel for KVM or out for + * migration. This only needs to be provided if there is also a + * readfn and it has side effects (for instance clear-on-read bits). + */ + CPReadFn *raw_readfn; + /* + * Function for doing a "raw" write; used when we need to copy KVM + * kernel coprocessor state into userspace, or for inbound + * migration. This only needs to be provided if there is also a + * writefn and it masks out "unwritable" bits or has write-one-to-clear + * or similar behaviour. + */ + CPWriteFn *raw_writefn; + /* + * Function for resetting the register. If NULL, then reset will be do= ne + * by writing resetvalue to the field specified in fieldoffset. If + * fieldoffset is 0 then no reset will be done. + */ + CPResetFn *resetfn; + + /* + * "Original" writefn and readfn. + * For ARMv8.1-VHE register aliases, we overwrite the read/write + * accessor functions of various EL1/EL0 to perform the runtime + * check for which sysreg should actually be modified, and then + * forwards the operation. Before overwriting the accessors, + * the original function is copied here, so that accesses that + * really do go to the EL1/EL0 version proceed normally. + * (The corresponding EL2 register is linked via opaque.) + */ + CPReadFn *orig_readfn; + CPWriteFn *orig_writefn; +}; + +/* + * Macros which are lvalues for the field in CPUARMState for the + * ARMCPRegInfo *ri. + */ +#define CPREG_FIELD32(env, ri) \ + (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) +#define CPREG_FIELD64(env, ri) \ + (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) + +#define REGINFO_SENTINEL { .type =3D ARM_CP_SENTINEL } + +void define_arm_cp_regs_with_opaque(ARMCPU *cpu, + const ARMCPRegInfo *regs, void *opaque= ); +void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, + const ARMCPRegInfo *regs, void *opa= que); +static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *reg= s) +{ + define_arm_cp_regs_with_opaque(cpu, regs, 0); +} +static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *= regs) +{ + define_one_arm_cp_reg_with_opaque(cpu, regs, 0); +} +const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encode= d_cp); + +/* + * Definition of an ARM co-processor register as viewed from + * userspace. This is used for presenting sanitised versions of + * registers to userspace when emulating the Linux AArch64 CPU + * ID/feature ABI (advertised as HWCAP_CPUID). + */ +typedef struct ARMCPRegUserSpaceInfo { + /* Name of register */ + const char *name; + + /* Is the name actually a glob pattern */ + bool is_glob; + + /* Only some bits are exported to user space */ + uint64_t exported_bits; + + /* Fixed bits are applied after the mask */ + uint64_t fixed_bits; +} ARMCPRegUserSpaceInfo; + +#define REGUSERINFO_SENTINEL { .name =3D NULL } + +void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *m= ods); + +/* CPWriteFn that can be used to implement writes-ignored behaviour */ +void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value); +/* CPReadFn that can be used for read-as-zero behaviour */ +uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); + +/* + * CPResetFn that does nothing, for use if no reset is required even + * if fieldoffset is non zero. + */ +void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); + +/* + * Return true if this reginfo struct's field in the cpu state struct + * is 64 bits wide. + */ +static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) +{ + return (ri->state =3D=3D ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BI= T); +} + +static inline bool cp_access_ok(int current_el, + const ARMCPRegInfo *ri, int isread) +{ + return (ri->access >> ((current_el * 2) + isread)) & 1; +} + +/* Raw read of a coprocessor register (as needed for migration, etc) */ +uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); + +#endif /* TARGET_ARM_CPREGS_H */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index e7f669d0a9..76c0dd37cd 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2594,144 +2594,6 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpr= egid) return kvmid; } =20 -/* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a - * special-behaviour cp reg and bits [11..8] indicate what behaviour - * it has. Otherwise it is a simple cp reg, where CONST indicates that - * TCG can assume the value to be constant (ie load at translate time) - * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END - * indicates that the TB should not be ended after a write to this register - * (the default is that the TB ends after cp writes). OVERRIDE permits - * a register definition to override a previous definition for the - * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the - * old must have the OVERRIDE bit set. - * ALIAS indicates that this register is an alias view of some underlying - * state which is also visible via another register, and that the other - * register is handling migration and reset; registers marked ALIAS will n= ot be - * migrated but may have their state set by syncing of register state from= KVM. - * NO_RAW indicates that this register has no underlying state and does not - * support raw access for state saving/loading; it will not be used for ei= ther - * migration or KVM state synchronization. (Typically this is for "registe= rs" - * which are actually used as instructions for cache maintenance and so on= .) - * IO indicates that this register does I/O and therefore its accesses - * need to be marked with gen_io_start() and also end the TB. In particula= r, - * registers which implement clocks or timers require this. - * RAISES_EXC is for when the read or write hook might raise an exception; - * the generated code will synchronize the CPU state before calling the ho= ok - * so that it is safe for the hook to call raise_exception(). - * NEWEL is for writes to registers that might change the exception - * level - typically on older ARM chips. For those cases we need to - * re-read the new el when recomputing the translation flags. - */ -#define ARM_CP_SPECIAL 0x0001 -#define ARM_CP_CONST 0x0002 -#define ARM_CP_64BIT 0x0004 -#define ARM_CP_SUPPRESS_TB_END 0x0008 -#define ARM_CP_OVERRIDE 0x0010 -#define ARM_CP_ALIAS 0x0020 -#define ARM_CP_IO 0x0040 -#define ARM_CP_NO_RAW 0x0080 -#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) -#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) -#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) -#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) -#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) -#define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600) -#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700) -#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA -#define ARM_CP_FPU 0x1000 -#define ARM_CP_SVE 0x2000 -#define ARM_CP_NO_GDB 0x4000 -#define ARM_CP_RAISES_EXC 0x8000 -#define ARM_CP_NEWEL 0x10000 -/* Used only as a terminator for ARMCPRegInfo lists */ -#define ARM_CP_SENTINEL 0xfffff -/* Mask of only the flag bits in a type field */ -#define ARM_CP_FLAG_MASK 0x1f0ff - -/* Valid values for ARMCPRegInfo state field, indicating which of - * the AArch32 and AArch64 execution states this register is visible in. - * If the reginfo doesn't explicitly specify then it is AArch32 only. - * If the reginfo is declared to be visible in both states then a second - * reginfo is synthesised for the AArch32 view of the AArch64 register, - * such that the AArch32 view is the lower 32 bits of the AArch64 one. - * Note that we rely on the values of these enums as we iterate through - * the various states in some places. - */ -enum { - ARM_CP_STATE_AA32 =3D 0, - ARM_CP_STATE_AA64 =3D 1, - ARM_CP_STATE_BOTH =3D 2, -}; - -/* ARM CP register secure state flags. These flags identify security state - * attributes for a given CP register entry. - * The existence of both or neither secure and non-secure flags indicates = that - * the register has both a secure and non-secure hash entry. A single one= of - * these flags causes the register to only be hashed for the specified - * security state. - * Although definitions may have any combination of the S/NS bits, each - * registered entry will only have one to identify whether the entry is se= cure - * or non-secure. - */ -enum { - ARM_CP_SECSTATE_S =3D (1 << 0), /* bit[0]: Secure state register */ - ARM_CP_SECSTATE_NS =3D (1 << 1), /* bit[1]: Non-secure state register= */ -}; - -/* Return true if cptype is a valid type field. This is used to try to - * catch errors where the sentinel has been accidentally left off the end - * of a list of registers. - */ -static inline bool cptype_valid(int cptype) -{ - return ((cptype & ~ARM_CP_FLAG_MASK) =3D=3D 0) - || ((cptype & ARM_CP_SPECIAL) && - ((cptype & ~ARM_CP_FLAG_MASK) <=3D ARM_LAST_SPECIAL)); -} - -/* Access rights: - * We define bits for Read and Write access for what rev C of the v7-AR AR= M ARM - * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and - * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 - * (ie any of the privileged modes in Secure state, or Monitor mode). - * If a register is accessible in one privilege level it's always accessib= le - * in higher privilege levels too. Since "Secure PL1" also follows this ru= le - * (ie anything visible in PL2 is visible in S-PL1, some things are only - * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the - * terminology a little and call this PL3. - * In AArch64 things are somewhat simpler as the PLx bits line up exactly - * with the ELx exception levels. - * - * If access permissions for a register are more complex than can be - * described with these bits, then use a laxer set of restrictions, and - * do the more restrictive/complex check inside a helper function. - */ -#define PL3_R 0x80 -#define PL3_W 0x40 -#define PL2_R (0x20 | PL3_R) -#define PL2_W (0x10 | PL3_W) -#define PL1_R (0x08 | PL2_R) -#define PL1_W (0x04 | PL2_W) -#define PL0_R (0x02 | PL1_R) -#define PL0_W (0x01 | PL1_W) - -/* - * For user-mode some registers are accessible to EL0 via a kernel - * trap-and-emulate ABI. In this case we define the read permissions - * as actually being PL0_R. However some bits of any given register - * may still be masked. - */ -#ifdef CONFIG_USER_ONLY -#define PL0U_R PL0_R -#else -#define PL0U_R PL1_R -#endif - -#define PL3_RW (PL3_R | PL3_W) -#define PL2_RW (PL2_R | PL2_W) -#define PL1_RW (PL1_R | PL1_W) -#define PL0_RW (PL0_R | PL0_W) - /* Return the highest implemented Exception Level */ static inline int arm_highest_el(CPUARMState *env) { @@ -2783,236 +2645,6 @@ static inline int arm_current_el(CPUARMState *env) } } =20 -typedef struct ARMCPRegInfo ARMCPRegInfo; - -typedef enum CPAccessResult { - /* Access is permitted */ - CP_ACCESS_OK =3D 0, - /* Access fails due to a configurable trap or enable which would - * result in a categorized exception syndrome giving information about - * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, - * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or - * PL1 if in EL0, otherwise to the current EL). - */ - CP_ACCESS_TRAP =3D 1, - /* Access fails and results in an exception syndrome 0x0 ("uncategoriz= ed"). - * Note that this is not a catch-all case -- the set of cases which may - * result in this failure is specifically defined by the architecture. - */ - CP_ACCESS_TRAP_UNCATEGORIZED =3D 2, - /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ - CP_ACCESS_TRAP_EL2 =3D 3, - CP_ACCESS_TRAP_EL3 =3D 4, - /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ - CP_ACCESS_TRAP_UNCATEGORIZED_EL2 =3D 5, - CP_ACCESS_TRAP_UNCATEGORIZED_EL3 =3D 6, -} CPAccessResult; - -/* Access functions for coprocessor registers. These cannot fail and - * may not raise exceptions. - */ -typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); -typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, - uint64_t value); -/* Access permission check functions for coprocessor registers. */ -typedef CPAccessResult CPAccessFn(CPUARMState *env, - const ARMCPRegInfo *opaque, - bool isread); -/* Hook function for register reset */ -typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); - -#define CP_ANY 0xff - -/* Definition of an ARM coprocessor register */ -struct ARMCPRegInfo { - /* Name of register (useful mainly for debugging, need not be unique) = */ - const char *name; - /* Location of register: coprocessor number and (crn,crm,opc1,opc2) - * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a - * 'wildcard' field -- any value of that field in the MRC/MCR insn - * will be decoded to this register. The register read and write - * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 - * used by the program, so it is possible to register a wildcard and - * then behave differently on read/write if necessary. - * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 - * must both be zero. - * For AArch64-visible registers, opc0 is also used. - * Since there are no "coprocessors" in AArch64, cp is purely used as a - * way to distinguish (for KVM's benefit) guest-visible system registe= rs - * from demuxed ones provided to preserve the "no side effects on - * KVM register read/write from QEMU" semantics. cp=3D=3D0x13 is guest - * visible (to match KVM's encoding); cp=3D=3D0 will be converted to - * cp=3D=3D0x13 when the ARMCPRegInfo is registered, for convenience. - */ - uint8_t cp; - uint8_t crn; - uint8_t crm; - uint8_t opc0; - uint8_t opc1; - uint8_t opc2; - /* Execution state in which this register is visible: ARM_CP_STATE_* */ - int state; - /* Register type: ARM_CP_* bits/values */ - int type; - /* Access rights: PL*_[RW] */ - int access; - /* Security state: ARM_CP_SECSTATE_* bits/values */ - int secure; - /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when - * this register was defined: can be used to hand data through to the - * register read/write functions, since they are passed the ARMCPRegIn= fo*. - */ - void *opaque; - /* Value of this register, if it is ARM_CP_CONST. Otherwise, if - * fieldoffset is non-zero, the reset value of the register. - */ - uint64_t resetvalue; - /* Offset of the field in CPUARMState for this register. - * - * This is not needed if either: - * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs - * 2. both readfn and writefn are specified - */ - ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ - - /* Offsets of the secure and non-secure fields in CPUARMState for the - * register if it is banked. These fields are only used during the st= atic - * registration of a register. During hashing the bank associated - * with a given security state is copied to fieldoffset which is used = from - * there on out. - * - * It is expected that register definitions use either fieldoffset or - * bank_fieldoffsets in the definition but not both. It is also expec= ted - * that both bank offsets are set when defining a banked register. Th= is - * use indicates that a register is banked. - */ - ptrdiff_t bank_fieldoffsets[2]; - - /* Function for making any access checks for this register in addition= to - * those specified by the 'access' permissions bits. If NULL, no extra - * checks required. The access check is performed at runtime, not at - * translate time. - */ - CPAccessFn *accessfn; - /* Function for handling reads of this register. If NULL, then reads - * will be done by loading from the offset into CPUARMState specified - * by fieldoffset. - */ - CPReadFn *readfn; - /* Function for handling writes of this register. If NULL, then writes - * will be done by writing to the offset into CPUARMState specified - * by fieldoffset. - */ - CPWriteFn *writefn; - /* Function for doing a "raw" read; used when we need to copy - * coprocessor state to the kernel for KVM or out for - * migration. This only needs to be provided if there is also a - * readfn and it has side effects (for instance clear-on-read bits). - */ - CPReadFn *raw_readfn; - /* Function for doing a "raw" write; used when we need to copy KVM - * kernel coprocessor state into userspace, or for inbound - * migration. This only needs to be provided if there is also a - * writefn and it masks out "unwritable" bits or has write-one-to-clear - * or similar behaviour. - */ - CPWriteFn *raw_writefn; - /* Function for resetting the register. If NULL, then reset will be do= ne - * by writing resetvalue to the field specified in fieldoffset. If - * fieldoffset is 0 then no reset will be done. - */ - CPResetFn *resetfn; - - /* - * "Original" writefn and readfn. - * For ARMv8.1-VHE register aliases, we overwrite the read/write - * accessor functions of various EL1/EL0 to perform the runtime - * check for which sysreg should actually be modified, and then - * forwards the operation. Before overwriting the accessors, - * the original function is copied here, so that accesses that - * really do go to the EL1/EL0 version proceed normally. - * (The corresponding EL2 register is linked via opaque.) - */ - CPReadFn *orig_readfn; - CPWriteFn *orig_writefn; -}; - -/* Macros which are lvalues for the field in CPUARMState for the - * ARMCPRegInfo *ri. - */ -#define CPREG_FIELD32(env, ri) \ - (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) -#define CPREG_FIELD64(env, ri) \ - (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) - -#define REGINFO_SENTINEL { .type =3D ARM_CP_SENTINEL } - -void define_arm_cp_regs_with_opaque(ARMCPU *cpu, - const ARMCPRegInfo *regs, void *opaque= ); -void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, - const ARMCPRegInfo *regs, void *opa= que); -static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *reg= s) -{ - define_arm_cp_regs_with_opaque(cpu, regs, 0); -} -static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *= regs) -{ - define_one_arm_cp_reg_with_opaque(cpu, regs, 0); -} -const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encode= d_cp); - -/* - * Definition of an ARM co-processor register as viewed from - * userspace. This is used for presenting sanitised versions of - * registers to userspace when emulating the Linux AArch64 CPU - * ID/feature ABI (advertised as HWCAP_CPUID). - */ -typedef struct ARMCPRegUserSpaceInfo { - /* Name of register */ - const char *name; - - /* Is the name actually a glob pattern */ - bool is_glob; - - /* Only some bits are exported to user space */ - uint64_t exported_bits; - - /* Fixed bits are applied after the mask */ - uint64_t fixed_bits; -} ARMCPRegUserSpaceInfo; - -#define REGUSERINFO_SENTINEL { .name =3D NULL } - -void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *m= ods); - -/* CPWriteFn that can be used to implement writes-ignored behaviour */ -void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value); -/* CPReadFn that can be used for read-as-zero behaviour */ -uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); - -/* CPResetFn that does nothing, for use if no reset is required even - * if fieldoffset is non zero. - */ -void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); - -/* Return true if this reginfo struct's field in the cpu state struct - * is 64 bits wide. - */ -static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) -{ - return (ri->state =3D=3D ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BI= T); -} - -static inline bool cp_access_ok(int current_el, - const ARMCPRegInfo *ri, int isread) -{ - return (ri->access >> ((current_el * 2) + isread)) & 1; -} - -/* Raw read of a coprocessor register (as needed for migration, etc) */ -uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); - /** * write_list_to_cpustate * @cpu: ARMCPU diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index a6f938f115..0683714733 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -30,6 +30,7 @@ #include "qemu/cutils.h" #include "qemu/log.h" #include "qom/object.h" +#include "target/arm/cpregs.h" =20 static struct { hwaddr io_base; diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c index ed032fed54..b80d75d839 100644 --- a/hw/arm/pxa2xx_pic.c +++ b/hw/arm/pxa2xx_pic.c @@ -17,6 +17,7 @@ #include "hw/sysbus.h" #include "migration/vmstate.h" #include "qom/object.h" +#include "target/arm/cpregs.h" =20 #define ICIP 0x00 /* Interrupt Controller IRQ Pending register */ #define ICMR 0x04 /* Interrupt Controller Mask register */ diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 1a3d440a54..d43ba970f9 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -20,6 +20,7 @@ #include "gicv3_internal.h" #include "hw/irq.h" #include "cpu.h" +#include "target/arm/cpregs.h" =20 static GICv3CPUState *icc_cs_from_env(CPUARMState *env) { diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 5ec5ff9ef6..ed2a583b0c 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -31,6 +31,8 @@ #include "vgic_common.h" #include "migration/blocker.h" #include "qom/object.h" +#include "target/arm/cpregs.h" + =20 #ifdef DEBUG_GICV3_KVM #define DPRINTF(fmt, ...) \ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 561f180067..066fe6250a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -43,6 +43,7 @@ #include "kvm_arm.h" #include "disas/capstone.h" #include "fpu/softfloat.h" +#include "cpregs.h" =20 static void arm_cpu_set_pc(CPUState *cs, vaddr value) { diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index eb44c05822..9561714c23 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -34,6 +34,7 @@ #include "hvf_arm.h" #include "qapi/visitor.h" #include "hw/qdev-properties.h" +#include "cpregs.h" =20 =20 #ifndef CONFIG_USER_ONLY diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 13d0e9b195..0e693b182e 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -18,6 +18,7 @@ #if !defined(CONFIG_USER_ONLY) #include "hw/boards.h" #endif +#include "cpregs.h" =20 /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index ca1de47511..f01a126108 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -19,8 +19,9 @@ */ #include "qemu/osdep.h" #include "cpu.h" -#include "internals.h" #include "exec/gdbstub.h" +#include "internals.h" +#include "cpregs.h" =20 typedef struct RegisterSysregXmlParam { CPUState *cs; diff --git a/target/arm/helper.c b/target/arm/helper.c index 60d9233b7e..8928ffb6a7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -37,6 +37,7 @@ #include "exec/cpu_ldst.h" #include "semihosting/common-semi.h" #endif +#include "cpregs.h" =20 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ #define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */ diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 2b87e8808b..67be91c732 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -23,6 +23,7 @@ #include "internals.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" +#include "cpregs.h" =20 #define SIGNBIT (uint32_t)0x80000000 #define SIGNBIT64 ((uint64_t)1 << 63) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 3867910ed4..92b91f0307 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -27,14 +27,12 @@ #include "translate.h" #include "internals.h" #include "qemu/host-utils.h" - #include "semihosting/semihost.h" #include "exec/gen-icount.h" - #include "exec/helper-proto.h" #include "exec/helper-gen.h" #include "exec/log.h" - +#include "cpregs.h" #include "translate-a64.h" #include "qemu/atomic128.h" =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index 5cb4b3da33..1fe48e4e1c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -30,11 +30,10 @@ #include "qemu/bitops.h" #include "arm_ldst.h" #include "semihosting/semihost.h" - #include "exec/helper-proto.h" #include "exec/helper-gen.h" - #include "exec/log.h" +#include "cpregs.h" =20 =20 #define ENABLE_ARCH_4T arm_dc_feature(s, ARM_FEATURE_V4T) --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650219839; cv=none; d=zohomail.com; s=zohoarc; b=mkGtqe82DDXjl5EQFz6NQYCQ4Y/NzB4pc3Qk70PppMQozQb8z34hApXAV1urK7qKtjLhf9jpFlHthJBqRHDKElFkYX+2dXUhZdK5CA3MZVuDegt0+aZ0+8FaMvaSnzZbcRGJBAfpcMTPe6dsKCIJSJkwAqetG9jW3Clo+KEGduU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650219839; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/kQGH0Cy2HcRWOzQdszvWYCvmoLOtgBt5ZPwOUyma0Q=; b=lmjUDI1yv4lddlzoqKD7mQqboDRm3nc65Ye2prNduQh31jd+gZnOMt5P6A3MYiASTZiKEaPZqny3z5E7ixNnkyDb6J4YwnU2pbWBc+dIRwHWfe6J6/EpUFMRP9gxDFfIFxExPmR/sN2W3YNi+0BJf5T9v3fdHAe2H7mVuDJQm5E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650219839308585.9084832119156; Sun, 17 Apr 2022 11:23:59 -0700 (PDT) Received: from localhost ([::1]:35814 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9Yz-00054R-Vh for importer@patchew.org; Sun, 17 Apr 2022 14:23:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48392) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng8xD-0000yW-9x for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:55 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:46649) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng8xA-0003MY-Ua for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:44:54 -0400 Received: by mail-pj1-x1033.google.com with SMTP id h15-20020a17090a054f00b001cb7cd2b11dso12207472pjf.5 for ; Sun, 17 Apr 2022 10:44:52 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/kQGH0Cy2HcRWOzQdszvWYCvmoLOtgBt5ZPwOUyma0Q=; b=wQAAsmyg3n5S4LCPwHVToO0VZ2joUjpYmEbZ+5t0AWJ0EgNje3FkibzaA+gW4ndzCp EMcj8aWHiRsksbK7rsBECqUAgNUt7DHZavxlvgUWi2cuamDnuRfAQZ2wadKYkGNDE4o+ uX9/JB/7NFYKHlD8d4kxFGGcYbDdeo1ua2n7otSJWjQE0IBfxC/woMGJHWi5iqtFqGLh jNYggpGlIR5kawCPT/E3aYUpJpBZNp/s4Yr9HSmzkmov03S+u5Loh1kDq9BjGVyDclgE cUjFYhpkSvZTXVpfBV79SMvSd7IouIHokZvdlFbGI5lxazmKjehWrbYzjKyvNpgg9r6M WBYg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/kQGH0Cy2HcRWOzQdszvWYCvmoLOtgBt5ZPwOUyma0Q=; b=IaP6hXokvrA2AtAS+RoIsS0cI5JlYT4xNIAoCcOVoqcSUn3VuTSKYVhBSDW3WwELNJ 8SFjATCwfSCONyEVpfNdL52p31+CxPIqIGAaL/X8k7NX9GsYuLwb6pDMFykofOv4hYiz l3CddwE0utxJlJazBbDNZzRTgCnQ+0C77Mk3DX9PPri48YugLJRUE1uN7+BNqQVNzN4W XB1O2oefie4XP2z0v9eLLmSvc4OGSr43E5H+pcYV8CEyvUVbhGJNbk1PX8vPUPe6rrR6 LiVm4dp0Z5cq6fqWzVTxwpse21V1WVJCszxXr8hOinKJD2v2awYXwEX192w72uolPhnG ZBXQ== X-Gm-Message-State: AOAM532TAni9RTtOBVyMixZaPAPiUHTPuJ6ikQUbVEYAGHohOg5tLZsx PtRdmshpjLMXRFugkx6B4H+AlzsMmrDC9A== X-Google-Smtp-Source: ABdhPJxcs3UM5RWSpnFYg/ZuKXWa2HfYB5+ucs7+4AWJmJu+EkqyNvZxCVADm5KyKGk+s9r5qeP/Ew== X-Received: by 2002:a17:902:e0ca:b0:158:cc0a:44f7 with SMTP id e10-20020a170902e0ca00b00158cc0a44f7mr7343242pla.70.1650217491599; Sun, 17 Apr 2022 10:44:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 25/60] target/arm: Reorg CPAccessResult and access_check_cp_reg Date: Sun, 17 Apr 2022 10:43:51 -0700 Message-Id: <20220417174426.711829-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650219840845100001 Content-Type: text/plain; charset="utf-8" Rearrange the values of the enumerators of CPAccessResult so that we may directly extract the target el. For the two special cases in access_check_cp_reg, use CPAccessResult. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell --- target/arm/cpregs.h | 26 ++++++++++++-------- target/arm/op_helper.c | 56 +++++++++++++++++++++--------------------- 2 files changed, 44 insertions(+), 38 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 005aa2d3a5..700fcc1478 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -167,26 +167,32 @@ static inline bool cptype_valid(int cptype) typedef enum CPAccessResult { /* Access is permitted */ CP_ACCESS_OK =3D 0, + + /* + * Combined with one of the following, the low 2 bits indicate the + * target exception level. If 0, the exception is taken to the usual + * target EL (EL1 or PL1 if in EL0, otherwise to the current EL). + */ + CP_ACCESS_EL_MASK =3D 3, + /* * Access fails due to a configurable trap or enable which would * result in a categorized exception syndrome giving information about * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, - * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or - * PL1 if in EL0, otherwise to the current EL). + * 0xc or 0x18). */ - CP_ACCESS_TRAP =3D 1, + CP_ACCESS_TRAP =3D (1 << 2), + CP_ACCESS_TRAP_EL2 =3D CP_ACCESS_TRAP | 2, + CP_ACCESS_TRAP_EL3 =3D CP_ACCESS_TRAP | 3, + /* * Access fails and results in an exception syndrome 0x0 ("uncategoriz= ed"). * Note that this is not a catch-all case -- the set of cases which may * result in this failure is specifically defined by the architecture. */ - CP_ACCESS_TRAP_UNCATEGORIZED =3D 2, - /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ - CP_ACCESS_TRAP_EL2 =3D 3, - CP_ACCESS_TRAP_EL3 =3D 4, - /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ - CP_ACCESS_TRAP_UNCATEGORIZED_EL2 =3D 5, - CP_ACCESS_TRAP_UNCATEGORIZED_EL3 =3D 6, + CP_ACCESS_TRAP_UNCATEGORIZED =3D (2 << 2), + CP_ACCESS_TRAP_UNCATEGORIZED_EL2 =3D CP_ACCESS_TRAP_UNCATEGORIZED | 2, + CP_ACCESS_TRAP_UNCATEGORIZED_EL3 =3D CP_ACCESS_TRAP_UNCATEGORIZED | 3, } CPAccessResult; =20 typedef struct ARMCPRegInfo ARMCPRegInfo; diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 67be91c732..76499ffa14 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -632,11 +632,13 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, vo= id *rip, uint32_t syndrome, uint32_t isread) { const ARMCPRegInfo *ri =3D rip; + CPAccessResult res =3D CP_ACCESS_OK; int target_el; =20 if (arm_feature(env, ARM_FEATURE_XSCALE) && ri->cp < 14 && extract32(env->cp15.c15_cpar, ri->cp, 1) =3D=3D 0) { - raise_exception(env, EXCP_UDEF, syndrome, exception_target_el(env)= ); + res =3D CP_ACCESS_TRAP; + goto fail; } =20 /* @@ -655,48 +657,46 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, vo= id *rip, uint32_t syndrome, mask &=3D ~((1 << 4) | (1 << 14)); =20 if (env->cp15.hstr_el2 & mask) { - target_el =3D 2; - goto exept; + res =3D CP_ACCESS_TRAP_EL2; + goto fail; } } =20 - if (!ri->accessfn) { + if (ri->accessfn) { + res =3D ri->accessfn(env, ri, isread); + } + if (likely(res =3D=3D CP_ACCESS_OK)) { return; } =20 - switch (ri->accessfn(env, ri, isread)) { - case CP_ACCESS_OK: - return; + fail: + switch (res & ~CP_ACCESS_EL_MASK) { case CP_ACCESS_TRAP: - target_el =3D exception_target_el(env); - break; - case CP_ACCESS_TRAP_EL2: - /* Requesting a trap to EL2 when we're in EL3 is - * a bug in the access function. - */ - assert(arm_current_el(env) !=3D 3); - target_el =3D 2; - break; - case CP_ACCESS_TRAP_EL3: - target_el =3D 3; break; case CP_ACCESS_TRAP_UNCATEGORIZED: - target_el =3D exception_target_el(env); - syndrome =3D syn_uncategorized(); - break; - case CP_ACCESS_TRAP_UNCATEGORIZED_EL2: - target_el =3D 2; - syndrome =3D syn_uncategorized(); - break; - case CP_ACCESS_TRAP_UNCATEGORIZED_EL3: - target_el =3D 3; syndrome =3D syn_uncategorized(); break; default: g_assert_not_reached(); } =20 -exept: + target_el =3D res & CP_ACCESS_EL_MASK; + switch (target_el) { + case 0: + target_el =3D exception_target_el(env); + break; + case 2: + assert(arm_current_el(env) !=3D 3); + assert(arm_is_el2_enabled(env)); + break; + case 3: + assert(arm_feature(env, ARM_FEATURE_EL3)); + break; + default: + /* No "direct" traps to EL1 */ + g_assert_not_reached(); + } + raise_exception(env, EXCP_UDEF, syndrome, target_el); } =20 --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650218857; cv=none; d=zohomail.com; s=zohoarc; b=mOdB1njBhcovXo+RBSjl2PURiYXGQVNPCa1/rhscIsHb21lae2PKpYOBgHzSug2HAUpQxaAOYejIDpU644gVOeq4VIuLCV3Xqn/MimHG0iUtbqXYIug1d+njzEN56OzcJ5BTNSgPFUOf2HkfCk7AhFG5PWggh9IWIibnWmWDpS0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650218857; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Gkgsg3onX5Hjd+QC7tmsSKQPPIxaAKKPbGO7yUYNElE=; b=umJh2AFu+eFcKCMhFALZXsAWF9bQ1+3PXOcaeH0ztFhm66dA4WPK2l4qysFtQQi8X8 e1PiAzZamzJatA78kTzaZk2wCrbKjhI2I1EZa07SlaEdnhDkqYt5W/PXFCw+egnGqdAj DlI30Mzj/WM4mpEiyXoCxzn2Rc2kTQEtcrzrU8yEEkTMDlyfYnQ7SPcy/i0ned0/F2V1 zCIhBfEayA7MG3U+Y/dACmDtu+S1XKko8IJTcW+ZCy6ofUqnuiQariVhctxjL6t9DwmM AHVBVo2enRPkKhPNgq9gbe9FLXgIUS+Z8hA3GOhaPs1IBoPRM5hpbh3T7vQzgGO8lHMD wsvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Gkgsg3onX5Hjd+QC7tmsSKQPPIxaAKKPbGO7yUYNElE=; b=MqnEEySIDzsLzUEbZQgRolAidL9YVr2YKzPKENzz//XVpaikWRcrInwA5FJvpQhyJM 7xzEEjk0J3wrI92J3NwNtQpXFPklZXowJUtZGmkNwFh4aTFvAT/wRSJthi0HmZuCpUTy xn3be+TkA1Wogx6Cth/yivhzi3SEYDEfCFIDzF3ECbnAdcXrx/PnDJld2xtqJ4X3GwTq cfSwnlyO4E2MBkAmkIDAa6ECL9PIeDk752NvLa537l/dQofrBSjyoBuVYnAYgscPcHxN AzENy5zo5+VGsYg9LSlQtRuaefNACqLlkHlE6hv6lENkPT74I9385A8kzbJme55xu4/t EOPg== X-Gm-Message-State: AOAM531NklVItKx+tYhKdH/9eEBi3VKR9Hjhz7+hERz9zCOLHd3br8GL wT3lyDIG5ZULzqQuXyRD6mK3kHIwwiQsJg== X-Google-Smtp-Source: ABdhPJyG3kzUbKcSQNUVzxfN6ACi7fjulJXjZLC2WRNxBozd5imYY1Z0km7ooVwFqHey5u6g6/Ykng== X-Received: by 2002:a63:fb05:0:b0:39d:a07b:cf4 with SMTP id o5-20020a63fb05000000b0039da07b0cf4mr7168606pgh.440.1650217492723; Sun, 17 Apr 2022 10:44:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 26/60] target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h Date: Sun, 17 Apr 2022 10:43:52 -0700 Message-Id: <20220417174426.711829-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650218858444100001 Content-Type: text/plain; charset="utf-8" Remove a possible source of error by removing REGINFO_SENTINEL and using ARRAY_SIZE (convinently hidden inside a macro) to find the end of the set of regs being registered or modified. The space saved by not having the extra array element reduces the executable's .data.rel.ro section by about 9k. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell --- target/arm/cpregs.h | 57 +++++++++++--------- hw/arm/pxa2xx.c | 1 - hw/arm/pxa2xx_pic.c | 1 - hw/intc/arm_gicv3_cpuif.c | 5 -- hw/intc/arm_gicv3_kvm.c | 1 - target/arm/cpu64.c | 1 - target/arm/cpu_tcg.c | 4 -- target/arm/helper.c | 111 ++++++++------------------------------ 8 files changed, 52 insertions(+), 129 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 700fcc1478..bd321d6d23 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -71,8 +71,6 @@ #define ARM_CP_NO_GDB 0x4000 #define ARM_CP_RAISES_EXC 0x8000 #define ARM_CP_NEWEL 0x10000 -/* Used only as a terminator for ARMCPRegInfo lists */ -#define ARM_CP_SENTINEL 0xfffff /* Mask of only the flag bits in a type field */ #define ARM_CP_FLAG_MASK 0x1f0ff =20 @@ -108,18 +106,6 @@ enum { ARM_CP_SECSTATE_NS =3D (1 << 1), /* bit[1]: Non-secure state register= */ }; =20 -/* - * Return true if cptype is a valid type field. This is used to try to - * catch errors where the sentinel has been accidentally left off the end - * of a list of registers. - */ -static inline bool cptype_valid(int cptype) -{ - return ((cptype & ~ARM_CP_FLAG_MASK) =3D=3D 0) - || ((cptype & ARM_CP_SPECIAL) && - ((cptype & ~ARM_CP_FLAG_MASK) <=3D ARM_LAST_SPECIAL)); -} - /* * Access rights: * We define bits for Read and Write access for what rev C of the v7-AR AR= M ARM @@ -346,20 +332,31 @@ struct ARMCPRegInfo { #define CPREG_FIELD64(env, ri) \ (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) =20 -#define REGINFO_SENTINEL { .type =3D ARM_CP_SENTINEL } +void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, const ARMCPRegInfo *re= g, + void *opaque); =20 -void define_arm_cp_regs_with_opaque(ARMCPU *cpu, - const ARMCPRegInfo *regs, void *opaque= ); -void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, - const ARMCPRegInfo *regs, void *opa= que); -static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *reg= s) -{ - define_arm_cp_regs_with_opaque(cpu, regs, 0); -} static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *= regs) { - define_one_arm_cp_reg_with_opaque(cpu, regs, 0); + define_one_arm_cp_reg_with_opaque(cpu, regs, NULL); } + +void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *r= egs, + void *opaque, size_t len); + +#define define_arm_cp_regs_with_opaque(CPU, REGS, OPAQUE) \ + do { \ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) =3D=3D 0); = \ + if (ARRAY_SIZE(REGS) =3D=3D 1) { = \ + define_one_arm_cp_reg_with_opaque(CPU, REGS, OPAQUE); \ + } else { \ + define_arm_cp_regs_with_opaque_len(CPU, REGS, OPAQUE, \ + ARRAY_SIZE(REGS)); \ + } \ + } while (0) + +#define define_arm_cp_regs(CPU, REGS) \ + define_arm_cp_regs_with_opaque(CPU, REGS, NULL) + const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encode= d_cp); =20 /* @@ -382,9 +379,17 @@ typedef struct ARMCPRegUserSpaceInfo { uint64_t fixed_bits; } ARMCPRegUserSpaceInfo; =20 -#define REGUSERINFO_SENTINEL { .name =3D NULL } +void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len, + const ARMCPRegUserSpaceInfo *mods, + size_t mods_len); =20 -void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *m= ods); +#define modify_arm_cp_regs(REGS, MODS) \ + do { \ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) =3D=3D 0); = \ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(MODS) =3D=3D 0); = \ + modify_arm_cp_regs_with_len(REGS, ARRAY_SIZE(REGS), \ + MODS, ARRAY_SIZE(MODS)); \ + } while (0) =20 /* CPWriteFn that can be used to implement writes-ignored behaviour */ void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index 0683714733..f4f687df68 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -384,7 +384,6 @@ static const ARMCPRegInfo pxa_cp_reginfo[] =3D { { .name =3D "PWRMODE", .cp =3D 14, .crn =3D 7, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, .access =3D PL1_RW, .type =3D ARM_CP_IO, .readfn =3D arm_cp_read_zero, .writefn =3D pxa2xx_pwrmode_write }, - REGINFO_SENTINEL }; =20 static void pxa2xx_setup_cp14(PXA2xxState *s) diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c index b80d75d839..47132ab982 100644 --- a/hw/arm/pxa2xx_pic.c +++ b/hw/arm/pxa2xx_pic.c @@ -257,7 +257,6 @@ static const ARMCPRegInfo pxa_pic_cp_reginfo[] =3D { REGINFO_FOR_PIC_CP("ICLR2", 8), REGINFO_FOR_PIC_CP("ICFP2", 9), REGINFO_FOR_PIC_CP("ICPR2", 0xa), - REGINFO_SENTINEL }; =20 static const MemoryRegionOps pxa2xx_pic_ops =3D { diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index d43ba970f9..a4c08f2ff9 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -2309,7 +2309,6 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] =3D { .readfn =3D icc_igrpen1_el3_read, .writefn =3D icc_igrpen1_el3_write, }, - REGINFO_SENTINEL }; =20 static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -2559,7 +2558,6 @@ static const ARMCPRegInfo gicv3_cpuif_hcr_reginfo[] = =3D { .readfn =3D ich_vmcr_read, .writefn =3D ich_vmcr_write, }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_reginfo[] =3D { @@ -2577,7 +2575,6 @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_regin= fo[] =3D { .readfn =3D ich_ap_read, .writefn =3D ich_ap_write, }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] =3D { @@ -2609,7 +2606,6 @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_regi= nfo[] =3D { .readfn =3D ich_ap_read, .writefn =3D ich_ap_write, }, - REGINFO_SENTINEL }; =20 static void gicv3_cpuif_el_change_hook(ARMCPU *cpu, void *opaque) @@ -2678,7 +2674,6 @@ void gicv3_init_cpuif(GICv3State *s) .readfn =3D ich_lr_read, .writefn =3D ich_lr_write, }, - REGINFO_SENTINEL }; define_arm_cp_regs(cpu, lr_regset); } diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index ed2a583b0c..36accae257 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -735,7 +735,6 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] =3D { */ .resetfn =3D arm_gicv3_icc_reset, }, - REGINFO_SENTINEL }; =20 /** diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 9561714c23..c40373bd18 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -91,7 +91,6 @@ static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[]= =3D { { .name =3D "L2MERRSR", .cp =3D 15, .opc1 =3D 3, .crm =3D 15, .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, - REGINFO_SENTINEL }; =20 static void aarch64_a57_initfn(Object *obj) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 0e693b182e..9338088b22 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -264,7 +264,6 @@ static const ARMCPRegInfo cortexa8_cp_reginfo[] =3D { .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "L2AUXCR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1= , .opc2 =3D 2, .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 static void cortex_a8_initfn(Object *obj) @@ -332,7 +331,6 @@ static const ARMCPRegInfo cortexa9_cp_reginfo[] =3D { .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST }, { .name =3D "TLB_ATTR", .cp =3D 15, .crn =3D 15, .crm =3D 7, .opc1 =3D= 5, .opc2 =3D 2, .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST }, - REGINFO_SENTINEL }; =20 static void cortex_a9_initfn(Object *obj) @@ -398,7 +396,6 @@ static const ARMCPRegInfo cortexa15_cp_reginfo[] =3D { #endif { .name =3D "L2ECTLR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1= , .opc2 =3D 3, .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 static void cortex_a7_initfn(Object *obj) @@ -686,7 +683,6 @@ static const ARMCPRegInfo cortexr5_cp_reginfo[] =3D { .access =3D PL1_RW, .type =3D ARM_CP_CONST }, { .name =3D "DCACHE_INVAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 15, .crm= =3D 5, .opc2 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NOP }, - REGINFO_SENTINEL }; =20 static void cortex_r5_initfn(Object *obj) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8928ffb6a7..d6c34c7826 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -674,7 +674,6 @@ static const ARMCPRegInfo cp_reginfo[] =3D { .secure =3D ARM_CP_SECSTATE_S, .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_s), .resetvalue =3D 0, .writefn =3D contextidr_write, .raw_writefn =3D r= aw_write, }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo not_v8_cp_reginfo[] =3D { @@ -703,7 +702,6 @@ static const ARMCPRegInfo not_v8_cp_reginfo[] =3D { { .name =3D "CACHEMAINT", .cp =3D 15, .crn =3D 7, .crm =3D CP_ANY, .opc1 =3D 0, .opc2 =3D CP_ANY, .access =3D PL1_W, .type =3D ARM_CP_NOP | ARM_CP_OVERRIDE }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo not_v6_cp_reginfo[] =3D { @@ -712,7 +710,6 @@ static const ARMCPRegInfo not_v6_cp_reginfo[] =3D { */ { .name =3D "WFI_v5", .cp =3D 15, .crn =3D 7, .crm =3D 8, .opc1 =3D 0,= .opc2 =3D 2, .access =3D PL1_W, .type =3D ARM_CP_WFI }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo not_v7_cp_reginfo[] =3D { @@ -761,7 +758,6 @@ static const ARMCPRegInfo not_v7_cp_reginfo[] =3D { .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .type =3D ARM_CP_NOP }, { .name =3D "NMRR", .cp =3D 15, .crn =3D 10, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .type =3D ARM_CP_NOP }, - REGINFO_SENTINEL }; =20 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -890,7 +886,6 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { .crn =3D 1, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, .accessfn =3D cpac= r_access, .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.cpac= r_el1), .resetfn =3D cpacr_reset, .writefn =3D cpacr_write, .readfn =3D cpac= r_read }, - REGINFO_SENTINEL }; =20 typedef struct pm_event { @@ -2136,7 +2131,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { { .name =3D "TLBIMVAA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 3, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, .writefn =3D tlbimvaa_write }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo v7mp_cp_reginfo[] =3D { @@ -2153,7 +2147,6 @@ static const ARMCPRegInfo v7mp_cp_reginfo[] =3D { { .name =3D "TLBIMVAAIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 3, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, .writefn =3D tlbimvaa_is_write }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo pmovsset_cp_reginfo[] =3D { @@ -2171,7 +2164,6 @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmovsr), .writefn =3D pmovsset_write, .raw_writefn =3D raw_write }, - REGINFO_SENTINEL }; =20 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -2212,7 +2204,6 @@ static const ARMCPRegInfo t2ee_cp_reginfo[] =3D { { .name =3D "TEEHBR", .cp =3D 14, .crn =3D 1, .crm =3D 0, .opc1 =3D 6,= .opc2 =3D 0, .access =3D PL0_RW, .fieldoffset =3D offsetof(CPUARMState, teehbr), .accessfn =3D teehbr_access, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo v6k_cp_reginfo[] =3D { @@ -2244,7 +2235,6 @@ static const ARMCPRegInfo v6k_cp_reginfo[] =3D { .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tpidrprw_s), offsetoflow32(CPUARMState, cp15.tpidrprw_ns) = }, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 #ifndef CONFIG_USER_ONLY @@ -3092,7 +3082,6 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cv= al), .writefn =3D gt_sec_cval_write, .raw_writefn =3D raw_write, }, - REGINFO_SENTINEL }; =20 static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3133,7 +3122,6 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .access =3D PL0_R, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .readfn =3D gt_virt_cnt_read, }, - REGINFO_SENTINEL }; =20 #endif @@ -3497,7 +3485,6 @@ static const ARMCPRegInfo vapa_cp_reginfo[] =3D { .access =3D PL1_W, .accessfn =3D ats_access, .writefn =3D ats_write, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC = }, #endif - REGINFO_SENTINEL }; =20 /* Return basic MPU access permission bits. */ @@ -3620,7 +3607,6 @@ static const ARMCPRegInfo pmsav7_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]), .writefn =3D pmsav7_rgnr_write, .resetfn =3D arm_cp_reset_ignore }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo pmsav5_cp_reginfo[] =3D { @@ -3671,7 +3657,6 @@ static const ARMCPRegInfo pmsav5_cp_reginfo[] =3D { { .name =3D "946_PRBS7", .cp =3D 15, .crn =3D 6, .crm =3D 7, .opc1 =3D= 0, .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[7]) }, - REGINFO_SENTINEL }; =20 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3825,7 +3810,6 @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fieldoffset =3D offsetof(CPUARMState, cp15.far_el[1]), .resetvalue =3D 0, }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { @@ -3858,7 +3842,6 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { /* No offsetoflow32 -- pass the entire TCR to writefn/raw_writefn. */ .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.tcr_el[3]), offsetof(CPUARMState, cp15.tcr_el[1])} }, - REGINFO_SENTINEL }; =20 /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing @@ -3943,7 +3926,6 @@ static const ARMCPRegInfo omap_cp_reginfo[] =3D { { .name =3D "C9", .cp =3D 15, .crn =3D 9, .crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1= _RW, .type =3D ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3976,7 +3958,6 @@ static const ARMCPRegInfo xscale_cp_reginfo[] =3D { { .name =3D "XSCALE_UNLOCK_DCACHE", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 2, .opc2 =3D 1, .access =3D PL1_W, .type =3D ARM_CP_NOP }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo dummy_c15_cp_reginfo[] =3D { @@ -3990,7 +3971,6 @@ static const ARMCPRegInfo dummy_c15_cp_reginfo[] =3D { .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] =3D { @@ -3998,7 +3978,6 @@ static const ARMCPRegInfo cache_dirty_status_cp_regin= fo[] =3D { { .name =3D "CDSR", .cp =3D 15, .crn =3D 7, .crm =3D 10, .opc1 =3D 0, = .opc2 =3D 6, .access =3D PL1_R, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] =3D { @@ -4019,7 +3998,6 @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[= ] =3D { .access =3D PL0_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, { .name =3D "CIDCR", .cp =3D 15, .crm =3D 14, .opc1 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] =3D { @@ -4032,7 +4010,6 @@ static const ARMCPRegInfo cache_test_clean_cp_reginfo= [] =3D { { .name =3D "TCI_DCACHE", .cp =3D 15, .crn =3D 7, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 3, .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW, .resetvalue =3D (1 << 30) }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo strongarm_cp_reginfo[] =3D { @@ -4041,7 +4018,6 @@ static const ARMCPRegInfo strongarm_cp_reginfo[] =3D { .crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW }, - REGINFO_SENTINEL }; =20 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -4108,7 +4084,6 @@ static const ARMCPRegInfo lpae_cp_reginfo[] =3D { .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) }, .writefn =3D vmsa_ttbr_write, }, - REGINFO_SENTINEL }; =20 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -5127,7 +5102,6 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_trap_aa32s_el1, .writefn =3D sdcr_write, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.mdcr_el3) }, - REGINFO_SENTINEL }; =20 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ @@ -5238,7 +5212,6 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] =3D= { .type =3D ARM_CP_CONST, .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 2, .access =3D PL2_RW, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 /* Ditto, but for registers which exist in ARMv8 but not v7 */ @@ -5247,7 +5220,6 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = =3D { .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 4, .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_= mask) @@ -5680,7 +5652,6 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .cp =3D 15, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 = =3D 3, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.hstr_el2) }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo el2_v8_cp_reginfo[] =3D { @@ -5690,7 +5661,6 @@ static const ARMCPRegInfo el2_v8_cp_reginfo[] =3D { .access =3D PL2_RW, .fieldoffset =3D offsetofhigh32(CPUARMState, cp15.hcr_el2), .writefn =3D hcr_writehigh }, - REGINFO_SENTINEL }; =20 static CPAccessResult sel2_access(CPUARMState *env, const ARMCPRegInfo *ri, @@ -5711,7 +5681,6 @@ static const ARMCPRegInfo el2_sec_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 6, .opc2 =3D 2, .access =3D PL2_RW, .accessfn =3D sel2_access, .fieldoffset =3D offsetof(CPUARMState, cp15.vstcr_el2) }, - REGINFO_SENTINEL }; =20 static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *r= i, @@ -5837,7 +5806,6 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D { .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 5, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, .writefn =3D tlbi_aa64_vae3_write }, - REGINFO_SENTINEL }; =20 #ifndef CONFIG_USER_ONLY @@ -6123,7 +6091,6 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 = =3D 0, .access =3D PL1_RW, .accessfn =3D access_tda, .type =3D ARM_CP_NOP }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo debug_lpae_cp_reginfo[] =3D { @@ -6132,7 +6099,6 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] =3D= { .access =3D PL0_R, .type =3D ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = =3D 0 }, { .name =3D "DBGDSAR", .cp =3D 14, .crm =3D 2, .opc1 =3D 0, .access =3D PL0_R, .type =3D ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = =3D 0 }, - REGINFO_SENTINEL }; =20 /* Return the exception level to which exceptions should be taken @@ -6618,7 +6584,6 @@ static void define_debug_regs(ARMCPU *cpu) .fieldoffset =3D offsetof(CPUARMState, cp15.dbgbcr[i]), .writefn =3D dbgbcr_write, .raw_writefn =3D raw_write }, - REGINFO_SENTINEL }; define_arm_cp_regs(cpu, dbgregs); } @@ -6637,7 +6602,6 @@ static void define_debug_regs(ARMCPU *cpu) .fieldoffset =3D offsetof(CPUARMState, cp15.dbgwcr[i]), .writefn =3D dbgwcr_write, .raw_writefn =3D raw_write }, - REGINFO_SENTINEL }; define_arm_cp_regs(cpu, dbgregs); } @@ -6700,7 +6664,6 @@ static void define_pmu_regs(ARMCPU *cpu) .type =3D ARM_CP_IO, .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_writefn, .raw_writefn =3D pmevtyper_rawwrite }, - REGINFO_SENTINEL }; define_arm_cp_regs(cpu, pmev_regs); g_free(pmevcntr_name); @@ -6718,7 +6681,6 @@ static void define_pmu_regs(ARMCPU *cpu) .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 5, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, .resetvalue =3D extract64(cpu->pmceid1, 32, 32) }, - REGINFO_SENTINEL }; define_arm_cp_regs(cpu, v81_pmu_regs); } @@ -6815,7 +6777,6 @@ static const ARMCPRegInfo lor_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 7, .access =3D PL1_R, .accessfn =3D access_lor_ns, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 #ifdef TARGET_AARCH64 @@ -6878,7 +6839,6 @@ static const ARMCPRegInfo pauth_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 1, .opc2 =3D 3, .access =3D PL1_RW, .accessfn =3D access_pauth, .fieldoffset =3D offsetof(CPUARMState, keys.apib.hi) }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo tlbirange_reginfo[] =3D { @@ -6990,7 +6950,6 @@ static const ARMCPRegInfo tlbirange_reginfo[] =3D { .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, .writefn =3D tlbi_aa64_rvae3_write }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo tlbios_reginfo[] =3D { @@ -7062,7 +7021,6 @@ static const ARMCPRegInfo tlbios_reginfo[] =3D { .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 5, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, .writefn =3D tlbi_aa64_vae3is_write }, - REGINFO_SENTINEL }; =20 static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) @@ -7101,7 +7059,6 @@ static const ARMCPRegInfo rndr_reginfo[] =3D { .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 2, .crm =3D 4, .opc2 =3D 1, .access =3D PL0_R, .readfn =3D rndr_readfn }, - REGINFO_SENTINEL }; =20 #ifndef CONFIG_USER_ONLY @@ -7137,7 +7094,6 @@ static const ARMCPRegInfo dcpop_reg[] =3D { .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, .accessfn =3D aa64_cacheop_poc_access, .writefn =3D dccvap_writefn }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo dcpodp_reg[] =3D { @@ -7145,7 +7101,6 @@ static const ARMCPRegInfo dcpodp_reg[] =3D { .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, .accessfn =3D aa64_cacheop_poc_access, .writefn =3D dccvap_writefn }, - REGINFO_SENTINEL }; #endif /*CONFIG_USER_ONLY*/ =20 @@ -7247,14 +7202,12 @@ static const ARMCPRegInfo mte_reginfo[] =3D { { .name =3D "DC_CIGDSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 6, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo mte_tco_ro_reginfo[] =3D { { .name =3D "TCO", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 4, .crm =3D 2, .opc2 =3D 7, .type =3D ARM_CP_CONST, .access =3D PL0_RW, }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo mte_el0_cacheop_reginfo[] =3D { @@ -7306,7 +7259,6 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = =3D { .accessfn =3D aa64_zva_access, #endif }, - REGINFO_SENTINEL }; =20 #endif @@ -7352,7 +7304,6 @@ static const ARMCPRegInfo predinv_reginfo[] =3D { { .name =3D "CPPRCTX", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 3, .opc2 =3D 7, .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, - REGINFO_SENTINEL }; =20 static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -7367,7 +7318,6 @@ static const ARMCPRegInfo ccsidr2_reginfo[] =3D { .access =3D PL1_R, .accessfn =3D access_aa64_tid2, .readfn =3D ccsidr2_read, .type =3D ARM_CP_NO_RAW }, - REGINFO_SENTINEL }; =20 static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInf= o *ri, @@ -7428,7 +7378,6 @@ static const ARMCPRegInfo jazelle_regs[] =3D { .cp =3D 14, .crn =3D 2, .crm =3D 0, .opc1 =3D 7, .opc2 =3D 0, .accessfn =3D access_joscr_jmcr, .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo vhe_reginfo[] =3D { @@ -7493,7 +7442,6 @@ static const ARMCPRegInfo vhe_reginfo[] =3D { .access =3D PL2_RW, .accessfn =3D e2h_access, .writefn =3D gt_virt_cval_write, .raw_writefn =3D raw_write }, #endif - REGINFO_SENTINEL }; =20 #ifndef CONFIG_USER_ONLY @@ -7506,7 +7454,6 @@ static const ARMCPRegInfo ats1e1_reginfo[] =3D { .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 1, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn =3D ats_write64 }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo ats1cp_reginfo[] =3D { @@ -7518,7 +7465,6 @@ static const ARMCPRegInfo ats1cp_reginfo[] =3D { .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 1, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn =3D ats_write }, - REGINFO_SENTINEL }; #endif =20 @@ -7540,7 +7486,6 @@ static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = =3D { .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D 3, .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 void register_cp_regs_for_features(ARMCPU *cpu) @@ -7647,7 +7592,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, .resetvalue =3D cpu->isar.id_isar6 }, - REGINFO_SENTINEL }; define_arm_cp_regs(cpu, v6_idregs); define_arm_cp_regs(cpu, v6_cp_reginfo); @@ -7915,7 +7859,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D= 7, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, .resetvalue =3D cpu->pmceid1 }, - REGINFO_SENTINEL }; #ifdef CONFIG_USER_ONLY ARMCPRegUserSpaceInfo v8_user_idregs[] =3D { @@ -7945,7 +7888,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .exported_bits =3D 0x000000f0ffffffff }, { .name =3D "ID_AA64ISAR*_EL1_RESERVED", .is_glob =3D true }, - REGUSERINFO_SENTINEL }; modify_arm_cp_regs(v8_idregs, v8_user_idregs); #endif @@ -7985,7 +7927,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL2_RW, .resetvalue =3D vmpidr_def, .fieldoffset =3D offsetof(CPUARMState, cp15.vmpidr_el2) }, - REGINFO_SENTINEL }; define_arm_cp_regs(cpu, vpidr_regs); define_arm_cp_regs(cpu, el2_cp_reginfo); @@ -8024,7 +7965,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, .type =3D ARM_CP_NO_RAW, .writefn =3D arm_cp_write_ignore, .readfn =3D mpidr_read= }, - REGINFO_SENTINEL }; define_arm_cp_regs(cpu, vpidr_regs); define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); @@ -8047,7 +7987,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .raw_writefn =3D raw_write, .writefn =3D sctlr_write, .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr_el[3]), .resetvalue =3D cpu->reset_sctlr }, - REGINFO_SENTINEL }; =20 define_arm_cp_regs(cpu, el3_regs); @@ -8182,7 +8121,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "DUMMY", .cp =3D 15, .crn =3D 0, .crm =3D 7, .opc1 =3D 0, .opc2 =3D C= P_ANY, .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0= }, - REGINFO_SENTINEL }; ARMCPRegInfo id_v8_midr_cp_reginfo[] =3D { { .name =3D "MIDR_EL1", .state =3D ARM_CP_STATE_BOTH, @@ -8202,7 +8140,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .accessfn =3D access_aa64_tid1, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->revidr }, - REGINFO_SENTINEL }; ARMCPRegInfo id_cp_reginfo[] =3D { /* These are common to v8 and pre-v8 */ @@ -8220,7 +8157,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .accessfn =3D access_aa32_tid1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; /* TLBTR is specific to VMSA */ ARMCPRegInfo id_tlbtr_reginfo =3D { @@ -8247,25 +8183,23 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "MIDR_EL1", .exported_bits =3D 0x00000000ffffffff }, { .name =3D "REVIDR_EL1" }, - REGUSERINFO_SENTINEL }; modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_regin= fo); #endif if (arm_feature(env, ARM_FEATURE_OMAPCP) || arm_feature(env, ARM_FEATURE_STRONGARM)) { - ARMCPRegInfo *r; + size_t i; /* Register the blanket "writes ignored" value first to cover = the * whole space. Then update the specific ID registers to allow= write * access, so that they ignore writes rather than causing them= to * UNDEF. */ define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); - for (r =3D id_pre_v8_midr_cp_reginfo; - r->type !=3D ARM_CP_SENTINEL; r++) { - r->access =3D PL1_RW; + for (i =3D 0; i < ARRAY_SIZE(id_pre_v8_midr_cp_reginfo); ++i) { + id_pre_v8_midr_cp_reginfo[i].access =3D PL1_RW; } - for (r =3D id_cp_reginfo; r->type !=3D ARM_CP_SENTINEL; r++) { - r->access =3D PL1_RW; + for (i =3D 0; i < ARRAY_SIZE(id_cp_reginfo); ++i) { + id_cp_reginfo[i].access =3D PL1_RW; } id_mpuir_reginfo.access =3D PL1_RW; id_tlbtr_reginfo.access =3D PL1_RW; @@ -8288,13 +8222,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "MPIDR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D = 5, .access =3D PL1_R, .readfn =3D mpidr_read, .type =3D ARM_CP_= NO_RAW }, - REGINFO_SENTINEL }; #ifdef CONFIG_USER_ONLY ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] =3D { { .name =3D "MPIDR_EL1", .fixed_bits =3D 0x0000000080000000 }, - REGUSERINFO_SENTINEL }; modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo); #endif @@ -8315,7 +8247,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 0, .opc2 =3D = 1, .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; define_arm_cp_regs(cpu, auxcr_reginfo); if (cpu_isar_feature(aa32_ac2, cpu)) { @@ -8350,7 +8281,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .type =3D ARM_CP_CONST, .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 3, .opc2= =3D 0, .access =3D PL1_R, .resetvalue =3D cpu->reset_cbar }, - REGINFO_SENTINEL }; /* We don't implement a r/w 64 bit CBAR currently */ assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); @@ -8380,7 +8310,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.vbar_s), offsetof(CPUARMState, cp15.vbar_ns) }, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; define_arm_cp_regs(cpu, vbar_cp_reginfo); } @@ -8834,8 +8763,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, r->writefn); } } - /* Bad type field probably means missing sentinel at end of reg list */ - assert(cptype_valid(r->type)); + for (crm =3D crmmin; crm <=3D crmmax; crm++) { for (opc1 =3D opc1min; opc1 <=3D opc1max; opc1++) { for (opc2 =3D opc2min; opc2 <=3D opc2max; opc2++) { @@ -8881,13 +8809,13 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, } } =20 -void define_arm_cp_regs_with_opaque(ARMCPU *cpu, - const ARMCPRegInfo *regs, void *opaque) +/* Define a whole list of registers */ +void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *r= egs, + void *opaque, size_t len) { - /* Define a whole list of registers */ - const ARMCPRegInfo *r; - for (r =3D regs; r->type !=3D ARM_CP_SENTINEL; r++) { - define_one_arm_cp_reg_with_opaque(cpu, r, opaque); + size_t i; + for (i =3D 0; i < len; ++i) { + define_one_arm_cp_reg_with_opaque(cpu, regs + i, opaque); } } =20 @@ -8899,17 +8827,20 @@ void define_arm_cp_regs_with_opaque(ARMCPU *cpu, * user-space cannot alter any values and dynamic values pertaining to * execution state are hidden from user space view anyway. */ -void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *m= ods) +void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len, + const ARMCPRegUserSpaceInfo *mods, + size_t mods_len) { - const ARMCPRegUserSpaceInfo *m; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YXryGBC0mqaWtLXkO2uZG/YEkw1cD0lQU+28RrwCGRA=; b=TweJb6J6wLAoDBG5UGnAOmIKBdjETERRYBwSOQ/kwAwgA5S4bsW792/otcOkCTN7Dv +1KCKqFc5PwrNcWjGvdqlotlZqQreufp6RLV36OWTRhA0F/Cl3Oe/qzuIwfbyVUB0PAq uCxUOna2NzRGMl8mKvApGw/ylIZ8KmG4cUtbaCXt33Qc2pMB/F6mqEQcV/byNVJ+vzcH gQkH/ILdNHebvoOzTIHn0W5vTg/wFU8JnsduZCaf2aR4K/MX2q4+EQ7s8Bl2we4CLTXn cPbBspqyeIUgyyekaotD0grQOHDmSlgBCxOiz0dVlnRcAx3yzP1ypl3LFJLyOIxe24qz X6rQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YXryGBC0mqaWtLXkO2uZG/YEkw1cD0lQU+28RrwCGRA=; b=P8CW9v/Tu90v9JM+wskOqzJN2Mn/CVa+GZtUj1Q4LhnWZmv29TYZLYezR85PlfpNki K0Xcw0VhDUyMTmbDc+fsIN8ja0juwvKMwoXWSsikBBb6m63iadXHgkxvqmLof2IZdlLR GLPZmv6qFiyvn5jqOM3NCVRM8BmRDQRaLTf1k2ZrCiTxjHEgO+yRUY6ToyD8N8denN6+ sScbIAPTLnS5EoRuWzHM6H7ukngzQQWGZtZWey1rqjVSOWS+dToy8NRzVHXt3MPUKFjj GL10yEJ/qOvymyw90zVrwu8GK/9B7ODRDNtGnbE5cnfSRDxw06ld3v4yctuZa0lRmn9r wffQ== X-Gm-Message-State: AOAM531Yi+9ZipYrlALwEdf016t6rPBV0ZwDU0aCW8N5QvCFZDhmq05y XQxlwAmw4fd430J1O95WIDNUOouVVE06aA== X-Google-Smtp-Source: ABdhPJz1EMIP+8BTk8wa3PlNLjV2Pq+yuizfYtvjz+aTqCMrQV6fRNM9yuTwaDdERxrsgCsOkbNybQ== X-Received: by 2002:a17:902:c412:b0:158:72da:6fdd with SMTP id k18-20020a170902c41200b0015872da6fddmr7673772plk.165.1650217493597; Sun, 17 Apr 2022 10:44:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 27/60] target/arm: Make some more cpreg data static const Date: Sun, 17 Apr 2022 10:43:53 -0700 Message-Id: <20220417174426.711829-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650219045168100001 Content-Type: text/plain; charset="utf-8" These particular data structures are not modified at runtime. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell --- target/arm/helper.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index d6c34c7826..94b41c7e88 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7861,7 +7861,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .resetvalue =3D cpu->pmceid1 }, }; #ifdef CONFIG_USER_ONLY - ARMCPRegUserSpaceInfo v8_user_idregs[] =3D { + static const ARMCPRegUserSpaceInfo v8_user_idregs[] =3D { { .name =3D "ID_AA64PFR0_EL1", .exported_bits =3D 0x000f000f00ff0000, .fixed_bits =3D 0x0000000000000011 }, @@ -8001,7 +8001,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) */ if (arm_feature(env, ARM_FEATURE_EL3)) { if (arm_feature(env, ARM_FEATURE_AARCH64)) { - ARMCPRegInfo nsacr =3D { + static const ARMCPRegInfo nsacr =3D { .name =3D "NSACR", .type =3D ARM_CP_CONST, .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D= 2, .access =3D PL1_RW, .accessfn =3D nsacr_access, @@ -8009,7 +8009,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) }; define_one_arm_cp_reg(cpu, &nsacr); } else { - ARMCPRegInfo nsacr =3D { + static const ARMCPRegInfo nsacr =3D { .name =3D "NSACR", .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D= 2, .access =3D PL3_RW | PL1_R, @@ -8020,7 +8020,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) } } else { if (arm_feature(env, ARM_FEATURE_V8)) { - ARMCPRegInfo nsacr =3D { + static const ARMCPRegInfo nsacr =3D { .name =3D "NSACR", .type =3D ARM_CP_CONST, .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D= 2, .access =3D PL1_R, @@ -8173,13 +8173,13 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->pmsav7_dregion << 8 }; - ARMCPRegInfo crn0_wi_reginfo =3D { + static const ARMCPRegInfo crn0_wi_reginfo =3D { .name =3D "CRN0_WI", .cp =3D 15, .crn =3D 0, .crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_W, .type =3D ARM_CP_NOP | ARM_CP_OVERRIDE }; #ifdef CONFIG_USER_ONLY - ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] =3D { + static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = =3D { { .name =3D "MIDR_EL1", .exported_bits =3D 0x00000000ffffffff }, { .name =3D "REVIDR_EL1" }, @@ -8224,7 +8224,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .readfn =3D mpidr_read, .type =3D ARM_CP_= NO_RAW }, }; #ifdef CONFIG_USER_ONLY - ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] =3D { + static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] =3D { { .name =3D "MPIDR_EL1", .fixed_bits =3D 0x0000000080000000 }, }; @@ -8303,7 +8303,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) } =20 if (arm_feature(env, ARM_FEATURE_VBAR)) { - ARMCPRegInfo vbar_cp_reginfo[] =3D { + static const ARMCPRegInfo vbar_cp_reginfo[] =3D { { .name =3D "VBAR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 12, .crm =3D 0, .opc1 =3D 0, .opc2 =3D= 0, .access =3D PL1_RW, .writefn =3D vbar_write, --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650218557; cv=none; d=zohomail.com; s=zohoarc; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CZCDzfeb570yxQzv9X4suIogFVnxMMmltWWaLeklfQM=; b=VruFN/U1NQfnq457nOEpP+acnNZSJwhJjXQH1yiZe8pGXG/sPD7F/GeEz4QjGb9/Gw zxf/LnzFpFw9Y+CWrSXk5CUtEWRx6+HU8V37RQsrUv7S+iK2EFyLk2FEzy8IiYPuttDd 3tM0IYdDxzzG1u/ju+SsF436LLNcjq2HFrzj8+aJ6lWbZsKRgJCmv64MjUotqPQ0Wuik hObf+NiF5yReCV3lw7n0/ytMtuOkS+G+QhCM+ipqpMvx1HWEwUDTB4VJb9w8Ylj8zxWT sSxfTPVKioCYb6x5zrSdnvcQ/QMqoQDbb0HkReDrlV9/I7jfooTdXvzmircctKBLCK1r kgCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CZCDzfeb570yxQzv9X4suIogFVnxMMmltWWaLeklfQM=; b=b2szmSn1dLV7c/u1uUWMYUb9tEKp/wvmrB5yDjuibVP+T0GQyZ52WMvrBYIZ5RwwF2 cXKNCs8k552fIX+3j8WdVuT/A+nWdU5zNwSyvqMshtPv+7KdA+gKAj5YzJfHtSjMa7hd WL0YVd49sVNlw7Zf/o0Z+zicorUsuMSDc/5gU72Q4GafJb9c+rW3cVjb8eI5TmFpP1WM s5zaPHS3uB78FfTFOvnpYOvOuMGzFRO5MbEvpGBJ2bfq5RkCQVNLQYn/1sb7a5+iQaeU QMdId/cYEdoirig2UdZbhXoM6r7LHkBt5ciwxYk9RRJdrvrowPM2N18O/xJywtRxCg8T WS2Q== X-Gm-Message-State: AOAM530ua07MFWkokocOBelLEpkOMPBUNqwH7L/Oxos/k8BDGKbpaKeb UyiSqE2Ifqb4OHrkk8qwQ1Q6qFR/0SUWzw== X-Google-Smtp-Source: ABdhPJxonUU6Yy9RDBLwuZt98Aq0hukwYuyBPOZ5PUAOxkV2UA+NP3X5RJq32knU9k8BHI8GwWLdiw== X-Received: by 2002:a17:902:9308:b0:158:da34:ab55 with SMTP id bc8-20020a170902930800b00158da34ab55mr7767123plb.84.1650217494365; Sun, 17 Apr 2022 10:44:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 28/60] target/arm: Reorg ARMCPRegInfo type field bits Date: Sun, 17 Apr 2022 10:43:54 -0700 Message-Id: <20220417174426.711829-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650218559173100001 Content-Type: text/plain; charset="utf-8" Instead of defining ARM_CP_FLAG_MASK to remove flags, define ARM_CP_SPECIAL_MASK to isolate special cases. Sort the specials to the low bits. Use an enum. Make ARM_CP_CONST a special case, and ARM_CP_NOP an alias. Split the large comment block so as to document each value separately. Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 134 +++++++++++++++++++++++-------------- target/arm/cpu.c | 4 +- target/arm/helper.c | 4 +- target/arm/translate-a64.c | 21 +++--- target/arm/translate.c | 27 ++++---- 5 files changed, 111 insertions(+), 79 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index bd321d6d23..031e4b7ec8 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -22,57 +22,89 @@ #define TARGET_ARM_CPREGS_H 1 =20 /* - * ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a - * special-behaviour cp reg and bits [11..8] indicate what behaviour - * it has. Otherwise it is a simple cp reg, where CONST indicates that - * TCG can assume the value to be constant (ie load at translate time) - * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END - * indicates that the TB should not be ended after a write to this register - * (the default is that the TB ends after cp writes). OVERRIDE permits - * a register definition to override a previous definition for the - * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the - * old must have the OVERRIDE bit set. - * ALIAS indicates that this register is an alias view of some underlying - * state which is also visible via another register, and that the other - * register is handling migration and reset; registers marked ALIAS will n= ot be - * migrated but may have their state set by syncing of register state from= KVM. - * NO_RAW indicates that this register has no underlying state and does not - * support raw access for state saving/loading; it will not be used for ei= ther - * migration or KVM state synchronization. (Typically this is for "registe= rs" - * which are actually used as instructions for cache maintenance and so on= .) - * IO indicates that this register does I/O and therefore its accesses - * need to be marked with gen_io_start() and also end the TB. In particula= r, - * registers which implement clocks or timers require this. - * RAISES_EXC is for when the read or write hook might raise an exception; - * the generated code will synchronize the CPU state before calling the ho= ok - * so that it is safe for the hook to call raise_exception(). - * NEWEL is for writes to registers that might change the exception - * level - typically on older ARM chips. For those cases we need to - * re-read the new el when recomputing the translation flags. + * ARMCPRegInfo type field bits: */ -#define ARM_CP_SPECIAL 0x0001 -#define ARM_CP_CONST 0x0002 -#define ARM_CP_64BIT 0x0004 -#define ARM_CP_SUPPRESS_TB_END 0x0008 -#define ARM_CP_OVERRIDE 0x0010 -#define ARM_CP_ALIAS 0x0020 -#define ARM_CP_IO 0x0040 -#define ARM_CP_NO_RAW 0x0080 -#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) -#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) -#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) -#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) -#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) -#define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600) -#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700) -#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA -#define ARM_CP_FPU 0x1000 -#define ARM_CP_SVE 0x2000 -#define ARM_CP_NO_GDB 0x4000 -#define ARM_CP_RAISES_EXC 0x8000 -#define ARM_CP_NEWEL 0x10000 -/* Mask of only the flag bits in a type field */ -#define ARM_CP_FLAG_MASK 0x1f0ff +enum { + /* + * Register must be handled specially during translation. + * The method is one of the values below: + */ + ARM_CP_SPECIAL_MASK =3D 0x000f, + /* + * Special: sysreg with constant value, writes ignored. + * The nop alias is slightly clearer for describing write-only sysregs. + */ + ARM_CP_CONST =3D 0x0001, + ARM_CP_NOP =3D ARM_CP_CONST, + /* Special: sysreg is WFI, for v5 and v6. */ + ARM_CP_WFI =3D 0x0002, + /* Special: sysreg is NZCV. */ + ARM_CP_NZCV =3D 0x0003, + /* Special: sysreg is CURRENTEL. */ + ARM_CP_CURRENTEL =3D 0x0004, + /* Special: sysreg is DC ZVA or similar. */ + ARM_CP_DC_ZVA =3D 0x0005, + ARM_CP_DC_GVA =3D 0x0006, + ARM_CP_DC_GZVA =3D 0x0007, + + /* Flag: For ARM_CP_STATE_AA32, sysreg is 64-bit. */ + ARM_CP_64BIT =3D 1 << 4, + /* + * Flag: TB should not be ended after a write to this register + * (the default is that the TB ends after cp writes). + */ + ARM_CP_SUPPRESS_TB_END =3D 1 << 5, + /* + * Flag: Permit a register definition to override a previous definition + * for the same (cp, is64, crn, crm, opc1, opc2) tuple: either the new + * or the old must have the ARM_CP_OVERRIDE bit set. + */ + ARM_CP_OVERRIDE =3D 1 << 6, + /* + * Flag: Register is an alias view of some underlying state which is a= lso + * visible via another register, and that the other register is handli= ng + * migration and reset; registers marked ARM_CP_ALIAS will not be migr= ated + * but may have their state set by syncing of register state from KVM. + */ + ARM_CP_ALIAS =3D 1 << 7, + /* + * Flag: Register does I/O and therefore its accesses need to be marked + * with gen_io_start() and also end the TB. In particular, registers w= hich + * implement clocks or timers require this. + */ + ARM_CP_IO =3D 1 << 8, + /* + * Flag: Register has no underlying state and does not support raw acc= ess + * for state saving/loading; it will not be used for either migration = or + * KVM state synchronization. Typically this is for "registers" which = are + * actually used as instructions for cache maintenance and so on. + */ + ARM_CP_NO_RAW =3D 1 << 9, + /* + * Flag: The read or write hook might raise an exception; the generated + * code will synchronize the CPU state before calling the hook so that= it + * is safe for the hook to call raise_exception(). + */ + ARM_CP_RAISES_EXC =3D 1 << 10, + /* + * Flag: Writes to the sysreg might change the exception level - typic= ally + * on older ARM chips. For those cases we need to re-read the new el w= hen + * recomputing the translation flags. + */ + ARM_CP_NEWEL =3D 1 << 11, + /* + * Flag: Access check for this sysreg is identical to accessing FPU st= ate + * from an instruction: use translation fp_access_check(). + */ + ARM_CP_FPU =3D 1 << 12, + /* + * Flag: Access check for this sysreg is identical to accessing SVE st= ate + * from an instruction: use translation sve_access_check(). + */ + ARM_CP_SVE =3D 1 << 13, + /* Flag: Do not expose in gdb sysreg xml. */ + ARM_CP_NO_GDB =3D 1 << 14, +}; =20 /* * Valid values for ARMCPRegInfo state field, indicating which of @@ -249,7 +281,7 @@ struct ARMCPRegInfo { /* * Offset of the field in CPUARMState for this register. * This is not needed if either: - * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs + * 1. type has ARM_CP_SPECIAL_MASK non-zero * 2. both readfn and writefn are specified */ ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 066fe6250a..92fc75b2bf 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -117,7 +117,7 @@ static void cp_reg_reset(gpointer key, gpointer value, = gpointer opaque) ARMCPRegInfo *ri =3D value; ARMCPU *cpu =3D opaque; =20 - if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { + if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { return; } =20 @@ -153,7 +153,7 @@ static void cp_reg_check_reset(gpointer key, gpointer v= alue, gpointer opaque) ARMCPU *cpu =3D opaque; uint64_t oldvalue, newvalue; =20 - if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { + if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { return; } =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 94b41c7e88..1bbaf0a3af 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8601,7 +8601,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, * multiple times. Special registers (ie NOP/WFI) are * never migratable and not even raw-accessible. */ - if ((r->type & ARM_CP_SPECIAL)) { + if (r->type & ARM_CP_SPECIAL_MASK) { r2->type |=3D ARM_CP_NO_RAW; } if (((r->crm =3D=3D CP_ANY) && crm !=3D 0) || @@ -8751,7 +8751,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, /* Check that the register definition has enough info to handle * reads and writes if they are permitted. */ - if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) { + if (!(r->type & (ARM_CP_SPECIAL_MASK | ARM_CP_CONST))) { if (r->access & PL3_R) { assert((r->fieldoffset || (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 92b91f0307..98dbc8203f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1833,8 +1833,14 @@ static void handle_sys(DisasContext *s, uint32_t ins= n, bool isread, } =20 /* Handle special cases first */ - switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) { - case ARM_CP_NOP: + switch (ri->type & ARM_CP_SPECIAL_MASK) { + case 0: + break; + case ARM_CP_CONST: + if (isread) { + tcg_rt =3D cpu_reg(s, rt); + tcg_gen_movi_i64(tcg_rt, ri->resetvalue); + } return; case ARM_CP_NZCV: tcg_rt =3D cpu_reg(s, rt); @@ -1908,7 +1914,7 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, } return; default: - break; + g_assert_not_reached(); } if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) { return; @@ -1923,18 +1929,13 @@ static void handle_sys(DisasContext *s, uint32_t in= sn, bool isread, tcg_rt =3D cpu_reg(s, rt); =20 if (isread) { - if (ri->type & ARM_CP_CONST) { - tcg_gen_movi_i64(tcg_rt, ri->resetvalue); - } else if (ri->readfn) { + if (ri->readfn) { gen_helper_get_cp_reg64(tcg_rt, cpu_env, tcg_constant_ptr(ri)); } else { tcg_gen_ld_i64(tcg_rt, cpu_env, ri->fieldoffset); } } else { - if (ri->type & ARM_CP_CONST) { - /* If not forbidden by access permissions, treat as WI */ - return; - } else if (ri->writefn) { + if (ri->writefn) { gen_helper_set_cp_reg64(cpu_env, tcg_constant_ptr(ri), tcg_rt); } else { tcg_gen_st_i64(tcg_rt, cpu_env, ri->fieldoffset); diff --git a/target/arm/translate.c b/target/arm/translate.c index 1fe48e4e1c..9370b44707 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4744,8 +4744,16 @@ static void do_coproc_insn(DisasContext *s, int cpnu= m, int is64, } =20 /* Handle special cases first */ - switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) { - case ARM_CP_NOP: + switch (ri->type & ARM_CP_SPECIAL_MASK) { + case 0: + break; + case ARM_CP_CONST: + if (isread) { + store_reg(s, rt, tcg_constant_i32(ri->resetvalue)); + if (is64) { + store_reg(s, rt2, tcg_constant_i32(ri->resetvalue >> 3= 2)); + } + } return; case ARM_CP_WFI: if (isread) { @@ -4756,7 +4764,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, s->base.is_jmp =3D DISAS_WFI; return; default: - break; + g_assert_not_reached(); } =20 if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_= IO)) { @@ -4768,9 +4776,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, if (is64) { TCGv_i64 tmp64; TCGv_i32 tmp; - if (ri->type & ARM_CP_CONST) { - tmp64 =3D tcg_constant_i64(ri->resetvalue); - } else if (ri->readfn) { + if (ri->readfn) { tmp64 =3D tcg_temp_new_i64(); gen_helper_get_cp_reg64(tmp64, cpu_env, tcg_constant_ptr(ri)); @@ -4787,9 +4793,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, store_reg(s, rt2, tmp); } else { TCGv_i32 tmp; - if (ri->type & ARM_CP_CONST) { - tmp =3D tcg_constant_i32(ri->resetvalue); - } else if (ri->readfn) { + if (ri->readfn) { tmp =3D tcg_temp_new_i32(); gen_helper_get_cp_reg(tmp, cpu_env, tcg_constant_ptr(r= i)); } else { @@ -4807,11 +4811,6 @@ static void do_coproc_insn(DisasContext *s, int cpnu= m, int is64, } } else { /* Write */ - if (ri->type & ARM_CP_CONST) { - /* If not forbidden by access permissions, treat as WI */ - return; - } - if (is64) { TCGv_i32 tmplo, tmphi; TCGv_i64 tmp64 =3D tcg_temp_new_i64(); --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cNQuYWlWJo1H5z1dgSCS+oQAsg1LmaUsgazYdgc9pgo=; b=ym3Y2Isq+BXoC2A9zRIR6pePFMeZnt2Y7+I1qAuS3ZvonwR7P9BlWi84Y5W2XNzSpR LpvPOjMiAahrDGD1fqOOMl/a0P/pEgv1/g7sB2O2Q+U0AVgmbBRTEROPJ4SLStTw0UiR UDJcMIArWg4UjD8Gagg+1rzUto7+LWZdpURYxmesbMtCS+Uqq1khyUtNF5DvzVSO5Cmp gwsAB+P/+cVQPaPQnxN+xFLLCyrwklEkyu0QAeqm4RMmteRe/yJbORbp6vEAKvCo0J8n SqvVl4NmghpXqHWuZsjCeawVvU33rPsB+ufwwGhnNWmDuGsvhik4DXyZ6MdRMJ0dkKjb Wg7g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cNQuYWlWJo1H5z1dgSCS+oQAsg1LmaUsgazYdgc9pgo=; b=fUb6QVc8/0okXtPpI2feN7dTrftreMidqcGK3QZu0EWNS4OUnJ44hJAYcmLCsj+N2O bCusd9EHtLjhV99b3ZSxxjyz5LuppKFonIcT4Ok66M5FZtK4QEdMcgRwQZETwOov/Hqa R18k9i94/07AplrFkyIAnJa0dqnlWC1+WMBCG56p9KPM2dKdI6bynqUNnSEprdzgpAna 4O75mrEhgbRqBVPsXoDeB7IU0/2LNQy1jaTELhRwJcC8rGed6dRVrk/5CgCuLWFd/1NG yYRjA08nj6x/dj2UIN6grSxt9vIn6nf6Oe4KHKqlepYEsoXSIvxpo0ZgxR5xDGitQS5Y C1kQ== X-Gm-Message-State: AOAM532ThEyv3CJ4jjqczoWksX+/wyefRVtU+/38oVOGW65Mm/QPFWUp K0X9YDgQUpcDS4b3iJWM4HSJPn/KIrRdqw== X-Google-Smtp-Source: ABdhPJzwn59B6UjD+PKR0F9QtQ8noDL9+7s/Kg4HbwFSN8E5LEUGWKPsdQYUyzjFeY+Ae3a1nWIzcw== X-Received: by 2002:a63:cf0c:0:b0:380:fb66:fa2a with SMTP id j12-20020a63cf0c000000b00380fb66fa2amr7099075pgg.273.1650217495172; Sun, 17 Apr 2022 10:44:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 29/60] target/arm: Change cpreg access permissions to enum Date: Sun, 17 Apr 2022 10:43:55 -0700 Message-Id: <20220417174426.711829-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650220162033100001 Content-Type: text/plain; charset="utf-8" Create a typedef as well, and use it in ARMCPRegInfo. This won't be perfect for debugging, but it'll nicely display the most common cases. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpregs.h | 44 +++++++++++++++++++++++--------------------- target/arm/helper.c | 5 ++--- 2 files changed, 25 insertions(+), 24 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 031e4b7ec8..2c991ab5df 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -156,31 +156,33 @@ enum { * described with these bits, then use a laxer set of restrictions, and * do the more restrictive/complex check inside a helper function. */ -#define PL3_R 0x80 -#define PL3_W 0x40 -#define PL2_R (0x20 | PL3_R) -#define PL2_W (0x10 | PL3_W) -#define PL1_R (0x08 | PL2_R) -#define PL1_W (0x04 | PL2_W) -#define PL0_R (0x02 | PL1_R) -#define PL0_W (0x01 | PL1_W) +typedef enum { + PL3_R =3D 0x80, + PL3_W =3D 0x40, + PL2_R =3D 0x20 | PL3_R, + PL2_W =3D 0x10 | PL3_W, + PL1_R =3D 0x08 | PL2_R, + PL1_W =3D 0x04 | PL2_W, + PL0_R =3D 0x02 | PL1_R, + PL0_W =3D 0x01 | PL1_W, =20 -/* - * For user-mode some registers are accessible to EL0 via a kernel - * trap-and-emulate ABI. In this case we define the read permissions - * as actually being PL0_R. However some bits of any given register - * may still be masked. - */ + /* + * For user-mode some registers are accessible to EL0 via a kernel + * trap-and-emulate ABI. In this case we define the read permissions + * as actually being PL0_R. However some bits of any given register + * may still be masked. + */ #ifdef CONFIG_USER_ONLY -#define PL0U_R PL0_R + PL0U_R =3D PL0_R, #else -#define PL0U_R PL1_R + PL0U_R =3D PL1_R, #endif =20 -#define PL3_RW (PL3_R | PL3_W) -#define PL2_RW (PL2_R | PL2_W) -#define PL1_RW (PL1_R | PL1_W) -#define PL0_RW (PL0_R | PL0_W) + PL3_RW =3D PL3_R | PL3_W, + PL2_RW =3D PL2_R | PL2_W, + PL1_RW =3D PL1_R | PL1_W, + PL0_RW =3D PL0_R | PL0_W, +} CPAccessRights; =20 typedef enum CPAccessResult { /* Access is permitted */ @@ -264,7 +266,7 @@ struct ARMCPRegInfo { /* Register type: ARM_CP_* bits/values */ int type; /* Access rights: PL*_[RW] */ - int access; + CPAccessRights access; /* Security state: ARM_CP_SECSTATE_* bits/values */ int secure; /* diff --git a/target/arm/helper.c b/target/arm/helper.c index 1bbaf0a3af..33ba77890b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8712,7 +8712,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, * to encompass the generic architectural permission check. */ if (r->state !=3D ARM_CP_STATE_AA32) { - int mask =3D 0; + CPAccessRights mask; switch (r->opc1) { case 0: /* min_EL EL1, but some accessible to EL0 via kernel ABI */ @@ -8741,8 +8741,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, break; default: /* broken reginfo with out-of-range opc1 */ - assert(false); - break; + g_assert_not_reached(); } /* assert our permissions are not too lax (stricter is fine) */ assert((r->access & ~mask) =3D=3D 0); --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650219305; cv=none; d=zohomail.com; s=zohoarc; b=Hh0J+l1f7JMezK0UesxkNywG0LHBwD2TUyTUt84za7/8n/7FW3FyD3A3pT00BU2i2Fgtjv9YD/BsN0LKe0E0cmlNpFyjLobP9QIyrTrBMSmVJ309a1Xxhw/u7A5brKGxhnNNADNCe35Nme3bdZGMCsXm4um+6XNuvrcRpcxOjwA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650219305; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=25C7iOsGqfSeEIqOCeDhxny3HAl1dQf5ZHtQgWZYi98=; b=lOgLR19W1R7Lag2QW9X7RYsF8EA1qFzd851gAiAmB9+Jbc0XYBHT4C/1N6ALo4OUwkRJslyJV5knQibS7nv7vtG+kPzJ+9t0lwB+Ut5giJ09hKncFYphXWbdsz1k1wHA53uqRman4n9zokLhglI7f0ERzvfpkypXhLOIKy1T6Ts= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650219305414619.5076316913602; Sun, 17 Apr 2022 11:15:05 -0700 (PDT) Received: from localhost ([::1]:46700 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9QO-0001oo-80 for importer@patchew.org; Sun, 17 Apr 2022 14:15:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48612) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng8xI-0001EM-Ko for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:45:00 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:39817) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng8xF-0003OQ-54 for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:45:00 -0400 Received: by mail-pj1-x1029.google.com with SMTP id mp16-20020a17090b191000b001cb5efbcab6so15506215pjb.4 for ; Sun, 17 Apr 2022 10:44:56 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=25C7iOsGqfSeEIqOCeDhxny3HAl1dQf5ZHtQgWZYi98=; b=PNrKfzbz8AE8ekSFNMGR/HM/6UM1sgoNIs/tQLjBoA+Ic/j46APdoa0qZ++o2E65Qq +gXHNqcdf1brdqNSPqBngM25HU3XkBlK4zyjBkNmnrJX/H3/jo2DneEqQqa7QkMQET5D s2WA9jFW4KzJxlUFQJp3G/Y133ISZfHtjzVxmJPNsv+tM0QhrB2PQQDXHaC0fDS66ETA xhsXwndF/NzIqB52UdIhwstF9V8K95an/lMCYRnuErODWtz8fyfwZHjPMhUxNqOEwB9r BQwoLq1JGnGrmoZ86GgWKQ0b3v2ORB0j+u3rg81DehCnbhsO7US5WWNZtMOu5Pl5i8pJ 68Rg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=25C7iOsGqfSeEIqOCeDhxny3HAl1dQf5ZHtQgWZYi98=; b=KytMhme5xEeE9nhVpBITwmRMW1+QGQWLEDrfdKh0LHG4IkjfZ5nUVVHzO4/tcxpGRp h+eeksx9N/uMhIC9nO3NH0GkEJMpu7ZMPUVQWQq1bqlmyqp2Ya9uM6JPwLYXNqFo80ii qjOtEdTeL095SZol1DbcnOxnGIrHS3PWqVPd+AOBZwJ2hw0f9w5LSRQljKiQ5D/Uu0qk 6I91pFiuRITmI1yGvlw0r0L6JxeCx+NWoDq8K93WktF2rqw9k5oPn545SV6t1XBXsuY3 6qCaVL7d+Av1x2Dc7kFeyEvCe0PGfLDrAz0ZgCxNVMJcKjmPISJA5aucDvgZUwxIgPNR tdkw== X-Gm-Message-State: AOAM532Z82KPFopu01xWdNXcA3m9O3Q+wymy7S9cnP99OE3oZv7XwnwF 8gaRB46oCNSZolMibkLJNPf7rhdD+98jTQ== X-Google-Smtp-Source: ABdhPJzjQN290ryDfjXA2XISuFnHbWhzFgJl6UxRkf/tLWGUkp4LBXY/LXRZXTuIUEvkFkYedUIbUg== X-Received: by 2002:a17:902:6bc9:b0:158:a0d3:d080 with SMTP id m9-20020a1709026bc900b00158a0d3d080mr7753890plt.24.1650217495858; Sun, 17 Apr 2022 10:44:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 30/60] target/arm: Name CPState type Date: Sun, 17 Apr 2022 10:43:56 -0700 Message-Id: <20220417174426.711829-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650219306094100003 Content-Type: text/plain; charset="utf-8" Give this enum a name and use in ARMCPRegInfo, add_cpreg_to_hashtable and define_one_arm_cp_reg_with_opaque. Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell --- target/arm/cpregs.h | 6 +++--- target/arm/helper.c | 6 ++++-- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 2c991ab5df..fe338730ab 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -116,11 +116,11 @@ enum { * Note that we rely on the values of these enums as we iterate through * the various states in some places. */ -enum { +typedef enum { ARM_CP_STATE_AA32 =3D 0, ARM_CP_STATE_AA64 =3D 1, ARM_CP_STATE_BOTH =3D 2, -}; +} CPState; =20 /* * ARM CP register secure state flags. These flags identify security state @@ -262,7 +262,7 @@ struct ARMCPRegInfo { uint8_t opc1; uint8_t opc2; /* Execution state in which this register is visible: ARM_CP_STATE_* */ - int state; + CPState state; /* Register type: ARM_CP_* bits/values */ int type; /* Access rights: PL*_[RW] */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 33ba77890b..8b89039667 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8503,7 +8503,7 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Erro= r **errp) } =20 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, - void *opaque, int state, int secstate, + void *opaque, CPState state, int secsta= te, int crm, int opc1, int opc2, const char *name) { @@ -8663,13 +8663,15 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of * the register, if any. */ - int crm, opc1, opc2, state; + int crm, opc1, opc2; int crmmin =3D (r->crm =3D=3D CP_ANY) ? 0 : r->crm; int crmmax =3D (r->crm =3D=3D CP_ANY) ? 15 : r->crm; int opc1min =3D (r->opc1 =3D=3D CP_ANY) ? 0 : r->opc1; int opc1max =3D (r->opc1 =3D=3D CP_ANY) ? 7 : r->opc1; int opc2min =3D (r->opc2 =3D=3D CP_ANY) ? 0 : r->opc2; int opc2max =3D (r->opc2 =3D=3D CP_ANY) ? 7 : r->opc2; + CPState state; + /* 64 bit registers have only CRm and Opc1 fields */ assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); /* op0 only exists in the AArch64 encodings */ --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650219642; cv=none; d=zohomail.com; s=zohoarc; b=UAjVbMrwRQN+Ds++8yjmIZ7rcxfCzxiGl0Bc6YPP54R1nVFDcxSf3blI1WS4TavPEKTk3MeMCcX8KdRPHMg8BDffB9EOVrJvgPcg1AsxszEGSGbOB4caI73i33QPLiMUpVaIm8cDLPN2BuDJu68KmBpTiWXFnGv4Re/szthZioA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650219642; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BnQW0DvgaZN0T2yAGdSifoOIby01eTPtmMKzkfkFCKA=; b=bXn4Eb/xkepq4WpVOyfNWlOdT5mvHkicqrYMpcL7894NCL6EYZmgEINMCzoIcTY7DPURP4nMnVSDtcb42Yoq8drXuNcO3tQWOhFtX7tRbDdF3dyd3/yCsp93E60Zf0BFe+kmIZUM2OnU7UnUKL6Ho5EQa46Q8rjAzZMnXQoxJW0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650219642314565.0980880230604; Sun, 17 Apr 2022 11:20:42 -0700 (PDT) Received: from localhost ([::1]:55534 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9Vo-0007mn-O7 for importer@patchew.org; Sun, 17 Apr 2022 14:20:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48684) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng8xK-0001K2-4A for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:45:02 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]:37670) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng8xF-0003Os-Tx for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:45:01 -0400 Received: by mail-pg1-x534.google.com with SMTP id t184so1964669pgd.4 for ; Sun, 17 Apr 2022 10:44:57 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BnQW0DvgaZN0T2yAGdSifoOIby01eTPtmMKzkfkFCKA=; b=hcuQu8voPCRuXAiORVOPesCbSkdH/eGScTBpwFhlgYfLw1Lshzg9bCPpCOTA61qUHX 7cVDId3AoNvzBn8j6vhwREthUp1eLRzyCzlMPSjYcGrEj9pcGdMnH4PUYy1UbfCf1BQD MfVImbJXqfJJ00RYdAHblQ6MYqFkrdeXxaP/DAG56tvS9M+qwoOjy+u6AzR0N/5j6ktS 00EYgcfy7Zrulu42RD3roya+q7WTZjQAZV2p1a/bicsLEWHa+E4vKDO4hdb5a8qubwdW GFx1uenOzx9LGE3LU6/sKkcSoCdR5S6z/T1pMqgfBF9zg1+bOKefO1zgRBkFcbeYTCLG umIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BnQW0DvgaZN0T2yAGdSifoOIby01eTPtmMKzkfkFCKA=; b=0opnDS3Z8NbtgF0D+1z6+UL7BLgW1IOu+LPxCzAippqqF4cRd4TVufK8vH3eCl2YMb pxpLLuArSiBjJOC+EnH4vVMqI23EDpLgot+aGxcdMoLc9BFq5ZYXDRYYCJzeAWCPpFUz yC4ZYqUF+phDs2GHburfsgbB78o79bBqvbYnfIYkn2mi+SbVDhLvbuF7TmPtD8QHM3Ju 4QDU6cHhrORlev6/MS7+ghIVAswzNB4WNy3eIVF6k53Ms5nivZZnoBV2CGXAvEVWx0NE sJabdYrZe7bqCXSqagOgBSgZZ7hD1akj5kh1MkuVp1rqQwjeXmn2Yc7YJeWMFBxsfWE3 iKZw== X-Gm-Message-State: AOAM533V+vKz/3VM1rXbzq6h63BOMc0+j/hUeh0xMNQN2Dz6qKqNvk5/ cDQHCEy93x6MdoqrBhyIwKm1vb6DJ2Fudw== X-Google-Smtp-Source: ABdhPJyzBIQbrDc+0nl32q2rfIvqPxQvYKGnwqC9+pFF73NbsEZIC8nSlMKYKz6+nAkbY7Cm3WgQng== X-Received: by 2002:a65:6216:0:b0:39d:5e6c:7578 with SMTP id d22-20020a656216000000b0039d5e6c7578mr6921313pgv.114.1650217496699; Sun, 17 Apr 2022 10:44:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 31/60] target/arm: Name CPSecureState type Date: Sun, 17 Apr 2022 10:43:57 -0700 Message-Id: <20220417174426.711829-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650219643805100001 Content-Type: text/plain; charset="utf-8" Give this enum a name and use in ARMCPRegInfo and add_cpreg_to_hashtable. Add the enumerator ARM_CP_SECSTATE_BOTH to clarify how 0 is handled in define_one_arm_cp_reg_with_opaque. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpregs.h | 7 ++++--- target/arm/helper.c | 3 ++- 2 files changed, 6 insertions(+), 4 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index fe338730ab..3528c0ebb1 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -133,10 +133,11 @@ typedef enum { * registered entry will only have one to identify whether the entry is se= cure * or non-secure. */ -enum { +typedef enum { + ARM_CP_SECSTATE_BOTH =3D 0, /* define one cpreg for each secstat= e */ ARM_CP_SECSTATE_S =3D (1 << 0), /* bit[0]: Secure state register */ ARM_CP_SECSTATE_NS =3D (1 << 1), /* bit[1]: Non-secure state register= */ -}; +} CPSecureState; =20 /* * Access rights: @@ -268,7 +269,7 @@ struct ARMCPRegInfo { /* Access rights: PL*_[RW] */ CPAccessRights access; /* Security state: ARM_CP_SECSTATE_* bits/values */ - int secure; + CPSecureState secure; /* * The opaque pointer passed to define_arm_cp_regs_with_opaque() when * this register was defined: can be used to hand data through to the diff --git a/target/arm/helper.c b/target/arm/helper.c index 8b89039667..7c569a569a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8503,7 +8503,8 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Erro= r **errp) } =20 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, - void *opaque, CPState state, int secsta= te, + void *opaque, CPState state, + CPSecureState secstate, int crm, int opc1, int opc2, const char *name) { --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650218797; cv=none; d=zohomail.com; s=zohoarc; b=ksFy0KCSgUEyZ8e9Ld0EGCdo5goCbTSAk/E2PlSz+SD7x/DiFO9N9oFuqdmeaxPtkbWyrtptbT9DtWCbCnq2iDNqd3zyEb3fki973AJ7NmydOPLqndpx1kdHu9eOCLdHFu6HsQbnIVvNxQUqHDLmUtCtdLSRsR5tD0z2s6Aq3Bg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650218797; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=S1tmxjtzChOlXlFN2H8r9mWpojIz96JDvEta62yTA5I=; b=aDcKQQnVInRAFx9bObRqoNJoeMthgo15IdtA7suSAy5amozz/RxbpcDpbe8l+Sj0AC0RMj6aauDkMfIipsa3fRJtALp6WOgvrQ4LUHfjOr4NEz8B5IS1XcKM+yHmcI1Aup9+5lI7whNAcRGVoq7DUBl/ucR2/eekI+dIxwl0TUg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16502187969771023.0962922490502; Sun, 17 Apr 2022 11:06:36 -0700 (PDT) Received: from localhost ([::1]:48864 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9IB-000180-V7 for importer@patchew.org; Sun, 17 Apr 2022 14:06:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48692) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng8xK-0001KC-AU for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:45:02 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]:38898) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng8xG-0003P6-SU for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:45:01 -0400 Received: by mail-pg1-x535.google.com with SMTP id s137so14960264pgs.5 for ; Sun, 17 Apr 2022 10:44:58 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S1tmxjtzChOlXlFN2H8r9mWpojIz96JDvEta62yTA5I=; b=Zne17NRUnh0wV0VRNjlf17bWBhR6aWhrYRfQZQQqXWiJJV446MgEBy89v0vWksqDOG fvaGxpOQViz2x6FcpbsKhcmcAcVBA7zafyDVRH2ISVowbzAvFoySKOzCgc9DDwKwV0R+ NJytjU2kLtiOlny2peLrTeoMovw7IZ+ubG9rtJ6rI/w7Hzk6L4pIuDEYWu2PeV94strA pZ3jt5IpS3Y6hTg0+fU0lIlXqBUBrgm1/xZiO6ldH5HkmRp6F9GT6iJK2t92Te7g137d iLXM35ugMD5K5yt5+DM36gL6ThOH0bo4um5qlKVWvLE4NqpQ5unmM/3Wff603FPPSEWm QsEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S1tmxjtzChOlXlFN2H8r9mWpojIz96JDvEta62yTA5I=; b=v32OeWQv4TCFe/G/0t3zPHiKba8tRPGhY4Ju202lIerTsAFLWTZlsd//PLLIiyF10N V0utz4J2Df74FIif/ok4lVJD6ghsGrpbs8Hb1dbBNtf39z3OZUtWKFWuogwAgk3qQX8m d92HlVbed+j+LxGK55O/sB3F2aCNpqIxUA6Fe/DZ8waOBLBbuVSBtSZExrQ7UflrO7Ya NW1DcJuYhTgNzGVGKnSOAwJ8G2Q3vnwYfGgqqT2n8nj4NaBtuqvXOeLzj6RK2bTqlQvi x+MYQNrP7+IBqBItWq9fg2DeioBQiLxTC61Or7kGb2zQbstohX4N667e+qwRKdkAEb+U crFA== X-Gm-Message-State: AOAM531z8N3y/KC05NOxIZKJARkogD5PUnmKNsJFsOPOHtEQcLZZKODl p1QSNK8K5G1M1TPohG3Ip1XKKlL6E4vzdw== X-Google-Smtp-Source: ABdhPJwMkVsA1BLHMtRqLUUCTAcHp5NIl5gxKu4FkD0XjJMVD0wyQBrON+z8uQVz7LZ0FvXXeFFUEg== X-Received: by 2002:a65:614e:0:b0:380:bfd9:d4ea with SMTP id o14-20020a65614e000000b00380bfd9d4eamr7020955pgv.92.1650217497383; Sun, 17 Apr 2022 10:44:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 32/60] target/arm: Update sysreg fields when redirecting for E2H Date: Sun, 17 Apr 2022 10:43:58 -0700 Message-Id: <20220417174426.711829-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650218798146100001 Content-Type: text/plain; charset="utf-8" The new_key is always non-zero during redirection, so remove the if. Update opc0 et al from the new key. Signed-off-by: Richard Henderson --- target/arm/helper.c | 35 +++++++++++++++++++++++------------ 1 file changed, 23 insertions(+), 12 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7c569a569a..aee195400b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5915,7 +5915,9 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCP= U *cpu) =20 for (i =3D 0; i < ARRAY_SIZE(aliases); i++) { const struct E2HAlias *a =3D &aliases[i]; - ARMCPRegInfo *src_reg, *dst_reg; + ARMCPRegInfo *src_reg, *dst_reg, *new_reg; + uint32_t *new_key; + bool ok; =20 if (a->feature && !a->feature(&cpu->isar)) { continue; @@ -5934,19 +5936,28 @@ static void define_arm_vh_e2h_redirects_aliases(ARM= CPU *cpu) g_assert(src_reg->opaque =3D=3D NULL); =20 /* Create alias before redirection so we dup the right data. */ - if (a->new_key) { - ARMCPRegInfo *new_reg =3D g_memdup(src_reg, sizeof(ARMCPRegInf= o)); - uint32_t *new_key =3D g_memdup(&a->new_key, sizeof(uint32_t)); - bool ok; + new_reg =3D g_memdup(src_reg, sizeof(ARMCPRegInfo)); + new_key =3D g_memdup(&a->new_key, sizeof(uint32_t)); =20 - new_reg->name =3D a->new_name; - new_reg->type |=3D ARM_CP_ALIAS; - /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ - new_reg->access &=3D PL2_RW | PL3_RW; + new_reg->name =3D a->new_name; + new_reg->type |=3D ARM_CP_ALIAS; + /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ + new_reg->access &=3D PL2_RW; =20 - ok =3D g_hash_table_insert(cpu->cp_regs, new_key, new_reg); - g_assert(ok); - } +#define E(X, N) \ + ((X & CP_REG_ARM64_SYSREG_##N##_MASK) >> CP_REG_ARM64_SYSREG_##N##_SHI= FT) + + /* Update the sysreg fields */ + new_reg->opc0 =3D E(a->new_key, OP0); + new_reg->opc1 =3D E(a->new_key, OP1); + new_reg->crn =3D E(a->new_key, CRN); + new_reg->crm =3D E(a->new_key, CRM); + new_reg->opc2 =3D E(a->new_key, OP2); + +#undef E + + ok =3D g_hash_table_insert(cpu->cp_regs, new_key, new_reg); + g_assert(ok); =20 src_reg->opaque =3D dst_reg; src_reg->orig_readfn =3D src_reg->readfn ?: raw_read; --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650218950; cv=none; d=zohomail.com; s=zohoarc; b=S5ZJmtZQJCqpkUQuEjwLLHlN4DEZ+a+9dBxptl/K2C8dU/RO6KK/MbIMxbYSclrpJwgdTm8wUmGAtimlTqsBPSebukpJlM05aD1fLj2ulCF2qwRrd4xMUpAACCoaBSsHWNSISf4oHvsot6ODyQZ4i9lFumJt3eet1+1ddMHiP9c= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650218950; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aDgvjaxwViELgB4ykiyMAgIgM6sZRWkjwRFfHxxhnR0=; b=KzP1CsFcUFHQgVqWHdf4PGWFmkqs+Ujfijzr8zRgr3CKMud55o2l2ohzIHj1bpC6R8JsPrdcLtMf3Juh6BQ18qdwoTTCnKJO74MU+5JXyC2Dygs/E8/aCL8gmwdb7Jeh0f6qxOPznQpN95VVM13TPceZvib2b4LYf69XdI19Idk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650218950835957.3851845499956; Sun, 17 Apr 2022 11:09:10 -0700 (PDT) Received: from localhost ([::1]:57420 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9Kf-0006v8-DT for importer@patchew.org; Sun, 17 Apr 2022 14:09:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48766) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng8xM-0001PE-09 for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:45:04 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:46663) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng8xH-0003Pb-Hm for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:45:03 -0400 Received: by mail-pl1-x634.google.com with SMTP id be5so10713848plb.13 for ; Sun, 17 Apr 2022 10:44:59 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aDgvjaxwViELgB4ykiyMAgIgM6sZRWkjwRFfHxxhnR0=; b=q+10ZK4QziaY93HK4YRlUUL5E30RQARthfc6o4zouS9fSYBBEM1Cmf9bcC6LbhWJI+ P2MBwBI5kjOhkGR2faHETErquGN/Tu5b6pvpfju1I8Malon3SCrW5y5vHWZF97n+dPPl BlDzPP89Lh1xQy62Klv0m1umntPrV/DO3GM+JVqnJ3dR2zzRspyQVSRz11g6S5AsQAT5 HU8/GdHjArTwVfD0YDRIdPnQe3I3rgyYr/wTGoQGaTXV3WvC8umqzkRMHry64wnSgSD9 nweyMu79SxtGMPem61MWoNIAJv3nX0g/84ktjiPoHapK5wIHW/F7xUTZWKmZSqWm+yvW tsrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aDgvjaxwViELgB4ykiyMAgIgM6sZRWkjwRFfHxxhnR0=; b=zrxeKQyulkScvvSDgcGqVH4f5NXCLMjIftkXAO08vPWR7ut8UhJypau8bzUwavU1T4 igmYhpDSbvm7KiORdLv+/Tjp158WlEJaq082Ar7rY59C2W9bMTlW25+8roWePnGCzE+n kP1Cg9cSwUgFJmq7zDsR7sNeh3H672At3O794HlvDWe1hAHhlekWIFNqqwsLyfX/ougJ vxZXXWsHp0RFLuYjX6Fzkaxo+qQ/lyffp7RgahTSva9lGESe+Fu2k3wv5rehMaXSdN1t Q9G2z976kfLuOwTMpeJO5dwabiJPth+kD9YaggvSGwlUbsjM0zt35Jf4Sre2iBO8L61t jr+A== X-Gm-Message-State: AOAM532NlmIcvrUElREEQ1kkNcR2mQ8cW7FYf3IcXIPkQ4gBztb1Hho+ kNmZEiQqxTZhwP9+nJa/EGtwgtm7OS0ZTQ== X-Google-Smtp-Source: ABdhPJzRt8n4xHzQVVryvU7AVDL19Es9oEomVRJqNVLLi/Xzdl/dSjXsX6NiYya0fhadXqKdCz+UIQ== X-Received: by 2002:a17:902:cece:b0:158:d875:e6d6 with SMTP id d14-20020a170902cece00b00158d875e6d6mr7354133plg.165.1650217498102; Sun, 17 Apr 2022 10:44:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 33/60] target/arm: Store cpregs key in the hash table directly Date: Sun, 17 Apr 2022 10:43:59 -0700 Message-Id: <20220417174426.711829-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650218952765100001 Content-Type: text/plain; charset="utf-8" Cast the uint32_t key into a gpointer directly, which allows us to avoid allocating storage for each key. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 4 ++-- target/arm/gdbstub.c | 2 +- target/arm/helper.c | 45 ++++++++++++++++++++------------------------ 3 files changed, 23 insertions(+), 28 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 92fc75b2bf..af13b34697 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1080,8 +1080,8 @@ static void arm_cpu_initfn(Object *obj) ARMCPU *cpu =3D ARM_CPU(obj); =20 cpu_set_cpustate_pointers(cpu); - cpu->cp_regs =3D g_hash_table_new_full(g_int_hash, g_int_equal, - g_free, cpreg_hashtable_data_dest= roy); + cpu->cp_regs =3D g_hash_table_new_full(g_direct_hash, g_direct_equal, + NULL, cpreg_hashtable_data_destro= y); =20 QLIST_INIT(&cpu->pre_el_change_hooks); QLIST_INIT(&cpu->el_change_hooks); diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index f01a126108..f5b35cd55f 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -273,7 +273,7 @@ static void arm_gen_one_xml_sysreg_tag(GString *s, Dyna= micGDBXMLInfo *dyn_xml, static void arm_register_sysreg_for_xml(gpointer key, gpointer value, gpointer p) { - uint32_t ri_key =3D *(uint32_t *)key; + uint32_t ri_key =3D (uintptr_t)key; ARMCPRegInfo *ri =3D value; RegisterSysregXmlParam *param =3D (RegisterSysregXmlParam *)p; GString *s =3D param->s; diff --git a/target/arm/helper.c b/target/arm/helper.c index aee195400b..db9e75a42d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -215,11 +215,8 @@ bool write_list_to_cpustate(ARMCPU *cpu) static void add_cpreg_to_list(gpointer key, gpointer opaque) { ARMCPU *cpu =3D opaque; - uint64_t regidx; - const ARMCPRegInfo *ri; - - regidx =3D *(uint32_t *)key; - ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); + uint32_t regidx =3D (uintptr_t)key; + const ARMCPRegInfo *ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); =20 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { cpu->cpreg_indexes[cpu->cpreg_array_len] =3D cpreg_to_kvm_id(regid= x); @@ -231,11 +228,9 @@ static void add_cpreg_to_list(gpointer key, gpointer o= paque) static void count_cpreg(gpointer key, gpointer opaque) { ARMCPU *cpu =3D opaque; - uint64_t regidx; const ARMCPRegInfo *ri; =20 - regidx =3D *(uint32_t *)key; - ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); + ri =3D g_hash_table_lookup(cpu->cp_regs, key); =20 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { cpu->cpreg_array_len++; @@ -244,8 +239,8 @@ static void count_cpreg(gpointer key, gpointer opaque) =20 static gint cpreg_key_compare(gconstpointer a, gconstpointer b) { - uint64_t aidx =3D cpreg_to_kvm_id(*(uint32_t *)a); - uint64_t bidx =3D cpreg_to_kvm_id(*(uint32_t *)b); + uint64_t aidx =3D cpreg_to_kvm_id((uintptr_t)a); + uint64_t bidx =3D cpreg_to_kvm_id((uintptr_t)b); =20 if (aidx > bidx) { return 1; @@ -5915,16 +5910,17 @@ static void define_arm_vh_e2h_redirects_aliases(ARM= CPU *cpu) =20 for (i =3D 0; i < ARRAY_SIZE(aliases); i++) { const struct E2HAlias *a =3D &aliases[i]; - ARMCPRegInfo *src_reg, *dst_reg, *new_reg; - uint32_t *new_key; + const ARMCPRegInfo *dst_reg; + ARMCPRegInfo *src_reg; + ARMCPRegInfo *new_reg; bool ok; =20 if (a->feature && !a->feature(&cpu->isar)) { continue; } =20 - src_reg =3D g_hash_table_lookup(cpu->cp_regs, &a->src_key); - dst_reg =3D g_hash_table_lookup(cpu->cp_regs, &a->dst_key); + src_reg =3D (ARMCPRegInfo *)get_arm_cp_reginfo(cpu->cp_regs, a->sr= c_key); + dst_reg =3D get_arm_cp_reginfo(cpu->cp_regs, a->dst_key); g_assert(src_reg !=3D NULL); g_assert(dst_reg !=3D NULL); =20 @@ -5937,7 +5933,6 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCP= U *cpu) =20 /* Create alias before redirection so we dup the right data. */ new_reg =3D g_memdup(src_reg, sizeof(ARMCPRegInfo)); - new_key =3D g_memdup(&a->new_key, sizeof(uint32_t)); =20 new_reg->name =3D a->new_name; new_reg->type |=3D ARM_CP_ALIAS; @@ -5956,10 +5951,11 @@ static void define_arm_vh_e2h_redirects_aliases(ARM= CPU *cpu) =20 #undef E =20 - ok =3D g_hash_table_insert(cpu->cp_regs, new_key, new_reg); + ok =3D g_hash_table_insert(cpu->cp_regs, + (gpointer)(uintptr_t)a->new_key, new_reg); g_assert(ok); =20 - src_reg->opaque =3D dst_reg; + src_reg->opaque =3D (void *)dst_reg; src_reg->orig_readfn =3D src_reg->readfn ?: raw_read; src_reg->orig_writefn =3D src_reg->writefn ?: raw_write; if (!src_reg->raw_readfn) { @@ -8522,7 +8518,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, /* Private utility function for define_one_arm_cp_reg_with_opaque(): * add a single reginfo struct to the hash table. */ - uint32_t *key =3D g_new(uint32_t, 1); + uint32_t key; ARMCPRegInfo *r2 =3D g_memdup(r, sizeof(ARMCPRegInfo)); int is64 =3D (r->type & ARM_CP_64BIT) ? 1 : 0; int ns =3D (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; @@ -8589,10 +8585,10 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con= st ARMCPRegInfo *r, if (r->cp =3D=3D 0 || r->state =3D=3D ARM_CP_STATE_BOTH) { r2->cp =3D CP_REG_ARM64_SYSREG_CP; } - *key =3D ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, - r2->opc0, opc1, opc2); + key =3D ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, + r2->opc0, opc1, opc2); } else { - *key =3D ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); + key =3D ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); } if (opaque) { r2->opaque =3D opaque; @@ -8634,8 +8630,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, * requested. */ if (!(r->type & ARM_CP_OVERRIDE)) { - ARMCPRegInfo *oldreg; - oldreg =3D g_hash_table_lookup(cpu->cp_regs, key); + const ARMCPRegInfo *oldreg =3D get_arm_cp_reginfo(cpu->cp_regs, ke= y); if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { fprintf(stderr, "Register redefined: cp=3D%d %d bit " "crn=3D%d crm=3D%d opc1=3D%d opc2=3D%d, " @@ -8645,7 +8640,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, g_assert_not_reached(); } } - g_hash_table_insert(cpu->cp_regs, key, r2); + g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2); } =20 =20 @@ -8875,7 +8870,7 @@ void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, = size_t regs_len, =20 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encode= d_cp) { - return g_hash_table_lookup(cpregs, &encoded_cp); + return g_hash_table_lookup(cpregs, (gpointer)(uintptr_t)encoded_cp); } =20 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650220110; cv=none; d=zohomail.com; s=zohoarc; b=Ouzxc8B+eQoDu3ksdfiDOGH8/kgnc58KkC1YN2ItFrvS8L8XJC9bMQuNr1muobzCCavjoMMFJtQtX+iy4jryVcIvIDcu0UlAtnYJyg+JqeZF3S1MQb45MTKed5DUCgsG6z/iYr3DWeqgRVHELReuFaRyKioVp/RMCM8nmW0/HoY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650220110; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KVOnCjEQiAnuJHjeIoAiZ0aHmG7YiIy0zMzqF1b7fG4=; b=fBpS7FC05TZwFjpgyKc992cHc+vNcIcwhgCK72V34Upu9wgOcfZELs6kGRl2eRpLeY8UVd+1+5Bge1iAt+LV3ZmJDeHkLW12eSglV0ATY7oQXppIYzXoB70vIRKeuM83zSxq0NWCcAT4p5z8vJYXOLtzKTfgfPvANz5J1kVp94Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650220110313210.47305650295073; Sun, 17 Apr 2022 11:28:30 -0700 (PDT) Received: from localhost ([::1]:45538 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9dN-0003JX-6J for importer@patchew.org; Sun, 17 Apr 2022 14:28:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48782) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng8xM-0001QN-BW for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:45:04 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]:35498) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng8xI-0003QB-8Q for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:45:03 -0400 Received: by mail-pg1-x536.google.com with SMTP id k62so8888438pgd.2 for ; Sun, 17 Apr 2022 10:44:59 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KVOnCjEQiAnuJHjeIoAiZ0aHmG7YiIy0zMzqF1b7fG4=; b=TqDEJM02ssx29JOqmz9Ai/+UgG1EM0RDDecBUXMP9J+WMfeXKpilxyLuyJJFIPn19B B9DYeglGHwX0uURJL+g9eJSz5yj1GWODAKqBkZchjbrOBRzZ0LABrkSArdMJEBUJu20Q iz/gPVM18G8ayOY+FUEWdbGWdpysESPccDmN64MRouWzPuS6BJ7Db8DWOQL2FTz+xtyg 1AiJjOQZMq3qWQ2LnLqt/zJy8xI4MRD54gshSr1/3LSZl5ZRg488lPmxA2er17cPz8Hr pYDGZ4DxjYpnv6v5/SzEKqn41gvfv83ndUq5PtFkvTdFTiE/FYIi0BMkUQDQ6NhOq514 MdeA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KVOnCjEQiAnuJHjeIoAiZ0aHmG7YiIy0zMzqF1b7fG4=; b=HdG+2Xe+SFQ56GzQl8YHV4jbw33CVGoVgVqfb7ggNOKvtr9exNTBBNlxwXmlIdyHz5 XWDQpQS4VG5uSKgxC0lSKBGcTkvNLFBqgs16wShC4h08Te24JZfl75iqxqV+B+PXPHIQ l8Rxt4LqHagryhGWIgVNAAmXUl6UtyDWweCEhOJbMBHYBLbkTZH1u11Mc1/c2DLPkdhC bSfYGkhTv4jLAFvyWoqPU/WifciLglITF6BBnqZapBadl6h5a0bRPuWe011aVF3SvuEB iziiG84FPuSQyUKl0hV37ojjw7uJUBVr7RSRS2Vn1S1ZM94ujAA5QSkzNVXSdnGIQxd4 vQ8g== X-Gm-Message-State: AOAM533rM3s+G8Cj80BxPZrE+faGBuzLD+DotOmXu9StRPG9RYF9soWH O55qfpSNj52MJf5GM3qgOdOQbqtzICe9kw== X-Google-Smtp-Source: ABdhPJxAzvANBVyMl+OFjETehWHeAaYoP+LoD84mj0oCdPSUZjJybOA/crFXUPZYGiKX6T4W3SvPZQ== X-Received: by 2002:a63:444f:0:b0:39d:3aa5:c9f0 with SMTP id t15-20020a63444f000000b0039d3aa5c9f0mr7176015pgk.363.1650217498857; Sun, 17 Apr 2022 10:44:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 34/60] target/arm: Cleanup add_cpreg_to_hashtable Date: Sun, 17 Apr 2022 10:44:00 -0700 Message-Id: <20220417174426.711829-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650220112117100001 Content-Type: text/plain; charset="utf-8" Use a single memory allocation for name and reginfo. Perform the override check early; use assert not printf+abort. Use a switch statement to validate state. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 16 +---- target/arm/helper.c | 154 +++++++++++++++++++++++--------------------- 2 files changed, 81 insertions(+), 89 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index af13b34697..3da8841eb2 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1061,27 +1061,13 @@ uint64_t arm_cpu_mp_affinity(int idx, uint8_t clust= ersz) return (Aff1 << ARM_AFF1_SHIFT) | Aff0; } =20 -static void cpreg_hashtable_data_destroy(gpointer data) -{ - /* - * Destroy function for cpu->cp_regs hashtable data entries. - * We must free the name string because it was g_strdup()ed in - * add_cpreg_to_hashtable(). It's OK to cast away the 'const' - * from r->name because we know we definitely allocated it. - */ - ARMCPRegInfo *r =3D data; - - g_free((void *)r->name); - g_free(r); -} - static void arm_cpu_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); =20 cpu_set_cpustate_pointers(cpu); cpu->cp_regs =3D g_hash_table_new_full(g_direct_hash, g_direct_equal, - NULL, cpreg_hashtable_data_destro= y); + NULL, g_free); =20 QLIST_INIT(&cpu->pre_el_change_hooks); QLIST_INIT(&cpu->el_change_hooks); diff --git a/target/arm/helper.c b/target/arm/helper.c index db9e75a42d..562ea5c418 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8509,37 +8509,90 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Er= ror **errp) return cpu_list; } =20 +/* + * Private utility function for define_one_arm_cp_reg_with_opaque(): + * add a single reginfo struct to the hash table. + */ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, void *opaque, CPState state, CPSecureState secstate, int crm, int opc1, int opc2, const char *name) { - /* Private utility function for define_one_arm_cp_reg_with_opaque(): - * add a single reginfo struct to the hash table. - */ uint32_t key; - ARMCPRegInfo *r2 =3D g_memdup(r, sizeof(ARMCPRegInfo)); - int is64 =3D (r->type & ARM_CP_64BIT) ? 1 : 0; - int ns =3D (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; + ARMCPRegInfo *r2; + bool is64 =3D r->type & ARM_CP_64BIT; + bool ns =3D secstate & ARM_CP_SECSTATE_NS; + int cp =3D r->cp; + bool isbanked; + size_t name_len; =20 - r2->name =3D g_strdup(name); - /* Reset the secure state to the specific incoming state. This is - * necessary as the register may have been defined with both states. + switch (state) { + case ARM_CP_STATE_AA32: + /* We assume it is a cp15 register if the .cp field is left unset.= */ + if (cp =3D=3D 0 && r->state =3D=3D ARM_CP_STATE_BOTH) { + cp =3D 15; + } + key =3D ENCODE_CP_REG(cp, is64, ns, r->crn, crm, opc1, opc2); + break; + case ARM_CP_STATE_AA64: + /* + * To allow abbreviation of ARMCPRegInfo definitions, we treat + * cp =3D=3D 0 as equivalent to the value for "standard guest-visi= ble + * sysreg". STATE_BOTH definitions are also always "standard sysr= eg" + * in their AArch64 view (the .cp value may be non-zero for the + * benefit of the AArch32 view). + */ + if (cp =3D=3D 0 || r->state =3D=3D ARM_CP_STATE_BOTH) { + cp =3D CP_REG_ARM64_SYSREG_CP; + } + key =3D ENCODE_AA64_CP_REG(cp, r->crn, crm, r->opc0, opc1, opc2); + break; + default: + g_assert_not_reached(); + } + + /* Overriding of an existing definition must be explicitly requested. = */ + if (!(r->type & ARM_CP_OVERRIDE)) { + const ARMCPRegInfo *oldreg =3D get_arm_cp_reginfo(cpu->cp_regs, ke= y); + if (oldreg) { + assert(oldreg->type & ARM_CP_OVERRIDE); + } + } + + /* Combine cpreg and name into one allocation. */ + name_len =3D strlen(name) + 1; + r2 =3D g_malloc(sizeof(*r2) + name_len); + *r2 =3D *r; + r2->name =3D memcpy(r2 + 1, name, name_len); + + /* + * Update fields to match the instantiation, overwiting wildcards + * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH. */ + r2->cp =3D cp; + r2->crm =3D crm; + r2->opc1 =3D opc1; + r2->opc2 =3D opc2; + r2->state =3D state; r2->secure =3D secstate; + if (opaque) { + r2->opaque =3D opaque; + } =20 - if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { - /* Register is banked (using both entries in array). + isbanked =3D r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]; + if (isbanked) { + /* + * Register is banked (using both entries in array). * Overwriting fieldoffset as the array is only used to define * banked registers but later only fieldoffset is used. */ r2->fieldoffset =3D r->bank_fieldoffsets[ns]; } - if (state =3D=3D ARM_CP_STATE_AA32) { - if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { - /* If the register is banked then we don't need to migrate or + if (isbanked) { + /* + * If the register is banked then we don't need to migrate or * reset the 32-bit instance in certain cases: * * 1) If the register has both 32-bit and 64-bit instances the= n we @@ -8554,56 +8607,22 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con= st ARMCPRegInfo *r, r2->type |=3D ARM_CP_ALIAS; } } else if ((secstate !=3D r->secure) && !ns) { - /* The register is not banked so we only want to allow migrati= on of - * the non-secure instance. + /* + * The register is not banked so we only want to allow migrati= on + * of the non-secure instance. */ r2->type |=3D ARM_CP_ALIAS; } =20 - if (r->state =3D=3D ARM_CP_STATE_BOTH) { - /* We assume it is a cp15 register if the .cp field is left un= set. - */ - if (r2->cp =3D=3D 0) { - r2->cp =3D 15; - } - + if (r->state =3D=3D ARM_CP_STATE_BOTH && r->fieldoffset) { #ifdef HOST_WORDS_BIGENDIAN - if (r2->fieldoffset) { - r2->fieldoffset +=3D sizeof(uint32_t); - } + r2->fieldoffset +=3D sizeof(uint32_t); #endif } } - if (state =3D=3D ARM_CP_STATE_AA64) { - /* To allow abbreviation of ARMCPRegInfo - * definitions, we treat cp =3D=3D 0 as equivalent to - * the value for "standard guest-visible sysreg". - * STATE_BOTH definitions are also always "standard - * sysreg" in their AArch64 view (the .cp value may - * be non-zero for the benefit of the AArch32 view). - */ - if (r->cp =3D=3D 0 || r->state =3D=3D ARM_CP_STATE_BOTH) { - r2->cp =3D CP_REG_ARM64_SYSREG_CP; - } - key =3D ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, - r2->opc0, opc1, opc2); - } else { - key =3D ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); - } - if (opaque) { - r2->opaque =3D opaque; - } - /* reginfo passed to helpers is correct for the actual access, - * and is never ARM_CP_STATE_BOTH: - */ - r2->state =3D state; - /* Make sure reginfo passed to helpers for wildcarded regs - * has the correct crm/opc1/opc2 for this reg, not CP_ANY: - */ - r2->crm =3D crm; - r2->opc1 =3D opc1; - r2->opc2 =3D opc2; - /* By convention, for wildcarded registers only the first + + /* + * By convention, for wildcarded registers only the first * entry is used for migration; the others are marked as * ALIAS so we don't try to transfer the register * multiple times. Special registers (ie NOP/WFI) are @@ -8612,13 +8631,14 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con= st ARMCPRegInfo *r, if (r->type & ARM_CP_SPECIAL_MASK) { r2->type |=3D ARM_CP_NO_RAW; } - if (((r->crm =3D=3D CP_ANY) && crm !=3D 0) || - ((r->opc1 =3D=3D CP_ANY) && opc1 !=3D 0) || - ((r->opc2 =3D=3D CP_ANY) && opc2 !=3D 0)) { + if ((r->crm =3D=3D CP_ANY && crm !=3D 0) || + (r->opc1 =3D=3D CP_ANY && opc1 !=3D 0) || + (r->opc2 =3D=3D CP_ANY && opc2 !=3D 0)) { r2->type |=3D ARM_CP_ALIAS | ARM_CP_NO_GDB; } =20 - /* Check that raw accesses are either forbidden or handled. Note that + /* + * Check that raw accesses are either forbidden or handled. Note that * we can't assert this earlier because the setup of fieldoffset for * banked registers has to be done first. */ @@ -8626,20 +8646,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, assert(!raw_accessors_invalid(r2)); } =20 - /* Overriding of an existing definition must be explicitly - * requested. - */ - if (!(r->type & ARM_CP_OVERRIDE)) { - const ARMCPRegInfo *oldreg =3D get_arm_cp_reginfo(cpu->cp_regs, ke= y); - if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { - fprintf(stderr, "Register redefined: cp=3D%d %d bit " - "crn=3D%d crm=3D%d opc1=3D%d opc2=3D%d, " - "was %s, now %s\n", r2->cp, 32 + 32 * is64, - r2->crn, r2->crm, r2->opc1, r2->opc2, - oldreg->name, r2->name); - g_assert_not_reached(); - } - } g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2); } =20 --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650219637; cv=none; d=zohomail.com; s=zohoarc; b=g+2dh1RVRrlu1QF1F/CFkiJctyGcltN7j2oYcQPpR5AFr1FvlxXxf9LNr+QOIlYpt5iy33IFGILMDrEFaW+9+ZPazBKe8FZyp5XIZ6KEZOf/yjMW9Nx0HRqE4a4wc84Dd9mzv8Chn58kKiLFKreGToc4WKYTQvyfqCLR2+YW3Os= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650219637; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=5StdWYGeCOlRyUwqJZ4tniRcd6lDfQV+KGHmy0NGmEs=; b=A5Xqk7ctjHPJj1AN+DVMF2+7QOrxzwk54PoKGx1YMMtKQKKLT1HJinmMBe37SNcqBbIJNco1JaWVzgwSFFzo/sNWkHYAvSItczg3VabHHcuN0LGRqLGXYXe7VfqCsbcFbOsaeg5fRBz5BjAs5/lZTRgKigoPRikRSyQ6tURJh+0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650219637594876.6703892565044; Sun, 17 Apr 2022 11:20:37 -0700 (PDT) Received: from localhost ([::1]:55454 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9Vg-0007jf-3V for importer@patchew.org; Sun, 17 Apr 2022 14:20:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48844) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng8xN-0001St-Ks for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:45:05 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:46641) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng8xJ-0003Qf-6t for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:45:05 -0400 Received: by mail-pj1-x102a.google.com with SMTP id h15-20020a17090a054f00b001cb7cd2b11dso12207611pjf.5 for ; Sun, 17 Apr 2022 10:45:00 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:44:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5StdWYGeCOlRyUwqJZ4tniRcd6lDfQV+KGHmy0NGmEs=; b=sGMHhfGMu4AyH73jaartkjimFmwe4BN4cvzK6EbMrQ//YXEMVxgtrLRSO92nv27n+W nIP4MeZwQBCnqgnRznep81tFU1LqaYLPQ6BlNW8AGUhuxer7gts8xDnK4YLbLF/hshIm mIYMDQt7kr+ubwmoXAF3sC1ucKSS3azskLCYdEX/Y0rLdsEgkKCqHJorVgpgHaBHeHVJ e4hoL6U0Q96IojvRIs4ijxOVg7v+ByAaPib/59YCwS8NBJTwl9UtON8SENQjhdTu6Rpx uSb/kdmcgEA5JcYxOz/Lw7zyLGdUTbFCxXWzelpBV+KPxCpen56l4JZsL2d67A5YCmgs z8ng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5StdWYGeCOlRyUwqJZ4tniRcd6lDfQV+KGHmy0NGmEs=; b=JJdpQgtt3WWmgjB2+SZA+yEVCflWVSS3T9VQYOvsGab3fT0VjQGFm3KQh7Q/9ghea9 8D4aXr5t2V1RXW7hMbENG4Q05dOjIbAloXpz+4qU+78RgIu8/rcQK/EdcpXi5CkITwjW URZSflA3WS8qasm5Y9c4mmSiQoeqEfST3kF4itd5zVsWqS8f+KqHWAuCM61sdVZgfGah VB5P1QGpUkIX5d8rIMbs9NSzBu3vLUNAPElSPBv4VGvsL1Us52P8bFAUVnnNvBcpMqbu 15au+PZl5Yi9bvYHv3lgMMg/eQiFOqvwpuEjHUIW1OUzo52pbU+y5Z0lWiK1oimrqMXs iguA== X-Gm-Message-State: AOAM530mF0kagvLPBDI4V//Jez3KAdXncmX8E2qMQJJGClBObjrsosMy Y/dkaKcrqr0ivaymEjIZPzBDSMhaILwTFA== X-Google-Smtp-Source: ABdhPJwPNQTz+nD2fp2ihVFe0K66kkgT2/Lj9KrE2L3IdIKXpqQx8W9xELdEMfErB63Z7xRI39LIUg== X-Received: by 2002:a17:902:cec3:b0:158:d5b4:2572 with SMTP id d3-20020a170902cec300b00158d5b42572mr7955297plg.52.1650217499754; Sun, 17 Apr 2022 10:44:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 35/60] target/arm: Handle cpreg registration for missing EL Date: Sun, 17 Apr 2022 10:44:01 -0700 Message-Id: <20220417174426.711829-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650219639894100001 Content-Type: text/plain; charset="utf-8" More gracefully handle cpregs when EL2 and/or EL3 are missing. If the reg is entirely inaccessible, do not register it at all. If the reg is for EL2, and EL3 is present but EL2 is not, squash to ARM_CP_CONST. This will simplify cpreg registration for conditional arm features. Signed-off-by: Richard Henderson --- target/arm/helper.c | 109 ++++++++++++++++++++++++++++++++------------ 1 file changed, 79 insertions(+), 30 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 562ea5c418..d9837b5bd2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8519,13 +8519,14 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con= st ARMCPRegInfo *r, int crm, int opc1, int opc2, const char *name) { + CPUARMState *env =3D &cpu->env; uint32_t key; ARMCPRegInfo *r2; bool is64 =3D r->type & ARM_CP_64BIT; bool ns =3D secstate & ARM_CP_SECSTATE_NS; int cp =3D r->cp; - bool isbanked; size_t name_len; + bool make_const; =20 switch (state) { case ARM_CP_STATE_AA32: @@ -8560,6 +8561,24 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, } } =20 + /* + * Eliminate registers that are not present because the EL is missing. + * Doing this here makes it easier to put all registers for a given + * feature into the same ARMCPRegInfo array and define them all at onc= e. + */ + if (arm_feature(env, ARM_FEATURE_EL3)) { + /* An EL2 register without EL2 but with EL3 is (usually) RES0. */ + int min_el =3D ctz32(r->access) / 2; + make_const =3D min_el =3D=3D 2 && !arm_feature(env, ARM_FEATURE_EL= 2); + } else { + CPAccessRights max_el =3D (arm_feature(env, ARM_FEATURE_EL2) + ? PL2_RW : PL1_RW); + if ((r->access & max_el) =3D=3D 0) { + return; + } + make_const =3D false; + } + /* Combine cpreg and name into one allocation. */ name_len =3D strlen(name) + 1; r2 =3D g_malloc(sizeof(*r2) + name_len); @@ -8580,44 +8599,74 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con= st ARMCPRegInfo *r, r2->opaque =3D opaque; } =20 - isbanked =3D r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]; - if (isbanked) { + if (make_const) { + /* This should not have been a very special register to begin. */ + int old_special =3D r2->type & ARM_CP_SPECIAL_MASK; + assert(old_special =3D=3D 0 || old_special =3D=3D ARM_CP_CONST); /* - * Register is banked (using both entries in array). - * Overwriting fieldoffset as the array is only used to define - * banked registers but later only fieldoffset is used. + * Set the special function to CONST, retaining the flags. + * This is important for e.g. ARM_CP_SVE so that we still + * take the SVE trap if CPTR_EL3.EZ =3D=3D 0. */ - r2->fieldoffset =3D r->bank_fieldoffsets[ns]; - } - if (state =3D=3D ARM_CP_STATE_AA32) { + r2->type |=3D ARM_CP_CONST; + /* + * Usually, these registers become RES0, but there are a few + * special cases like VPIDR_EL2 which have a constant non-zero + * value with writes ignored. So leave resetvalue as is. + * + * ARM_CP_SPECIAL_MASK has precedence, so removing the callbacks + * and offsets are not strictly necessary, but is potentially + * less confusing to debug later. + */ + r2->readfn =3D NULL; + r2->writefn =3D NULL; + r2->raw_readfn =3D NULL; + r2->raw_writefn =3D NULL; + r2->resetfn =3D NULL; + r2->fieldoffset =3D 0; + r2->bank_fieldoffsets[0] =3D 0; + r2->bank_fieldoffsets[1] =3D 0; + } else { + bool isbanked =3D r->bank_fieldoffsets[0] && r->bank_fieldoffsets[= 1]; + if (isbanked) { /* - * If the register is banked then we don't need to migrate or - * reset the 32-bit instance in certain cases: - * - * 1) If the register has both 32-bit and 64-bit instances the= n we - * can count on the 64-bit instance taking care of the - * non-secure bank. - * 2) If ARMv8 is enabled then we can count on a 64-bit version - * taking care of the secure bank. This requires that sepa= rate - * 32 and 64-bit definitions are provided. + * Register is banked (using both entries in array). + * Overwriting fieldoffset as the array is only used to define + * banked registers but later only fieldoffset is used. */ - if ((r->state =3D=3D ARM_CP_STATE_BOTH && ns) || - (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) { + r2->fieldoffset =3D r->bank_fieldoffsets[ns]; + } + if (state =3D=3D ARM_CP_STATE_AA32) { + if (isbanked) { + /* + * If the register is banked then we don't need to migrate= or + * reset the 32-bit instance in certain cases: + * + * 1) If the register has both 32-bit and 64-bit instances + * then we can count on the 64-bit instance taking care + * of the non-secure bank. + * 2) If ARMv8 is enabled then we can count on a 64-bit + * version taking care of the secure bank. This requir= es + * that separate 32 and 64-bit definitions are provided. + */ + if ((r->state =3D=3D ARM_CP_STATE_BOTH && ns) || + (arm_feature(env, ARM_FEATURE_V8) && !ns)) { + r2->type |=3D ARM_CP_ALIAS; + } + } else if ((secstate !=3D r->secure) && !ns) { + /* + * The register is not banked so we only want to allow + * migration of the non-secure instance. + */ r2->type |=3D ARM_CP_ALIAS; } - } else if ((secstate !=3D r->secure) && !ns) { - /* - * The register is not banked so we only want to allow migrati= on - * of the non-secure instance. - */ - r2->type |=3D ARM_CP_ALIAS; - } =20 - if (r->state =3D=3D ARM_CP_STATE_BOTH && r->fieldoffset) { + if (r->state =3D=3D ARM_CP_STATE_BOTH && r->fieldoffset) { #ifdef HOST_WORDS_BIGENDIAN - r2->fieldoffset +=3D sizeof(uint32_t); + r2->fieldoffset +=3D sizeof(uint32_t); #endif + } } } =20 @@ -8628,7 +8677,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, * multiple times. Special registers (ie NOP/WFI) are * never migratable and not even raw-accessible. */ - if (r->type & ARM_CP_SPECIAL_MASK) { + if (r2->type & ARM_CP_SPECIAL_MASK) { r2->type |=3D ARM_CP_NO_RAW; } if ((r->crm =3D=3D CP_ANY && crm !=3D 0) || --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650220336; cv=none; d=zohomail.com; s=zohoarc; b=DFmE+ojhIK4xJXC75IBRtLSyrH9dntnaYk/E0jWtwGgUESuojGLU2x9xMov9PqO2duY3Io1x0DrQoDODamUClC0rqPG5Rw0eJ1Ni3CO5KDWYFLX3yn8aWtpGGGq22RC/TiqHASOTMh26tm9TZ+Ryb8pZXbA68P3WIvRfUZMkxLY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650220336; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ejRoUXpC9pNdpYPEkTcVE2TTGW1PPspJDDIBjsGqdiY=; b=PlBRUU/2p8vaXLDH5Jim7X+xMqj/V7AeQE2u6SPOecW1FJRf6YmGGzrIbAyTNIOrJbKgxpy6L9BmIy0fj02lkB+jKjZPLoiz4aY2muuCFq+n8fpqnbE9Ys89Pp49OtxH75xZq57cQbpNDZgFXwMTverGOVeJCRi6hEMp2RLvyKY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650220336332997.003534542455; Sun, 17 Apr 2022 11:32:16 -0700 (PDT) Received: from localhost ([::1]:54500 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9h1-0000sD-1a for importer@patchew.org; Sun, 17 Apr 2022 14:32:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48868) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng8xO-0001Up-57 for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:45:06 -0400 Received: from mail-pg1-x52a.google.com ([2607:f8b0:4864:20::52a]:33594) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng8xK-0003RR-7V for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:45:05 -0400 Received: by mail-pg1-x52a.google.com with SMTP id k14so14987254pga.0 for ; Sun, 17 Apr 2022 10:45:01 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.44.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:45:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ejRoUXpC9pNdpYPEkTcVE2TTGW1PPspJDDIBjsGqdiY=; b=TAaqPBvrORxDPELRwR1iQbWOef+kBL+uSVObm9hvkQ4J+5EkNRxtuEP3U0YnBtVj7u RGj15rLxFPGSjESNSYc7u4aun0q1np7JvN3TNXZZdCtMSgnk9AdS67LaRroc1SAIYEQH 3IDJhk/TqjUViY+3AeCPYHYjvdD9/fw3P6tonRPHnfqtIOajdjf3MqBmD41ZYlKA9niw Qa9cxyliN+pEAiZ6842tMdfTXq/8b3hx818rJnMKoAFjHOKPluDgY3jbxqPJPssqtII6 yv4DodSPbMfbuOx2MR+t/h0ybuaiY83yWnuGvMkhlUnjzM3+UjXBVfL+UACfOPgWo7JX Nq5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ejRoUXpC9pNdpYPEkTcVE2TTGW1PPspJDDIBjsGqdiY=; b=Q2v/JAgNrG+uTXbqxHbQl3VCbtRTr4XcRsGyeCjX91HRQ7Yanoci7+8fIdnVGDkMq6 HEkVMLxVNk2tInub8N0oVmQw/Gnu1yuV9t+/GIDz7vtrxGzIbdn1OgSr2GdT+Lr4kUEa lN2zIwcb3v+1uoxdBSsHV0VftoAN8+pNyF1VAO3CRfqqvegFJXW4/kUi1Pak7onmd205 05DwJsB3GjkdCVNlgt2HUwavzD1suyUCs+RnKkC+T4R72c4SYV064C8SAL4IwL4IvJPp Z4U5bisua7wF67oK5fyW65Z5WMr514hAtSeQpV91xxyVwp6hql5yKrXJtshCy06kGO3t eerw== X-Gm-Message-State: AOAM531u3iZ3qWeIHHe5cdNzU/LOOF/xllIH7Qe5iHhbCnTih9HzAi5b IEvIWfQxQhy9ExxOw8hgkMEonaz19gVL7w== X-Google-Smtp-Source: ABdhPJww9boLMkfgZn+2v4MJlO49TFDh8FDMDfRXILaRoPXQcVCHoQnH0HuzuyXU2d9bB41CXE+CQw== X-Received: by 2002:a63:f642:0:b0:386:53e:9cd4 with SMTP id u2-20020a63f642000000b00386053e9cd4mr6990379pgj.265.1650217500650; Sun, 17 Apr 2022 10:45:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 36/60] target/arm: Drop EL3 no EL2 fallbacks Date: Sun, 17 Apr 2022 10:44:02 -0700 Message-Id: <20220417174426.711829-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650220336822100001 Content-Type: text/plain; charset="utf-8" Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo, and the local vpidr_regs definition, and rely on the squasing to ARM_CP_CONST while registering. Signed-off-by: Richard Henderson --- target/arm/helper.c | 158 ++++---------------------------------------- 1 file changed, 13 insertions(+), 145 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index d9837b5bd2..cc65ab887e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5099,124 +5099,6 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .fieldoffset =3D offsetoflow32(CPUARMState, cp15.mdcr_el3) }, }; =20 -/* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ -static const ARMCPRegInfo el3_no_el2_cp_reginfo[] =3D { - { .name =3D "VBAR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, - .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore }, - { .name =3D "HCR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "HACR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 7, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "ESR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CPTR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "MAIR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "HMAIR1", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 1, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "AMAIR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "HAMAIR1", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 1, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "AFSR0_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "AFSR1_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "TCR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "VTCR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "VTTBR", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 6, .crm =3D 2, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetvalue =3D 0 }, - { .name =3D "VTTBR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "SCTLR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "TPIDR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "TTBR0_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "HTTBR", .cp =3D 15, .opc1 =3D 4, .crm =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "CNTHCTL_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CNTVOFF_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 0, .opc2 =3D 3, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CNTVOFF", .cp =3D 15, .opc1 =3D 4, .crm =3D 14, - .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "CNTHP_CVAL_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CNTHP_CVAL", .cp =3D 15, .opc1 =3D 6, .crm =3D 14, - .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "CNTHP_TVAL_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CNTHP_CTL_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 1, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "MDCR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, - .access =3D PL2_RW, .accessfn =3D access_tda, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "HPFAR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 4, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "HSTR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 3, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "FAR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "HIFAR", .state =3D ARM_CP_STATE_AA32, - .type =3D ARM_CP_CONST, - .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 2, - .access =3D PL2_RW, .resetvalue =3D 0 }, -}; - -/* Ditto, but for registers which exist in ARMv8 but not v7 */ -static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] =3D { - { .name =3D "HCR2", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 4, - .access =3D PL2_RW, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, -}; - static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_= mask) { ARMCPU *cpu =3D env_archcpu(env); @@ -7912,7 +7794,17 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, v8_idregs); define_arm_cp_regs(cpu, v8_cp_reginfo); } - if (arm_feature(env, ARM_FEATURE_EL2)) { + + /* + * Register the base EL2 cpregs. + * Pre v8, these registers are implemented only as part of the + * Virtualization Extensions (EL2 present). Beginning with v8, + * if EL2 is missing but EL3 is enabled, mostly these become + * RES0 from EL3, with some specific exceptions. + */ + if (arm_feature(env, ARM_FEATURE_EL2) + || (arm_feature(env, ARM_FEATURE_EL3) + && arm_feature(env, ARM_FEATURE_V8))) { uint64_t vmpidr_def =3D mpidr_read_val(env); ARMCPRegInfo vpidr_regs[] =3D { { .name =3D "VPIDR", .state =3D ARM_CP_STATE_AA32, @@ -7953,33 +7845,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) }; define_one_arm_cp_reg(cpu, &rvbar); } - } else { - /* If EL2 is missing but higher ELs are enabled, we need to - * register the no_el2 reginfos. - */ - if (arm_feature(env, ARM_FEATURE_EL3)) { - /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value - * of MIDR_EL1 and MPIDR_EL1. - */ - ARMCPRegInfo vpidr_regs[] =3D { - { .name =3D "VPIDR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 = =3D 0, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .type =3D ARM_CP_CONST, .resetvalue =3D cpu->midr, - .fieldoffset =3D offsetof(CPUARMState, cp15.vpidr_el2) }, - { .name =3D "VMPIDR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 = =3D 5, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .type =3D ARM_CP_NO_RAW, - .writefn =3D arm_cp_write_ignore, .readfn =3D mpidr_read= }, - }; - define_arm_cp_regs(cpu, vpidr_regs); - define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); - if (arm_feature(env, ARM_FEATURE_V8)) { - define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo); - } - } } + + /* Register the base EL3 cpregs. */ if (arm_feature(env, ARM_FEATURE_EL3)) { define_arm_cp_regs(cpu, el3_cp_reginfo); ARMCPRegInfo el3_regs[] =3D { --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650219116; cv=none; d=zohomail.com; s=zohoarc; b=SQzCryeYuB3RNdac0YZt14SqplcCeX+6eXxvmefc/3pkfqkAjnFTE1+CiBW5HRE94EtkL5QI9Ei+8IuPFhJnnJINO61QGJ4mVQASctVhbMM0V7aN5WN7XJ5LhGv4TuVKNk5emVc+HoncWAW6vsYcqYc6PQuZQVMtb21QRqAutlQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650219116; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=X9GROJ2XF7+CSyCmZaDichiw/5K3bO7LPiqj5yPTM2o=; b=PaZNyKGZ8Bcse+7kPEmulUAUv8yZoWfav5CAD+QWZ03I/Q9dosm9zhOcMVtBLzkEYr30zsW9qpL59rnydAulAl+jZNJZllEiqur6YNwBHpP1iyT5710GUxFn1SuhMYgNAd3n9aRedpqvWWgKZK18Ms7jdTrBBZkxXz9tS7sQIPA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650219116745550.6274862538614; Sun, 17 Apr 2022 11:11:56 -0700 (PDT) Received: from localhost ([::1]:37726 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9NL-0004BC-G8 for importer@patchew.org; Sun, 17 Apr 2022 14:11:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48846) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng8xN-0001T8-Mu for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:45:05 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]:42705) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng8xK-0003S2-Sh for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:45:05 -0400 Received: by mail-pg1-x534.google.com with SMTP id bg9so14932516pgb.9 for ; Sun, 17 Apr 2022 10:45:02 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.45.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:45:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=X9GROJ2XF7+CSyCmZaDichiw/5K3bO7LPiqj5yPTM2o=; b=TiJ/iHh+jx0A4f0aUVSWgh+fNcmuIZfwpS5D7JDnZ2AZp/mHW1sXqA814ap6ZQfI2C OviNEvii8EHqK7SaDXi2QnkNPIkmBFIRLskgQEeyTc3kOEuwbwjOEU3DsC4OGw4nR8W9 eeG9IBP5+ZFzBMSDJ2DhL2p8KP5v7rAkjGk/IKzrv4hARZ2+35gf+tW+wDXq7lGSQK8/ SnZlOdsiqWtjGUAdU/0YNUOIz5BjUgot2bHEecifCTS3E1scBG2xeZyzAz6q7uiSZ74C XRZJzLD44PVdYE5Gzx/I3vK29tWX3bqZKGpu+9kbgSd64XmygePzMOFvWC+ighkt7gMV rumg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X9GROJ2XF7+CSyCmZaDichiw/5K3bO7LPiqj5yPTM2o=; b=g2CcrnrmMX4TfDs1xIWgl/A9Zrzrxl0zQ5OoZncMpvJapQ/1tJviplWBH8sUTEgNM1 LyWF9hk9qMqARUbyFJ6hl0QAc0daFy94CKR6CXl9KV+yuvRe5a9UbEXZcgIAkaFPKLU1 Jovqv6ifA+5cDXwXLwwHfETL1NgCVWLy4U1ceJ4D6jPNsEO80dQ+G4MaMXoEh6pYNPa4 eOTRRAa8FeAOjySQ6saW+stVMXoXmUBwuPDJfstDkV3X0UpcSN/QthhT+ep9s2y9gtkT EZRsxwA/dAj6NONHfQKedKZjTTzuGQ8GF+DXxOske4Cdl9s2LT1UJDbnIs4DnoJTMRvp 8O/A== X-Gm-Message-State: AOAM530AOU2vre1e93MnHedDenY7czOCphX9JAsh+/nATgTEzmhhDf3p TbW0G5k4nEhDmcNa7ngtQj9IRFK6KWo+Jg== X-Google-Smtp-Source: ABdhPJxwcVXbBdDLXPGKreBVbeLJ48+OfCqWIJjjLxP1YNgioBZYQuVcahjAcS9+XAktClG7pf3Bog== X-Received: by 2002:a05:6a00:23d2:b0:4fa:f262:719 with SMTP id g18-20020a056a0023d200b004faf2620719mr8494563pfc.4.1650217501473; Sun, 17 Apr 2022 10:45:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 37/60] target/arm: Merge zcr reginfo Date: Sun, 17 Apr 2022 10:44:03 -0700 Message-Id: <20220417174426.711829-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650219117374100001 Content-Type: text/plain; charset="utf-8" Drop zcr_no_el2_reginfo and merge the 3 registers into one array, now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped while registering. Signed-off-by: Richard Henderson --- target/arm/helper.c | 55 ++++++++++++++------------------------------- 1 file changed, 17 insertions(+), 38 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index cc65ab887e..e762054b5d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6132,35 +6132,22 @@ static void zcr_write(CPUARMState *env, const ARMCP= RegInfo *ri, } } =20 -static const ARMCPRegInfo zcr_el1_reginfo =3D { - .name =3D "ZCR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_SVE, - .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[1]), - .writefn =3D zcr_write, .raw_writefn =3D raw_write -}; - -static const ARMCPRegInfo zcr_el2_reginfo =3D { - .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_SVE, - .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[2]), - .writefn =3D zcr_write, .raw_writefn =3D raw_write -}; - -static const ARMCPRegInfo zcr_no_el2_reginfo =3D { - .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_SVE, - .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore -}; - -static const ARMCPRegInfo zcr_el3_reginfo =3D { - .name =3D "ZCR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL3_RW, .type =3D ARM_CP_SVE, - .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[3]), - .writefn =3D zcr_write, .raw_writefn =3D raw_write +static const ARMCPRegInfo zcr_reginfo[] =3D { + { .name =3D "ZCR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_SVE, + .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[1]), + .writefn =3D zcr_write, .raw_writefn =3D raw_write }, + { .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_SVE, + .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[2]), + .writefn =3D zcr_write, .raw_writefn =3D raw_write }, + { .name =3D "ZCR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, + .access =3D PL3_RW, .type =3D ARM_CP_SVE, + .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[3]), + .writefn =3D zcr_write, .raw_writefn =3D raw_write }, }; =20 void hw_watchpoint_update(ARMCPU *cpu, int n) @@ -8240,15 +8227,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) } =20 if (cpu_isar_feature(aa64_sve, cpu)) { - define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); - if (arm_feature(env, ARM_FEATURE_EL2)) { - define_one_arm_cp_reg(cpu, &zcr_el2_reginfo); - } else { - define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo); - } - if (arm_feature(env, ARM_FEATURE_EL3)) { - define_one_arm_cp_reg(cpu, &zcr_el3_reginfo); - } + define_arm_cp_regs(cpu, zcr_reginfo); } =20 #ifdef TARGET_AARCH64 --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650220551662560.0381208490368; Sun, 17 Apr 2022 11:35:51 -0700 (PDT) Received: from localhost ([::1]:33866 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9kU-0006AT-8R for importer@patchew.org; Sun, 17 Apr 2022 14:35:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48892) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng8xO-0001YP-VP for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:45:07 -0400 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]:33595) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng8xL-0003TI-OZ for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:45:06 -0400 Received: by mail-pg1-x52b.google.com with SMTP id k14so14987299pga.0 for ; Sun, 17 Apr 2022 10:45:03 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1650220553674100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 76c0dd37cd..20bf70545e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3703,6 +3703,11 @@ static inline bool isar_feature_aa32_ssbs(const ARMI= SARegisters *id) return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) !=3D 0; } =20 +static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >=3D 8; +} + /* * 64-bit feature tests via id registers. */ @@ -4009,6 +4014,11 @@ static inline bool isar_feature_aa64_ssbs(const ARMI= SARegisters *id) return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) !=3D 0; } =20 +static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >=3D 8; +} + static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) !=3D 0; @@ -4092,6 +4102,11 @@ static inline bool isar_feature_any_tts2uxn(const AR= MISARegisters *id) return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); } =20 +static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id) +{ + return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(= id); +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id i2-20020a17090a138200b001cb6512b579sm10372119pja.44.2022.04.17.10.45.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:45:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hifCwEGN2LJwACcTt38/T1y33ShijigpbIfXemOwv90=; b=bIU79iLYpnr7IjvMxoxod5GuDpIgVIn1Avh2GoMgxsmZLL2IoqwwzjcNoIuS/a+W8z s9dKhfNRJwa8u4nfYbN2PwoV1ppvEBt+C+ptX4nDlv3UEmc2zKqUY43kZ8JhpUkb+GS9 MapzNxpClvFm2U1cGk+hxTnsrtTGqQZVsqrZ0ECWAqBBakG94xgvL9TwmWSAlpR94nsQ vuTR0IFstPBZZKfaeGFCz/sJwo6OIHHHzlLHws0QejNpsl7bSZppGL1MSMCYVXfzxkzl M8Mag44UVqQ09aUtSv/yZdgWhSFeFAhDcxS4zJ5VMXdVzT8oxj1ydXILyOQ399NAR59q QMSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hifCwEGN2LJwACcTt38/T1y33ShijigpbIfXemOwv90=; b=SsYl74+VmrsG4xJA2zbnqaejGD4wvbkKLf02PXFfebZigrbRu7jNGdaSIo1Ri4AJOa kc9D7Sl05txwyqiRmP0iHOLp7cRW/Cwst2uOpjoZJ3Ie26pbugZsudECh/AMrcDMphGs pQTMgD7lvTX172T2VqeTRX5Qg5msT+1mRuXgqD2HIZFcCP1ZGj/arxqF0M97XOwdlLWQ s68gXSCGn9Sj9gQY7BR1eF8Mj5c3w0e0AKV9ZYuBInLWLAGWxPsDN6F+4UeUv5OlLheq XJ80PStvxxvCA0D2O70myDl+0UoIfLbaTiRQBSTz9RIF8hNFVfDmM6386p7g/EVkYcMD UAKw== X-Gm-Message-State: AOAM5313gXnda6fOHsTIkxYeN9rm8xVbrUjtY0SVgulvBd/n+X/W//GA NoQHV6DDrCbWYJ6qLUfQcu6gWsSrN4u8xw== X-Google-Smtp-Source: ABdhPJw3VtM8hoKlhaOIlcNozX6XO8ky6LPqwVGQDw86qYq6+83+ssoRKWkOV1Pak2fIxRt/9INYHg== X-Received: by 2002:aa7:9522:0:b0:4e1:d277:ce8 with SMTP id c2-20020aa79522000000b004e1d2770ce8mr8479794pfp.16.1650217503114; Sun, 17 Apr 2022 10:45:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 39/60] target/arm: Adjust definition of CONTEXTIDR_EL2 Date: Sun, 17 Apr 2022 10:44:05 -0700 Message-Id: <20220417174426.711829-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1650219854879100001 Content-Type: text/plain; charset="utf-8" This register is present for either VHE or Debugv8p2. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Rely on EL3-no-EL2 squashing during registration. --- target/arm/helper.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e762054b5d..3570212089 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7256,11 +7256,14 @@ static const ARMCPRegInfo jazelle_regs[] =3D { .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, }; =20 +static const ARMCPRegInfo contextidr_el2 =3D { + .name =3D "CONTEXTIDR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[2]) +}; + static const ARMCPRegInfo vhe_reginfo[] =3D { - { .name =3D "CONTEXTIDR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, - .access =3D PL2_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[2]) }, { .name =3D "TTBR1_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, .access =3D PL2_RW, .writefn =3D vmsa_tcr_ttbr_el2_write, @@ -8222,6 +8225,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &ssbs_reginfo); } =20 + if (cpu_isar_feature(aa64_vh, cpu) || + cpu_isar_feature(aa64_debugv8p2, cpu)) { + define_one_arm_cp_reg(cpu, &contextidr_el2); + } if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= )) { define_arm_cp_regs(cpu, vhe_reginfo); } --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650220121; cv=none; d=zohomail.com; s=zohoarc; b=lZ5zmkPk8+c3FP9M2ibD9MXu7fFO1d5DwF68j2oMKiAGDhXpmzIBMbzG4Zka/RpNey54Q8g1fxJnVduy1RwX5+TezDjusNirX1pUIB0a+NFPHRTFnkYMvUIKQ1dB5I8Ay85+vRYwLEPwzRbKzoK0n/HyY0nmCWG+4Kqf8t78VpI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650220121; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SQLjPgr/00ZHzz+LXu9cgSfnxSwNm0BkUh4Gx2ZNmzI=; b=AFJVeJspFpd2Cijtb0j5X0KLFt+P1QMJBiEIeTm99EV1W5aCIqV0wrAV6A6tJ3tYk3GV1Yi8Kjz/11sJ2Kf0oQFiij4WkL7VtZjFlX87FhC9f/DRlzHwrFX5CuLAdYAna1SVdQML47+sealNW5TJX3lSwwPAsQOmFD/LA0G4jBY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650220121296732.9603964530615; Sun, 17 Apr 2022 11:28:41 -0700 (PDT) Received: from localhost ([::1]:45882 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9dV-0003XW-I8 for importer@patchew.org; Sun, 17 Apr 2022 14:28:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49304) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng90K-0004Lm-2k for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:48:08 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:37746) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng90I-00041T-1y for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:48:07 -0400 Received: by mail-pl1-x62a.google.com with SMTP id v12so10752466plv.4 for ; Sun, 17 Apr 2022 10:48:05 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id e14-20020aa78c4e000000b00506475da4cesm9372055pfd.49.2022.04.17.10.48.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:48:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SQLjPgr/00ZHzz+LXu9cgSfnxSwNm0BkUh4Gx2ZNmzI=; b=mIyi9tON29gCMputm9X387391rlIQRigK/2td+qN81SyAhQ0d22YW7PCoxlsh/mMpH PylBOWsaBCK3yEbbCVTBKU8ygZsxCUp8+lfwQIA9uYo1iVltbaPPJymwqyMzrGDpQv6o YySd8xchjrIJ/D8y14i4jByoSzy46K8ADqXfldvy/xuEY9K8849cAwaUwLcstmaROEtU ijnhgBmvMZSE5Nse732dIkF5SqeVghln0+sHqBOd34QwLwfQnsmGcZX/ZMFJtPF00AxX LYIwDwjrz80vrZ66iAqOoBqcPzMmVbQpunRvGWfPm9ONlko2SHzmU1PLnZlHY9tpXrFh pzCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SQLjPgr/00ZHzz+LXu9cgSfnxSwNm0BkUh4Gx2ZNmzI=; b=n+vTKODzJI8EYNHOWShHYF+sG+10jGuL9VXbQU+1ktm5nc0g9NOYiPY76Go+YUk04+ MklrLua+LCQKgwTOXiCzfwhoKDkXEDQQzaP35yYSokPA/1rgasg5NR2L+X8ukvEnNbrP 7os+YOgmPKTesVpnSaVgz2y0IKvP3ESl/byC91ZJeXV2ex/jW/A+/tdP2kgr3AFIJHwx Zta1ezmmUsHVv7cXebLMEm98dpTI7KqoDUGiK2Zb2e1QXlGQtFs9rh4/6v7Og7xeAl+y APc3Ih7T4AvWRQze39LtXQizd6F00J2Ldcgzw3AiKrWo6UstrpF7mCxLdQElIocpIQhb QBWA== X-Gm-Message-State: AOAM532W2SRDqWxk4jk/sGeLDejiyFwkbujd9T+fGz6A4GK71CZF5wvT bV+3AI+rbAkEprO83nRa55UYSkx6lgsnFA== X-Google-Smtp-Source: ABdhPJzfm2aATVzjjTYGD5Ksr83PRThd18L1oihvWJS/m+SVri1UySiegkAfViatU/F8UV4dYEtsEg== X-Received: by 2002:a17:90b:38cb:b0:1d2:6c52:5be0 with SMTP id nn11-20020a17090b38cb00b001d26c525be0mr6620290pjb.32.1650217684476; Sun, 17 Apr 2022 10:48:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 40/60] target/arm: Move cortex impdef sysregs to cpu_tcg.c Date: Sun, 17 Apr 2022 10:44:06 -0700 Message-Id: <20220417174426.711829-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650220121856100001 Content-Type: text/plain; charset="utf-8" Previously we were defining some of these in user-only mode, but none of them are accessible from user-only, therefore define them only in system mode. This will shortly be used from cpu_tcg.c also. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v2: New patch. --- target/arm/internals.h | 6 ++++ target/arm/cpu64.c | 64 +++--------------------------------------- target/arm/cpu_tcg.c | 59 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 69 insertions(+), 60 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 7f696cd36a..96a57ee68f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1295,4 +1295,10 @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteA= rray *buf, int reg); int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg); #endif =20 +#ifdef CONFIG_USER_ONLY +static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } +#else +void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); +#endif + #endif diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index c40373bd18..67d628c0af 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -34,65 +34,9 @@ #include "hvf_arm.h" #include "qapi/visitor.h" #include "hw/qdev-properties.h" -#include "cpregs.h" +#include "internals.h" =20 =20 -#ifndef CONFIG_USER_ONLY -static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *= ri) -{ - ARMCPU *cpu =3D env_archcpu(env); - - /* Number of cores is in [25:24]; otherwise we RAZ */ - return (cpu->core_count - 1) << 24; -} -#endif - -static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] =3D { -#ifndef CONFIG_USER_ONLY - { .name =3D "L2CTLR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 11, .crm =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, .readfn =3D a57_a53_l2ctlr_read, - .writefn =3D arm_cp_write_ignore }, - { .name =3D "L2CTLR", - .cp =3D 15, .opc1 =3D 1, .crn =3D 9, .crm =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, .readfn =3D a57_a53_l2ctlr_read, - .writefn =3D arm_cp_write_ignore }, -#endif - { .name =3D "L2ECTLR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 11, .crm =3D 0, .opc2 =3D 3, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "L2ECTLR", - .cp =3D 15, .opc1 =3D 1, .crn =3D 9, .crm =3D 0, .opc2 =3D 3, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "L2ACTLR", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CPUACTLR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CPUACTLR", - .cp =3D 15, .opc1 =3D 0, .crm =3D 15, - .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, - { .name =3D "CPUECTLR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 1, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CPUECTLR", - .cp =3D 15, .opc1 =3D 1, .crm =3D 15, - .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, - { .name =3D "CPUMERRSR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 2, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CPUMERRSR", - .cp =3D 15, .opc1 =3D 2, .crm =3D 15, - .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, - { .name =3D "L2MERRSR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 3, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "L2MERRSR", - .cp =3D 15, .opc1 =3D 3, .crm =3D 15, - .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, -}; - static void aarch64_a57_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -143,7 +87,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); + define_cortex_a72_a57_a53_cp_reginfo(cpu); } =20 static void aarch64_a53_initfn(Object *obj) @@ -196,7 +140,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); + define_cortex_a72_a57_a53_cp_reginfo(cpu); } =20 static void aarch64_a72_initfn(Object *obj) @@ -247,7 +191,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); + define_cortex_a72_a57_a53_cp_reginfo(cpu); } =20 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 9338088b22..d078f06931 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -20,6 +20,65 @@ #endif #include "cpregs.h" =20 +#ifndef CONFIG_USER_ONLY +static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + ARMCPU *cpu =3D env_archcpu(env); + + /* Number of cores is in [25:24]; otherwise we RAZ */ + return (cpu->core_count - 1) << 24; +} + +static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] =3D { + { .name =3D "L2CTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 11, .crm =3D 0, .opc2 =3D 2, + .access =3D PL1_RW, .readfn =3D l2ctlr_read, + .writefn =3D arm_cp_write_ignore }, + { .name =3D "L2CTLR", + .cp =3D 15, .opc1 =3D 1, .crn =3D 9, .crm =3D 0, .opc2 =3D 2, + .access =3D PL1_RW, .readfn =3D l2ctlr_read, + .writefn =3D arm_cp_write_ignore }, + { .name =3D "L2ECTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 11, .crm =3D 0, .opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "L2ECTLR", + .cp =3D 15, .opc1 =3D 1, .crn =3D 9, .crm =3D 0, .opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "L2ACTLR", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUACTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUACTLR", + .cp =3D 15, .opc1 =3D 0, .crm =3D 15, + .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, + { .name =3D "CPUECTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUECTLR", + .cp =3D 15, .opc1 =3D 1, .crm =3D 15, + .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, + { .name =3D "CPUMERRSR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 2, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUMERRSR", + .cp =3D 15, .opc1 =3D 2, .crm =3D 15, + .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, + { .name =3D "L2MERRSR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "L2MERRSR", + .cp =3D 15, .opc1 =3D 3, .crm =3D 15, + .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, +}; + +void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) +{ + define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); +} +#endif /* !CONFIG_USER_ONLY */ + /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) =20 --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650220755; cv=none; d=zohomail.com; s=zohoarc; b=TDVtdDp9LvuiC80a6fXac8wFymkVD3Nix7pmOg+PIzbqjzomdBbWtCrutNuWMoKziGxvrDmb2llXNxUOR5eobmCKW+FRk5cJXy2ka4anuiP5xq5ChAOuTmBEXZ/qE+67mvSrFKfMogKnyqjCuyZIBNmo9k32Wx/uazBeH5KQL7w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650220755; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=jZO2s2Dq5qIWYyOsW4ddvrBCzFuwwq3hNNH5bBMwhnA=; b=CpPJoI0AO61Yp/YSsSalye0JsEqZM0tesobp1eGiInn9r5JENrorDXjQl1ydPnopL367G75CeqqyYSCkSxFiyKOZnsiu0Xv7Yga7iUC8WDHPdJvj6vU0zZukfu7YF9YK/MAVC/JJFNsASDx7BPxTFSej8EF+Z+jD40mGI+gfGGI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650220755586376.2131065428987; Sun, 17 Apr 2022 11:39:15 -0700 (PDT) Received: from localhost ([::1]:42620 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9nm-0003iL-Ja for importer@patchew.org; Sun, 17 Apr 2022 14:39:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49390) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng90M-0004Mb-79 for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:48:10 -0400 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]:41899) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng90I-00041b-O6 for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:48:09 -0400 Received: by mail-pj1-x1035.google.com with SMTP id e8-20020a17090a118800b001cb13402ea2so12268357pja.0 for ; Sun, 17 Apr 2022 10:48:06 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id e14-20020aa78c4e000000b00506475da4cesm9372055pfd.49.2022.04.17.10.48.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:48:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jZO2s2Dq5qIWYyOsW4ddvrBCzFuwwq3hNNH5bBMwhnA=; b=G9t9ymgXECL3lYrFCM65aJJ00LL6+XU5nUFcmgLdS5K/3O5QjXT2PxvJodG6ao8IjM BFQcM5fVwXRYZ9mXgPD0QPmfaA2bXsiVR7WmGHmqU3fn433EGesnVx6A6gEbuZia+jUn mV7eDqD9R+tUVIVvX1aZ4eEa8Zay8UV/o3tu8EOdOd5RkHvlhLWB6Yk3rw+/Gg/oIjqD pPShJpnfqEjpoLW2iIdW6dBqTbhX0K8oJHnSHZ3NN1fdgtYonfkVWx/LV9BVgsHrI3AY 2KjSzzf7lbsc8Fu3k96w/vJPfCJzbx3j29IWH3siwXKm/WmPb1myhqDd0Mdo714c4RLd h34A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jZO2s2Dq5qIWYyOsW4ddvrBCzFuwwq3hNNH5bBMwhnA=; b=rzs11OK2qPmgZkR3v26C1Nx31qZ6iHWAe4et49QkXd+SQT9u9bddgfEClau96tCVqn 6D+lgo0bEsS32CCQouTptma5gOcuA4BV30j86fT903j1Jn5QF6C1qYIMB5RbmBaKGpZu 6lmrJK+EmVWzH6I9JnAS9EMX9/GRHlBa+oain2/DkF/kRvqvIYiqRSKbRjQFZ03dCLQd tBv+1gD+s+gCc+RB/VrjXchiLCTSHxvlD12yYbVZ9VtuloekzK0SkJvT6qRZtYlJhxTS E773PuBBXAwCQRjLn+RDnIjPsRv3bTU2u2fM2tRVnFKL4GJ5BgQR+EuFtiO7SOhE33h/ 0Hxg== X-Gm-Message-State: AOAM532E3VPGmfmHLvGs0MOim+dwcc9R8aaIVs3c5kDW5zlDTWsvY2JE Ne9W9Nbgcp9/9vgbWPMaw5DxrRk6V+j3FA== X-Google-Smtp-Source: ABdhPJwi1PnUaQ2X/n/G7mB9YVujrqRZlm8mchFuLJ/ixu6Rew1cx2Fjtr2QWp7eu430167BvRdijA== X-Received: by 2002:a17:90b:3852:b0:1d2:7cae:220a with SMTP id nl18-20020a17090b385200b001d27cae220amr5039570pjb.197.1650217685301; Sun, 17 Apr 2022 10:48:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 41/60] target/arm: Update qemu-system-arm -cpu max to cortex-a57 Date: Sun, 17 Apr 2022 10:44:07 -0700 Message-Id: <20220417174426.711829-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650220756555100001 Content-Type: text/plain; charset="utf-8" Instead of starting with cortex-a15 and adding v8 features to a v7 cpu, begin with a v8 cpu stripped of its aarch64 features. This fixes the long-standing to-do where we only enabled v8 features for user-only. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v2: Create impdef sysregs; only enable short-vector support for user-only. --- target/arm/cpu_tcg.c | 151 ++++++++++++++++++++++++++----------------- 1 file changed, 92 insertions(+), 59 deletions(-) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index d078f06931..f9094c1752 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -994,71 +994,104 @@ static void arm_v7m_class_init(ObjectClass *oc, void= *data) static void arm_max_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + uint32_t t; =20 - cortex_a15_initfn(obj); + /* aarch64_a57_initfn, advertising none of the aarch64 features */ + cpu->dtb_compatible =3D "arm,cortex-a57"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->midr =3D 0x411fd070; + cpu->revidr =3D 0x00000000; + cpu->reset_fpsid =3D 0x41034070; + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x12111111; + cpu->isar.mvfr2 =3D 0x00000043; + cpu->ctr =3D 0x8444c004; + cpu->reset_sctlr =3D 0x00c50838; + cpu->isar.id_pfr0 =3D 0x00000131; + cpu->isar.id_pfr1 =3D 0x00011011; + cpu->isar.id_dfr0 =3D 0x03010066; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x10101105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02102211; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00011142; + cpu->isar.id_isar5 =3D 0x00011121; + cpu->isar.id_isar6 =3D 0; + cpu->isar.dbgdidr =3D 0x3516d000; + cpu->clidr =3D 0x0a200023; + cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe012; /* 48KB L1 icache */ + cpu->ccsidr[2] =3D 0x70ffe07a; /* 2048KB L2 cache */ + define_cortex_a72_a57_a53_cp_reginfo(cpu); =20 - /* old-style VFP short-vector support */ - cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); + /* Add additional features supported by QEMU */ + t =3D cpu->isar.id_isar5; + t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); + t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); + t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); + t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); + t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); + t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); + cpu->isar.id_isar5 =3D t; + + t =3D cpu->isar.id_isar6; + t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); + t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); + t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); + t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); + t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); + cpu->isar.id_isar6 =3D t; + + t =3D cpu->isar.mvfr1; + t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ + t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ + cpu->isar.mvfr1 =3D t; + + t =3D cpu->isar.mvfr2; + t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ + t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ + cpu->isar.mvfr2 =3D t; + + t =3D cpu->isar.id_mmfr3; + t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ + cpu->isar.id_mmfr3 =3D t; + + t =3D cpu->isar.id_mmfr4; + t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ + t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ + t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ + cpu->isar.id_mmfr4 =3D t; + + t =3D cpu->isar.id_pfr0; + t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); + cpu->isar.id_pfr0 =3D t; + + t =3D cpu->isar.id_pfr2; + t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); + cpu->isar.id_pfr2 =3D t; =20 #ifdef CONFIG_USER_ONLY /* - * We don't set these in system emulation mode for the moment, - * since we don't correctly set (all of) the ID registers to - * advertise them. + * Break with true ARMv8 and add back old-style VFP short-vector suppo= rt. + * Only do this for user-mode, where -cpu max is the default, so that + * older v6 and v7 programs are more likely to work without adjustment. */ - set_feature(&cpu->env, ARM_FEATURE_V8); - { - uint32_t t; - - t =3D cpu->isar.id_isar5; - t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); - t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); - t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); - t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); - t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); - t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); - cpu->isar.id_isar5 =3D t; - - t =3D cpu->isar.id_isar6; - t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); - t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); - t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); - t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); - t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); - cpu->isar.id_isar6 =3D t; - - t =3D cpu->isar.mvfr1; - t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ - t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ - cpu->isar.mvfr1 =3D t; - - t =3D cpu->isar.mvfr2; - t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ - t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ - cpu->isar.mvfr2 =3D t; - - t =3D cpu->isar.id_mmfr3; - t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ - cpu->isar.id_mmfr3 =3D t; - - t =3D cpu->isar.id_mmfr4; - t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ - t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ - t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ - cpu->isar.id_mmfr4 =3D t; - - t =3D cpu->isar.id_pfr0; - t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); - cpu->isar.id_pfr0 =3D t; - - t =3D cpu->isar.id_pfr2; - t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); - cpu->isar.id_pfr2 =3D t; - } -#endif /* CONFIG_USER_ONLY */ + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); +#endif } #endif /* !TARGET_AARCH64 */ =20 --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id e14-20020aa78c4e000000b00506475da4cesm9372055pfd.49.2022.04.17.10.48.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:48:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dXnzIOLVWxiQUUxJDgWm+uk0rCunZPcvtv01su9duzA=; b=IwyoYnQ3gcGuhO0cGuMFU6sYQovqwQ/KBdTKSL+LakbeC9SNFcYpPGtfJyc8us6hUU IvHVl3rFlQvyxN1mwiQSvDYnVoX6yS96xdbJT+p2aJPmrx/DoFTo+/AC6SWmDSgrLHsG Zpbd4W6j9bXEav5vHd6sO1FYNvH+kr97mnh37aPIcliVFXtciwQokPAwljIdLEkd/Dmm YkoPGb0zzvurqI0cIdZyhaZQFYH5p7NZOKchSjhJ6uZCujtROVWQKU4Kg1DBBUQNTozk ETMshohEnweRB+j3IsfCZtGrFfVso9MrEhfGNvasc4vZEpeQpTLXK2mIo743zf72AFGN XxNg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dXnzIOLVWxiQUUxJDgWm+uk0rCunZPcvtv01su9duzA=; b=cSJ/8UbhE2bf89z2xZ0BmEg8BT0ymeRbnHFVa+0R3OvxFha0XzCpgSvzYAQE/VMoi1 TKxVX5ycIjWl7Rhd54ExevncLNYy3UmIFZ1BXrbbxV9Vq0s9/XRRmA/6AZKsbV08THyN qj7jdWExKSiiuYdzvei9fIVsdH7q1yG4Chcc130YA6162hbRl9CC4665S2c3YAW7XOg/ tpPT3WJVrZHuzLxNp+IfYqccsGsio4U9WQZG+cidBU5vGSlLvJPOAKtc/ruuUbuYwAnT 6RlyGpWx2nayCFpkB4Vlzh7KfdhYwqT59zVnK1TVBefQ9cyBWD3/0BLGXZNKyAQ9L+jI 0NFg== X-Gm-Message-State: AOAM531ub09x6q/Vo8XkKfnKO4Qubz0E9hMq6Z1ZXy0zo5YBanFbyeL+ zSbgThn0P8mrdSd8MIewocL83nS6MAGSLw== X-Google-Smtp-Source: ABdhPJyn2ceG2Z12XC4oGnuZN73U9cmedZmvqtYmP39Kvbm6p5n/Jhvd5k/1obDFqwEotcbh/zXVNQ== X-Received: by 2002:a17:90b:268b:b0:1cd:3f24:d52d with SMTP id pl11-20020a17090b268b00b001cd3f24d52dmr9072835pjb.174.1650217686237; Sun, 17 Apr 2022 10:48:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 42/60] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max Date: Sun, 17 Apr 2022 10:44:08 -0700 Message-Id: <20220417174426.711829-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1650220561570100001 Content-Type: text/plain; charset="utf-8" We set this for qemu-system-aarch64, but failed to do so for the strictly 32-bit emulation. Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'") Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu_tcg.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index f9094c1752..9aa2f737c1 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -1084,6 +1084,10 @@ static void arm_max_initfn(Object *obj) t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); cpu->isar.id_pfr2 =3D t; =20 + t =3D cpu->isar.id_dfr0; + t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ + cpu->isar.id_dfr0 =3D t; + #ifdef CONFIG_USER_ONLY /* * Break with true ARMv8 and add back old-style VFP short-vector suppo= rt. --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650221048; cv=none; d=zohomail.com; s=zohoarc; b=Ab7zT95FwLwtS6w+zv6+Ik72rGKqnf3ehJhi6r26oCNFyIVvRV4giB/Yca4fH7dcc/a2fklZyvwgA17gOm9TUfCyQiBg1sg4KyK96MT3frZO34V+3GNdefJmska0LvEbK6osDyc1MfKIGIKh5Kw2rNtrjkth4UdMfK0XZdT5gDY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650221048; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=GHF+a2Qyrz5F/3+6IDTyiWH9/YuVGk55F/V8AQHmA28=; b=iDCfVU5q0dgvvfPRaiu8bDHQJEjjcWvMf90yS8oVF/m2Il18FyRlnW/DcAwI3fJKXNQEdjP8sT8e/bk0gLEjiCaadeeM5f/ieSbPpNwMKgR1hurP2wmTrBddnabH6grMKDqK97tbpbc8cWL5Z3XGcRNd8Pdo7rXSEGVDeqYX9/U= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650221048853724.908865769534; Sun, 17 Apr 2022 11:44:08 -0700 (PDT) Received: from localhost ([::1]:51622 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9sV-0001Qa-QH for importer@patchew.org; Sun, 17 Apr 2022 14:44:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49422) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng90N-0004O5-3a for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:48:11 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]:46655) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng90K-00041w-E4 for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:48:10 -0400 Received: by mail-pj1-x102e.google.com with SMTP id h15-20020a17090a054f00b001cb7cd2b11dso12210984pjf.5 for ; Sun, 17 Apr 2022 10:48:08 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id e14-20020aa78c4e000000b00506475da4cesm9372055pfd.49.2022.04.17.10.48.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:48:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GHF+a2Qyrz5F/3+6IDTyiWH9/YuVGk55F/V8AQHmA28=; b=DrAa0WWw/F/0hcMlPC+j+px3kp/pyL9uHgbgDVXU3yxbIWxmi31xmEBgqKjV6vJE9S m5/rAUt0M2tuSvnpKCwixvNRdTgYRxpaj+FMSYXgonxSYbYfxBaOQYpgnI4aZPY/GBLn +8NKuSCMvkJ/kEDUsIghAqVc5Yntj6Hdnnxg34/4E2DzzHCgClSp4N65aw3uZ+wsStpm uDz4Qj6WvSnw8bOrctAhv/aFn/cIzgRKR2V4xC9uCXAMuPa6R/jgZmC+tiJ7WVpC9lcc bYIwCIKsaIqNkgyjEPi15xdMDnb21HI3rKoCdtseML91gpSWoGA5gU2CrXa9DANtibAF 3Rew== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GHF+a2Qyrz5F/3+6IDTyiWH9/YuVGk55F/V8AQHmA28=; b=scvKIIgnOgk7NbfbGT/RRqyDyf8j1I0gJYmJnY7HISqt6NB6o06hxBRGHcDNCkFhq/ uQ8jngURGBWXhi2Up3ePkhovKkzhg+i0p/vSibzoGbUyR5Tbw/fI4eqoKRV3q8DovZSJ waHm7P2L2nqmtQFm2A+BU27NXnVH5ZohMzg6UbDQfwIzSuyXzB5xQjndTeyhzD2KsGeH klBAmEIvFeIaOvdDNSIOOGnWsiKkjFbjkkdnSthbhxz2Hr3AQvNZUgSUHBO3z1QtbW05 +YCs3GrT+cdGh2cvArXz+pcrOgLlda23RK7smj3ryQ6aNtMxLNXyd8UPKRRsG9afUzVK jRrA== X-Gm-Message-State: AOAM5311uYqmoWytQaSUfNsQgxaGe3cqpRRfLzFtyY/+PNZQFAtYf5CO d5xwKgdj5iFxan6AXmSsHen5PjlnCSbD0A== X-Google-Smtp-Source: ABdhPJwwnlWdVW5obEsVN6Eb9OVCisWStrYrarMmk6bboSPduYjVdBF9826pldQQeMVvyvTAVZUiyA== X-Received: by 2002:a17:902:b941:b0:14d:af72:3f23 with SMTP id h1-20020a170902b94100b0014daf723f23mr7896592pls.6.1650217687176; Sun, 17 Apr 2022 10:48:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 43/60] target/arm: Split out aa32_max_features Date: Sun, 17 Apr 2022 10:44:09 -0700 Message-Id: <20220417174426.711829-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650221049437100001 Content-Type: text/plain; charset="utf-8" Share the code to set AArch32 max features so that we no longer have code drift between qemu{-system,}-{arm,aarch64}. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/internals.h | 2 + target/arm/cpu64.c | 50 +----------------- target/arm/cpu_tcg.c | 114 ++++++++++++++++++++++------------------- 3 files changed, 65 insertions(+), 101 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 96a57ee68f..baa2a7e1f4 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1301,4 +1301,6 @@ static inline void define_cortex_a72_a57_a53_cp_regin= fo(ARMCPU *cpu) { } void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); #endif =20 +void aa32_max_features(ARMCPU *cpu); + #endif diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 67d628c0af..8f9e9d6dff 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -682,7 +682,6 @@ static void aarch64_max_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); uint64_t t; - uint32_t u; =20 if (kvm_enabled() || hvf_enabled()) { /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */ @@ -797,57 +796,12 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); cpu->isar.id_aa64zfr0 =3D t; =20 - /* Replicate the same data to the 32-bit id registers. */ - u =3D cpu->isar.id_isar5; - u =3D FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ - u =3D FIELD_DP32(u, ID_ISAR5, SHA1, 1); - u =3D FIELD_DP32(u, ID_ISAR5, SHA2, 1); - u =3D FIELD_DP32(u, ID_ISAR5, CRC32, 1); - u =3D FIELD_DP32(u, ID_ISAR5, RDM, 1); - u =3D FIELD_DP32(u, ID_ISAR5, VCMA, 1); - cpu->isar.id_isar5 =3D u; - - u =3D cpu->isar.id_isar6; - u =3D FIELD_DP32(u, ID_ISAR6, JSCVT, 1); - u =3D FIELD_DP32(u, ID_ISAR6, DP, 1); - u =3D FIELD_DP32(u, ID_ISAR6, FHM, 1); - u =3D FIELD_DP32(u, ID_ISAR6, SB, 1); - u =3D FIELD_DP32(u, ID_ISAR6, SPECRES, 1); - u =3D FIELD_DP32(u, ID_ISAR6, BF16, 1); - u =3D FIELD_DP32(u, ID_ISAR6, I8MM, 1); - cpu->isar.id_isar6 =3D u; - - u =3D cpu->isar.id_pfr0; - u =3D FIELD_DP32(u, ID_PFR0, DIT, 1); - cpu->isar.id_pfr0 =3D u; - - u =3D cpu->isar.id_pfr2; - u =3D FIELD_DP32(u, ID_PFR2, SSBS, 1); - cpu->isar.id_pfr2 =3D u; - - u =3D cpu->isar.id_mmfr3; - u =3D FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ - cpu->isar.id_mmfr3 =3D u; - - u =3D cpu->isar.id_mmfr4; - u =3D FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */ - u =3D FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - u =3D FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */ - u =3D FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */ - cpu->isar.id_mmfr4 =3D u; - t =3D cpu->isar.id_aa64dfr0; t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ cpu->isar.id_aa64dfr0 =3D t; =20 - u =3D cpu->isar.id_dfr0; - u =3D FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ - cpu->isar.id_dfr0 =3D u; - - u =3D cpu->isar.mvfr1; - u =3D FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */ - u =3D FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ - cpu->isar.mvfr1 =3D u; + /* Replicate the same data to the 32-bit id registers. */ + aa32_max_features(cpu); =20 #ifdef CONFIG_USER_ONLY /* diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 9aa2f737c1..b0dbf2c991 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -20,6 +20,66 @@ #endif #include "cpregs.h" =20 + +/* Share AArch32 -cpu max features with AArch64. */ +void aa32_max_features(ARMCPU *cpu) +{ + uint32_t t; + + /* Add additional features supported by QEMU */ + t =3D cpu->isar.id_isar5; + t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); + t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); + t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); + t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); + t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); + t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); + cpu->isar.id_isar5 =3D t; + + t =3D cpu->isar.id_isar6; + t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); + t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); + t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); + t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); + t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); + cpu->isar.id_isar6 =3D t; + + t =3D cpu->isar.mvfr1; + t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ + t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ + cpu->isar.mvfr1 =3D t; + + t =3D cpu->isar.mvfr2; + t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ + t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ + cpu->isar.mvfr2 =3D t; + + t =3D cpu->isar.id_mmfr3; + t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ + cpu->isar.id_mmfr3 =3D t; + + t =3D cpu->isar.id_mmfr4; + t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ + t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ + t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ + cpu->isar.id_mmfr4 =3D t; + + t =3D cpu->isar.id_pfr0; + t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); + cpu->isar.id_pfr0 =3D t; + + t =3D cpu->isar.id_pfr2; + t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); + cpu->isar.id_pfr2 =3D t; + + t =3D cpu->isar.id_dfr0; + t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ + cpu->isar.id_dfr0 =3D t; +} + #ifndef CONFIG_USER_ONLY static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) { @@ -994,7 +1054,6 @@ static void arm_v7m_class_init(ObjectClass *oc, void *= data) static void arm_max_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); - uint32_t t; =20 /* aarch64_a57_initfn, advertising none of the aarch64 features */ cpu->dtb_compatible =3D "arm,cortex-a57"; @@ -1035,58 +1094,7 @@ static void arm_max_initfn(Object *obj) cpu->ccsidr[2] =3D 0x70ffe07a; /* 2048KB L2 cache */ define_cortex_a72_a57_a53_cp_reginfo(cpu); =20 - /* Add additional features supported by QEMU */ - t =3D cpu->isar.id_isar5; - t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); - t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); - t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); - t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); - t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); - t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); - cpu->isar.id_isar5 =3D t; - - t =3D cpu->isar.id_isar6; - t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); - t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); - t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); - t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); - t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); - cpu->isar.id_isar6 =3D t; - - t =3D cpu->isar.mvfr1; - t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ - t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ - cpu->isar.mvfr1 =3D t; - - t =3D cpu->isar.mvfr2; - t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ - t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ - cpu->isar.mvfr2 =3D t; - - t =3D cpu->isar.id_mmfr3; - t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ - cpu->isar.id_mmfr3 =3D t; - - t =3D cpu->isar.id_mmfr4; - t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ - t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ - t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ - cpu->isar.id_mmfr4 =3D t; - - t =3D cpu->isar.id_pfr0; - t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); - cpu->isar.id_pfr0 =3D t; - - t =3D cpu->isar.id_pfr2; - t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); - cpu->isar.id_pfr2 =3D t; - - t =3D cpu->isar.id_dfr0; - t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ - cpu->isar.id_dfr0 =3D t; + aa32_max_features(cpu); =20 #ifdef CONFIG_USER_ONLY /* --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650221313869882.692894927476; Sun, 17 Apr 2022 11:48:33 -0700 (PDT) Received: from localhost ([::1]:33494 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9wm-0008F4-Pu for importer@patchew.org; Sun, 17 Apr 2022 14:48:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49478) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng90O-0004Qk-Dm for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:48:12 -0400 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]:43674) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng90L-00042K-LM for qemu-devel@nongnu.org; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id e14-20020aa78c4e000000b00506475da4cesm9372055pfd.49.2022.04.17.10.48.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:48:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Mn5JAnPbX/HurKUs1s7BoD9tJ2ismYowQ5yfOSBMbhQ=; b=Tjsib9k8ZsIN/wvDuHPchkYDSpMMfZBWaOa+fMvddO5H0psHzmExhKyXkOGljum7/y 0umvITqL/4XJ+RaIgprdfProK4E8OJ+Z4tntMsr2fL3pz6cL3I0EGj/HML8Q9uXSrG9F cyS+3Z6aehnHeN/WueYrvgGDP9PfeSZXkr8JNhEWDfYiU+50scSXwH+Fgqh++HtZWCMp a9PyjDwiVLYFdOCAtJMrXIAJQcIoumtzuewf6G0ilMXRiCYWQMT3NJ1iYjnxcjrx9jzt wMWTzeh6i+0se8O9Ezd+hGhy6I81bor99/WbEs3JQ0yJb8tBu/xWf4VsIJhQAr87DJU9 C+6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Mn5JAnPbX/HurKUs1s7BoD9tJ2ismYowQ5yfOSBMbhQ=; b=ANtBBrPahwiO9IBDxvG3Ih+H2DqFZ5K2MeVZEcpghLR1IiIvSq/PuMKMkfSwapFN4y gfbnocmy4j1cNU2jrUmfhUvNn+jsndSOZHEO7J563UwHv0mb97RIngikji7dtzhTgGJm OaS/aexYZAoCwG3TIwXwNoqPdjHvvfcBjNJHWmYaaha0c5vo2pge30PkQpZ17r9DIWIP NL9GWpiqpQegxnC5yOFSnTfMAZeTpxSokAtNDaEkaJKTzZTfUTa6sOZW0HnufLc92g3/ Z/JDdiELRmqB6S5s9snl0EUQeWtXtr2R+MCQ7utX0HH98t33+hhhLT1mM6WKhqlPA41b lbVg== X-Gm-Message-State: AOAM532JNUz1QweukHzejlaUU4FB0U9vRw/VQxjiW/KHXkoQU7KkXd19 t9VpoIcdf8tAA82SseYpI9gqPfjM7+EtpA== X-Google-Smtp-Source: ABdhPJxLQHABgNb0kfJUK5BuLC7wAyazTL5Pgyu4UXNRvVAaRVZ59k93KRZq/JdbiGANgBvsNMs0qw== X-Received: by 2002:a17:902:8f94:b0:14f:d9b3:52c2 with SMTP id z20-20020a1709028f9400b0014fd9b352c2mr7482183plo.103.1650217688188; Sun, 17 Apr 2022 10:48:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 44/60] target/arm: Annotate arm_max_initfn with FEAT identifiers Date: Sun, 17 Apr 2022 10:44:10 -0700 Message-Id: <20220417174426.711829-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1650221314449100001 Content-Type: text/plain; charset="utf-8" Update the legacy feature names to the current names. Provide feature names for id changes that were not marked. Sort the field updates into increasing bitfield order. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 96 ++++++++++++++++++++++---------------------- target/arm/cpu_tcg.c | 48 +++++++++++----------- 2 files changed, 72 insertions(+), 72 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 8f9e9d6dff..c9476680d4 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -713,51 +713,51 @@ static void aarch64_max_initfn(Object *obj) cpu->midr =3D t; =20 t =3D cpu->isar.id_aa64isar0; - t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ t =3D FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); - t =3D FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */ cpu->isar.id_aa64isar0 =3D t; =20 t =3D cpu->isar.id_aa64isar1; - t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); - t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ cpu->isar.id_aa64isar1 =3D t; =20 t =3D cpu->isar.id_aa64pfr0; + t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); + t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ cpu->isar.id_aa64pfr0 =3D t; =20 t =3D cpu->isar.id_aa64pfr1; - t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); - t =3D FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); + t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */ + t =3D FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */ /* * Begin with full support for MTE. This will be downgraded to MTE=3D0 * during realize if the board provides no tag memory, much like * we do for EL2 with the virtualization=3Don property. */ - t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); + t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ cpu->isar.id_aa64pfr1 =3D t; =20 t =3D cpu->isar.id_aa64mmfr0; @@ -769,35 +769,35 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64mmfr0 =3D t; =20 t =3D cpu->isar.id_aa64mmfr1; - t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); - t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); - t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ cpu->isar.id_aa64mmfr1 =3D t; =20 t =3D cpu->isar.id_aa64mmfr2; - t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); - t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ cpu->isar.id_aa64mmfr2 =3D t; =20 t =3D cpu->isar.id_aa64zfr0; t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); + t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ cpu->isar.id_aa64zfr0 =3D t; =20 t =3D cpu->isar.id_aa64dfr0; - t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ + t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_aa64dfr0 =3D t; =20 /* Replicate the same data to the 32-bit id registers. */ diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index b0dbf2c991..bc8f9d0edf 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -28,55 +28,55 @@ void aa32_max_features(ARMCPU *cpu) =20 /* Add additional features supported by QEMU */ t =3D cpu->isar.id_isar5; - t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); - t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); - t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); + t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ + t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ + t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); - t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); - t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); + t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ + t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ cpu->isar.id_isar5 =3D t; =20 t =3D cpu->isar.id_isar6; - t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); - t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); - t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); - t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); - t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); + t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ + t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ + t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ + t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */ + t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */ + t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */ + t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */ cpu->isar.id_isar6 =3D t; =20 t =3D cpu->isar.mvfr1; - t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ - t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ + t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */ + t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */ cpu->isar.mvfr1 =3D t; =20 t =3D cpu->isar.mvfr2; - t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ - t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ + t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ + t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ cpu->isar.mvfr2 =3D t; =20 t =3D cpu->isar.id_mmfr3; - t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ + t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ cpu->isar.id_mmfr3 =3D t; =20 t =3D cpu->isar.id_mmfr4; - t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ - t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ - t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ + t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* FEAT_AA32HPD */ + t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ + t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX*/ cpu->isar.id_mmfr4 =3D t; =20 t =3D cpu->isar.id_pfr0; - t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); + t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ cpu->isar.id_pfr0 =3D t; =20 t =3D cpu->isar.id_pfr2; - t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); + t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ cpu->isar.id_pfr2 =3D t; =20 t =3D cpu->isar.id_dfr0; - t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ + t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_dfr0 =3D t; } =20 --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650220375761585.4217711699371; Sun, 17 Apr 2022 11:32:55 -0700 (PDT) Received: from localhost ([::1]:57104 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9he-0002ps-Qd for importer@patchew.org; Sun, 17 Apr 2022 14:32:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49482) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng90O-0004Qw-Eu for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:48:12 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:35552) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng90M-00042Y-FF for qemu-devel@nongnu.org; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id e14-20020aa78c4e000000b00506475da4cesm9372055pfd.49.2022.04.17.10.48.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:48:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xLPmYgqDe1CN+qFThm+PXn8LkgCmKzZ27jOhFMTIeFk=; b=yPoF9KWzys3/WPeMOlwKtIfxR2KTN/W6FHj9xpcKodjmop9nihstHGsGy6LHWRaM1b a2DLVl95EF3osz00hw4zPAyyEXFvOCS4HGJHGq48/JnWq26d9A+rpwit2bDVWP/133Jq NIwopTiiSpaNCQWLhP8XQXv6neFcJ2IBudaqAGfCw1Z13EthoUD7jyS1nfDNDUR0C0sC d/ID/32E/tXpFegCZs/YcKnF6UsH3jm3W3Kv2vUTgjq8dUhXO0x3bZhNOlLLAq0/5zKo UF7rmHowu2KAxhkFMc7bD8e589hXv9mdN8kU16B9YmpGXK6gPvSKlT5jrGK0xuqR9Eng vYcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xLPmYgqDe1CN+qFThm+PXn8LkgCmKzZ27jOhFMTIeFk=; b=dc6bpP7phPtZ7B1sN10AoQ/84SH5nSJj5PiTZSHPuIOYOxgN89GoQkjbtEHNGfzO7G ut6jnFPPZMLSDEktRbr1q96WQmwg6Ql9HNxCKWXlym7txdHMseYIvYlOxU8FdHt2W5Yg 52XegtvVW8sUigwi9Ia+Z5oYDUJsTe974UXj3vFHr2BrfaRuuV5B96BgUFmNXNgrL7bH fMD4RMjakdytoK9HfixlxdsLZxjOiqp2iLRK5jHVmuPHGlP+9bASA3hR5bhCaYG/PQQA UHlLd0lyqnM8LfmKUOnjrbOFtv+PGHbnfA2QeeQCLXhk9ScCnsJSQ2OR1qu4tX/qvsIO HCyg== X-Gm-Message-State: AOAM530si3XNgEdlUYeEKi8rcvIYQ2Z81lirhUXS57o59jotgFxHCD3R 7NQF0/aUvOrKkCo6YqWeC0vN5I6BOAaY0w== X-Google-Smtp-Source: ABdhPJwuXeHZkxhrwr4tPwBEYx/kmXJnXu10372G/0kyDx+hB+MXzWW2yvIE6SWk//3KqDhZwBSA0w== X-Received: by 2002:a17:90a:6c64:b0:1cb:a150:52d with SMTP id x91-20020a17090a6c6400b001cba150052dmr9133416pjj.111.1650217689193; Sun, 17 Apr 2022 10:48:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 45/60] target/arm: Use field names for manipulating EL2 and EL3 modes Date: Sun, 17 Apr 2022 10:44:11 -0700 Message-Id: <20220417174426.711829-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1650220376953100001 Content-Type: text/plain; charset="utf-8" Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0 during arm_cpu_realizefn. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 3da8841eb2..33451cecf7 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1782,11 +1782,13 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) */ unset_feature(env, ARM_FEATURE_EL3); =20 - /* Disable the security extension feature bits in the processor fe= ature - * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12= ]. + /* + * Disable the security extension feature bits in the processor + * feature registers as well. */ - cpu->isar.id_pfr1 &=3D ~0xf0; - cpu->isar.id_aa64pfr0 &=3D ~0xf000; + cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECUR= ITY, 0); + cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, + ID_AA64PFR0, EL3, 0); } =20 if (!cpu->has_el2) { @@ -1817,12 +1819,14 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) } =20 if (!arm_feature(env, ARM_FEATURE_EL2)) { - /* Disable the hypervisor feature bits in the processor feature - * registers if we don't have EL2. These are id_pfr1[15:12] and - * id_aa64pfr0_el1[11:8]. + /* + * Disable the hypervisor feature bits in the processor feature + * registers if we don't have EL2. */ - cpu->isar.id_aa64pfr0 &=3D ~0xf00; - cpu->isar.id_pfr1 &=3D ~0xf000; + cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, + ID_AA64PFR0, EL2, 0); + cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, + ID_PFR1, VIRTUALIZATION, 0); } =20 #ifndef CONFIG_USER_ONLY --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165021941278453.78913410425548; Sun, 17 Apr 2022 11:16:52 -0700 (PDT) Received: from localhost ([::1]:49396 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9S7-0003Zl-QM for importer@patchew.org; Sun, 17 Apr 2022 14:16:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49526) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng90P-0004Ts-EN for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:48:13 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:41889) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng90N-000433-KL for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:48:13 -0400 Received: by mail-pj1-x102a.google.com with SMTP id e8-20020a17090a118800b001cb13402ea2so12268436pja.0 for ; Sun, 17 Apr 2022 10:48:11 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id e14-20020aa78c4e000000b00506475da4cesm9372055pfd.49.2022.04.17.10.48.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:48:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5kb+iTgkLaSEzVf4MDtkdZKydBzZHBfZ2pA462UB2xc=; b=LAnuF1jOKOzfPTqMmI3XRB1A8iNc9BUZJHTEgtEiSYvltLlKIP59zk+EAI7Jp1Zf9n in6qEe74gknIMt1rzPX2JQum+fultlfARmW15Q/SpVGo/l5uIgp7ZABtocKh3ganTXVG pCLcr3Z4XDKxNasLY8nnLFuyi+fW0IGmijNzKbLkqp5hJIoXetEzCHjbvUCFEt4EkAcC rqkrNEsRYjm+LAunjXXgXilOXtNuNNr8IGwy6w0rIvcHLWbyAItOrgET3xEZbrp5eJKC 9nXZcvqPqkPZgj7fQmxoqYTXjcHC9egwcVPcLbslJ0DvajVCHyoz4DaLrKV6W+xTBZHq oOmw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5kb+iTgkLaSEzVf4MDtkdZKydBzZHBfZ2pA462UB2xc=; b=EySsdkT5Jv834ZqjoR7O3luMBQC+hcpFo65KNLSId0RcPcDP7uugpArr3shpWUr2cI hBZdvP1OvxQ6d8SQKhH4ttenktG4LrnwZcnLovIKZAZ5J45FvCSRwGuvq/qqsKUXhCgq zj3gja4THVydoSKLqbRh3YYKlYjJv9KXzAh2hGGY1vWRVSNN/6s1LtNlLE9EQLVGm31N WNU5KJKDtovOXpLFNrkiUwTcLM4icjphdEuoctqYi0CdQ3LCluRA0OH5xgMonfFSzHzi Ov0bC/WmdXWIZ/6X3NwKrCOylasFu4vWL63z/+0KdN8FYH49WsE4ILc2ewHRj66FdhlH RvwA== X-Gm-Message-State: AOAM532lFP4V33Q4XGVT9sM55kWrCckVacKjKtolZSSHrngxZIV8s0CC jODWqYECRVCiL+SCXYzWw4bmZAOIBMfRTA== X-Google-Smtp-Source: ABdhPJz6LCKMfDYiA3oO/64pMB4E1UqYhJnbhPkqfN/R9UwsuvgHC2hzwE79Nj+00txqcY2yugNqBg== X-Received: by 2002:a17:90a:fa8d:b0:1d2:8126:ce15 with SMTP id cu13-20020a17090afa8d00b001d28126ce15mr4284693pjb.162.1650217690072; Sun, 17 Apr 2022 10:48:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 46/60] target/arm: Enable FEAT_Debugv8p2 for -cpu max Date: Sun, 17 Apr 2022 10:44:12 -0700 Message-Id: <20220417174426.711829-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1650219414588100001 Content-Type: text/plain; charset="utf-8" The only portion of FEAT_Debugv8p2 that is relevant to QEMU is CONTEXTIDR_EL2, which is also conditionally implemented with FEAT_VHE. The rest of the debug extension concerns the External debug interface, which is outside the scope of QEMU. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update emulation.rst --- docs/system/arm/emulation.rst | 1 + target/arm/cpu.c | 1 + target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 2 ++ 4 files changed, 5 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 520fd39071..035f7cf9d0 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -13,6 +13,7 @@ the following architecture extensions: - FEAT_BTI (Branch Target Identification) - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) +- FEAT_Debugv8p2 (Debug changes for v8.2) - FEAT_DotProd (Advanced SIMD dot product instructions) - FEAT_FCMA (Floating-point complex number instructions) - FEAT_FHM (Floating-point half-precision multiplication instructions) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 33451cecf7..fc0d74b4d1 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1787,6 +1787,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * feature registers as well. */ cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECUR= ITY, 0); + cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSD= BG, 0); cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, EL3, 0); } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index c9476680d4..2003d0a8c9 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -797,6 +797,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64zfr0 =3D t; =20 t =3D cpu->isar.id_aa64dfr0; + t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */ t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_aa64dfr0 =3D t; =20 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index bc8f9d0edf..b6fc3752f2 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -76,6 +76,8 @@ void aa32_max_features(ARMCPU *cpu) cpu->isar.id_pfr2 =3D t; =20 t =3D cpu->isar.id_dfr0; + t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */ + t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */ t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_dfr0 =3D t; } --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650219686752663.110595043937; Sun, 17 Apr 2022 11:21:26 -0700 (PDT) Received: from localhost ([::1]:57904 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9WX-0000y5-PC for importer@patchew.org; Sun, 17 Apr 2022 14:21:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49538) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng90P-0004V7-Sk for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:48:13 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]:39669) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng90O-00043K-4G for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:48:13 -0400 Received: by mail-pl1-x62b.google.com with SMTP id c12so10744597plr.6 for ; Sun, 17 Apr 2022 10:48:11 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id e14-20020aa78c4e000000b00506475da4cesm9372055pfd.49.2022.04.17.10.48.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:48:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9f+PlxCLNeNyBioSPuOwi62FLmam0QN4BYbQ6xWfffE=; b=Q5+ie27fkjujR7+dLFpBF91AX5F3BvHYwsbkr8De1huyL94ArsSChoJUZmrQXO7LfG 7lcBEO8PLMVMAxVmSH9VJz0li4YBEmsmLyfC46jQovSyXFbdL+PL4LrBivLjZ2y8aJ1r s6TM6ujXsmXQAzJ03mlQ/HjOwONiK+C+D6GAjb7zt/jsfU+VwkyKzfs6Hs3/AODNoHg+ cfLpUyUQWQY1zetbNN6u50nuQlX3JIf8zGuejP01XQKQQtZ9u8/G+P+cB5WkQXVZvqAi VQkuNDMFE3D8pbe+M9yb6OWNHNqXqNKYmDCSyCHGgr/Vp9lkN4+lGH67rmDHXM2v32Pi i3ag== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9f+PlxCLNeNyBioSPuOwi62FLmam0QN4BYbQ6xWfffE=; b=TvDF0OkUc8r9AMSB7QhgQ9jDH3dUiwtACKs7MogbNSVCM6xQQJLnggL9eXRcXHQqEg tHjEkxvIQIb9YC5rHyp9Q79zjviKCnuc5rN9SMZ7MsHdKLu+mqYZPCZeuSyL+QnFkky2 2VKJ/S58Gh1slYA1ET+VpRMpsj6T2HgJF1p4AXERO5Wh2l+WkLPDvZpx21GszwWyML94 J/ycslVWTD+E97aQhUw3V6SN1FiRVvF7D782LVGoz0ZLuSAoH27rJQGccc3htYhrKdsv zPdF+/9Z4sMs6Yo3IHKbD0QZUd3uE1IEPkRK+WnmF5rbeNWRTaF4ZRoNytf/hTdy7rA5 8aNg== X-Gm-Message-State: AOAM533qzoeb+Qv/yy7MW+XmHK3rgsvOiCObY6JPeACEpraV0cYiTsZ3 OUsD+yq4fZLHo4/hVFHrze4qLYYCXxJppQ== X-Google-Smtp-Source: ABdhPJzfQR6zFXs8He7K8sQqXm4cguEV/4htKiz4Til0L2GClQ6YFBK+O9vz0uJl8elxq/cBNpBCXg== X-Received: by 2002:a17:902:8217:b0:156:9c4f:90eb with SMTP id x23-20020a170902821700b001569c4f90ebmr7423442pln.121.1650217690787; Sun, 17 Apr 2022 10:48:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 47/60] target/arm: Enable FEAT_Debugv8p4 for -cpu max Date: Sun, 17 Apr 2022 10:44:13 -0700 Message-Id: <20220417174426.711829-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1650219688093100001 Content-Type: text/plain; charset="utf-8" This extension concerns changes to the External Debug interface, with Secure and Non-secure access to the debug registers, and all of it is outside the scope of QEMU. Indicating support for this is mandatory with FEAT_SEL2, which we do implement. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update emulation.rst --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 2 +- target/arm/cpu_tcg.c | 4 ++-- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 035f7cf9d0..c89c344de1 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -14,6 +14,7 @@ the following architecture extensions: - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) - FEAT_Debugv8p2 (Debug changes for v8.2) +- FEAT_Debugv8p4 (Debug changes for v8.4) - FEAT_DotProd (Advanced SIMD dot product instructions) - FEAT_FCMA (Floating-point complex number instructions) - FEAT_FHM (Floating-point half-precision multiplication instructions) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 2003d0a8c9..136590382a 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -797,7 +797,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64zfr0 =3D t; =20 t =3D cpu->isar.id_aa64dfr0; - t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */ + t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */ t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_aa64dfr0 =3D t; =20 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index b6fc3752f2..337598e949 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -76,8 +76,8 @@ void aa32_max_features(ARMCPU *cpu) cpu->isar.id_pfr2 =3D t; =20 t =3D cpu->isar.id_dfr0; - t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */ - t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */ + t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */ + t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */ t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_dfr0 =3D t; } --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650219893320882.6564009619597; Sun, 17 Apr 2022 11:24:53 -0700 (PDT) Received: from localhost ([::1]:38362 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9Zq-0006ou-T6 for importer@patchew.org; Sun, 17 Apr 2022 14:24:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49578) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng90Q-0004X6-T1 for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:48:14 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]:37522) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng90P-00043b-0l for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:48:14 -0400 Received: by mail-pj1-x102b.google.com with SMTP id mm4-20020a17090b358400b001cb93d8b137so15541256pjb.2 for ; Sun, 17 Apr 2022 10:48:12 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id e14-20020aa78c4e000000b00506475da4cesm9372055pfd.49.2022.04.17.10.48.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:48:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QrZ4LAIma7K6buALjtxKDFsEKoasy1WK64ZnNEpjen0=; b=dh+0OvM+1fhLJ5bLIEGS34EBfRXobJqfZ4g+YfjBUCBNpnDWxyhwJusLJ4uQoofIXP huKVukvqdIuC3uTFs3MfQq6GrGEkEPA3CI7QuSTVjE7D3ZE5yomy1UoO4iooxmXalve2 SIkHTviXYlJzQsGxF2fYheHU7Zrw6eaa+GGRgNeEj4t6pX1+7dNlmv43nPFLcyMl7eGk Vi0gv2mNUd8trkS3EvvIcjgNvrPYK7voooZzRq/tkseFkSseOJfR9ap5OregW3rP334X NnrrEd+IQnc4PFKPTyvP/SPvX/NFeShcrSRclFPGKt8PWWvME00nu93SCgzwQjAowfHs s8VA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QrZ4LAIma7K6buALjtxKDFsEKoasy1WK64ZnNEpjen0=; b=7KSgOudYzNy0KiatftXkVtRPAODA75+gF9kJ+CEUua8Z7pOCu/ElfQvJCxdsYpt7F/ ay+6Dp9KE2K/8qzx87PZ8Fhq5Qj5QCf2H+9nggyiP0SbzAnIJv9l3NtGOyG6Rzs0cApM b7J/Up/e+gRa+VrnbhmLzzqA4YDQySB2DnHJ+RI9H4p/rGnt3gLCepupH8Wa3Co4gOQe QfmMN82PyPOd4Wc6XtXF+y4f5x0jNsVC/rs+TdeEJ+/Z7kOzAw3pldT1YgEmft+NJ+sK 4qQ837wnm3eJvbMGoQKKAT6J+S9KfUzFYAFe2LK/wec8ZemAt9jym1b3/jciKlItuyIM UsMA== X-Gm-Message-State: AOAM530cortTe1D+nIHnK/3sK+LDBp37ODdNcdS1+4HLAk/8WvEF/qFO +u+yGJC6fArBIhHgcyIuVeFcfF02nxxvzA== X-Google-Smtp-Source: ABdhPJxYdbtIMD7VW7+p1PR8PRc0BSJMKmkoDvTim4b/6OPsn/jsTHY4vlhXTCIAV4dHruBhWyi8iw== X-Received: by 2002:a17:90b:255:b0:1cf:39e7:a7aa with SMTP id fz21-20020a17090b025500b001cf39e7a7aamr9111100pjb.137.1650217691657; Sun, 17 Apr 2022 10:48:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 48/60] target/arm: Add isar_feature_{aa64,any}_ras Date: Sun, 17 Apr 2022 10:44:14 -0700 Message-Id: <20220417174426.711829-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1650219895121100001 Content-Type: text/plain; charset="utf-8" Add the aa64 predicate for detecting RAS support from id registers. We already have the aa32 version from the M-profile work. Add the 'any' predicate for testing both aa64 and aa32. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 20bf70545e..d71edfc1c1 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3885,6 +3885,11 @@ static inline bool isar_feature_aa64_aa32_el1(const = ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >=3D 2; } =20 +static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) !=3D 0; +} + static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) !=3D 0; @@ -4107,6 +4112,11 @@ static inline bool isar_feature_any_debugv8p2(const = ARMISARegisters *id) return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(= id); } =20 +static inline bool isar_feature_any_ras(const ARMISARegisters *id) +{ + return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id); +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650220626; cv=none; d=zohomail.com; s=zohoarc; b=QBSTiyp0RjJOuNfV6TqzkWqaxoaOY+kHSKBUtyQSmOnRdh1vmGVIIX+PLAGOO+oPKXH11h1HetKYkAiHtS7Vha1qctAgqmDXXurGofaBILiGItXa/t3BY+RITtAchp6cbxEUed5NaomaZE9gMuYeTKVpW77FrMm9p7hixpS2Qg0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650220626; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/2nhgssP4ozHtkanpGxF4AjgUdqOVfu1fnJToSIqjPk=; b=WMOurhxI/LW0e128iuJCQp0y6RuM0ozaS1MqnR+Snpue9z+hbso2RJrqzN4UxeVmBg6FD5WVE3HOW+id6+9mzW1XkTdJLwlCMq06FQ9K8p5xduE0AozN+x1Qsm0ZmEnOIgdhGhHVEC6c/oC59/XNjdtJEnHmg6rcI7hKqDd73hQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650220626507883.9467350737951; Sun, 17 Apr 2022 11:37:06 -0700 (PDT) Received: from localhost ([::1]:38824 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9lh-0001Bj-F1 for importer@patchew.org; Sun, 17 Apr 2022 14:37:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49624) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng90R-0004Zk-SP for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:48:15 -0400 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:41891) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng90P-000445-UH for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:48:15 -0400 Received: by mail-pj1-x102c.google.com with SMTP id e8-20020a17090a118800b001cb13402ea2so12268475pja.0 for ; Sun, 17 Apr 2022 10:48:13 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id e14-20020aa78c4e000000b00506475da4cesm9372055pfd.49.2022.04.17.10.48.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:48:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/2nhgssP4ozHtkanpGxF4AjgUdqOVfu1fnJToSIqjPk=; b=UCpPlrx21KIcmgbDRdTOFwmykcYLUpzv/jUoYAou4AyXOn4fRDpyIHwk3ZHR4dUIUJ yxad8LsJb8UPnr9Mys9L5N+b7Ydv+IwlEI6sy6ghylOs0HfMioRIedXyTkE99702dlww nn1LgmlyoZdQ+0UiJVvT05+zqbzit2eJK609QdBSnHIXx63HocpVU8SHKxVqCT2GfMM+ UqkG4yVzNHO9PLZx2xFrEcrsHJBTlZCcQNTZXMfpxKcO21nyIiU8L4rH/UJk40/ndIlk 0Bd6qx40T1Jf9qWR+efRZvuMHnG/bpNSEzwvgdNJPel88peciE9FrEV/MMjdkrRJyzkj NtZA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/2nhgssP4ozHtkanpGxF4AjgUdqOVfu1fnJToSIqjPk=; b=TF6e01hHFFeC3TrWTYiQDQPGwXjUC1RojvX5DB2WmYcNP925LrQ/xH5M7pwQl78cxD I2pGUeI1aBZ0e4Fi1okQR4B5pM913VpP7cxnj9ze2fSHq0OBYquHhef8xvv3lo3+RbnD ksea/79WbgUIaq+alCDMr/cy6aMew1af8aXuQSUjgOD6JkMsWAbMmuVOM4R4JTNURfTz My84lE7914ZmR2ngZNYuDszqJbVm6JBP5dY1z14yzFHX3gsf/lGj/466ByGeHsy3UMND wW6GTReVLUq467WfribykQcy9SLG//kN123PcSmk44iQymIOSeIwIqELIBAef1FtZbXT qcYw== X-Gm-Message-State: AOAM53011E1uADIuI5hgc1ycA52kkyE9LJ/h8TxgM4gf9cMFIMq64kQ1 GuBu1UgfT9xNGFRmgocaLMSzDieeUNp8XA== X-Google-Smtp-Source: ABdhPJz9K2JqUrOlnV1JBVj+Zd5MuZBbIz1Un5iayRcrsbe55tUuaRwtcmAIJ739c7camVxVQM26fg== X-Received: by 2002:a17:902:7c01:b0:156:17a5:a68 with SMTP id x1-20020a1709027c0100b0015617a50a68mr7612430pll.166.1650217692666; Sun, 17 Apr 2022 10:48:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 49/60] target/arm: Add minimal RAS registers Date: Sun, 17 Apr 2022 10:44:15 -0700 Message-Id: <20220417174426.711829-50-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650220627840100001 Content-Type: text/plain; charset="utf-8" Add only the system registers required to implement zero error records. This means we need to save state for ERRSELR, but all values are out of range, so none of the indexed error record registers need be implemented. Add the EL2 registers required for injecting virtual SError. Signed-off-by: Richard Henderson --- v2: Leave ERRSELR_EL1 undefined. v3: Rely on EL3-no-EL2 squashing during registration. --- target/arm/cpu.h | 5 +++ target/arm/helper.c | 84 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d71edfc1c1..a6d1923a78 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -524,6 +524,11 @@ typedef struct CPUArchState { uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ uint64_t gcr_el1; uint64_t rgsr_el1; + + /* Minimal RAS registers */ + uint64_t disr_el1; + uint64_t vdisr_el2; + uint64_t vsesr_el2; } cp15; =20 struct { diff --git a/target/arm/helper.c b/target/arm/helper.c index 3570212089..655beba3d6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5990,6 +5990,87 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = =3D { .access =3D PL0_R, .type =3D ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = =3D 0 }, }; =20 +/* + * Check for traps to RAS registers, which are controlled + * by HCR_EL2.TERR and SCR_EL3.TERR. + */ +static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el =3D arm_current_el(env); + + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + int el =3D arm_current_el(env); + + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { + return env->cp15.vdisr_el2; + } + if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { + return 0; /* RAZ/WI */ + } + return env->cp15.disr_el1; +} + +static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = val) +{ + int el =3D arm_current_el(env); + + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { + env->cp15.vdisr_el2 =3D val; + return; + } + if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { + return; /* RAZ/WI */ + } + env->cp15.disr_el1 =3D val; +} + +/* + * Minimal RAS implementation with no Error Records. + * Which means that all of the Error Record registers: + * ERXADDR_EL1 + * ERXCTLR_EL1 + * ERXFR_EL1 + * ERXMISC0_EL1 + * ERXMISC1_EL1 + * ERXMISC2_EL1 + * ERXMISC3_EL1 + * ERXPFGCDN_EL1 (RASv1p1) + * ERXPFGCTL_EL1 (RASv1p1) + * ERXPFGF_EL1 (RASv1p1) + * ERXSTATUS_EL1 + * and + * ERRSELR_EL1 + * may generate UNDEFINED, which is the effect we get by not + * listing them at all. + */ +static const ARMCPRegInfo minimal_ras_reginfo[] =3D { + { .name =3D "DISR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 1, + .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.disr= _el1), + .readfn =3D disr_read, .writefn =3D disr_write, .raw_writefn =3D raw= _write }, + { .name =3D "ERRIDR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 3, .opc2 =3D 0, + .access =3D PL1_R, .accessfn =3D access_terr, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "VDISR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 1, .opc2 =3D 1, + .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.vdis= r_el2) }, + { .name =3D "VSESR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 2, .opc2 =3D 3, + .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.vses= r_el2) }, +}; + /* Return the exception level to which exceptions should be taken * via SVEAccessTrap. If an exception should be routed through * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should @@ -8224,6 +8305,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_ssbs, cpu)) { define_one_arm_cp_reg(cpu, &ssbs_reginfo); } + if (cpu_isar_feature(any_ras, cpu)) { + define_arm_cp_regs(cpu, minimal_ras_reginfo); + } =20 if (cpu_isar_feature(aa64_vh, cpu) || cpu_isar_feature(aa64_debugv8p2, cpu)) { --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650220977610494.87043005783255; Sun, 17 Apr 2022 11:42:57 -0700 (PDT) Received: from localhost ([::1]:48894 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9rM-00081H-Jc for importer@patchew.org; Sun, 17 Apr 2022 14:42:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49638) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng90S-0004bf-Cw for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:48:16 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:46660) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng90Q-00044Y-O1 for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:48:16 -0400 Received: by mail-pj1-x1033.google.com with SMTP id h15-20020a17090a054f00b001cb7cd2b11dso12211090pjf.5 for ; Sun, 17 Apr 2022 10:48:14 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. 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These bits are otherwise RES0. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 655beba3d6..f6468fed43 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1756,6 +1756,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) } valid_mask &=3D ~SCR_NET; =20 + if (cpu_isar_feature(aa64_ras, cpu)) { + valid_mask |=3D SCR_TERR; + } if (cpu_isar_feature(aa64_lor, cpu)) { valid_mask |=3D SCR_TLOR; } @@ -1770,6 +1773,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) } } else { valid_mask &=3D ~(SCR_RW | SCR_ST); + if (cpu_isar_feature(aa32_ras, cpu)) { + valid_mask |=3D SCR_TERR; + } } =20 if (!arm_feature(env, ARM_FEATURE_EL2)) { @@ -5126,6 +5132,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t v= alue, uint64_t valid_mask) if (cpu_isar_feature(aa64_vh, cpu)) { valid_mask |=3D HCR_E2H; } + if (cpu_isar_feature(aa64_ras, cpu)) { + valid_mask |=3D HCR_TERR | HCR_TEA; + } if (cpu_isar_feature(aa64_lor, cpu)) { valid_mask |=3D HCR_TLOR; } --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650221263; cv=none; d=zohomail.com; s=zohoarc; b=iv4diJKqMH8ud2GnG9qv3TOpDalX6vvqzMXyn6ITxHL2o6VreKoMLEhTJdSgtRtZntQV5aMwe0OozUMSoVHJ6KhvNEJfhe8lCcIFeNjRQF1vUSkxJVkM/6j4ECvQgCgOplYJ1/OB4L9dRAu0AW9oyuz/S1n1Ri84jdro/S0+N3U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650221263; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WEUJ3ZdOA9PTVRw0mKKElsPVyH1qTnSIppSOTeNDGHQ=; b=lNwco68c5dinGc2LfYHPEGV0G5ujrWfRgcnGkDJcPPNGdHrkvVTG6/DD+l9m0/EdYkqtm5Fgztt9YOCK92PdiDid533PHm4WkrfsKkKk3KjOk1uG1vlJ5VDupfGSG8CNWanHqufkHoINevGUT+GchEJvbVEmYVAdVtPKaLw1ZY4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650221262995367.95947354987425; Sun, 17 Apr 2022 11:47:42 -0700 (PDT) Received: from localhost ([::1]:60062 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9vx-00078U-QJ for importer@patchew.org; Sun, 17 Apr 2022 14:47:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49684) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng90T-0004e6-Hc for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:48:17 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:45725) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng90R-00044o-Ib for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:48:17 -0400 Received: by mail-pj1-x102f.google.com with SMTP id n33-20020a17090a5aa400b001d28f5ee3f9so736633pji.4 for ; Sun, 17 Apr 2022 10:48:15 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id e14-20020aa78c4e000000b00506475da4cesm9372055pfd.49.2022.04.17.10.48.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:48:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=WEUJ3ZdOA9PTVRw0mKKElsPVyH1qTnSIppSOTeNDGHQ=; b=sg/tHhaYw20Yi24QuT+JA7WdAWfTB/c9E+mdzrCNstCM3Gw+MchIIXfTKf/VtswOQ9 8915hSAumOR7rli6v3TZtkJniUNVCCFShM0suWnlrjmvT6hQGhaVoNgi8+fp8wGUBRuf GDJIOmdEM7L2Y3UVjk5s0RQ7DV9mpDG1D4t20nBX2yTJ3htOMjBaGbO553vUjNkWkF3m pIMvCjKPOevRkKqXojAZLFaop2wGxuUKDzcOQ7TMw6OUX3rulfU1I1oZcsHV8o0Sdl1H xPZ5PDeWBlrL5AKf7peIwacuzyA3/XU43DIR/aPKHOcgHxSonHuacsMfAUBW16/FBWG3 vd8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WEUJ3ZdOA9PTVRw0mKKElsPVyH1qTnSIppSOTeNDGHQ=; b=wNl/B+lF6y6XXWMNZ9uVpDAKlD1+CBvDkCiXltDKIHGhbmESvYtOIjYGm9Vl0uD5uM l3u5oUsGRG5kpV16mlKJW0tluo8G237aiFeu2Plt2ygSO2Oz0LEh+YQc07Yvs3DXjVLV PKOQPOrFB2knO1dRHlbz5KPs1XyJL2keMJbt/cr3tESp1qTlPYjkYgMh9NCr6/o+jwjh 73BZzvRQkoncQxhrsbvsYfR5AODLZsLvbiDrcDf94PziNSGZLLOcRkndSeAljGBLJq6R 1MbrGZBQappBDwDyRxkcXj0d0Saji7UZNXXqN6aGhcgn69VQ59fscGs7jI8kmGkoQm8/ IkgQ== X-Gm-Message-State: AOAM531CjgIulZA6Sp1NG3IGfXNr2DnNGQbEgaIum8Yeq2Vf2SYKmNr2 NcJ+dHUZqTTB+glVMa482CdTAVZdVXWpxQ== X-Google-Smtp-Source: ABdhPJxvi09bM1ZDWIS3IoNBW2ul4QypavttmFKPgBOBGV83Gkk8BGal72/WHNgEYltSwLw0VlwL0A== X-Received: by 2002:a17:903:11c7:b0:151:9769:3505 with SMTP id q7-20020a17090311c700b0015197693505mr7727181plh.72.1650217694204; Sun, 17 Apr 2022 10:48:14 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 51/60] target/arm: Implement virtual SError exceptions Date: Sun, 17 Apr 2022 10:44:17 -0700 Message-Id: <20220417174426.711829-52-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650221264473100001 Content-Type: text/plain; charset="utf-8" Virtual SError exceptions are raised by setting HCR_EL2.VSE, and are routed to EL1 just like other virtual exceptions. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v2: Honor EAE for reporting VSERR to aa32. --- target/arm/cpu.h | 2 ++ target/arm/internals.h | 8 ++++++++ target/arm/syndrome.h | 5 +++++ target/arm/cpu.c | 38 +++++++++++++++++++++++++++++++++++++- target/arm/helper.c | 40 +++++++++++++++++++++++++++++++++++++++- 5 files changed, 91 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a6d1923a78..b90b6d91bd 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -55,6 +55,7 @@ #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ +#define EXCP_VSERR 24 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ =20 #define ARMV7M_EXCP_RESET 1 @@ -88,6 +89,7 @@ enum { #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 +#define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 =20 /* The usual mapping for an AArch64 system register to its AArch32 * counterpart is for the 32 bit world to have access to the lower diff --git a/target/arm/internals.h b/target/arm/internals.h index baa2a7e1f4..2e55c9a8ae 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -935,6 +935,14 @@ void arm_cpu_update_virq(ARMCPU *cpu); */ void arm_cpu_update_vfiq(ARMCPU *cpu); =20 +/** + * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit + * + * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request, + * following a change to the HCR_EL2.VSE bit. + */ +void arm_cpu_update_vserr(ARMCPU *cpu); + /** * arm_mmu_idx_el: * @env: The cpu environment diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 8cde8e7243..0cb26dde7d 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -287,4 +287,9 @@ static inline uint32_t syn_pcalignment(void) return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; } =20 +static inline uint32_t syn_serror(uint32_t extra) +{ + return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra; +} + #endif /* TARGET_ARM_SYNDROME_H */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index fc0d74b4d1..20ae69e83b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -85,7 +85,7 @@ static bool arm_cpu_has_work(CPUState *cs) return (cpu->power_state !=3D PSCI_OFF) && cs->interrupt_request & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD - | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ + | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR | CPU_INTERRUPT_EXITTB); } =20 @@ -509,6 +509,12 @@ static inline bool arm_excp_unmasked(CPUState *cs, uns= igned int excp_idx, return false; } return !(env->daif & PSTATE_I); + case EXCP_VSERR: + if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { + /* VIRQs are only taken when hypervized. */ + return false; + } + return !(env->daif & PSTATE_A); default: g_assert_not_reached(); } @@ -630,6 +636,17 @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int i= nterrupt_request) goto found; } } + if (interrupt_request & CPU_INTERRUPT_VSERR) { + excp_idx =3D EXCP_VSERR; + target_el =3D 1; + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { + /* Taking a virtual abort clears HCR_EL2.VSE */ + env->cp15.hcr_el2 &=3D ~HCR_VSE; + cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); + goto found; + } + } return false; =20 found: @@ -682,6 +699,25 @@ void arm_cpu_update_vfiq(ARMCPU *cpu) } } =20 +void arm_cpu_update_vserr(ARMCPU *cpu) +{ + /* + * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. + */ + CPUARMState *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); + + bool new_state =3D env->cp15.hcr_el2 & HCR_VSE; + + if (new_state !=3D ((cs->interrupt_request & CPU_INTERRUPT_VSERR) !=3D= 0)) { + if (new_state) { + cpu_interrupt(cs, CPU_INTERRUPT_VSERR); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); + } + } +} + #ifndef CONFIG_USER_ONLY static void arm_cpu_set_irq(void *opaque, int irq, int level) { diff --git a/target/arm/helper.c b/target/arm/helper.c index f6468fed43..7e4178c594 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1864,7 +1864,12 @@ static uint64_t isr_read(CPUARMState *env, const ARM= CPRegInfo *ri) } } =20 - /* External aborts are not possible in QEMU so A bit is always clear */ + if (hcr_el2 & HCR_AMO) { + if (cs->interrupt_request & CPU_INTERRUPT_VSERR) { + ret |=3D CPSR_A; + } + } + return ret; } =20 @@ -5175,6 +5180,7 @@ static void do_hcr_write(CPUARMState *env, uint64_t v= alue, uint64_t valid_mask) g_assert(qemu_mutex_iothread_locked()); arm_cpu_update_virq(cpu); arm_cpu_update_vfiq(cpu); + arm_cpu_update_vserr(cpu); } =20 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) @@ -9325,6 +9331,7 @@ void arm_log_exception(CPUState *cs) [EXCP_LSERR] =3D "v8M LSERR UsageFault", [EXCP_UNALIGNED] =3D "v7M UNALIGNED UsageFault", [EXCP_DIVBYZERO] =3D "v7M DIVBYZERO UsageFault", + [EXCP_VSERR] =3D "Virtual SERR", }; =20 if (idx >=3D 0 && idx < ARRAY_SIZE(excnames)) { @@ -9837,6 +9844,31 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *c= s) mask =3D CPSR_A | CPSR_I | CPSR_F; offset =3D 4; break; + case EXCP_VSERR: + { + /* + * Note that this is reported as a data abort, but the DFAR + * has an UNKNOWN value. Construct the SError syndrome from + * AET and ExT fields. + */ + ARMMMUFaultInfo fi =3D { .type =3D ARMFault_AsyncExternal, }; + + if (extended_addresses_enabled(env)) { + env->exception.fsr =3D arm_fi_to_lfsc(&fi); + } else { + env->exception.fsr =3D arm_fi_to_sfsc(&fi); + } + env->exception.fsr |=3D env->cp15.vsesr_el2 & 0xd000; + A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); + qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x\n", + env->exception.fsr); + + new_mode =3D ARM_CPU_MODE_ABT; + addr =3D 0x10; + mask =3D CPSR_A | CPSR_I; + offset =3D 8; + } + break; case EXCP_SMC: new_mode =3D ARM_CPU_MODE_MON; addr =3D 0x08; @@ -10057,6 +10089,12 @@ static void arm_cpu_do_interrupt_aarch64(CPUState = *cs) case EXCP_VFIQ: addr +=3D 0x100; break; + case EXCP_VSERR: + addr +=3D 0x180; + /* Construct the SError syndrome from IDS and ISS fields. */ + env->exception.syndrome =3D syn_serror(env->cp15.vsesr_el2 & 0x1ff= ffff); + env->cp15.esr_el[new_el] =3D env->exception.syndrome; + break; default: cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); } --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650220171952362.16144257371; Sun, 17 Apr 2022 11:29:31 -0700 (PDT) Received: from localhost ([::1]:48346 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9eM-0005GY-ST for importer@patchew.org; Sun, 17 Apr 2022 14:29:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49734) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng90U-0004gc-OY for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:48:18 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:53771) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng90S-00045K-Kd for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:48:18 -0400 Received: by mail-pj1-x102d.google.com with SMTP id bx5so11322322pjb.3 for ; Sun, 17 Apr 2022 10:48:16 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id e14-20020aa78c4e000000b00506475da4cesm9372055pfd.49.2022.04.17.10.48.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:48:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zYEZAarhcV8VbvRrhZATBlBb0FycBEBDo1cg0e6bHok=; b=v9w9ZfsWI/2WgL1V2DeC4tQa3BRlHstrcoOpXegpv1ZZHoihPt6CUWGbq6V8iEx/we vT8eb//mBxmzxQMvNG/n3eiKxbuYstOLbjYXyhcQgLL5GmZest0LoXJkJRxQRwxpWgXp d7csZvBBM/lCCpLD5i8yB8XLq74YkkmALza1hm+0JDgKwjrnnfZgMHk1lm+an8n07nDH jTE5r2v16fYJ4OOKFvkTBi1TxeqAi/0q3tTp/4kgN5jupizHH3nnhH/tq1ASmiXi5msM shgi5Fk8rtoUnM6hLeGpIp4ey2AkemZketNZGCd4bw+FDDLcWBIfIUWF4URre5GRAKgp fP0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zYEZAarhcV8VbvRrhZATBlBb0FycBEBDo1cg0e6bHok=; b=VBCoiIllBqDJpy6k7OKiuqMIGyJlhGM2qsuykG17edayyYfHObUfJHwiOm0akd5qlh l/W23kq7bkNbrd3zaOLMh2ES3KoClWmnzyd7HAlNASTcLys3sahfkjEnoPgTQtfS7rib RWI4F/m0i37YEp2aRuhHQ2G8cIz/kifFRVOmfNRI8TL0+vQMp1JI1+OvGWlJgsn9wUFm fOMMZKVBzU1m0gpNCl5IxZtT6C8U6v2GtqF1FcDgQutcZ5zDYv1Tu+bgmbAuoetlg5PE Oxe1Lbci0fH36FVVNGeflWqmjX54Z1Jym2DhA1ulZTty20Lw4w2zn7k5ahaAv5XMbVhH 0lXQ== X-Gm-Message-State: AOAM532FRSlotRqSA+PdjrJmhNpmtK0LDTvTD7lCWHCAw5YysAYczhIg FPnSnAmtW4X93OXYhnPvwM5SEsu8jmAyoA== X-Google-Smtp-Source: ABdhPJzFMR7RZ7g/XBmYbFgPkCDn6ja4ZUhNW9Si1t+KewLGL5ijqL+KUz3lOGELxhrVsTi7BwyH+Q== X-Received: by 2002:a17:90a:e7cd:b0:1c7:acbd:215d with SMTP id kb13-20020a17090ae7cd00b001c7acbd215dmr9045455pjb.153.1650217695242; Sun, 17 Apr 2022 10:48:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 52/60] target/arm: Implement ESB instruction Date: Sun, 17 Apr 2022 10:44:18 -0700 Message-Id: <20220417174426.711829-53-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1650220174024100003 Content-Type: text/plain; charset="utf-8" Check for and defer any pending virtual SError. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Retain m-profile check; improve comments. --- target/arm/helper.h | 1 + target/arm/a32.decode | 16 ++++++++------ target/arm/t32.decode | 18 ++++++++-------- target/arm/op_helper.c | 43 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 17 +++++++++++++++ target/arm/translate.c | 23 ++++++++++++++++++++ 6 files changed, 103 insertions(+), 15 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index b463d9343b..b1334e0c42 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -54,6 +54,7 @@ DEF_HELPER_1(wfe, void, env) DEF_HELPER_1(yield, void, env) DEF_HELPER_1(pre_hvc, void, env) DEF_HELPER_2(pre_smc, void, env, i32) +DEF_HELPER_1(vesb, void, env) =20 DEF_HELPER_3(cpsr_write, void, env, i32, i32) DEF_HELPER_2(cpsr_write_eret, void, env, i32) diff --git a/target/arm/a32.decode b/target/arm/a32.decode index fcd8cd4f7d..f2ca480949 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -187,13 +187,17 @@ SMULTT .... 0001 0110 .... 0000 .... 1110 .= ... @rd0mn =20 { { - YIELD ---- 0011 0010 0000 1111 ---- 0000 0001 - WFE ---- 0011 0010 0000 1111 ---- 0000 0010 - WFI ---- 0011 0010 0000 1111 ---- 0000 0011 + [ + YIELD ---- 0011 0010 0000 1111 ---- 0000 0001 + WFE ---- 0011 0010 0000 1111 ---- 0000 0010 + WFI ---- 0011 0010 0000 1111 ---- 0000 0011 =20 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 - # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 + # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 + + ESB ---- 0011 0010 0000 1111 ---- 0001 0000 + ] =20 # The canonical nop ends in 00000000, but the whole of the # rest of the space executes as nop if otherwise unsupported. diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 78fadef9d6..f21ad0167a 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -364,17 +364,17 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .= ... @rdm [ # Hints, and CPS { - YIELD 1111 0011 1010 1111 1000 0000 0000 0001 - WFE 1111 0011 1010 1111 1000 0000 0000 0010 - WFI 1111 0011 1010 1111 1000 0000 0000 0011 + [ + YIELD 1111 0011 1010 1111 1000 0000 0000 0001 + WFE 1111 0011 1010 1111 1000 0000 0000 0010 + WFI 1111 0011 1010 1111 1000 0000 0000 0011 =20 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV 1111 0011 1010 1111 1000 0000 0000 0100 - # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1111 0011 1010 1111 1000 0000 0000 0100 + # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 =20 - # For M-profile minimal-RAS ESB can be a NOP, which is the - # default behaviour since it is in the hint space. - # ESB 1111 0011 1010 1111 1000 0000 0001 0000 + ESB 1111 0011 1010 1111 1000 0000 0001 0000 + ] =20 # The canonical nop ends in 0000 0000, but the whole rest # of the space is "reserved hint, behaves as nop". diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 76499ffa14..390b6578a8 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -960,3 +960,46 @@ void HELPER(probe_access)(CPUARMState *env, target_ulo= ng ptr, access_type, mmu_idx, ra); } } + +/* + * This function corresponds to AArch64.vESBOperation(). + * Note that the AArch32 version is not functionally different. + */ +void HELPER(vesb)(CPUARMState *env) +{ + /* + * The EL2Enabled() check is done inside arm_hcr_el2_eff, + * and will return HCR_EL2.VSE =3D=3D 0, so nothing happens. + */ + uint64_t hcr =3D arm_hcr_el2_eff(env); + bool enabled =3D !(hcr & HCR_TGE) && (hcr & HCR_AMO); + bool pending =3D enabled && (hcr & HCR_VSE); + bool masked =3D (env->daif & PSTATE_A); + + /* If VSE pending and masked, defer the exception. */ + if (pending && masked) { + uint32_t syndrome; + + if (arm_el_is_aa64(env, 1)) { + /* Copy across IDS and ISS from VSESR. */ + syndrome =3D env->cp15.vsesr_el2 & 0x1ffffff; + } else { + ARMMMUFaultInfo fi =3D { .type =3D ARMFault_AsyncExternal }; + + if (extended_addresses_enabled(env)) { + syndrome =3D arm_fi_to_lfsc(&fi); + } else { + syndrome =3D arm_fi_to_sfsc(&fi); + } + /* Copy across AET and ExT from VSESR. */ + syndrome |=3D env->cp15.vsesr_el2 & 0xd000; + } + + /* Set VDISR_EL2.A along with the syndrome. */ + env->cp15.vdisr_el2 =3D syndrome | (1u << 31); + + /* Clear pending virtual SError */ + env->cp15.hcr_el2 &=3D ~HCR_VSE; + cpu_reset_interrupt(env_cpu(env), CPU_INTERRUPT_VSERR); + } +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 98dbc8203f..fc0b3ebf44 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1454,6 +1454,23 @@ static void handle_hint(DisasContext *s, uint32_t in= sn, gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); } break; + case 0b10000: /* ESB */ + /* Without RAS, we must implement this as NOP. */ + if (dc_isar_feature(aa64_ras, s)) { + /* + * QEMU does not have a source of physical SErrors, + * so we are only concerned with virtual SErrors. + * The pseudocode in the ARM for this case is + * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then + * AArch64.vESBOperation(); + * Most of the condition can be evaluated at translation time. + * Test for EL2 present, and defer test for SEL2 to runtime. + */ + if (s->current_el <=3D 1 && arm_dc_feature(s, ARM_FEATURE_EL2)= ) { + gen_helper_vesb(cpu_env); + } + } + break; case 0b11000: /* PACIAZ */ if (s->pauth_active) { gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], diff --git a/target/arm/translate.c b/target/arm/translate.c index 9370b44707..fef7ccea5c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6236,6 +6236,29 @@ static bool trans_WFI(DisasContext *s, arg_WFI *a) return true; } =20 +static bool trans_ESB(DisasContext *s, arg_ESB *a) +{ + /* + * For M-profile, minimal-RAS ESB can be a NOP. + * Without RAS, we must implement this as NOP. + */ + if (!arm_dc_feature(s, ARM_FEATURE_M) && dc_isar_feature(aa32_ras, s))= { + /* + * QEMU does not have a source of physical SErrors, + * so we are only concerned with virtual SErrors. + * The pseudocode in the ARM for this case is + * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then + * AArch32.vESBOperation(); + * Most of the condition can be evaluated at translation time. + * Test for EL2 present, and defer test for SEL2 to runtime. + */ + if (s->current_el <=3D 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) { + gen_helper_vesb(cpu_env); + } + } + return true; +} + static bool trans_NOP(DisasContext *s, arg_NOP *a) { return true; --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650220376813486.7101454256896; Sun, 17 Apr 2022 11:32:56 -0700 (PDT) Received: from localhost ([::1]:57268 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9hf-0002wB-QS for importer@patchew.org; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id e14-20020aa78c4e000000b00506475da4cesm9372055pfd.49.2022.04.17.10.48.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:48:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ROdZ8Y/MGQK0am4sMfTHzXw787CsxnIyvG7dCwMmzsg=; b=eji1jbkEL0wsoKqW8CX+3Da7Ve/88N1ePhPItro9WfnLubvEIz+dJYqHw1J2WD3XPP sG0h5XLLr7y5YlzU61WktWnIqc3z2+I+VhZcEr+ECXlz6bqnBZ0Il0ndDRTLzJOkSCm4 6DWDXA7cRsgsraW5XunzgtvN+2HRAZS64R990FpihsBjb63DWNY/n5WaMNpomc/gaksi /l50pruFaEVy8Tfwa7z+RxNxnb+O0Bu2q9IJSUMYLhSfBTPobcr+U+GaW5u0IA+NOye6 4+Kq7X/gA7VlzCSIvD25YUhfuf1X1HJQWu0B0RSIILBZnrmHZgISvhH6MqAwKtGYU9/j cl0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1650220378950100003 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update emulation.rst --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 1 + 3 files changed, 3 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index c89c344de1..35b6f7d4de 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -41,6 +41,7 @@ the following architecture extensions: - FEAT_PMULL (PMULL, PMULL2 instructions) - FEAT_PMUv3p1 (PMU Extensions v3.1) - FEAT_PMUv3p4 (PMU Extensions v3.4) +- FEAT_RAS (Reliability, availability, and serviceability) - FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions) - FEAT_RNG (Random number generator) - FEAT_SB (Speculation Barrier) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 136590382a..72fe7885f0 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -744,6 +744,7 @@ static void aarch64_max_initfn(Object *obj) t =3D cpu->isar.id_aa64pfr0; t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, RAS, 1); /* FEAT_RAS */ t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 337598e949..c5cf7efe95 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -69,6 +69,7 @@ void aa32_max_features(ARMCPU *cpu) =20 t =3D cpu->isar.id_pfr0; t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ + t =3D FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ cpu->isar.id_pfr0 =3D t; =20 t =3D cpu->isar.id_pfr2; --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id e14-20020aa78c4e000000b00506475da4cesm9372055pfd.49.2022.04.17.10.48.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:48:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DoRumaxtRe3qsin4W3djn/6A+2lT9q58rZZ6KjoMUec=; b=jmlC4sOqvOtfOzkh6swWRWx8MeweAKGvhFO4hOjhRwDyYr4nlxBTYFGudoMQyO6zCQ GjRIxl5kH+SNWL4B2fPPgh0Z8JGwCL9PdjbFy5evEOL4ByzNH1Yx2T1DFdsJlqVwpKVR UfhcTMs1HZ6MWJ8jT0xNL5D8uKv+FK7f2VbZwUmVmrv4kmIa4/7kB3GwlVRFaGccgcQW 4M4zU9xZwkS8yMB4sQ/QgAnhGSl6e7gqF+cnhj3Rbp2Wb3juuJJxtar1SkhBAEbkgdyM 1M3azCIR4m0x8Uz3tDYyvoFRXWVBF/MXEZD53ljpPK9xahQNrHLsp/hT+W/LsRRnkj1O wlfg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DoRumaxtRe3qsin4W3djn/6A+2lT9q58rZZ6KjoMUec=; b=pieT3mhiKDcXlsx/L+EUgNYCDHvj++QgJhDA3PVPzRngkBkgza+7/IMDZJ2jc862RK htyIdCBqi5imzvRX1kajYDqFzFws6zIav2FsdHPsGXgQTnOzn7fAhIvNeVImCsGySdAc 1Pu40G0VguxjwaOxuxmJ1vIAS4+9jD44lyZHlTMyD4rV65CztnC96kZ/36e3KPTF61DW 7po6pOn8WnT5KlSStR/l1DkOvUIKbb3EtP58xbqxtj22sN6aKwexNablbl6QsxmO7rTW 8ynlzfueH5DElKCTunUZ0YNIKes6t4io7uDbVNiBLPOLbFwWB8Bhs1tUWc54ruQUczW2 rQoQ== X-Gm-Message-State: AOAM532WBm32okQPaxSvLGDHJCun8Mx+MbSPT4oixo/hX+L45GCAAnCV FTV4aSpHYBGWAk91d72bXU+uFSpHdn7xSA== X-Google-Smtp-Source: ABdhPJwIV27XMrPEilKMRIAvCsXx4CPYmK1lhUp3dQvumb5j0frpFTQz5ErhdRR+HDZnUsCf8qa6Tg== X-Received: by 2002:a17:90b:3806:b0:1d2:6e95:f5cc with SMTP id mq6-20020a17090b380600b001d26e95f5ccmr6507650pjb.23.1650217696971; Sun, 17 Apr 2022 10:48:16 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 54/60] target/arm: Enable FEAT_IESB for -cpu max Date: Sun, 17 Apr 2022 10:44:20 -0700 Message-Id: <20220417174426.711829-55-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1650221541547100001 Content-Type: text/plain; charset="utf-8" This feature is AArch64 only, and applies to physical SErrors, which QEMU does not implement, thus the feature is a nop. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update emulation.rst --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + 2 files changed, 2 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 35b6f7d4de..ebd9e418cc 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -24,6 +24,7 @@ the following architecture extensions: - FEAT_FlagM2 (Enhancements to flag manipulation instructions) - FEAT_HPDS (Hierarchical permission disables) - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions) +- FEAT_IESB (Implicit error synchronization event) - FEAT_JSCVT (JavaScript conversion instructions) - FEAT_LOR (Limited ordering regions) - FEAT_LPA (Large Physical Address space) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 72fe7885f0..03fbb34e4e 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -781,6 +781,7 @@ static void aarch64_max_initfn(Object *obj) t =3D cpu->isar.id_aa64mmfr2; t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ t =3D FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ cpu->isar.id_aa64mmfr2 =3D t; --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650220977261401.52810691882894; Sun, 17 Apr 2022 11:42:57 -0700 (PDT) Received: from localhost ([::1]:48954 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9rK-00083U-Ap for importer@patchew.org; Sun, 17 Apr 2022 14:42:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49828) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng90W-0004jW-VW for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:48:21 -0400 Received: from mail-pg1-x534.google.com ([2607:f8b0:4864:20::534]:44613) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng90V-00046C-3d for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:48:20 -0400 Received: by mail-pg1-x534.google.com with SMTP id j71so1451371pge.11 for ; Sun, 17 Apr 2022 10:48:18 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id e14-20020aa78c4e000000b00506475da4cesm9372055pfd.49.2022.04.17.10.48.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:48:17 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4gebW4IdC/Bc62zWIHS5hydZkGTIlOLeMNTIUwSy2Ks=; b=CetYLbkrh2Emx4+viVrzNk2w06xK1Rh0zkQV/5RcLrJr2HpgyqKgR2xAFCrHXBm9Gh +xQKrxnGaTeocMQFYsn3+hpAl7IcOwCf+UVpYqGx9ENdsRGW3jxvAowQ5kDSIGKpIXBR VyGYdVEyzu1PZ2H/yOsov+XnQD7ChckHXaAvPFhdaAZsd9cGgY3OVVaeI61kqjqmkPrh zLGbLpSyXEdlXBTCEeWU+mBJ6c79GjO7UeonwJ1DCdREvt0Ld1TGAd23smVc6FDjxkqa jcw3M1m8gACwiH5M/+cB/9IVva5br17T8TFx5booqwz4Mfia9yyBfT8ayioPzYWpt6Sj hRlg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4gebW4IdC/Bc62zWIHS5hydZkGTIlOLeMNTIUwSy2Ks=; b=wKp2vN4mxp6dF1aAFtQWptqFJOgzROXfy2NIfDJ+oU4HLklJAjWKvLsLEVtB4NvQ2Z Xe/JPS62Hwbr30BEWnYFnxNwUjHLH9kOB1hMLJ38m4SWRjmn8ROoAxHW5qymwOuD/t65 ds8n9mEXoo2H42j71wAGUtPfAXK3479IeML1xbJuINNBDxfwlgpwe3yfpqeOsJVBps7g 3rCCjDQFCBHpBEzZzLYNAVy1KZArcSBEz8gA/Lm4auwWfJOog+w937h+l70N8lkj9TDy bDp3HYJPc69MpV9ljePP3bZIRttmx6CNkpRkFIRM/jmp4YioTX8p1919WMm1Iv4Aw258 IQOQ== X-Gm-Message-State: AOAM531TqTge3/Aetst0lqyt37NneKgM9njzze2hWxWFQc1w8Sm4QrP4 Hk/7+3MrTJZHN/ZyFaD1WRVSPFJOKlFxnw== X-Google-Smtp-Source: ABdhPJz/fyNwMOOCljTOwKeqawBHV+rfVTn4SD1hmL6kGH7RnhOArjakyc8KbIV0vPebbEgymrtjCQ== X-Received: by 2002:a05:6a00:8c5:b0:4fe:134d:30d3 with SMTP id s5-20020a056a0008c500b004fe134d30d3mr8405509pfu.3.1650217697790; Sun, 17 Apr 2022 10:48:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 55/60] target/arm: Enable FEAT_CSV2 for -cpu max Date: Sun, 17 Apr 2022 10:44:21 -0700 Message-Id: <20220417174426.711829-56-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::534; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x534.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1650220979224100002 Content-Type: text/plain; charset="utf-8" This extension concerns branch speculation, which TCG does not implement. Thus we can trivially enable this feature. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update emulation.rst --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 1 + 3 files changed, 3 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index ebd9e418cc..91fb06c579 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -11,6 +11,7 @@ the following architecture extensions: - FEAT_AES (AESD and AESE instructions) - FEAT_BF16 (AArch64 BFloat16 instructions) - FEAT_BTI (Branch Target Identification) +- FEAT_CSV2 (Cache speculation variant 2) - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) - FEAT_Debugv8p2 (Debug changes for v8.2) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 03fbb34e4e..b62656f3c3 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -748,6 +748,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ + t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */ cpu->isar.id_aa64pfr0 =3D t; =20 t =3D cpu->isar.id_aa64pfr1; diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index c5cf7efe95..762b961707 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -68,6 +68,7 @@ void aa32_max_features(ARMCPU *cpu) cpu->isar.id_mmfr4 =3D t; =20 t =3D cpu->isar.id_pfr0; + t =3D FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */ t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ t =3D FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ cpu->isar.id_pfr0 =3D t; --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650220627; cv=none; d=zohomail.com; s=zohoarc; b=hEUaKZGkxslT7k3dQwKZHqkFXbzp0H9yAlvV1B7YO+OK+anD0Cw+3LvV/zL1EwaLppdN04MsofI9vmbH1/EsmKeLIUJ5tvW3tYNtez4ijRW9t0hoqevgUSEH/uSFwAJUdF9Ls2UWvGtbS0XfvCdTZ3X460827+H9PmtPxwMqPrk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650220627; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=tg97pAzl6c8fQ/INZXGM16Pyz/AbXSyAlqpVeNxoRMU=; b=OiHPE9XIV7lvDTLxDy/W7vGqVkBD2Etsd6RAuE2Gq+DJX6MTjjHOG8eK5Xu0D++L7l9tGwhD+oSBMQ/0rj9F3Ixh8F/vPH2XWH+bSw7ht5tMtztTWcuk7ryoVHZHVQzGwBeHJE8Ra2sE1j3uEiBSdmS+IC213wnS89fjaTEf3cM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650220627903327.28672514712; Sun, 17 Apr 2022 11:37:07 -0700 (PDT) Received: from localhost ([::1]:38906 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9li-0001EN-Kr for importer@patchew.org; Sun, 17 Apr 2022 14:37:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49866) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng90X-0004kt-Og for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:48:21 -0400 Received: from mail-pj1-x1035.google.com ([2607:f8b0:4864:20::1035]:52114) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng90V-00046c-Ps for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:48:21 -0400 Received: by mail-pj1-x1035.google.com with SMTP id bg24so11340804pjb.1 for ; Sun, 17 Apr 2022 10:48:19 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id e14-20020aa78c4e000000b00506475da4cesm9372055pfd.49.2022.04.17.10.48.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:48:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tg97pAzl6c8fQ/INZXGM16Pyz/AbXSyAlqpVeNxoRMU=; b=RmAFVP8t2BZ3/Cg/otdBUbyo2kR5iHJiQLLbA32jJOgbJMLGq0QPxuo6ScgdFDwm8X TFoNDttTlTZaZvI0A8lmlUXWkvCZf03Aa/H/ECYj4LtL1fHt9ATZsum5ZlgokTyBWg1s IFxIyDXnuTHG2zwsEqTc4wYuwt2Lnk/qbPNGgNuSMrzkApgfUlljzN+Cd8dSGdWAYbXP mzcMY+yDD81PjJiczZkTw77b6tl1KDJLp9+dK0ASfjODoDNWmJiGQQP1vGeS1MqEx/CD IERE4/2L3dLudWVTe1Oemdi2mGDYh3nQkJw2ykj9wVdg/WeUEZgAtMvpj5Ft8Bzo+c4F y5Tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tg97pAzl6c8fQ/INZXGM16Pyz/AbXSyAlqpVeNxoRMU=; b=0rJkKPNV29EfrGQt+tFg5c9eId6VLEx7ysAybf7f9ny5zW4KMRipH4vMsxnxRVQ7r6 Ck6juPwSQRG3/GmnGMegjOnxOAUASxkXpTCKgWb+3DQenqmJl8fC7sVQPx/Yh/s8aqGH o72Z3MFdjheRbknOk+h/7WD3yxe1tjuKhBecHpKy9GNiHL5yGSBibkDGF28s6eew8cY9 4sqbPTY3ZFeT2ztKBvBUD/gr6AuR5i8YrF9fYvN2FsF4KBhnd9kNKqMmweEH68ht2svZ yio6odCAKDDTTzysAzNPy2Yf6MUA6g2d1ZRC6TG5lDr1i1CkHRVLVBLWiTPhs5N+ZuAw rnRQ== X-Gm-Message-State: AOAM531T3JfXf9FQVhzFMzA3ARJb231uce8a4FjsWxoeOeKzuX0wOKum 2Uw/YDx8Et4+ZSPrIqJ2/UOTAMXfA+W/9Q== X-Google-Smtp-Source: ABdhPJxDnJP8VWBasPNLMtUuJjvrJQj6kTq4bf/fNrGgkZMH6NPReNofbv+UKRiR/CMCDLBbypN7mg== X-Received: by 2002:a17:90b:1e49:b0:1d2:9d82:8bb1 with SMTP id pi9-20020a17090b1e4900b001d29d828bb1mr1224747pjb.226.1650217698502; Sun, 17 Apr 2022 10:48:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 56/60] target/arm: Enable FEAT_CSV2_2 for -cpu max Date: Sun, 17 Apr 2022 10:44:22 -0700 Message-Id: <20220417174426.711829-57-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650220629831100003 Content-Type: text/plain; charset="utf-8" There is no branch prediction in TCG, therefore there is no need to actually include the context number into the predictor. Therefore all we need to do is add the state for SCXTNUM_ELx. Signed-off-by: Richard Henderson --- v2: Update emulation.rst; clear CSV2_FRAC; use decimal; tidy access_scxtnum. v3: Rely on EL3-no-EL2 squashing during registration. --- docs/system/arm/emulation.rst | 3 ++ target/arm/cpu.h | 16 +++++++++ target/arm/cpu64.c | 3 +- target/arm/helper.c | 66 ++++++++++++++++++++++++++++++++++- 4 files changed, 86 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 91fb06c579..aebe3be1ba 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -12,6 +12,9 @@ the following architecture extensions: - FEAT_BF16 (AArch64 BFloat16 instructions) - FEAT_BTI (Branch Target Identification) - FEAT_CSV2 (Cache speculation variant 2) +- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) +- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) +- FEAT_CSV2_2 (Cache speculation variant 2, version 2) - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) - FEAT_Debugv8p2 (Debug changes for v8.2) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b90b6d91bd..a7582da7c2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -687,6 +687,8 @@ typedef struct CPUArchState { ARMPACKey apdb; ARMPACKey apga; } keys; + + uint64_t scxtnum_el[4]; #endif =20 #if defined(CONFIG_USER_ONLY) @@ -1210,6 +1212,7 @@ void pmu_init(ARMCPU *cpu); #define SCTLR_WXN (1U << 19) #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ +#define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ @@ -4021,6 +4024,19 @@ static inline bool isar_feature_aa64_dit(const ARMIS= ARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) !=3D 0; } =20 +static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) +{ + int key =3D FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); + if (key >=3D 2) { + return true; /* FEAT_CSV2_2 */ + } + if (key =3D=3D 1) { + key =3D FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); + return key >=3D 2; /* FEAT_CSV2_1p2 */ + } + return false; +} + static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) !=3D 0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index b62656f3c3..6ccbcb857d 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -748,7 +748,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ - t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ cpu->isar.id_aa64pfr0 =3D t; =20 t =3D cpu->isar.id_aa64pfr1; @@ -760,6 +760,7 @@ static void aarch64_max_initfn(Object *obj) * we do for EL2 with the virtualization=3Don property. */ t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ + t =3D FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ cpu->isar.id_aa64pfr1 =3D t; =20 t =3D cpu->isar.id_aa64mmfr0; diff --git a/target/arm/helper.c b/target/arm/helper.c index 7e4178c594..22728b9fbf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1771,6 +1771,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_mte, cpu)) { valid_mask |=3D SCR_ATA; } + if (cpu_isar_feature(aa64_scxtnum, cpu)) { + valid_mask |=3D SCR_ENSCXT; + } } else { valid_mask &=3D ~(SCR_RW | SCR_ST); if (cpu_isar_feature(aa32_ras, cpu)) { @@ -5149,6 +5152,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t v= alue, uint64_t valid_mask) if (cpu_isar_feature(aa64_mte, cpu)) { valid_mask |=3D HCR_ATA | HCR_DCT | HCR_TID5; } + if (cpu_isar_feature(aa64_scxtnum, cpu)) { + valid_mask |=3D HCR_ENSCXT; + } } =20 /* Clear RES0 bits. */ @@ -5798,6 +5804,10 @@ static void define_arm_vh_e2h_redirects_aliases(ARMC= PU *cpu) { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0), "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte }, =20 + { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7), + "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12", + isar_feature_aa64_scxtnum }, + /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ }; @@ -7233,7 +7243,57 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = =3D { }, }; =20 -#endif +static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo = *ri, + bool isread) +{ + int el =3D arm_current_el(env); + + if (el =3D=3D 0) { + uint64_t hcr =3D arm_hcr_el2_eff(env); + if ((hcr & (HCR_TGE | HCR_E2H)) !=3D (HCR_TGE | HCR_E2H)) { + if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) { + if (hcr & HCR_TGE) { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_TRAP; + } + if (arm_is_el2_enabled(env) && !(hcr & HCR_ENSCXT)) { + return CP_ACCESS_TRAP_EL2; + } + goto no_sctlr_el2; + } + } + if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) { + return CP_ACCESS_TRAP_EL2; + } + no_sctlr_el2: + if (el < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_ENSCXT)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo scxtnum_reginfo[] =3D { + { .name =3D "SCXTNUM_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, + .access =3D PL0_RW, .accessfn =3D access_scxtnum, + .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[0]) }, + { .name =3D "SCXTNUM_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, + .access =3D PL1_RW, .accessfn =3D access_scxtnum, + .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[1]) }, + { .name =3D "SCXTNUM_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, + .access =3D PL2_RW, .accessfn =3D access_scxtnum, + .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[2]) }, + { .name =3D "SCXTNUM_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, + .access =3D PL3_RW, + .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[3]) }, +}; +#endif /* TARGET_AARCH64 */ =20 static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo = *ri, bool isread) @@ -8372,6 +8432,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, mte_tco_ro_reginfo); define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); } + + if (cpu_isar_feature(aa64_scxtnum, cpu)) { + define_arm_cp_regs(cpu, scxtnum_reginfo); + } #endif =20 if (cpu_isar_feature(any_predinv, cpu)) { --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650220955441216.00342378713094; Sun, 17 Apr 2022 11:42:35 -0700 (PDT) Received: from localhost ([::1]:48744 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9r0-0007uz-5h for importer@patchew.org; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id e14-20020aa78c4e000000b00506475da4cesm9372055pfd.49.2022.04.17.10.48.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:48:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ra+HmlDmjq5MC1Bo0b0qUr7KsvywnTjoaMfVjleqeaE=; b=B5l28oZWCEaPX16JktO6lmO5Gg+6b++FQW/pRoaRiT3pmR6WbHSzmdhBF+JcFoPxJr e4vHea6LIEz+69Sy3oc8QKdn9L7hHrFX1P/jCRd3TTgEw2bIlX1jpt0zifUSQFqFd19d bbmZMNxPF7ahYoS1D8Ddnlf/hTa9Rz6/og4nRprVGnr53qWweEymRp9CAb0ieU7oFwxh d5aYOR0j8IMm5OR+FOfWowNE52DlkiorhYmwq4RU1o9UxCl8PSERY+dPona7/mLPpFlY 4xJgt/HjTLncszBMkEVBgS4BsR100Rmn6qOyRe7SE/jdQZs/bMzjG7veCpZcqFY8sSRG T38w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ra+HmlDmjq5MC1Bo0b0qUr7KsvywnTjoaMfVjleqeaE=; b=gvN9y5M8B4ChxLS5KNS+mOGkdDNBJuFd6MELJL+xIyOyWny0YLYOmfH69ajslzl/DP WvijPzUW+hOpsJGhz6e8rGZHvGJCiJEO3N69Wwnbw3lFkvpuihxArBj4bj0f4zuI3prq MAImwFz+WLJg9bKThIgwDlrE3sADNheUAJMn5mO+6doIkKPxn5XKT+Is4F1zSReiGLSK 067UdstJqac36fuKghdSIgGlPsWJzQYsJR9w1dXs8r/yZv2EBqC1vtUoQtZL86EL7N0T ddz6q6X+nAFNPaFquwL4oMAQ/YKWtg9Nz3BqrbI1N6sIiKSYK/e8HMdJ7cMPp50Fsgdc OP1Q== X-Gm-Message-State: AOAM533qKR1oojcpuZWqhCyq8b6HzasNMy0UPFQvoZv6oseBf88WJJm9 LhvbiMTkqZASNO0HeX6/y2LN3nR27ZAcRw== X-Google-Smtp-Source: ABdhPJwvzgIc0n5lqFqm9ZNqNwnhmldHHPIUtbElFcBImJiP+CtRq/k0J9HvPuJy+61bTkx4G0FJqQ== X-Received: by 2002:a17:90b:390d:b0:1d2:7a7d:170e with SMTP id ob13-20020a17090b390d00b001d27a7d170emr5351329pjb.230.1650217699222; Sun, 17 Apr 2022 10:48:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 57/60] target/arm: Enable FEAT_CSV3 for -cpu max Date: Sun, 17 Apr 2022 10:44:23 -0700 Message-Id: <20220417174426.711829-58-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1650220957215100001 Content-Type: text/plain; charset="utf-8" This extension concerns cache speculation, which TCG does not implement. Thus we can trivially enable this feature. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update emulation.rst --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 1 + 3 files changed, 3 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index aebe3be1ba..f75f0fc110 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -15,6 +15,7 @@ the following architecture extensions: - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) - FEAT_CSV2_2 (Cache speculation variant 2, version 2) +- FEAT_CSV3 (Cache speculation variant 3) - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) - FEAT_Debugv8p2 (Debug changes for v8.2) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 6ccbcb857d..6139f51267 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -749,6 +749,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ cpu->isar.id_aa64pfr0 =3D t; =20 t =3D cpu->isar.id_aa64pfr1; diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 762b961707..ea4eccddc3 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -74,6 +74,7 @@ void aa32_max_features(ARMCPU *cpu) cpu->isar.id_pfr0 =3D t; =20 t =3D cpu->isar.id_pfr2; + t =3D FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */ t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ cpu->isar.id_pfr2 =3D t; =20 --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165022147409127.75168708223339; Sun, 17 Apr 2022 11:51:14 -0700 (PDT) Received: from localhost ([::1]:41734 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ng9zM-0005KM-8O for importer@patchew.org; Sun, 17 Apr 2022 14:51:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49936) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng90a-0004nv-Ny for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:48:24 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]:33624) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng90X-000478-4a for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:48:22 -0400 Received: by mail-pg1-x536.google.com with SMTP id k14so14994481pga.0 for ; Sun, 17 Apr 2022 10:48:20 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id e14-20020aa78c4e000000b00506475da4cesm9372055pfd.49.2022.04.17.10.48.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:48:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7bwI399xmkYMZYOeiF66UP7rD5My88v054sfcO3BxLg=; b=zzb2qRTpQv5YOaWzGfE0jQkLcnBU+zDntc/eh/oowf/cKflXehA6hIbAtaFYICsHiY jR6w3MTb8AHbOEKJ9wRx8/LNe0ZeA2+G/UtjZMtL0CBwXoqMWferVNOOWJPU9D23yt2g NyEy7E2BE8ICudIycjncU36WJF+K/sZ6dxSU/J0cdvXQIASElqfqTWf8DfCsoG0u9yUJ QsJuMu+CDpz2HokuqofJokUNwlaasnnvy8ZORdqlBo3xLhNYazh2VQda6v72JW5XRalj 9/l6sy1eD75ZFAMlL+0kE2kssvvCR9fq79qqo85hp0JB8EV8Vs5dVus672lTiFafEmii dUSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7bwI399xmkYMZYOeiF66UP7rD5My88v054sfcO3BxLg=; b=BGb+7sZ3XuQdNQ/Husr2ABXPoUlS8Gc+6YQzkBG5gytnGN8fHJL4Ap2rFzvaoYslyD 1WMJaVrpBfTi6keHuUtUaSaCXn/8vT7t0wJAi6uXSvSNPgWNWcOtC6q1Olj7YQ7k5So4 Cu0237b6rCxli1Irq2rlbA5ZY/tvJT/CwXbdlfyOxfb9vp6TWF3FV6+/cR8gq3LKh6Ix p2TqYVREvbfRWPC4j6dBHaAJECFzdrQLDpNMAc57CMXgH4W585U+w7GTW4yZswQczGRA ex40aSunByRq3MsrHJqE0cY8kGdbwUyjo3WWu0E+9RY965oFVb+mDuhdfk4DYUj7XMFT rCgQ== X-Gm-Message-State: AOAM532V9zA6a8zSgpn+xzPZyHRjhpwkGg3Hx1ggkScy/Mc1Ebvvn7zA wFAdwzxJJ4RoF0kBbooo+WbR6Tlc7NWzLg== X-Google-Smtp-Source: ABdhPJwjhej7vM/4pMjYvlT4Tylq6UTCFOqJhtFl8wMMJ3eD5u7N2jHIm2Sv5nbiySjUqwM1ZEV8Bg== X-Received: by 2002:aa7:8a06:0:b0:506:28c:1282 with SMTP id m6-20020aa78a06000000b00506028c1282mr8418956pfa.19.1650217699937; Sun, 17 Apr 2022 10:48:19 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 58/60] target/arm: Enable FEAT_DGH for -cpu max Date: Sun, 17 Apr 2022 10:44:24 -0700 Message-Id: <20220417174426.711829-59-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1650221475119100001 Content-Type: text/plain; charset="utf-8" This extension concerns not merging memory access, which TCG does not implement. Thus we can trivially enable this feature. Add a comment to handle_hint for the DGH instruction, but no code. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update emulation.rst --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + target/arm/translate-a64.c | 1 + 3 files changed, 3 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index f75f0fc110..bc9cdda75a 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -16,6 +16,7 @@ the following architecture extensions: - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) - FEAT_CSV2_2 (Cache speculation variant 2, version 2) - FEAT_CSV3 (Cache speculation variant 3) +- FEAT_DGH (Data gathering hint) - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) - FEAT_Debugv8p2 (Debug changes for v8.2) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 6139f51267..336a941acd 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -738,6 +738,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ cpu->isar.id_aa64isar1 =3D t; =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index fc0b3ebf44..b44ab3ecf3 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1427,6 +1427,7 @@ static void handle_hint(DisasContext *s, uint32_t ins= n, break; case 0b00100: /* SEV */ case 0b00101: /* SEVL */ + case 0b00110: /* DGH */ /* we treat all as NOP at least for now */ break; case 0b00111: /* XPACLRI */ --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1650221695; cv=none; d=zohomail.com; s=zohoarc; b=IMh0z6u6a9fkla62073DhOqJpYTVl14WPI3w3OulfdiWjrC5ktHaUv7MPiANeIwPmYvZ4utzTckCyrg7zaTpX2Xvq7JjAQcY39O9I6RLG7RQQ8EyTO0X1ovbjG05bBi9P0dJfGfY6X/aV5W/I4hutGvqeSx6eHVP6KAe0Y821Rg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1650221695; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AWChTNub/svxMafWwyMDKgs1ZSDrVWcoRccpdVr6IWk=; b=DbWW7wZ16T3OFNp6TBLfBD6+3aCnPho9eJRzoWTELZ583OT6VCKrnFnifY0HZJ8mFqBsgvy/YNN0Kfog+OX/IY4VcmlV53CUVIPwiK7T2kHFVcC2D4OagLjxm6yoYEYT0S1rKGgxddgxYIZpOYL5LKlc7MwUumxSNPIqVLHY+MI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650221695487166.6842203599756; Sun, 17 Apr 2022 11:54:55 -0700 (PDT) Received: from localhost ([::1]:53626 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ngA2w-0004vZ-Bf for importer@patchew.org; Sun, 17 Apr 2022 14:54:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49934) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ng90a-0004nu-NY for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:48:24 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:38754) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ng90Y-00047S-5e for qemu-devel@nongnu.org; Sun, 17 Apr 2022 13:48:23 -0400 Received: by mail-pj1-x1031.google.com with SMTP id s14-20020a17090a880e00b001caaf6d3dd1so15528820pjn.3 for ; Sun, 17 Apr 2022 10:48:21 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id e14-20020aa78c4e000000b00506475da4cesm9372055pfd.49.2022.04.17.10.48.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:48:20 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=AWChTNub/svxMafWwyMDKgs1ZSDrVWcoRccpdVr6IWk=; b=MNvTwov8M7uHpW448lDUcuAo0h2kyuhJjIm5LWpKDNQdrzlCVDHGMEJeb2YnyPY3Uk m6OvjlpiU0PblON0aIFv1tf4AGB6BIKBzNatt1XFL2Myw5pTQSUlVPmpe18dS3g4MDAv 3D9eQ8iZjtBIzI9hcJkvl0SUHL96aB9qUzmifDE2BNK3rak7dspxjYTGeJAiSfS6/6w0 J5xbbhI7G9c9PMb/47rqBlEH1W7+OB3l45sjmRKGjzhaPtePEVo3a1lDpU92VF8m1Y0L BrkWbXYsNM98qpBNoDnn0N318Z0LolmEsK+Q9BectnRHZYA0Q2U7WvvTj44pfCWqfA85 4+JQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AWChTNub/svxMafWwyMDKgs1ZSDrVWcoRccpdVr6IWk=; b=EnztyQsyxRoAvnljS5HUDWAVVHfaQ0Rmf3rcqt3owEhY1FzttXXDyUQLMCw2l4b7G/ L4+guERgctQnt1u/JekLOPV2DYWhVMwVm2J0Cemn23DMRv9df7fTwCVBDIJLKPWgsdaA JSe8/zghaVMqZe4zCZBf4/hcG1VYM2Pri3GquXJtz94IN9JJ0uQry6dEMjRP7I8KdPp/ p4HoOAg1DlGSZLfemZJOklC08TEn/JmjBUuUtWX5eK3BU7cXCF2h1jrBkZKzKLVl16AC Vh3LyD/7aDHRappGsPPkLwmzIP2WEPhZG+FQGrfOlEORcK+KEvBvutqaZsQS+xFX1m2R qbrg== X-Gm-Message-State: AOAM530Ov4HBfZ6T6NnpvrOZTvxrDd96WaX7M9VIGIwjWARkOlRD7MYg dmJEvPXaxq5eZPAKXDx/foiLGKIRg8ERoQ== X-Google-Smtp-Source: ABdhPJx6TJ/UGx3jNJnRGftqSxsx+05QpeuO1DHUpGAWFawVpE2M71MUuGpUu1Gf+lgHWScGBUqM4Q== X-Received: by 2002:a17:90a:510e:b0:1cb:b1de:27a0 with SMTP id t14-20020a17090a510e00b001cbb1de27a0mr14567096pjh.196.1650217700857; Sun, 17 Apr 2022 10:48:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 59/60] target/arm: Define cortex-a76 Date: Sun, 17 Apr 2022 10:44:25 -0700 Message-Id: <20220417174426.711829-60-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650221695859100001 Content-Type: text/plain; charset="utf-8" Enable the a76 for virt and sbsa board use. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- docs/system/arm/virt.rst | 1 + hw/arm/sbsa-ref.c | 1 + hw/arm/virt.c | 1 + target/arm/cpu64.c | 66 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 69 insertions(+) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index 1544632b67..e9ff81aa21 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -55,6 +55,7 @@ Supported guest CPU types: - ``cortex-a53`` (64-bit) - ``cortex-a57`` (64-bit) - ``cortex-a72`` (64-bit) +- ``cortex-a76`` (64-bit) - ``a64fx`` (64-bit) - ``host`` (with KVM only) - ``max`` (same as ``host`` for KVM; best possible emulation with TCG) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 2387401963..2ddde88f5e 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -145,6 +145,7 @@ static const int sbsa_ref_irqmap[] =3D { static const char * const valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), + ARM_CPU_TYPE_NAME("cortex-a76"), ARM_CPU_TYPE_NAME("max"), }; =20 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index d2e5ecd234..ce15c36a7f 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -202,6 +202,7 @@ static const char *valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a53"), ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), + ARM_CPU_TYPE_NAME("cortex-a76"), ARM_CPU_TYPE_NAME("a64fx"), ARM_CPU_TYPE_NAME("host"), ARM_CPU_TYPE_NAME("max"), diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 336a941acd..d046351991 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -194,6 +194,71 @@ static void aarch64_a72_initfn(Object *obj) define_cortex_a72_a57_a53_cp_reginfo(cpu); } =20 +static void aarch64_a76_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a76"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* Ordered by B2.4 AArch64 registers by functional group */ + cpu->clidr =3D 0x82000023; + cpu->ctr =3D 0x8444C004; + cpu->dcz_blocksize =3D 4; + cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; + cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; + cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; + cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; + cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; + cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; + cpu->isar.id_aa64pfr0 =3D 0x1100000010111112ull; /* GIC filled in lat= er */ + cpu->isar.id_aa64pfr1 =3D 0x0000000000000010ull; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_dfr0 =3D 0x04010088; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00010142; + cpu->isar.id_isar5 =3D 0x01011121; + cpu->isar.id_isar6 =3D 0x00000010; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02122211; + cpu->isar.id_mmfr4 =3D 0x00021110; + cpu->isar.id_pfr0 =3D 0x10010131; + cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ + cpu->isar.id_pfr2 =3D 0x00000011; + cpu->midr =3D 0x414fd0b1; /* r4p1 */ + cpu->revidr =3D 0; + + /* From B2.18 CCSIDR_EL1 */ + cpu->ccsidr[0] =3D 0x701fe01a; /* 64KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe01a; /* 64KB L1 icache */ + cpu->ccsidr[2] =3D 0x707fe03a; /* 512KB L2 cache */ + + /* From B2.93 SCTLR_EL3 */ + cpu->reset_sctlr =3D 0x30c50838; + + /* From B4.23 ICH_VTR_EL2 */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + + /* From B5.1 AdvSIMD AArch64 register summary */ + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x13211111; + cpu->isar.mvfr2 =3D 0x00000043; +} + void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { /* @@ -879,6 +944,7 @@ static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a57", .initfn =3D aarch64_a57_initfn }, { .name =3D "cortex-a53", .initfn =3D aarch64_a53_initfn }, { .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn }, + { .name =3D "cortex-a76", .initfn =3D aarch64_a76_initfn }, { .name =3D "a64fx", .initfn =3D aarch64_a64fx_initfn }, { .name =3D "max", .initfn =3D aarch64_max_initfn }, #if defined(CONFIG_KVM) || defined(CONFIG_HVF) --=20 2.25.1 From nobody Sat Apr 27 12:37:20 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id e14-20020aa78c4e000000b00506475da4cesm9372055pfd.49.2022.04.17.10.48.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 17 Apr 2022 10:48:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rPFD4Uf75Ys0SRC54fKBDAw6RK6wxGzSGtCN20boZmA=; b=lc4+E0VSsqAiX5c9RB/KR2vwi/A0tUaaOd7nYMHe7cc6iYUSD2Ms9LybeplVxBPBgc 4uNBfukBDr4AGchjLsN5u84npFWOij2/DLiGwyF8RQLAG7zeHkduYGmiOozKtfhYR8/H JNxDXwNAex8UIhQRqn25a+ITbJoN99NYqDeeb/NixIfqjGrTZDt8A9bSvTqejDWIHvRK rM0oZG4DHhbYYKmfi2E8BSKRSVk98CdeqOC6Wkpl4TyMy5cmJlWTg9i/bgUIyUjnFDMY a+Z8Q4CR3nLRBQWhh+VgaGnB15sdZNQslqSUJQiBCOVrkKWRVgQADGx1/i7l82VZHwei Bp8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rPFD4Uf75Ys0SRC54fKBDAw6RK6wxGzSGtCN20boZmA=; b=CJJUtDyHShGwji8EBaOjVxLLU0xueqEKe4N0DclUXg9m4SWn4QjuQtO90jin02Sben SlXE89Hk+XKyHzeMjIG0K056rga82FBZLjzAMZcqYgVkLKSKPWG6AZp4tM4dSR3nU/Qj iZsOqGjgMtSanZtDFURfMEKYJC19pGve5UDkKxxRwO2zvECzQn9XbLlc5PIUf2mqOq20 9iniiiZNFvPgsaZizamcD8VKL3ShG7rHQ3r+IATE7ydY8wGRcZpbkRtc+kOsN8aa5mK+ TtC+ra/Y5ZscZCy73venNZ6Ftffl9XB/hwslZ0Rxj26JSC5R+O/UtxL7m2M1KzqsWcKa b3Qg== X-Gm-Message-State: AOAM533b59Zrq/EWRjrTHYc27W9qKxZMa0ydytpoqn5u4s8uJaQWwtNY JVzpNrJpkBn1ZMWdjrY9TJhGfvS0zXXsAg== X-Google-Smtp-Source: ABdhPJy31xiESbFUa8kVicl+R+bYw/Fv8C130rjQxEMtsvQnUj/2wwGlTmOV2px1sTQPvJ5lKvAlDg== X-Received: by 2002:a65:68c2:0:b0:39e:18d3:fe43 with SMTP id k2-20020a6568c2000000b0039e18d3fe43mr7183281pgt.602.1650217701857; Sun, 17 Apr 2022 10:48:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 60/60] target/arm: Define neoverse-n1 Date: Sun, 17 Apr 2022 10:44:26 -0700 Message-Id: <20220417174426.711829-61-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220417174426.711829-1-richard.henderson@linaro.org> References: <20220417174426.711829-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650221220128100001 Content-Type: text/plain; charset="utf-8" Enable the n1 for virt and sbsa board use. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- docs/system/arm/virt.rst | 1 + hw/arm/sbsa-ref.c | 1 + hw/arm/virt.c | 1 + target/arm/cpu64.c | 66 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 69 insertions(+) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index e9ff81aa21..e8e851a15b 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -58,6 +58,7 @@ Supported guest CPU types: - ``cortex-a76`` (64-bit) - ``a64fx`` (64-bit) - ``host`` (with KVM only) +- ``neoverse-n1`` (64-bit) - ``max`` (same as ``host`` for KVM; best possible emulation with TCG) =20 Note that the default is ``cortex-a15``, so for an AArch64 guest you must diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 2ddde88f5e..dac8860f2d 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -146,6 +146,7 @@ static const char * const valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), ARM_CPU_TYPE_NAME("cortex-a76"), + ARM_CPU_TYPE_NAME("neoverse-n1"), ARM_CPU_TYPE_NAME("max"), }; =20 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ce15c36a7f..82dd934de6 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -204,6 +204,7 @@ static const char *valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a72"), ARM_CPU_TYPE_NAME("cortex-a76"), ARM_CPU_TYPE_NAME("a64fx"), + ARM_CPU_TYPE_NAME("neoverse-n1"), ARM_CPU_TYPE_NAME("host"), ARM_CPU_TYPE_NAME("max"), }; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index d046351991..da311b2eb5 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -259,6 +259,71 @@ static void aarch64_a76_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; } =20 +static void aarch64_neoverse_n1_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,neoverse-n1"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* Ordered by B2.4 AArch64 registers by functional group */ + cpu->clidr =3D 0x82000023; + cpu->ctr =3D 0x8444c004; + cpu->dcz_blocksize =3D 4; + cpu->isar.id_aa64dfr0 =3D 0x0000000110305408ull; + cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; + cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; + cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; + cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; + cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; + cpu->isar.id_aa64pfr0 =3D 0x1100000010111112ull; /* GIC filled in lat= er */ + cpu->isar.id_aa64pfr1 =3D 0x0000000000000020ull; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_dfr0 =3D 0x04010088; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00010142; + cpu->isar.id_isar5 =3D 0x01011121; + cpu->isar.id_isar6 =3D 0x00000010; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02122211; + cpu->isar.id_mmfr4 =3D 0x00021110; + cpu->isar.id_pfr0 =3D 0x10010131; + cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ + cpu->isar.id_pfr2 =3D 0x00000011; + cpu->midr =3D 0x414fd0c1; /* r4p1 */ + cpu->revidr =3D 0; + + /* From B2.23 CCSIDR_EL1 */ + cpu->ccsidr[0] =3D 0x701fe01a; /* 64KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe01a; /* 64KB L1 icache */ + cpu->ccsidr[2] =3D 0x70ffe03a; /* 1MB L2 cache */ + + /* From B2.98 SCTLR_EL3 */ + cpu->reset_sctlr =3D 0x30c50838; + + /* From B4.23 ICH_VTR_EL2 */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + + /* From B5.1 AdvSIMD AArch64 register summary */ + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x13211111; + cpu->isar.mvfr2 =3D 0x00000043; +} + void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { /* @@ -946,6 +1011,7 @@ static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn }, { .name =3D "cortex-a76", .initfn =3D aarch64_a76_initfn }, { .name =3D "a64fx", .initfn =3D aarch64_a64fx_initfn }, + { .name =3D "neoverse-n1", .initfn =3D aarch64_neoverse_n1_init= fn }, { .name =3D "max", .initfn =3D aarch64_max_initfn }, #if defined(CONFIG_KVM) || defined(CONFIG_HVF) { .name =3D "host", .initfn =3D aarch64_host_initfn }, --=20 2.25.1