From nobody Thu May 2 07:46:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1650080273033866.8805359377444; Fri, 15 Apr 2022 20:37:53 -0700 (PDT) Received: from localhost ([::1]:59986 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nfZFv-0004zK-4T for importer@patchew.org; Fri, 15 Apr 2022 23:37:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:51504) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nfZFG-0004Jf-Qk for qemu-devel@nongnu.org; Fri, 15 Apr 2022 23:37:10 -0400 Received: from applejack.8vit.me ([165.227.58.191]:44708) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nfZFF-0000od-BI for qemu-devel@nongnu.org; Fri, 15 Apr 2022 23:37:10 -0400 Received: from gabby.8vit.me (unknown [192.168.28.2]) by applejack.8vit.me (Postfix) with ESMTPS id C236923F7F4; Sat, 16 Apr 2022 12:28:03 +0900 (JST) Received: by gabby.8vit.me (Postfix, from userid 1000) id 619531A610F; Sat, 16 Apr 2022 12:28:02 +0900 (JST) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: None (mailfrom) identity=mailfrom; client-ip=192.168.28.2; helo=gabby.8vit.me; envelope-from=yvt@gabby.8vit.me; receiver= From: Tomoaki Kawada To: qemu-devel@nongnu.org Subject: [PATCH] target/rx: swap stack pointers on clrpsw/setpsw instruction Date: Sat, 16 Apr 2022 12:20:09 +0900 Message-Id: <20220416032009.1897719-1-i@yvt.jp> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: none client-ip=165.227.58.191; envelope-from=yvt@gabby.8vit.me; helo=applejack.8vit.me X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tomoaki Kawada , Yoshinori Sato Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650080274533100001 Content-Type: text/plain; charset="utf-8" The control register field PSW.U determines which stack pointer register (ISP or USP) is mapped as R0. In QEMU, this is implemented by having a value copied between ISP or USP and R0 whenever PSW.U is updated or access to ISP/USP is made by an mvtc/mvic instruction. However, this update process was incorrectly omitted in the clrpsw/setpsw (clear/set PSW) instructions, causing stack pointers to go out-of-sync. This patch updates the clrpsw/setpsw translator to handle PSW.U updates correctly and fix this problem. Signed-off-by: Tomoaki Kawada --- target/rx/translate.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/target/rx/translate.c b/target/rx/translate.c index 5db8f79a82..c282433fb7 100644 --- a/target/rx/translate.c +++ b/target/rx/translate.c @@ -2135,6 +2135,7 @@ enum { =20 static inline void clrsetpsw(DisasContext *ctx, int cb, int val) { + TCGv z; if (cb < 8) { switch (cb) { case PSW_C: @@ -2160,7 +2161,22 @@ static inline void clrsetpsw(DisasContext *ctx, int = cb, int val) ctx->base.is_jmp =3D DISAS_UPDATE; break; case PSW_U: + z =3D tcg_const_i32(0); + + /* (PSW.U ? USP : ISP) =3D R0 */ + tcg_gen_movcond_i32(TCG_COND_NE, cpu_usp, + cpu_psw_u, z, cpu_sp, cpu_usp); + tcg_gen_movcond_i32(TCG_COND_EQ, cpu_isp, + cpu_psw_u, z, cpu_sp, cpu_isp); + + /* Set PSW.U */ tcg_gen_movi_i32(cpu_psw_u, val); + + /* R0 =3D (PSW.U ? USP : ISP) */ + tcg_gen_movcond_i32(TCG_COND_NE, cpu_sp, + cpu_psw_u, z, cpu_usp, cpu_isp); + + tcg_temp_free(z); break; default: qemu_log_mask(LOG_GUEST_ERROR, "Invalid distination %d", cb); --=20 2.35.1