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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id g15-20020a056a0023cf00b004e17e11cb17sm38346669pfc.111.2022.04.11.17.33.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 17:33:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JoBBg/kSFjOXyAKcvYGCO5ADafkL/tC3ktVRL7z4yew=; b=WXsxxoBZj4APndTyi5P7xAxjtSreYBr+yzse7Wh2aMGYn00MFyGrcGokp/WIMQrObv DBov/cIUfpPNQmzoPU/odYQh4MKIYjbxvLjf6A0ydbt4RW0N7aaluSNlBSMbKYt07cqR 4FfA+VYUpYWVwo6EKHRk6IsixFeDikL3xhsOtqAdPRzj/DlZ3jFa+3fnaj/HlERCofcx hVt6giRgjf5ycYpx6sICskzYSgovHDiOpcB7Y7bK/gNwpklWSTNpJrGl65QWOGXiVlQp R0gpPBCGfoDg3pJsUA9xifSbwX5W8Sw1H6J7qInb7zTx2y55OmVc1UqVv/1ZGr0/yDAA XnNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JoBBg/kSFjOXyAKcvYGCO5ADafkL/tC3ktVRL7z4yew=; b=cX/jGWTnx1OXYFJBhS+igBb/vBOp8ACgChbZbZrA6aJdF7Rkt9xZXE7IzvOsiiO5ii 8N8ql+brWYjUwO/vfRQ4P4NVnc4xoouw9A32HPYIIx4vIhuupl6rbyY9s3fKUlMprSAC 6RjSGJ+6sVDFuRhmb8eWfzR7DBzgP5sYiI+gIZ9TPIea2xBvhIMO12TT4G6u/2/4SeIj PSWfRm0psBh7zOd+Ry4XMi6h2kY6vrgR+WnIZa4/sT3HF7u0q0AHxtoi8PIps2qHqLDa cUjYfv0ScXs1Z8FDdw12QQcUG+Jh5++CQgN9ZsCKI9IN4GSKHWNevrWbNlizA3e9FyH1 kXrA== X-Gm-Message-State: AOAM5336VYIqejXvjHDQpxZ9yreC3PN6tqhVHmTw8aq31mcjBzPYJ6yi ULI9IKcXTrJENH5sjIstEHElpHpDCKylIQ== X-Google-Smtp-Source: ABdhPJyHtoj4yFrJZfgBRTtd1BwiFhbPfOM7GvqzzrLPz74/EjVvVzl+POjbfWtNvvvZ1cEDs6W4AA== X-Received: by 2002:a17:903:186:b0:154:3606:7a73 with SMTP id z6-20020a170903018600b0015436067a73mr35276656plg.89.1649723621412; Mon, 11 Apr 2022 17:33:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 15/24] target/arm: Implement ESB instruction Date: Mon, 11 Apr 2022 17:33:17 -0700 Message-Id: <20220412003326.588530-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220412003326.588530-1-richard.henderson@linaro.org> References: <20220412003326.588530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1649725012488100001 Content-Type: text/plain; charset="utf-8" Check for and defer any pending virtual SError. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Retain m-profile check; improve comments. --- target/arm/helper.h | 1 + target/arm/a32.decode | 16 ++++++++------ target/arm/t32.decode | 18 ++++++++-------- target/arm/op_helper.c | 43 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 17 +++++++++++++++ target/arm/translate.c | 23 ++++++++++++++++++++ 6 files changed, 103 insertions(+), 15 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index b463d9343b..b1334e0c42 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -54,6 +54,7 @@ DEF_HELPER_1(wfe, void, env) DEF_HELPER_1(yield, void, env) DEF_HELPER_1(pre_hvc, void, env) DEF_HELPER_2(pre_smc, void, env, i32) +DEF_HELPER_1(vesb, void, env) =20 DEF_HELPER_3(cpsr_write, void, env, i32, i32) DEF_HELPER_2(cpsr_write_eret, void, env, i32) diff --git a/target/arm/a32.decode b/target/arm/a32.decode index fcd8cd4f7d..f2ca480949 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -187,13 +187,17 @@ SMULTT .... 0001 0110 .... 0000 .... 1110 .= ... @rd0mn =20 { { - YIELD ---- 0011 0010 0000 1111 ---- 0000 0001 - WFE ---- 0011 0010 0000 1111 ---- 0000 0010 - WFI ---- 0011 0010 0000 1111 ---- 0000 0011 + [ + YIELD ---- 0011 0010 0000 1111 ---- 0000 0001 + WFE ---- 0011 0010 0000 1111 ---- 0000 0010 + WFI ---- 0011 0010 0000 1111 ---- 0000 0011 =20 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 - # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 + # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 + + ESB ---- 0011 0010 0000 1111 ---- 0001 0000 + ] =20 # The canonical nop ends in 00000000, but the whole of the # rest of the space executes as nop if otherwise unsupported. diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 78fadef9d6..f21ad0167a 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -364,17 +364,17 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .= ... @rdm [ # Hints, and CPS { - YIELD 1111 0011 1010 1111 1000 0000 0000 0001 - WFE 1111 0011 1010 1111 1000 0000 0000 0010 - WFI 1111 0011 1010 1111 1000 0000 0000 0011 + [ + YIELD 1111 0011 1010 1111 1000 0000 0000 0001 + WFE 1111 0011 1010 1111 1000 0000 0000 0010 + WFI 1111 0011 1010 1111 1000 0000 0000 0011 =20 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV 1111 0011 1010 1111 1000 0000 0000 0100 - # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1111 0011 1010 1111 1000 0000 0000 0100 + # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 =20 - # For M-profile minimal-RAS ESB can be a NOP, which is the - # default behaviour since it is in the hint space. - # ESB 1111 0011 1010 1111 1000 0000 0001 0000 + ESB 1111 0011 1010 1111 1000 0000 0001 0000 + ] =20 # The canonical nop ends in 0000 0000, but the whole rest # of the space is "reserved hint, behaves as nop". diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 70b42b55fd..13076ee885 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -972,3 +972,46 @@ void HELPER(probe_access)(CPUARMState *env, target_ulo= ng ptr, access_type, mmu_idx, ra); } } + +/* + * This function corresponds to AArch64.vESBOperation(). + * Note that the AArch32 version is not functionally different. + */ +void HELPER(vesb)(CPUARMState *env) +{ + /* + * The EL2Enabled() check is done inside arm_hcr_el2_eff, + * and will return HCR_EL2.VSE =3D=3D 0, so nothing happens. + */ + uint64_t hcr =3D arm_hcr_el2_eff(env); + bool enabled =3D !(hcr & HCR_TGE) && (hcr & HCR_AMO); + bool pending =3D enabled && (hcr & HCR_VSE); + bool masked =3D (env->daif & PSTATE_A); + + /* If VSE pending and masked, defer the exception. */ + if (pending && masked) { + uint32_t syndrome; + + if (arm_el_is_aa64(env, 1)) { + /* Copy across IDS and ISS from VSESR. */ + syndrome =3D env->cp15.vsesr_el2 & 0x1ffffff; + } else { + ARMMMUFaultInfo fi =3D { .type =3D ARMFault_AsyncExternal }; + + if (extended_addresses_enabled(env)) { + syndrome =3D arm_fi_to_lfsc(&fi); + } else { + syndrome =3D arm_fi_to_sfsc(&fi); + } + /* Copy across AET and ExT from VSESR. */ + syndrome |=3D env->cp15.vsesr_el2 & 0xd000; + } + + /* Set VDISR_EL2.A along with the syndrome. */ + env->cp15.vdisr_el2 =3D syndrome | (1u << 31); + + /* Clear pending virtual SError */ + env->cp15.hcr_el2 &=3D ~HCR_VSE; + cpu_reset_interrupt(env_cpu(env), CPU_INTERRUPT_VSERR); + } +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9333d7be41..4fc31807ff 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1469,6 +1469,23 @@ static void handle_hint(DisasContext *s, uint32_t in= sn, gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); } break; + case 0b10000: /* ESB */ + /* Without RAS, we must implement this as NOP. */ + if (dc_isar_feature(aa64_ras, s)) { + /* + * QEMU does not have a source of physical SErrors, + * so we are only concerned with virtual SErrors. + * The pseudocode in the ARM for this case is + * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then + * AArch64.vESBOperation(); + * Most of the condition can be evaluated at translation time. + * Test for EL2 present, and defer test for SEL2 to runtime. + */ + if (s->current_el <=3D 1 && arm_dc_feature(s, ARM_FEATURE_EL2)= ) { + gen_helper_vesb(cpu_env); + } + } + break; case 0b11000: /* PACIAZ */ if (s->pauth_active) { gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], diff --git a/target/arm/translate.c b/target/arm/translate.c index bf2196b9e2..fa34b0ad4d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6275,6 +6275,29 @@ static bool trans_WFI(DisasContext *s, arg_WFI *a) return true; } =20 +static bool trans_ESB(DisasContext *s, arg_ESB *a) +{ + /* + * For M-profile, minimal-RAS ESB can be a NOP. + * Without RAS, we must implement this as NOP. + */ + if (!arm_dc_feature(s, ARM_FEATURE_M) && dc_isar_feature(aa32_ras, s))= { + /* + * QEMU does not have a source of physical SErrors, + * so we are only concerned with virtual SErrors. + * The pseudocode in the ARM for this case is + * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then + * AArch32.vESBOperation(); + * Most of the condition can be evaluated at translation time. + * Test for EL2 present, and defer test for SEL2 to runtime. + */ + if (s->current_el <=3D 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) { + gen_helper_vesb(cpu_env); + } + } + return true; +} + static bool trans_NOP(DisasContext *s, arg_NOP *a) { return true; --=20 2.25.1