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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1649723833457100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 23879de5fa..9c456ff23a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4026,6 +4026,11 @@ static inline bool isar_feature_aa32_ssbs(const ARMI= SARegisters *id) return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) !=3D 0; } =20 +static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >=3D 8; +} + /* * 64-bit feature tests via id registers. */ @@ -4332,6 +4337,11 @@ static inline bool isar_feature_aa64_ssbs(const ARMI= SARegisters *id) return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) !=3D 0; } =20 +static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >=3D 8; +} + static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) !=3D 0; @@ -4415,6 +4425,11 @@ static inline bool isar_feature_any_tts2uxn(const AR= MISARegisters *id) return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); } =20 +static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id) +{ + return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(= id); +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ --=20 2.25.1 From nobody Mon Feb 9 17:10:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1649723832578414.8862716973423; Mon, 11 Apr 2022 17:37:12 -0700 (PDT) Received: from localhost ([::1]:49216 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ne4Wt-0005gR-JK for importer@patchew.org; Mon, 11 Apr 2022 20:37:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58342) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ne4TN-0001lQ-Ao for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:33 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]:46735) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ne4TL-0001my-PP for qemu-devel@nongnu.org; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id g15-20020a056a0023cf00b004e17e11cb17sm38346669pfc.111.2022.04.11.17.33.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 17:33:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/hGWeYYiNWRormK6+Z3WghHxlA4vi4CjIBFLwBE3yec=; b=qAOQC5ia4f0xUXaZ4GpZ+XwLxJuROMspCPRDC+Ujf1EoyrcumETjX/1nXC1Jnuj8Id 8+/VsWoZQbrNzS1eXSBNkuRp3eS5fKBSq8Ll981k0EEax4XoJsd+oIqdDqLrpASV+qP5 A6mua8L66EO3NBUILTLqouo+zE0SaH3juukp30vmjKa0gfAmD2yVR6qwPbhrKgj1YlgG MLNOBq9v21hu4FR0Ilrma/VKej57og3iLx5JXmDyLv2c8anVhYojkQnjNRocy2tKZ4Uy Q70Izksa+h7NoL3pJJNglFv5jbSKh0ZNhT5tNpTuidsqCsKTGj3EI3hKPvnuQ3fely3u Gm8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/hGWeYYiNWRormK6+Z3WghHxlA4vi4CjIBFLwBE3yec=; b=mV/6fNpljThwIrL/qLvpPIEF6yfn/1ULmJc577mEdHaGwe/8jkdN135mOekd8PI+zo 0nnrEmPPtN5gT7nzcSeaaiM74zGuXATRBc1NjYL8L4bPH0zGfsgX1pBDgKyeK3kmgCaC 1PF/Q2XMoLwfVkBZY4yt2PJCFBTKWyfVMVvxLPvmLHPE6TmPILUXsnOTTGjbiNcsHzfA 8MRbdu+7fEtmY3Nn7Kj4SzTO4BL2XgVlp1UdU1kp8HIz7lOlXPgg+/ViQyaa0ElsCLmp WVfRHVxouF+1MH60cKY6uFNCj7UxQqlp3g08O6qBswkWmshac4VO3CRDvgX+sqNvX48L TrMw== X-Gm-Message-State: AOAM533IKQHSvVfDt/BlNtfLYyEwCUrcAdtHAPOeRwWNKa0k8gaQdeeL laKE7tyXmqcjhgp2Vf1bm8OqI+QV0wGppw== X-Google-Smtp-Source: ABdhPJwefxCUqyVX2DcoLjFjqqk29JXj4t5JT16qaBofOLOhZWGk7ChbhzqIyo4GjZf8pECRcen13g== X-Received: by 2002:a63:581d:0:b0:39d:5138:1ce2 with SMTP id m29-20020a63581d000000b0039d51381ce2mr6585338pgb.621.1649723610531; Mon, 11 Apr 2022 17:33:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 02/24] target/arm: Adjust definition of CONTEXTIDR_EL2 Date: Mon, 11 Apr 2022 17:33:04 -0700 Message-Id: <20220412003326.588530-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220412003326.588530-1-richard.henderson@linaro.org> References: <20220412003326.588530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1649723833578100002 Content-Type: text/plain; charset="utf-8" This register is present for either VHE or Debugv8p2, and is RES0 from EL3 when EL2 is not present. Move the definition out of vhe_reginfo and provide a fallback for missing EL2. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7d14650615..210c139818 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7443,11 +7443,20 @@ static const ARMCPRegInfo jazelle_regs[] =3D { REGINFO_SENTINEL }; =20 +static const ARMCPRegInfo contextidr_el2 =3D { + .name =3D "CONTEXTIDR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[2]) +}; + +static const ARMCPRegInfo contextidr_no_el2 =3D { + .name =3D "CONTEXTIDR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 +}; + static const ARMCPRegInfo vhe_reginfo[] =3D { - { .name =3D "CONTEXTIDR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, - .access =3D PL2_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[2]) }, { .name =3D "TTBR1_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, .access =3D PL2_RW, .writefn =3D vmsa_tcr_ttbr_el2_write, @@ -8443,6 +8452,14 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &ssbs_reginfo); } =20 + if (cpu_isar_feature(aa64_vh, cpu) || + cpu_isar_feature(aa64_debugv8p2, cpu)) { + if (arm_feature(env, ARM_FEATURE_EL2)) { + define_one_arm_cp_reg(cpu, &contextidr_el2); + } else { + define_one_arm_cp_reg(cpu, &contextidr_no_el2); + } + } if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= )) { define_arm_cp_regs(cpu, vhe_reginfo); } --=20 2.25.1 From nobody Mon Feb 9 17:10:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1649724042; cv=none; d=zohomail.com; s=zohoarc; b=ZQBO/IdTMJD4tcXJApUK51smzvoGuk5y0xRLhHMnXmTfaPGVpuWqKq+dAT4kV2xwXNadzyCttY+vboUTHiGMfdWEtZE4nLTEUkfZ0V8GRrVQt5l3se8Ym3BKUigrVabqL1QBjRKDoc/5mUxX+W8ij5Qdx6zPbXIpK4wZfFgJnPw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649724042; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=mPUhonasIJemUilwvsQlTh0u9tlZu5D9Evhh4LDSBlU=; b=VRbaLijNPrsnhI12PL5GcKSnLVYRE3ZoI1w5WhcJnqHwD3QrMO4m5mY7Zh7vQiKpHjkzcGh9CMBll4FqyGCP7Im8NwkrKIfm2SDzvPC1QHIOgU+ZlA32CikDCdxsOvD42m6UaIPsI0uRdDFTUge38HD/8MGPy4v5q9nLR+4Uu1A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1649724042968771.6018172656777; Mon, 11 Apr 2022 17:40:42 -0700 (PDT) Received: from localhost ([::1]:57886 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ne4aH-000343-SI for importer@patchew.org; Mon, 11 Apr 2022 20:40:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58404) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ne4TO-0001pR-SX for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:34 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]:40754) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ne4TM-0001nL-Lk for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:34 -0400 Received: by mail-pf1-x432.google.com with SMTP id a42so9478541pfx.7 for ; Mon, 11 Apr 2022 17:33:32 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id g15-20020a056a0023cf00b004e17e11cb17sm38346669pfc.111.2022.04.11.17.33.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 17:33:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mPUhonasIJemUilwvsQlTh0u9tlZu5D9Evhh4LDSBlU=; b=knsLUebHw8k5CUzOdmKietpczWhLz5IJ54PjFIcR5zjcDzGos9FujscfboULwGK+w4 iU5sV5+0sHe2EQ06GWekUm+9PkIKYKp+YeXbCCrU7Fdeqo6OkHiyfjn8sozyzDbbpkTe 65USwit86cUydFPkQEIlVvzpTFO6y84b2A+qOwEPpf8v594aqbNqXUMzZMTV2ouNtIaH zRrlH7obopjynUg16/JnUDp1FGG9X0bwTd8S0bzpw9I44HQledGJ+b87LuJZGA5RQAhA L2PapWXnbDEoMeHo/PjRkTP2OEi4QHMO3CcoUXlVGw5101JMXnJRXyap3VemNy8zUmty nE8w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mPUhonasIJemUilwvsQlTh0u9tlZu5D9Evhh4LDSBlU=; b=kTQAY8lQaUp0+6vRbBnqb6Z6/N7gnfbAojOJXvqWKqhSKdPyj8YW9yGiCt22dVcDt4 oLV2HVs93cLVJk2fzRRtcCXbah781BIzVzNVAKP4MVkFOKH+UYp7qWd6wJKevjyf1OOa QUwYLX5vcI1vGLUYaSQCJkuqZD1XMIHgozzPNC+snHoCHGOtSp3QFwIsA9T0zhLXhcRx DCkRRO0suIUyMSs97cTJajb7m+kbu49m2A742BGt6kai1AUD4n15bP7C5X7Fws3kP7N9 Vo69MM33oCAoS/h2dkHpY8v1wSbsBqcrP47GRhq/Y9hzJZc+6qxVy4oHQRfDKBmnTYaY DGWg== X-Gm-Message-State: AOAM532hlBiM7IH4Alh9SRIyG3NRqUYVTQ6Zztse8b3K176hrnUeBOcr OYwYnV5S4Xc6rO4kF+OOiIJvlDraAiWddg== X-Google-Smtp-Source: ABdhPJw/1U+zCmSYcsT842MXb5zS1SwJzrDUWt3jn6lYjh1jBTcRtY6ZN1MalqYYPtkynjPWG88i/Q== X-Received: by 2002:a65:6543:0:b0:39d:5e6e:24c3 with SMTP id a3-20020a656543000000b0039d5e6e24c3mr6043142pgw.560.1649723611288; Mon, 11 Apr 2022 17:33:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 03/24] target/arm: Move cortex impdef sysregs to cpu_tcg.c Date: Mon, 11 Apr 2022 17:33:05 -0700 Message-Id: <20220412003326.588530-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220412003326.588530-1-richard.henderson@linaro.org> References: <20220412003326.588530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1649724044367100001 Content-Type: text/plain; charset="utf-8" Previously we were defining some of these in user-only mode, but none of them are accessible from user-only, therefore define them only in system mode. This will shortly be used from cpu_tcg.c also. Signed-off-by: Richard Henderson --- v2: New patch. --- target/arm/internals.h | 6 ++++ target/arm/cpu64.c | 64 +++--------------------------------------- target/arm/cpu_tcg.c | 60 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 70 insertions(+), 60 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 7f696cd36a..96a57ee68f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1295,4 +1295,10 @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteA= rray *buf, int reg); int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg); #endif =20 +#ifdef CONFIG_USER_ONLY +static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } +#else +void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); +#endif + #endif diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index eb44c05822..67d628c0af 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -34,65 +34,9 @@ #include "hvf_arm.h" #include "qapi/visitor.h" #include "hw/qdev-properties.h" +#include "internals.h" =20 =20 -#ifndef CONFIG_USER_ONLY -static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *= ri) -{ - ARMCPU *cpu =3D env_archcpu(env); - - /* Number of cores is in [25:24]; otherwise we RAZ */ - return (cpu->core_count - 1) << 24; -} -#endif - -static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] =3D { -#ifndef CONFIG_USER_ONLY - { .name =3D "L2CTLR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 11, .crm =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, .readfn =3D a57_a53_l2ctlr_read, - .writefn =3D arm_cp_write_ignore }, - { .name =3D "L2CTLR", - .cp =3D 15, .opc1 =3D 1, .crn =3D 9, .crm =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, .readfn =3D a57_a53_l2ctlr_read, - .writefn =3D arm_cp_write_ignore }, -#endif - { .name =3D "L2ECTLR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 11, .crm =3D 0, .opc2 =3D 3, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "L2ECTLR", - .cp =3D 15, .opc1 =3D 1, .crn =3D 9, .crm =3D 0, .opc2 =3D 3, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "L2ACTLR", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CPUACTLR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CPUACTLR", - .cp =3D 15, .opc1 =3D 0, .crm =3D 15, - .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, - { .name =3D "CPUECTLR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 1, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CPUECTLR", - .cp =3D 15, .opc1 =3D 1, .crm =3D 15, - .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, - { .name =3D "CPUMERRSR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 2, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CPUMERRSR", - .cp =3D 15, .opc1 =3D 2, .crm =3D 15, - .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, - { .name =3D "L2MERRSR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 3, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "L2MERRSR", - .cp =3D 15, .opc1 =3D 3, .crm =3D 15, - .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, - REGINFO_SENTINEL -}; - static void aarch64_a57_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -143,7 +87,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); + define_cortex_a72_a57_a53_cp_reginfo(cpu); } =20 static void aarch64_a53_initfn(Object *obj) @@ -196,7 +140,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); + define_cortex_a72_a57_a53_cp_reginfo(cpu); } =20 static void aarch64_a72_initfn(Object *obj) @@ -247,7 +191,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); + define_cortex_a72_a57_a53_cp_reginfo(cpu); } =20 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 13d0e9b195..17bb5e5d76 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -19,6 +19,66 @@ #include "hw/boards.h" #endif =20 +#ifndef CONFIG_USER_ONLY +static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + ARMCPU *cpu =3D env_archcpu(env); + + /* Number of cores is in [25:24]; otherwise we RAZ */ + return (cpu->core_count - 1) << 24; +} + +static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] =3D { + { .name =3D "L2CTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 11, .crm =3D 0, .opc2 =3D 2, + .access =3D PL1_RW, .readfn =3D l2ctlr_read, + .writefn =3D arm_cp_write_ignore }, + { .name =3D "L2CTLR", + .cp =3D 15, .opc1 =3D 1, .crn =3D 9, .crm =3D 0, .opc2 =3D 2, + .access =3D PL1_RW, .readfn =3D l2ctlr_read, + .writefn =3D arm_cp_write_ignore }, + { .name =3D "L2ECTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 11, .crm =3D 0, .opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "L2ECTLR", + .cp =3D 15, .opc1 =3D 1, .crn =3D 9, .crm =3D 0, .opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "L2ACTLR", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUACTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUACTLR", + .cp =3D 15, .opc1 =3D 0, .crm =3D 15, + .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, + { .name =3D "CPUECTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUECTLR", + .cp =3D 15, .opc1 =3D 1, .crm =3D 15, + .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, + { .name =3D "CPUMERRSR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 2, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUMERRSR", + .cp =3D 15, .opc1 =3D 2, .crm =3D 15, + .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, + { .name =3D "L2MERRSR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "L2MERRSR", + .cp =3D 15, .opc1 =3D 3, .crm =3D 15, + .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, + REGINFO_SENTINEL +}; + +void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) +{ + define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); +} +#endif /* !CONFIG_USER_ONLY */ + /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) =20 --=20 2.25.1 From nobody Mon Feb 9 17:10:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1649723823; cv=none; d=zohomail.com; s=zohoarc; b=nsbLHwIuiGQ454k+KwkryN8dui9gaPAvH293w79WiF61QkdkHlhfwcKNgsLOE5lvqGMCJ7fZsHZbRDuDDkVDXnlODOZULaNz8Vma/oFX3fuzTegDmvhX7pXaDwB12ybLBc9OcX7uARxJo5MJ66eRqYEh1yP+E2ZHu7KXaJ3fggI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649723823; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HR8MUA8fBXQu193YcvQc60M+IS6UFPGuHEP3w6sFTCo=; b=X2cWwp5cl8q6CxOAbJlkXkO3GvkVhEkd55HWE36uhQo5RPxvuwhBLWOJIZ5M9HJz+FAl8ixEQVA4Cdiuiwru/0ZGHXmQFuVKKx5wKdeunqIONW9FuXD6panuLAddXEcIf2spULJDch7aY7s1kl1AKBKbVB01fNJ51aESFHU7x4w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1649723823472586.81079129947; Mon, 11 Apr 2022 17:37:03 -0700 (PDT) Received: from localhost ([::1]:48238 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ne4Wj-00052H-Sf for importer@patchew.org; Mon, 11 Apr 2022 20:37:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58432) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ne4TP-0001qY-FF for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:40 -0400 Received: from mail-pg1-x52d.google.com ([2607:f8b0:4864:20::52d]:37570) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ne4TN-0001nY-Fg for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:35 -0400 Received: by mail-pg1-x52d.google.com with SMTP id 32so13510024pgl.4 for ; Mon, 11 Apr 2022 17:33:32 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id g15-20020a056a0023cf00b004e17e11cb17sm38346669pfc.111.2022.04.11.17.33.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 17:33:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HR8MUA8fBXQu193YcvQc60M+IS6UFPGuHEP3w6sFTCo=; b=k//801UqOgonIkmqyU09EcQUoBzj2TXzWecMstijBmyislFOJtkilxjWM7wCbaL0O5 yFfmokwIThyGOeApSSbN8h2+FyfwLHSF8jTWoSUjplY2dT+wxv28eMg2DSk+eY7/buw0 Li2iQPfpU+DurZFfVGKAUegGahFAD/U+5b07aVVVQnrzmB008AneLIT2YkzNe3mqFBkV FlutHW7Q+TH5sefBbIwZEH2De8nZTnqtkuxH5ohXQdmJ109mNkPXomRjZj2gr1iRElcC 9IP8RrShes9+Vswo27UJu3vzLclPRGcNwcbh01UwdGJGfsOgWr+i8AyQjuIhbM4BvqBP 6xtg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HR8MUA8fBXQu193YcvQc60M+IS6UFPGuHEP3w6sFTCo=; b=AyQ5IHranShhStfLSJrEMBHB1SNX54e/Jgee+VMW9Z6UNBAXeavm2le53bRfoCVa4W t3mtg7eS7GR0hErnM0j5FR0GIaTe2QmtWLTv2FuTLgtSe2urSvMVO/7jBH2vGY3RTwg1 kXQjlSSNr1ha7cgbhKWW4PgW++VHmzLY+wvhDrN/CtZR9keMraX7dUkzObaDzsCqHcLu jmyjcEh0dPKhzgUlmCP3/n0ekfIX4hYqEiLsvjHLoj94ZCmCfhB0iOFHKQS0WyAwX8tz +JF0Eg61giPXxTq7AXZx9fgupmBTTjmxLD5Jhgwtwzf9/ih14fO0wn82YC6J62haV9Dq wUIQ== X-Gm-Message-State: AOAM530HwQi/OWI6cApmbCGQTEKnTSNmKBNkjqm1FqB6Yk/skdn+SdeD +p1G89UCuHZBHc5BEYqkGF82DKIQY8Gtdw== X-Google-Smtp-Source: ABdhPJxzIo0awn2BKcejj/Z/qVSUxBgV4IXb/G2MwaIT8b+4r0zjRgguRuwx6lvJ0Z+2jtgVvy377A== X-Received: by 2002:a05:6a00:1307:b0:4b0:b1c:6fd9 with SMTP id j7-20020a056a00130700b004b00b1c6fd9mr1911352pfu.27.1649723612047; Mon, 11 Apr 2022 17:33:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 04/24] target/arm: Update qemu-system-arm -cpu max to cortex-a57 Date: Mon, 11 Apr 2022 17:33:06 -0700 Message-Id: <20220412003326.588530-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220412003326.588530-1-richard.henderson@linaro.org> References: <20220412003326.588530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1649723825420100001 Content-Type: text/plain; charset="utf-8" Instead of starting with cortex-a15 and adding v8 features to a v7 cpu, begin with a v8 cpu stripped of its aarch64 features. This fixes the long-standing to-do where we only enabled v8 features for user-only. Signed-off-by: Richard Henderson --- v2: Create impdef sysregs; only enable short-vector support for user-only. --- target/arm/cpu_tcg.c | 151 ++++++++++++++++++++++++++----------------- 1 file changed, 92 insertions(+), 59 deletions(-) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 17bb5e5d76..b7cb3a6cb3 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -998,71 +998,104 @@ static void arm_v7m_class_init(ObjectClass *oc, void= *data) static void arm_max_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + uint32_t t; =20 - cortex_a15_initfn(obj); + /* aarch64_a57_initfn, advertising none of the aarch64 features */ + cpu->dtb_compatible =3D "arm,cortex-a57"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->midr =3D 0x411fd070; + cpu->revidr =3D 0x00000000; + cpu->reset_fpsid =3D 0x41034070; + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x12111111; + cpu->isar.mvfr2 =3D 0x00000043; + cpu->ctr =3D 0x8444c004; + cpu->reset_sctlr =3D 0x00c50838; + cpu->isar.id_pfr0 =3D 0x00000131; + cpu->isar.id_pfr1 =3D 0x00011011; + cpu->isar.id_dfr0 =3D 0x03010066; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x10101105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02102211; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00011142; + cpu->isar.id_isar5 =3D 0x00011121; + cpu->isar.id_isar6 =3D 0; + cpu->isar.dbgdidr =3D 0x3516d000; + cpu->clidr =3D 0x0a200023; + cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe012; /* 48KB L1 icache */ + cpu->ccsidr[2] =3D 0x70ffe07a; /* 2048KB L2 cache */ + define_cortex_a72_a57_a53_cp_reginfo(cpu); =20 - /* old-style VFP short-vector support */ - cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); + /* Add additional features supported by QEMU */ + t =3D cpu->isar.id_isar5; + t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); + t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); + t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); + t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); + t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); + t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); + cpu->isar.id_isar5 =3D t; + + t =3D cpu->isar.id_isar6; + t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); + t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); + t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); + t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); + t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); + cpu->isar.id_isar6 =3D t; + + t =3D cpu->isar.mvfr1; + t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ + t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ + cpu->isar.mvfr1 =3D t; + + t =3D cpu->isar.mvfr2; + t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ + t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ + cpu->isar.mvfr2 =3D t; + + t =3D cpu->isar.id_mmfr3; + t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ + cpu->isar.id_mmfr3 =3D t; + + t =3D cpu->isar.id_mmfr4; + t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ + t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ + t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ + cpu->isar.id_mmfr4 =3D t; + + t =3D cpu->isar.id_pfr0; + t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); + cpu->isar.id_pfr0 =3D t; + + t =3D cpu->isar.id_pfr2; + t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); + cpu->isar.id_pfr2 =3D t; =20 #ifdef CONFIG_USER_ONLY /* - * We don't set these in system emulation mode for the moment, - * since we don't correctly set (all of) the ID registers to - * advertise them. + * Break with true ARMv8 and add back old-style VFP short-vector suppo= rt. + * Only do this for user-mode, where -cpu max is the default, so that + * older v6 and v7 programs are more likely to work without adjustment. */ - set_feature(&cpu->env, ARM_FEATURE_V8); - { - uint32_t t; - - t =3D cpu->isar.id_isar5; - t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); - t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); - t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); - t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); - t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); - t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); - cpu->isar.id_isar5 =3D t; - - t =3D cpu->isar.id_isar6; - t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); - t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); - t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); - t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); - t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); - cpu->isar.id_isar6 =3D t; - - t =3D cpu->isar.mvfr1; - t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ - t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ - cpu->isar.mvfr1 =3D t; - - t =3D cpu->isar.mvfr2; - t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ - t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ - cpu->isar.mvfr2 =3D t; - - t =3D cpu->isar.id_mmfr3; - t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ - cpu->isar.id_mmfr3 =3D t; - - t =3D cpu->isar.id_mmfr4; - t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ - t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ - t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ - cpu->isar.id_mmfr4 =3D t; - - t =3D cpu->isar.id_pfr0; - t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); - cpu->isar.id_pfr0 =3D t; - - t =3D cpu->isar.id_pfr2; - t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); - cpu->isar.id_pfr2 =3D t; - } -#endif /* CONFIG_USER_ONLY */ + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); +#endif } #endif /* !TARGET_AARCH64 */ =20 --=20 2.25.1 From nobody Mon Feb 9 17:10:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id g15-20020a056a0023cf00b004e17e11cb17sm38346669pfc.111.2022.04.11.17.33.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 17:33:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=iu/nk65R8C0cFFrefP1P5ddg1mxr43JuiZQtJemOhVo=; b=YNT5+kX+OCdnuotux99K0OAuuIKN9wLbhrVeH4zOyc91ovHyZi+LAcri3t6Hvyl+Ww b9vypa7OKDYJFGYcnVo5gp1G3WUIsN8wwb4vR+udukYDNAxRyGZ+7DyJEFsUfItLOavp Q5Yy6b5fblxws0eCXulhVfMAbNaHCCC3Qf4mAPdJXllDOCIl0H7bi4Mdmic4sVwdgKtX tSNED6d6wgbLfjPQ6bquH0y9A70t+n3DosvI24yWjlJEpJA0YSTcUUKzKCFo0bOPiRcq LZrsE34nEqv2JoAK7M20miEcJwvv70XODkZkccQhsXdvgx+jjhUczVK14EpG3g0K9iyT tBGA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=iu/nk65R8C0cFFrefP1P5ddg1mxr43JuiZQtJemOhVo=; b=WNEenUgB9WDqzUoPpvWhSEEpztWi6DGcd6DBCseUGoBVJmlo8HmToW7i9Xy6W+N/Fn MC+Q9VHxcgPnfzA1H6+mdi+v51ibYPeKFIPzSjFVhKrF0d1d1SWjaBccs+ftqlTiFB4t wTYfsuewKd3no1zPtypqQcqylnD0tTTF5dXRaoSz21Cw4is8/UGYpD73E3faxDLzqgy5 Ez3/TWlDs4WojkTqM6HuiJrIvH5i9fNRe83oPv4j/Kdey0V24CjAIQe/Kt3gnuw1Fcow pmzaksoB97iF/zVbruEnB6LSbYxgaLbQthmlF6GHhGrsTSg8eGEcjsCNvKEp5tSlZZHy DF+g== X-Gm-Message-State: AOAM530DwbhgnENeBJRpQiXHOYq6b4x82/klqAK/LJYRsAa8pucYIb98 a0fwBH1DUph92wz4qART0IbIqNSCMfOcAA== X-Google-Smtp-Source: ABdhPJzsy+xon5WSUiY0LxWFM2zfnV8v+ia+3BZ2pVNHbaapBlWoH+v4SLtDoipjigl8zDE2tpcngQ== X-Received: by 2002:a63:485d:0:b0:39d:8ebf:9acf with SMTP id x29-20020a63485d000000b0039d8ebf9acfmr1203212pgk.351.1649723612776; Mon, 11 Apr 2022 17:33:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 05/24] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max Date: Mon, 11 Apr 2022 17:33:07 -0700 Message-Id: <20220412003326.588530-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220412003326.588530-1-richard.henderson@linaro.org> References: <20220412003326.588530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1649723998076100001 Content-Type: text/plain; charset="utf-8" We set this for qemu-system-aarch64, but failed to do so for the strictly 32-bit emulation. Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'") Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu_tcg.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index b7cb3a6cb3..ac782531a7 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -1088,6 +1088,10 @@ static void arm_max_initfn(Object *obj) t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); cpu->isar.id_pfr2 =3D t; =20 + t =3D cpu->isar.id_dfr0; + t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ + cpu->isar.id_dfr0 =3D t; + #ifdef CONFIG_USER_ONLY /* * Break with true ARMv8 and add back old-style VFP short-vector suppo= rt. --=20 2.25.1 From nobody Mon Feb 9 17:10:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1649724074; cv=none; d=zohomail.com; s=zohoarc; b=FWxavPn/LfdE9ozG+sdEp92/A2nvKIqmqCZjw/cdoXvFQb0Xli5vqnHt8lPCLlrKVu1A+AtnnENhSlz4mAMV6mN4Vss1puc6wTkbNPS/sDSmYGWe+3lEAvIHYboWBCsm0T4z7exi5KE5hBIj210UlfML0L5S6124ThURWrTSVwg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649724074; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=O7CK/hn1c4miDXXyB3iPi83XXfs+x8KY/s6DWMX2EPY=; b=Tp04JcCBC5EwN0n8oaj03Mm6QCwfhYN25NZwCHcv97tCcgGs7uojVDgpcGqwb2OsHIa1QQswTYaJAuj6pqoNjX7N0HXihXAru+2apqRA5wtlrqgmjSPDhRyzXQ06t4q4M3yixGYikNYvKqQI0f5eRvmryO7v0SgSGrE6ChwpBh4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1649724074627315.159106680032; Mon, 11 Apr 2022 17:41:14 -0700 (PDT) Received: from localhost ([::1]:58936 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ne4am-0003kX-1Q for importer@patchew.org; Mon, 11 Apr 2022 20:41:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58486) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ne4TQ-0001sF-Uf for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:40 -0400 Received: from mail-pf1-x42f.google.com ([2607:f8b0:4864:20::42f]:43582) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ne4TO-0001oE-Vl for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:36 -0400 Received: by mail-pf1-x42f.google.com with SMTP id a21so1089965pfv.10 for ; Mon, 11 Apr 2022 17:33:34 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id g15-20020a056a0023cf00b004e17e11cb17sm38346669pfc.111.2022.04.11.17.33.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 17:33:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=O7CK/hn1c4miDXXyB3iPi83XXfs+x8KY/s6DWMX2EPY=; b=sPWHGnDL3JbWHl8wqQ8qnAZhd7AePy0hBre7zKpxrXpSkqxOGwXA8za6AMgRKZ8CsO dmGG3kdU6UqzVCK4Lrb+K3avpNtD2sKq8yotQdY20+FlOE6J+1yjem6/mxl4jr1xSBZK bNxU9zCy3b3K28+PT001xz0Nj8xGgPOFJZBvjawHWlHHfS2oi2zCJMRRilP7N+2KaRvw 0F41yHVeJbJWZPyMV77RLwl27U1WWY3AmqddQbTjrhSzj46IDMc+e8lJ4+5AvVf75/wI A7lvsAKVymxrjdPoYoghBUnVmzXZqpdBiavEWnlGafVhSaLSFlvrsq8x+q5n1LX18rfE pqnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=O7CK/hn1c4miDXXyB3iPi83XXfs+x8KY/s6DWMX2EPY=; b=DVi3mqusjqDWL4bHWmUH9RcZJOsTtp2cv8ZXzNI7mymJMwsurKsJfnIqNqYEjGgcsD 8PQh/5tMq0q0rXsJWWiRO/gyWJY9XauwpWHB9HIeQn468gN4VQExtaTrlTPFVgSM9b4C Hlg6FZEVi52i+JOtgATLGKEm9iyHoSIHB+N9hISvFU4drR/32qEfHRWoSKh9kRROPBcD /IPafNViIl8TzlHbrIo/TzTtne7w04asOFpiXAMa5E9eZ1SXklaw2qmriv7f4YJQArta xChhoMBOOgLENKs/8SLeGm0teJLwuIfsAihFjDzlotJT7/2tJSWs9aj8kRB56IvhWaRU zTqw== X-Gm-Message-State: AOAM533G8Zuf+A7AAKuuehn+1rJHnXhmaKtbLN5jv6H0ZPA84ZvCSqDd UEHd3vwh1IfXUK6znk9LGdYXwh3RYfl5Ng== X-Google-Smtp-Source: ABdhPJxI9exQ/a85/FtAWX+wAhVkrJGCg+LHDIbM7oi8WyD6gha3AsiuXUGSsqtMxnPlPw1NoFQ2uQ== X-Received: by 2002:a63:d64d:0:b0:374:6edc:989c with SMTP id d13-20020a63d64d000000b003746edc989cmr28549691pgj.434.1649723613620; Mon, 11 Apr 2022 17:33:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 06/24] target/arm: Split out arm32_max_features Date: Mon, 11 Apr 2022 17:33:08 -0700 Message-Id: <20220412003326.588530-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220412003326.588530-1-richard.henderson@linaro.org> References: <20220412003326.588530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1649724076512100001 Content-Type: text/plain; charset="utf-8" Share the code to set AArch32 max features so that we no longer have code drift between qemu{-system,}-{arm,aarch64}. Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 + target/arm/cpu64.c | 50 +----------------- target/arm/cpu_tcg.c | 114 ++++++++++++++++++++++------------------- 3 files changed, 65 insertions(+), 101 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 96a57ee68f..ca9782b9f0 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1301,4 +1301,6 @@ static inline void define_cortex_a72_a57_a53_cp_regin= fo(ARMCPU *cpu) { } void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); #endif =20 +void arm32_max_features(ARMCPU *cpu); + #endif diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 67d628c0af..528b0f5e64 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -682,7 +682,6 @@ static void aarch64_max_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); uint64_t t; - uint32_t u; =20 if (kvm_enabled() || hvf_enabled()) { /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */ @@ -797,57 +796,12 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); cpu->isar.id_aa64zfr0 =3D t; =20 - /* Replicate the same data to the 32-bit id registers. */ - u =3D cpu->isar.id_isar5; - u =3D FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ - u =3D FIELD_DP32(u, ID_ISAR5, SHA1, 1); - u =3D FIELD_DP32(u, ID_ISAR5, SHA2, 1); - u =3D FIELD_DP32(u, ID_ISAR5, CRC32, 1); - u =3D FIELD_DP32(u, ID_ISAR5, RDM, 1); - u =3D FIELD_DP32(u, ID_ISAR5, VCMA, 1); - cpu->isar.id_isar5 =3D u; - - u =3D cpu->isar.id_isar6; - u =3D FIELD_DP32(u, ID_ISAR6, JSCVT, 1); - u =3D FIELD_DP32(u, ID_ISAR6, DP, 1); - u =3D FIELD_DP32(u, ID_ISAR6, FHM, 1); - u =3D FIELD_DP32(u, ID_ISAR6, SB, 1); - u =3D FIELD_DP32(u, ID_ISAR6, SPECRES, 1); - u =3D FIELD_DP32(u, ID_ISAR6, BF16, 1); - u =3D FIELD_DP32(u, ID_ISAR6, I8MM, 1); - cpu->isar.id_isar6 =3D u; - - u =3D cpu->isar.id_pfr0; - u =3D FIELD_DP32(u, ID_PFR0, DIT, 1); - cpu->isar.id_pfr0 =3D u; - - u =3D cpu->isar.id_pfr2; - u =3D FIELD_DP32(u, ID_PFR2, SSBS, 1); - cpu->isar.id_pfr2 =3D u; - - u =3D cpu->isar.id_mmfr3; - u =3D FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ - cpu->isar.id_mmfr3 =3D u; - - u =3D cpu->isar.id_mmfr4; - u =3D FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */ - u =3D FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - u =3D FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */ - u =3D FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */ - cpu->isar.id_mmfr4 =3D u; - t =3D cpu->isar.id_aa64dfr0; t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ cpu->isar.id_aa64dfr0 =3D t; =20 - u =3D cpu->isar.id_dfr0; - u =3D FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ - cpu->isar.id_dfr0 =3D u; - - u =3D cpu->isar.mvfr1; - u =3D FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */ - u =3D FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ - cpu->isar.mvfr1 =3D u; + /* Replicate the same data to the 32-bit id registers. */ + arm32_max_features(cpu); =20 #ifdef CONFIG_USER_ONLY /* diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index ac782531a7..94af0c3bda 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -19,6 +19,66 @@ #include "hw/boards.h" #endif =20 + +/* Share AArch32 -cpu max features with AArch64. */ +void arm32_max_features(ARMCPU *cpu) +{ + uint32_t t; + + /* Add additional features supported by QEMU */ + t =3D cpu->isar.id_isar5; + t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); + t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); + t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); + t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); + t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); + t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); + cpu->isar.id_isar5 =3D t; + + t =3D cpu->isar.id_isar6; + t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); + t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); + t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); + t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); + t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); + cpu->isar.id_isar6 =3D t; + + t =3D cpu->isar.mvfr1; + t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ + t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ + cpu->isar.mvfr1 =3D t; + + t =3D cpu->isar.mvfr2; + t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ + t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ + cpu->isar.mvfr2 =3D t; + + t =3D cpu->isar.id_mmfr3; + t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ + cpu->isar.id_mmfr3 =3D t; + + t =3D cpu->isar.id_mmfr4; + t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ + t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ + t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ + cpu->isar.id_mmfr4 =3D t; + + t =3D cpu->isar.id_pfr0; + t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); + cpu->isar.id_pfr0 =3D t; + + t =3D cpu->isar.id_pfr2; + t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); + cpu->isar.id_pfr2 =3D t; + + t =3D cpu->isar.id_dfr0; + t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ + cpu->isar.id_dfr0 =3D t; +} + #ifndef CONFIG_USER_ONLY static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) { @@ -998,7 +1058,6 @@ static void arm_v7m_class_init(ObjectClass *oc, void *= data) static void arm_max_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); - uint32_t t; =20 /* aarch64_a57_initfn, advertising none of the aarch64 features */ cpu->dtb_compatible =3D "arm,cortex-a57"; @@ -1039,58 +1098,7 @@ static void arm_max_initfn(Object *obj) cpu->ccsidr[2] =3D 0x70ffe07a; /* 2048KB L2 cache */ define_cortex_a72_a57_a53_cp_reginfo(cpu); =20 - /* Add additional features supported by QEMU */ - t =3D cpu->isar.id_isar5; - t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); - t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); - t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); - t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); - t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); - t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); - cpu->isar.id_isar5 =3D t; - - t =3D cpu->isar.id_isar6; - t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); - t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); - t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); - t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); - t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); - cpu->isar.id_isar6 =3D t; - - t =3D cpu->isar.mvfr1; - t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ - t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ - cpu->isar.mvfr1 =3D t; - - t =3D cpu->isar.mvfr2; - t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ - t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ - cpu->isar.mvfr2 =3D t; - - t =3D cpu->isar.id_mmfr3; - t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ - cpu->isar.id_mmfr3 =3D t; - - t =3D cpu->isar.id_mmfr4; - t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ - t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ - t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ - cpu->isar.id_mmfr4 =3D t; - - t =3D cpu->isar.id_pfr0; - t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); - cpu->isar.id_pfr0 =3D t; - - t =3D cpu->isar.id_pfr2; - t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); - cpu->isar.id_pfr2 =3D t; - - t =3D cpu->isar.id_dfr0; - t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ - cpu->isar.id_dfr0 =3D t; + arm32_max_features(cpu); =20 #ifdef CONFIG_USER_ONLY /* --=20 2.25.1 From nobody Mon Feb 9 17:10:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1649724085712612.3960357023195; Mon, 11 Apr 2022 17:41:25 -0700 (PDT) Received: from localhost ([::1]:59098 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ne4ay-0003qt-MV for importer@patchew.org; Mon, 11 Apr 2022 20:41:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58524) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ne4TS-0001sK-1U for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:40 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]:46737) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ne4TP-0001oa-VN for qemu-devel@nongnu.org; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id g15-20020a056a0023cf00b004e17e11cb17sm38346669pfc.111.2022.04.11.17.33.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 17:33:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=f7TMCikHYGZe4FickOXdMkS3gl97+oDV1Ibtip1y5ck=; b=DmJsujuiEnVFZkh/Mk12yaZqat+jSPXY0IOSrZWtQbr0nb45JAy50IIj0A9lqwWN7w 6mjRTGzDx1RH4oCMtxW8/VJlwBUT0yiiBWVxwKSl+9hQxW1u8NEZs1tc9cobUsDnu62a eJLQy/JgINApwgRuRSHxPPXowRfepVq37YP5s4MCW4qjTmZiZO9yXPgzmKF48Qf6tcxr j+kdc+/tmiLIVNPGFGCzIat6xjoB/pG06Gf99UwfAf5oJwnpbmsqqIAhPzLs8R8d5b3R QhzF8Aw7rt7u2/bwu1J84ctp1JIz5FCV9E6cSMoI4Me744+ZCyRhGRDv0p6LhvApEViN T92w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=f7TMCikHYGZe4FickOXdMkS3gl97+oDV1Ibtip1y5ck=; b=Jy8cq2gDTx19a1mh/Q+FH3dRqIS+fICWiFImX97khJSuhxhyCgt+F2kPF5TymBcI6l Zs9tOG+Xy8Oi25WOv/31q9cqQZI1X6/AJpwIVQGkrzA4PrLbX4Qnpdnc3HLLVf4hiQWa G73F9V5iTYVHBAOeKA1616FM6vfGPljkKeM0LYxASOjPhtHJX9s+wemEnrh48an1cNXL j7zPOSj5Si7nXzppM7IkFoGgj7jmcOqoZhmpsQFmgNgX/yFlfHHBwjMKbwFfy6cvG324 k+y0fY4D1nePqUb3tI7fo2z4f/BGQfBCBY2CWN8Z5pT02xpC8JLxt9c28Ykc+kpycot1 2Cfw== X-Gm-Message-State: AOAM532FdpjowdFE6gGih0AK6o5aAmI8sE03ZQMSoKQjfzoHSfuP2BjP gxZTAiF//UFz9Y93IrJyszFqmYeUuo9URw== X-Google-Smtp-Source: ABdhPJyvM8fYB9R32wkwYr0KgO1Wv/Nec56j1Nfa36eeRPMQpa7IL6qu9gpkRxHNRqcF1b0lPFmm4g== X-Received: by 2002:a65:6415:0:b0:39d:5138:8091 with SMTP id a21-20020a656415000000b0039d51388091mr6663450pgv.476.1649723614608; Mon, 11 Apr 2022 17:33:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 07/24] target/arm: Annotate arm_max_initfn with FEAT identifiers Date: Mon, 11 Apr 2022 17:33:09 -0700 Message-Id: <20220412003326.588530-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220412003326.588530-1-richard.henderson@linaro.org> References: <20220412003326.588530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1649724086580100001 Content-Type: text/plain; charset="utf-8" Update the legacy feature names to the current names. Provide feature names for id changes that were not marked. Sort the field updates into increasing bitfield order. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 96 ++++++++++++++++++++++---------------------- target/arm/cpu_tcg.c | 48 +++++++++++----------- 2 files changed, 72 insertions(+), 72 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 528b0f5e64..e4f630d83f 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -713,51 +713,51 @@ static void aarch64_max_initfn(Object *obj) cpu->midr =3D t; =20 t =3D cpu->isar.id_aa64isar0; - t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ t =3D FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); - t =3D FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */ cpu->isar.id_aa64isar0 =3D t; =20 t =3D cpu->isar.id_aa64isar1; - t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); - t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ cpu->isar.id_aa64isar1 =3D t; =20 t =3D cpu->isar.id_aa64pfr0; + t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); + t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ cpu->isar.id_aa64pfr0 =3D t; =20 t =3D cpu->isar.id_aa64pfr1; - t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); - t =3D FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); + t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */ + t =3D FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */ /* * Begin with full support for MTE. This will be downgraded to MTE=3D0 * during realize if the board provides no tag memory, much like * we do for EL2 with the virtualization=3Don property. */ - t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); + t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ cpu->isar.id_aa64pfr1 =3D t; =20 t =3D cpu->isar.id_aa64mmfr0; @@ -769,35 +769,35 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64mmfr0 =3D t; =20 t =3D cpu->isar.id_aa64mmfr1; - t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); - t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); - t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ cpu->isar.id_aa64mmfr1 =3D t; =20 t =3D cpu->isar.id_aa64mmfr2; - t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); - t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ cpu->isar.id_aa64mmfr2 =3D t; =20 t =3D cpu->isar.id_aa64zfr0; t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); + t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ cpu->isar.id_aa64zfr0 =3D t; =20 t =3D cpu->isar.id_aa64dfr0; - t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ + t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_aa64dfr0 =3D t; =20 /* Replicate the same data to the 32-bit id registers. */ diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 94af0c3bda..075c187286 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -27,55 +27,55 @@ void arm32_max_features(ARMCPU *cpu) =20 /* Add additional features supported by QEMU */ t =3D cpu->isar.id_isar5; - t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); - t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); - t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); + t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ + t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ + t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); - t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); - t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); + t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ + t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ cpu->isar.id_isar5 =3D t; =20 t =3D cpu->isar.id_isar6; - t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); - t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); - t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); - t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); - t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); + t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ + t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ + t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ + t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */ + t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */ + t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */ + t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */ cpu->isar.id_isar6 =3D t; =20 t =3D cpu->isar.mvfr1; - t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ - t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ + t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */ + t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */ cpu->isar.mvfr1 =3D t; =20 t =3D cpu->isar.mvfr2; - t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ - t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ + t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ + t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ cpu->isar.mvfr2 =3D t; =20 t =3D cpu->isar.id_mmfr3; - t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ + t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ cpu->isar.id_mmfr3 =3D t; =20 t =3D cpu->isar.id_mmfr4; - t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ - t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ - t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ + t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* FEAT_AA32HPD */ + t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ + t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX*/ cpu->isar.id_mmfr4 =3D t; =20 t =3D cpu->isar.id_pfr0; - t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); + t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ cpu->isar.id_pfr0 =3D t; =20 t =3D cpu->isar.id_pfr2; - t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); + t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ cpu->isar.id_pfr2 =3D t; =20 t =3D cpu->isar.id_dfr0; - t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ + t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_dfr0 =3D t; } =20 --=20 2.25.1 From nobody Mon Feb 9 17:10:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id g15-20020a056a0023cf00b004e17e11cb17sm38346669pfc.111.2022.04.11.17.33.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 17:33:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8luVauhihyr0PwbhR6mFW3lQ8iZWOtf74oqGGDI3uYM=; b=SMDna9xJ/wEfmSYqkkoBDDM6t1ZYkikLVsXMS6cUMcErY080AmRZm3dYRZNuQJpKPN tW1IYRPRz4olbl8QY4iJwlv9KQz97qdx0GvJxHpgAP6y3Ei7TO0NgymWLrEvv+bgy6Go HKo5LvKxiQEPtue8a03vbHP+DuQbReJGwCrOd1s/pt+Fbkt2Wf8X3CMzcEnTkvunUJ3Z BKhkcGOXrQifL3FJLQYgnM0GfMPJRVtzrq0Rhi/QZVI8Au/XEFPtQg3atf2iDA+29BOZ 5etx7vIMDPoHSaTBJhJ2jyKLH+KWY1e229PAg2bo+EeTUrsUvkm61Lfvd4jxJQ4WmXzP awAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8luVauhihyr0PwbhR6mFW3lQ8iZWOtf74oqGGDI3uYM=; b=GboVQvcx+THtREyy2CO6zGswu1F+XYLrdMO2hqjuMVA3BEgAt5UA//Ve6p6BdEOeH9 zAzzFQnbRa7wdPgSC/x3xwFBL6pQlWd0BefVcrOCnt9y14fxu6NjSrdSBiamLz0bGopq IWlWxD6ALKgsQr3dVK0IzrygFbiqzAbORKBtDa4G8RVpsgzDgMvsIFu6UhbMyhHKiQud PfFvFI1EQgDpwlECTXQbBxT5UnLH7J6ZjQgi4AJXGSNM9cyYGMOpmpBuus3x8ZLdmveB hacvBuiGdANbUY0HjqEm4hqNpZ975xZG49Te7Bi/AHR63Cb72S+AoHW0eytUX3fw0m2T BklA== X-Gm-Message-State: AOAM533kZG822UQ+veXJJqhr/tgX+PGqW51qbmfYmpHOR4chsQmYB47n NRZ1UgRAA7bqrBO5v6fpR7XJOTGcJjaODw== X-Google-Smtp-Source: ABdhPJz6Iwm/ZIwgbFIBBLP3jx21pMF+CQUTAFLJB2rKbqh/F6XTwukREA/PQCQRXM05ekP1O6aF6A== X-Received: by 2002:a17:902:70cc:b0:154:1cc8:9df8 with SMTP id l12-20020a17090270cc00b001541cc89df8mr35322752plt.32.1649723615480; Mon, 11 Apr 2022 17:33:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 08/24] target/arm: Use field names for manipulating EL2 and EL3 modes Date: Mon, 11 Apr 2022 17:33:10 -0700 Message-Id: <20220412003326.588530-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220412003326.588530-1-richard.henderson@linaro.org> References: <20220412003326.588530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1649724257320100001 Content-Type: text/plain; charset="utf-8" Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0 during arm_cpu_realizefn. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5d4ca7a227..6521f350f9 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1795,11 +1795,13 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) */ unset_feature(env, ARM_FEATURE_EL3); =20 - /* Disable the security extension feature bits in the processor fe= ature - * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12= ]. + /* + * Disable the security extension feature bits in the processor + * feature registers as well. */ - cpu->isar.id_pfr1 &=3D ~0xf0; - cpu->isar.id_aa64pfr0 &=3D ~0xf000; + cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECUR= ITY, 0); + cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, + ID_AA64PFR0, EL3, 0); } =20 if (!cpu->has_el2) { @@ -1830,12 +1832,14 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) } =20 if (!arm_feature(env, ARM_FEATURE_EL2)) { - /* Disable the hypervisor feature bits in the processor feature - * registers if we don't have EL2. These are id_pfr1[15:12] and - * id_aa64pfr0_el1[11:8]. + /* + * Disable the hypervisor feature bits in the processor feature + * registers if we don't have EL2. */ - cpu->isar.id_aa64pfr0 &=3D ~0xf00; - cpu->isar.id_pfr1 &=3D ~0xf000; + cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, + ID_AA64PFR0, EL2, 0); + cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, + ID_PFR1, VIRTUALIZATION, 0); } =20 #ifndef CONFIG_USER_ONLY --=20 2.25.1 From nobody Mon Feb 9 17:10:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1649724567852563.7853318786731; Mon, 11 Apr 2022 17:49:27 -0700 (PDT) Received: from localhost ([::1]:49644 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ne4ik-0008Kz-PO for importer@patchew.org; Mon, 11 Apr 2022 20:49:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58584) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ne4TU-0001sV-TM for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:42 -0400 Received: from mail-pg1-x535.google.com ([2607:f8b0:4864:20::535]:35402) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ne4TR-0001qP-Tf for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:39 -0400 Received: by mail-pg1-x535.google.com with SMTP id z128so15650784pgz.2 for ; Mon, 11 Apr 2022 17:33:37 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id g15-20020a056a0023cf00b004e17e11cb17sm38346669pfc.111.2022.04.11.17.33.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 17:33:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=13HoyrqJzJM1udVXlLkOrIOrEqLEasz9w/pSQOQ02PE=; b=uc06eI913KVDNmYMzRkLJbPSOhrbxbp6qkq/KKqcbICX32n9g4IvptMVj2R2mRJuFf 016UNTnOuYDO9LXC6UoRRzGd0B2HrDLqdaFX2X5+wwjyHKxvxlN8dSn0Zo10JXdc9qet 9lvXlu7oXj5sx+ouZwGYURkUTdU3SH/8ib3dx8GcveXE57zuRjYyKHqeW9Gx1ftynSEi arRW06W/IHZ8M1X/XcSAArQPknmP59zHuFHT9VirsdhfxldzuSOpw14pTqLtbEnTk5br OpfdEXkuqB4LDuu9yrn2cNS15nhwj5nzcPowkNOiGoR7rkBWGx8qAdF5ATRz4FQdBOYW U21Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=13HoyrqJzJM1udVXlLkOrIOrEqLEasz9w/pSQOQ02PE=; b=r31OidhIuZXztjBzWBZZ9B2N9OYdUPIarO6EgQw7XcdwVLNNRwJB8Y5Q6hnfrIhLEw u+oh64bMfg5eDHoTrqKn6/qM5rRLwlb3SeWoZT4ooAql8HfofJihqMJxeEP74MPGTG4O 6yYxOpNd3TvH+NtKOGH74aNLKpDJZxqRyvHqxAToqJ2xRVLcbB6eH8SiGCjzJrLK4USi INjQX/GtosjYflsy+FxamUoSTmUwCw7W3LwrN+mj6s93r90jxXBwA1MEQ45EjKlMpshe 62q2GDKuEFJfww7ludi1gKipmlCGLcUx83dMNJgDstsqENTk/0/AMma8e+dwG0EVgckt nVgA== X-Gm-Message-State: AOAM5307yxyWDzNLMmDmDtmgL40dmKG5Bj7f+fE9p4zkfADjN3jOP4z6 Ao8YdCdCDYSz6WkNN7Qsg53N9xw3jU70BQ== X-Google-Smtp-Source: ABdhPJxCqKisSonD+PTzMm9vzIhZkxz1rIDQWrFWV/gsSCposLHfNmgGuX0N0sN4x2bUNMI7D/FB9A== X-Received: by 2002:a05:6a02:10d:b0:381:f4c8:ad26 with SMTP id bg13-20020a056a02010d00b00381f4c8ad26mr28294821pgb.135.1649723616468; Mon, 11 Apr 2022 17:33:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 09/24] target/arm: Enable FEAT_Debugv8p2 for -cpu max Date: Mon, 11 Apr 2022 17:33:11 -0700 Message-Id: <20220412003326.588530-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220412003326.588530-1-richard.henderson@linaro.org> References: <20220412003326.588530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1649724569201100001 Content-Type: text/plain; charset="utf-8" The only portion of FEAT_Debugv8p2 that is relevant to QEMU is CONTEXTIDR_EL2, which is also conditionally implemented with FEAT_VHE. The rest of the debug extension concerns the External debug interface, which is outside the scope of QEMU. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update emulation.rst --- docs/system/arm/emulation.rst | 1 + target/arm/cpu.c | 1 + target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 2 ++ 4 files changed, 5 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 520fd39071..035f7cf9d0 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -13,6 +13,7 @@ the following architecture extensions: - FEAT_BTI (Branch Target Identification) - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) +- FEAT_Debugv8p2 (Debug changes for v8.2) - FEAT_DotProd (Advanced SIMD dot product instructions) - FEAT_FCMA (Floating-point complex number instructions) - FEAT_FHM (Floating-point half-precision multiplication instructions) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6521f350f9..d815d3a397 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1800,6 +1800,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * feature registers as well. */ cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECUR= ITY, 0); + cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSD= BG, 0); cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, EL3, 0); } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index e4f630d83f..33570c3b6d 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -797,6 +797,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64zfr0 =3D t; =20 t =3D cpu->isar.id_aa64dfr0; + t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */ t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_aa64dfr0 =3D t; =20 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 075c187286..e719696412 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -75,6 +75,8 @@ void arm32_max_features(ARMCPU *cpu) cpu->isar.id_pfr2 =3D t; =20 t =3D cpu->isar.id_dfr0; + t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */ + t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */ t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_dfr0 =3D t; } --=20 2.25.1 From nobody Mon Feb 9 17:10:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164972425138485.09066661618033; Mon, 11 Apr 2022 17:44:11 -0700 (PDT) Received: from localhost ([::1]:39456 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ne4de-0001Jt-4g for importer@patchew.org; Mon, 11 Apr 2022 20:44:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58630) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ne4TW-0001tc-1k for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:42 -0400 Received: from mail-pj1-x102b.google.com ([2607:f8b0:4864:20::102b]:40833) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ne4TT-0001qd-Ib for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:41 -0400 Received: by mail-pj1-x102b.google.com with SMTP id md20-20020a17090b23d400b001cb70ef790dso947914pjb.5 for ; Mon, 11 Apr 2022 17:33:38 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id g15-20020a056a0023cf00b004e17e11cb17sm38346669pfc.111.2022.04.11.17.33.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 17:33:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dtTGUMiSnFk96I625AJId4KHgbX9clvONkgy858IMl4=; b=kZ28dxrfHx3bNs4mON+0J38Vn00gfc3gAEQoai0tGz9dnd9JSsqO77qIRLIEue5Z9l zSOy8AaEcivvdrGBFI80NZGoqjgCAIGESvh4XxZG01afAka5co3Ad1HGSeb8D0LtzD+K FghvytqIigYO7AlSgVZRk/DjeacTUzFaxxAbu5lEUIEOw18ob3RY+0ZnYxvq5DN8jK6y /XBouTWJU6fXKAohZvWJEIjhKQ3qqikc1+dmHRNeVWpHHxpMZhLygEkuqfhDsZD7N7hl DNr1DL5NRm4Zc0SwbyJLNx390gYCAAXlc/vlnIAuooDsKgb5JVmOjFN5zBtC6ZLPAq7/ +84A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dtTGUMiSnFk96I625AJId4KHgbX9clvONkgy858IMl4=; b=bMDukrkOMBe9NmtVUdTrNPFMs6EG2BcGg5DdeHpWKVADqlOsYQX3Q4Gyun+6UxbOSN Sl37JyZLAMYUHSQ5cTHavmCAd48wAl8uQ6KO50TiUufl+SQn/Um1zNMqhc1EiVJjTvfG Hl95eyfuJrkraUNM+Svyj9CExqdm5WJlbYLfxfpTVTkitwlx/eo8KShUpm16vvxrnGp4 aYOq25MMwULQkBZFJz0NGzPTqZvMPk0CnI3OJywKagILnXcsZFbDkl4LFLCZ54FVD6qV Y4BIOYgYZA+SWsgPVcwl0ub8A1j/MY26HqW/5//Zj7y9TGnGFGgO3HTpi4MM2rJlYAyP afCg== X-Gm-Message-State: AOAM532zsmbtN3tSnjJWCCaKj/fhvz301AlrHwb6r2ldhqeCFLKXnbxe HDf5Rs5YS6AhqoAWQeWETRUik4R3YuMkvg== X-Google-Smtp-Source: ABdhPJwbXH438hGT9lld7wnOJP5xMDJCaUbF9QmtpGPc0aF9RPw2nXWYFrTajilMcYVr3gLU4nzFTA== X-Received: by 2002:a17:902:ef4d:b0:156:82dc:b7e1 with SMTP id e13-20020a170902ef4d00b0015682dcb7e1mr35105530plx.78.1649723617264; Mon, 11 Apr 2022 17:33:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 10/24] target/arm: Enable FEAT_Debugv8p4 for -cpu max Date: Mon, 11 Apr 2022 17:33:12 -0700 Message-Id: <20220412003326.588530-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220412003326.588530-1-richard.henderson@linaro.org> References: <20220412003326.588530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1649724253326100001 Content-Type: text/plain; charset="utf-8" This extension concerns changes to the External Debug interface, with Secure and Non-secure access to the debug registers, and all of it is outside the scope of QEMU. Indicating support for this is mandatory with FEAT_SEL2, which we do implement. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update emulation.rst --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 2 +- target/arm/cpu_tcg.c | 4 ++-- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 035f7cf9d0..c89c344de1 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -14,6 +14,7 @@ the following architecture extensions: - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) - FEAT_Debugv8p2 (Debug changes for v8.2) +- FEAT_Debugv8p4 (Debug changes for v8.4) - FEAT_DotProd (Advanced SIMD dot product instructions) - FEAT_FCMA (Floating-point complex number instructions) - FEAT_FHM (Floating-point half-precision multiplication instructions) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 33570c3b6d..9bed76342f 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -797,7 +797,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64zfr0 =3D t; =20 t =3D cpu->isar.id_aa64dfr0; - t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */ + t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */ t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_aa64dfr0 =3D t; =20 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index e719696412..4ff4f30e89 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -75,8 +75,8 @@ void arm32_max_features(ARMCPU *cpu) cpu->isar.id_pfr2 =3D t; =20 t =3D cpu->isar.id_dfr0; - t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */ - t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */ + t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */ + t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */ t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_dfr0 =3D t; } --=20 2.25.1 From nobody Mon Feb 9 17:10:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1649724284039837.411245698177; Mon, 11 Apr 2022 17:44:44 -0700 (PDT) Received: from localhost ([::1]:40474 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ne4eB-0001yr-3C for importer@patchew.org; Mon, 11 Apr 2022 20:44:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58628) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ne4TV-0001tb-Vx for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:42 -0400 Received: from mail-pf1-x436.google.com ([2607:f8b0:4864:20::436]:35335) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ne4TU-0001r0-Gf for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:41 -0400 Received: by mail-pf1-x436.google.com with SMTP id f3so16039172pfe.2 for ; Mon, 11 Apr 2022 17:33:38 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id g15-20020a056a0023cf00b004e17e11cb17sm38346669pfc.111.2022.04.11.17.33.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 17:33:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=faNCwnEjGzcd9KzSFRXFlNXpqp9BiPt3SM3b4mcstDA=; b=XyhiXgBpnmX0x0ZB3uBjnGU45f8+HPMmDIXqpbs6g6U3PLGcEoq5EGJvXih9jqIulJ Zwz/B3wzl1imDPZGxnaEhp3T7qbzIPWLcqNShucXuSMywKDUQEp13xMWtIBVz2fQRD/r IVFDsZhWoWQhRfDZlq9KA84up3N7uuaDXIHI6y5W43QfmQ9P5wse/LsxxygForRHE1YF EX2pIp9xt5j+XbMHnULpg9ghf69aIDAk11OwOLIPasVBXrfv89A8Sn5F3ycXbkgxpc+1 YnDhobKnqZfrZShKpxGm8feE0zdyJCe4KOCqWbiUiUDhF4tp7Q76no5VhJAmU/I0Cw+j RlBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=faNCwnEjGzcd9KzSFRXFlNXpqp9BiPt3SM3b4mcstDA=; b=rRWYctva/bM4UCJD0A9vEENa4Rhihx0GzSjeI89mMt/PqMGnbS2LrAbz4B5G44x0h/ HcZ+0XKg+0b5e07IIFPw6+kMa7LWmBrivQjWzWHz5AodduHgEUEWMjV3eVyDco4U4F+I v2r4VvqRRIZEtFHpXadnj4ulsZMspeVPTZxhdwM4OQFcgBAxdxsCH1RvGyeGwwK618DX y012hIWEuWd+SzguN1REx8xuVwqmLZXGvOXp5WluCd+uURWdu7mjYxnQLd8JWBzUVgXR QavQs7eInPblrJEWWfgpcGmoxPCBbEBk8DdoaPuOl4tgLjGEwCsLJKItZkX0U3zKA9Lu dG/Q== X-Gm-Message-State: AOAM533tdfH+PopXWyNErvafbfb/dOKH9NoZscBlctDuq1TeGlsg4Rwn zdiriMjJv4nKYBuA6nDDLZGj65ouMLIKKg== X-Google-Smtp-Source: ABdhPJwRfxz8xPRg3yOt1FOsk0DbWVNtitpvyThmYYgxOIh4tiWTQthLsRySTi7HV2Mdb4dZLtZ2lg== X-Received: by 2002:a63:e952:0:b0:382:65eb:257 with SMTP id q18-20020a63e952000000b0038265eb0257mr28518778pgj.465.1649723618004; Mon, 11 Apr 2022 17:33:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 11/24] target/arm: Add isar_feature_{aa64,any}_ras Date: Mon, 11 Apr 2022 17:33:13 -0700 Message-Id: <20220412003326.588530-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220412003326.588530-1-richard.henderson@linaro.org> References: <20220412003326.588530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1649724285483100003 Content-Type: text/plain; charset="utf-8" Add the aa64 predicate for detecting RAS support from id registers. We already have the aa32 version from the M-profile work. Add the 'any' predicate for testing both aa64 and aa32. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9c456ff23a..890001f26b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4208,6 +4208,11 @@ static inline bool isar_feature_aa64_aa32_el1(const = ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >=3D 2; } =20 +static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) !=3D 0; +} + static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) !=3D 0; @@ -4430,6 +4435,11 @@ static inline bool isar_feature_any_debugv8p2(const = ARMISARegisters *id) return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(= id); } =20 +static inline bool isar_feature_any_ras(const ARMISARegisters *id) +{ + return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id); +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ --=20 2.25.1 From nobody Mon Feb 9 17:10:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1649724251; cv=none; d=zohomail.com; s=zohoarc; b=AkA6fz/+sDaSkYpkofyGzF8LkeWFw/DYr6kllTYU2rGvvAzJ7eBRYYyxtnrrqF9wlkq16wj0zRRIiNVfUwA1yDDQgOlJ0s54rhmCRMcs8gu9W73jT/DhuNjtOOrUhXihQNCEMY+ggx3L1hdFfd3D06pkeFmR9BAtpvLc//Buok0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649724251; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=MftKlUzQkDeseaXdslWqkBX8Dus++JIPMAYpy80Nik0=; b=Cxlp4j+Exr25z4xKxzNsMzTxMZl39Xzpy7SYCkA/lEo8+kDUk5pWUtBYwSVYalYzmndq/VaeBtbc7IT6Q6tYiIjc4QQVdD/m4vrL4fxcicnDALGo4BMxhPjam9euuLvnY+BD73hvSyS8F9TkaSl0H2nEP0S4P3vhO5iU9Wk7gXQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1649724251711837.6382832822163; Mon, 11 Apr 2022 17:44:11 -0700 (PDT) Received: from localhost ([::1]:39502 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ne4de-0001Lj-J6 for importer@patchew.org; Mon, 11 Apr 2022 20:44:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58708) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ne4TX-0001ur-R5 for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:47 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]:45799) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ne4TU-0001rF-HM for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:43 -0400 Received: by mail-pl1-x636.google.com with SMTP id 12so3506743pll.12 for ; Mon, 11 Apr 2022 17:33:39 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id g15-20020a056a0023cf00b004e17e11cb17sm38346669pfc.111.2022.04.11.17.33.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 17:33:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MftKlUzQkDeseaXdslWqkBX8Dus++JIPMAYpy80Nik0=; b=H/BtuWPyvDyXbcxeihUa5X1usoa7Npv4JXuQA8lyyuhuAWAyU8M7Jgr093DhB4D63Y CaHDMDqIjnHEpX4KJ77ugEGfDmuxkPk7eyADWGsrkl9MgyEIxeDv8bifCvqm1ijjnFog 3wcvgtupGvNM4CPFth6QmTawzCBspU6q77uOkdlqBD5YQBe9Y3s3gd6xA/+9AEY0RfPX 7wrzs51gK74KOtXE7ToYbsAxZ9hxuGJMn2JFBG5cFYrVotOQ0gKwzIictpAUNjw0oqFv vL+7Du2XIp+8Whvx8eiN/g9NVmRNJ1pz3ZF1xll/43TKz6aOdhBUvDZZP5gIXaf+ITLD 6roA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MftKlUzQkDeseaXdslWqkBX8Dus++JIPMAYpy80Nik0=; b=HEbq9BXRTRhlpotjwuDgYbG+ssJxWO5rCgIaHhLVqjVlyCpvjuPFK2EdcxK8olg4Ms hNvPMq93FaxJXBZcCX4fM8T2vqJuUxq+p4hmiBY+jer4ZrP7JpQBN4tYx98iZI6RF0pb cjxBxMX1AJtGAJ9wMeyd67wz9eq0fGiIVnPNFjn6j3tIBvgdsE94zY3wqht6bIy91T6o Ct2oXOQvZJ2WqD7iStp/ReGJL2IlN3kk6hlTSXfxG3Ys3JtUua5O3jOaXUvmyt3++vaU TPMAAienwrIJJAMlzxFdyQgg7g1NaaV0N/ZP91/2VeR6imT7FRcYS4/p6pTa0uDs6sAN Xw8g== X-Gm-Message-State: AOAM531EaO4aiuevjzEpWC4UadimtDJvUA7XODTOpOgQWfvZORwhkgLu VZe7jWCx9sm3F9bH8B7YamcHqN6UubkYDw== X-Google-Smtp-Source: ABdhPJx9/KKfq5Anu8mOaRBixdBxwPhvAqWCrwgLaHGDzey0DMHaB1TPgvXcX0mv9CIprFkjKZRhPg== X-Received: by 2002:a17:902:7244:b0:158:41d3:b79b with SMTP id c4-20020a170902724400b0015841d3b79bmr12745945pll.50.1649723618691; Mon, 11 Apr 2022 17:33:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 12/24] target/arm: Add minimal RAS registers Date: Mon, 11 Apr 2022 17:33:14 -0700 Message-Id: <20220412003326.588530-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220412003326.588530-1-richard.henderson@linaro.org> References: <20220412003326.588530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1649724253343100002 Content-Type: text/plain; charset="utf-8" Add only the system registers required to implement zero error records. This means we need to save state for ERRSELR, but all values are out of range, so none of the indexed error record registers need be implemented. Add the EL2 registers required for injecting virtual SError. Signed-off-by: Richard Henderson --- v2: Leave ERRSELR_EL1 undefined. --- target/arm/cpu.h | 5 +++ target/arm/helper.c | 105 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 110 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 890001f26b..1f24eeee8b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -524,6 +524,11 @@ typedef struct CPUArchState { uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ uint64_t gcr_el1; uint64_t rgsr_el1; + + /* Minimal RAS registers */ + uint64_t disr_el1; + uint64_t vdisr_el2; + uint64_t vsesr_el2; } cp15; =20 struct { diff --git a/target/arm/helper.c b/target/arm/helper.c index 210c139818..b066a86f04 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6147,6 +6147,102 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = =3D { REGINFO_SENTINEL }; =20 +/* + * Check for traps to RAS registers, which are controlled + * by HCR_EL2.TERR and SCR_EL3.TERR. + */ +static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el =3D arm_current_el(env); + + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + int el =3D arm_current_el(env); + + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { + return env->cp15.vdisr_el2; + } + if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { + return 0; /* RAZ/WI */ + } + return env->cp15.disr_el1; +} + +static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = val) +{ + int el =3D arm_current_el(env); + + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { + env->cp15.vdisr_el2 =3D val; + return; + } + if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { + return; /* RAZ/WI */ + } + env->cp15.disr_el1 =3D val; +} + +/* + * Minimal RAS implementation with no Error Records. + * Which means that all of the Error Record registers: + * ERXADDR_EL1 + * ERXCTLR_EL1 + * ERXFR_EL1 + * ERXMISC0_EL1 + * ERXMISC1_EL1 + * ERXMISC2_EL1 + * ERXMISC3_EL1 + * ERXPFGCDN_EL1 (RASv1p1) + * ERXPFGCTL_EL1 (RASv1p1) + * ERXPFGF_EL1 (RASv1p1) + * ERXSTATUS_EL1 + * and + * ERRSELR_EL1 + * may generate UNDEFINED, which is the effect we get by not + * listing them at all. + */ +static const ARMCPRegInfo minimal_ras_reginfo_el1[] =3D { + { .name =3D "DISR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 1, + .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.disr= _el1), + .readfn =3D disr_read, .writefn =3D disr_write, .raw_writefn =3D raw= _write }, + { .name =3D "ERRIDR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 3, .opc2 =3D 0, + .access =3D PL1_R, .accessfn =3D access_terr, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo minimal_ras_reginfo_el2[] =3D { + { .name =3D "VDISR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 1, .opc2 =3D 1, + .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.vdis= r_el2) }, + { .name =3D "VSESR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 2, .opc2 =3D 3, + .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.vses= r_el2) }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo minimal_ras_reginfo_no_el2[] =3D { + { .name =3D "VDISR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 1, .opc2 =3D 1, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "VSESR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 2, .opc2 =3D 3, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + /* Return the exception level to which exceptions should be taken * via SVEAccessTrap. If an exception should be routed through * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should @@ -8452,6 +8548,15 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &ssbs_reginfo); } =20 + if (cpu_isar_feature(any_ras, cpu)) { + define_arm_cp_regs(cpu, minimal_ras_reginfo_el1); + if (arm_feature(env, ARM_FEATURE_EL2)) { + define_arm_cp_regs(cpu, minimal_ras_reginfo_el2); + } else { + define_arm_cp_regs(cpu, minimal_ras_reginfo_no_el2); + } + } + if (cpu_isar_feature(aa64_vh, cpu) || cpu_isar_feature(aa64_debugv8p2, cpu)) { if (arm_feature(env, ARM_FEATURE_EL2)) { --=20 2.25.1 From nobody Mon Feb 9 17:10:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1649724806960744.0201565831127; Mon, 11 Apr 2022 17:53:26 -0700 (PDT) Received: from localhost ([::1]:58830 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ne4mb-0007CO-U1 for importer@patchew.org; Mon, 11 Apr 2022 20:53:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58774) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ne4Tc-0001vA-F6 for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:51 -0400 Received: from mail-pj1-x102a.google.com ([2607:f8b0:4864:20::102a]:43858) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ne4TU-0001rO-Rg for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:44 -0400 Received: by mail-pj1-x102a.google.com with SMTP id b2-20020a17090a010200b001cb0c78db57so1052073pjb.2 for ; Mon, 11 Apr 2022 17:33:40 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id g15-20020a056a0023cf00b004e17e11cb17sm38346669pfc.111.2022.04.11.17.33.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 17:33:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=T/yvSxxK5KUGQ/GUB85StZPpHbnwQifk0lCtMvXSxOk=; b=IqTYOljpLcLx600eEcM+SBXVNMKLMTeLJ5LCHJrVFaUzv4+27whshnUcjijCTzHnXm lliGMWE6IbABrtZIl1fTRskQtDNh3VOPrATnYgJ5L6VkVYU+UvQB5xVxeBZnDsIkMRAg rTYU6aHt39Gpx0mmsFyO4IXcG1jnI9eUI+YzXdh2e25K1lFM+NgzTyWXaP6CZtQNojaw Eszs8auULG0Jh6CObAJrlLYylgmVCRjlY42OWTc8GGzMf3y1p0SoSID9p0lfZFFDveBs bEDCnoKib+rl82ZsXmrAwtPvby+K/3Rw9bCU794jWsrqNzCoH9q7zY9oEjFqlVeS/TQq ZqQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=T/yvSxxK5KUGQ/GUB85StZPpHbnwQifk0lCtMvXSxOk=; b=p7D8Qm5h88+cz0zhqIjfdkURWlJmdDf66pVmlI2Scv17QESE23RVBvU0BAXCxnhZCN W/jMaxYTlVbtqhhs0uT8d+bMsT97/XJ3pbuvPHgYt+AWMma3JImAqk9v/XYyZrR/NroW IMWDXZCl3NraEZdp1zSYuIQXYm6/Z83ivAPIEK1cq/7b/BE4NOwrU3q6DvKSaNfN81/7 MA2lmH5chBqhg0kPkPsIvs/s3pUMq72ZNU6xeotmN69mtBXmNsLjffBFY4fL75E1Yy2a +hqBt0cYbQrabIsP4hCgn2ips+pqnLH8/qwK6qCHxijx7WaKS/yC5s6J9DQ2tFWjs/xk zkYw== X-Gm-Message-State: AOAM533eK1Sx+plxf7DvXkcLBFJTeF1zJIn6UM9nNB+zBIbi+6seK317 EoH4fzmNeiawhggyA01+4XdUtXYhY9fXag== X-Google-Smtp-Source: ABdhPJymEK4e8vye9K9zZ8Ztv+4XmZNUNNhWvgQX06jFRTuG3Plj+KurMd/JS1vlAGnxv7Ku9QSQGw== X-Received: by 2002:a17:903:11c7:b0:154:b936:d1d4 with SMTP id q7-20020a17090311c700b00154b936d1d4mr35073116plh.78.1649723619571; Mon, 11 Apr 2022 17:33:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 13/24] target/arm: Enable SCR and HCR bits for RAS Date: Mon, 11 Apr 2022 17:33:15 -0700 Message-Id: <20220412003326.588530-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220412003326.588530-1-richard.henderson@linaro.org> References: <20220412003326.588530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1649724807545100001 Content-Type: text/plain; charset="utf-8" Enable writes to the TERR and TEA bits when RAS is enabled. These bits are otherwise RES0. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index b066a86f04..aa05a15e5c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1765,6 +1765,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) } valid_mask &=3D ~SCR_NET; =20 + if (cpu_isar_feature(aa64_ras, cpu)) { + valid_mask |=3D SCR_TERR; + } if (cpu_isar_feature(aa64_lor, cpu)) { valid_mask |=3D SCR_TLOR; } @@ -1779,6 +1782,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) } } else { valid_mask &=3D ~(SCR_RW | SCR_ST); + if (cpu_isar_feature(aa32_ras, cpu)) { + valid_mask |=3D SCR_TERR; + } } =20 if (!arm_feature(env, ARM_FEATURE_EL2)) { @@ -5289,6 +5295,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t v= alue, uint64_t valid_mask) if (cpu_isar_feature(aa64_vh, cpu)) { valid_mask |=3D HCR_E2H; } + if (cpu_isar_feature(aa64_ras, cpu)) { + valid_mask |=3D HCR_TERR | HCR_TEA; + } if (cpu_isar_feature(aa64_lor, cpu)) { valid_mask |=3D HCR_TLOR; } --=20 2.25.1 From nobody Mon Feb 9 17:10:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1649724518; cv=none; d=zohomail.com; s=zohoarc; b=RHoZqswYgH6TYJyeTtigftjDztA6VUAoJ/r5YVuAXBnSrTEjl6UhUJe1B1j/JAtWm1u7mEyOix1LO/zzIBLMmlJ2docBI5Mizu2Bldy7xkteby5yIR9s+67f0tWX+J4KcUpyOccZ9iN7qOTQEsaXZxCC1xJy1VWxgTqVPRulIEQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649724518; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=S41F4ejbIe/azbTfR7XiThoZ35VS3lYFkm3BNkKu8uE=; b=ejHGVrvyQ7JclFHYy93Q4AxXcdrDzCyPHHb7PTFbMMtaz+1DTl4pbiAvMj/s8aaY0rW0eMO4CxTD+6ARiHVhpeeImiOBaNZvP37LOfV3a/u6/g31j9SelL5DMQ3Zr/emUblJtN/sOqGm887FDf/HAQJY+c7QF68NSzUoVKPBw2c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164972451804638.376469767857316; Mon, 11 Apr 2022 17:48:38 -0700 (PDT) Received: from localhost ([::1]:48030 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ne4hx-0007G7-0c for importer@patchew.org; Mon, 11 Apr 2022 20:48:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58782) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ne4Tc-0001vE-HH for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:51 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:39602) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ne4TV-0001rf-Q3 for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:44 -0400 Received: by mail-pj1-x102f.google.com with SMTP id mp16-20020a17090b191000b001cb5efbcab6so955281pjb.4 for ; Mon, 11 Apr 2022 17:33:41 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id g15-20020a056a0023cf00b004e17e11cb17sm38346669pfc.111.2022.04.11.17.33.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 17:33:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=S41F4ejbIe/azbTfR7XiThoZ35VS3lYFkm3BNkKu8uE=; b=hrOaQHq9jAMul2XgiGvIkal5ZPwSj+oyr6t3NmPMUsH+odQRJYCA7VBMARxOHCHPZb i9rFYJ7YIcNTlbATtAFQZd1cb/6k5b7vMZJdO7QgePcUiBtroxwwvfvYANeJnuEp5iYT 4Xn/P9XCKqyoNytfQlQzrUvuQ7lfEfbKLLYZKhpFN9POKCNgRCu+Dy4wd2bl+eliUIuZ ml0UBvRsGPQaXHI/AJEoQ7w+XiQQNZx5O5ufM6NeA+AJpnVfWfkK7xYGJkrxmyQc4OWG un7J04D3EMeh6+2+Qv0CsseeUwIpMOqEEniz4P57BIGTDb7hxyF5o8hMo1cG1p76Wg0u jonQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=S41F4ejbIe/azbTfR7XiThoZ35VS3lYFkm3BNkKu8uE=; b=og8V2DZpdhyuz8eHERsDPYV2jEV6c5OF3giSHEIbVi13ozuSAzMxjxue2g3a/hdl+s /jkZcbkK0XY40yyruxPflPWfonIPYTdLAVDAVa3OTFdxDfOxy00bGU6qI+35jsFMzev5 9YbRVJvkHGXNRDvU2/rx0YhmsmGiKj4SdIjy4ZwoWARCpUg+l0cVWIKn59FFfMkJEr0k RL8VIZ2BXxAXByhDFd16F+7hHtcxHGaZi1k/63PjaMHCHw75lQa7/Zlg+temHnFDKg8H yMQXB5fr0JtkfnObCNERm1xlDdOQfFN1u13SZKtis63ntv560sIyBn9h4f1syRLQcC7g eWUg== X-Gm-Message-State: AOAM530wY2m2tNcI2d1K/wm8iguuEDCOO0tc5FbyZIiuwrxPwPAgXy6E kYD8xE1VX4xL9MAPAFXkeeRw6wUnTLskkA== X-Google-Smtp-Source: ABdhPJxPP28mWM4uGJGNZrfBWZPE2XIenEksHWn3LatrjQQHB9dgw3VTukBL9jy0zvZb8E3RQzehng== X-Received: by 2002:a17:903:1cc:b0:158:5db4:9073 with SMTP id e12-20020a17090301cc00b001585db49073mr8330395plh.154.1649723620555; Mon, 11 Apr 2022 17:33:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 14/24] target/arm: Implement virtual SError exceptions Date: Mon, 11 Apr 2022 17:33:16 -0700 Message-Id: <20220412003326.588530-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220412003326.588530-1-richard.henderson@linaro.org> References: <20220412003326.588530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1649724519191100002 Content-Type: text/plain; charset="utf-8" Virtual SError exceptions are raised by setting HCR_EL2.VSE, and are routed to EL1 just like other virtual exceptions. Signed-off-by: Richard Henderson --- v2: Honor EAE for reporting VSERR to aa32. --- target/arm/cpu.h | 2 ++ target/arm/internals.h | 8 ++++++++ target/arm/syndrome.h | 5 +++++ target/arm/cpu.c | 38 +++++++++++++++++++++++++++++++++++++- target/arm/helper.c | 40 +++++++++++++++++++++++++++++++++++++++- 5 files changed, 91 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 1f24eeee8b..7ca2463e17 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -55,6 +55,7 @@ #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ +#define EXCP_VSERR 24 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ =20 #define ARMV7M_EXCP_RESET 1 @@ -88,6 +89,7 @@ enum { #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 +#define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 =20 /* The usual mapping for an AArch64 system register to its AArch32 * counterpart is for the 32 bit world to have access to the lower diff --git a/target/arm/internals.h b/target/arm/internals.h index ca9782b9f0..5fdccb38d4 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -935,6 +935,14 @@ void arm_cpu_update_virq(ARMCPU *cpu); */ void arm_cpu_update_vfiq(ARMCPU *cpu); =20 +/** + * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit + * + * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request, + * following a change to the HCR_EL2.VSE bit. + */ +void arm_cpu_update_vserr(ARMCPU *cpu); + /** * arm_mmu_idx_el: * @env: The cpu environment diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 8cde8e7243..0cb26dde7d 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -287,4 +287,9 @@ static inline uint32_t syn_pcalignment(void) return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; } =20 +static inline uint32_t syn_serror(uint32_t extra) +{ + return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra; +} + #endif /* TARGET_ARM_SYNDROME_H */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d815d3a397..1a1b1612a8 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -84,7 +84,7 @@ static bool arm_cpu_has_work(CPUState *cs) return (cpu->power_state !=3D PSCI_OFF) && cs->interrupt_request & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD - | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ + | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR | CPU_INTERRUPT_EXITTB); } =20 @@ -508,6 +508,12 @@ static inline bool arm_excp_unmasked(CPUState *cs, uns= igned int excp_idx, return false; } return !(env->daif & PSTATE_I); + case EXCP_VSERR: + if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { + /* VIRQs are only taken when hypervized. */ + return false; + } + return !(env->daif & PSTATE_A); default: g_assert_not_reached(); } @@ -629,6 +635,17 @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int i= nterrupt_request) goto found; } } + if (interrupt_request & CPU_INTERRUPT_VSERR) { + excp_idx =3D EXCP_VSERR; + target_el =3D 1; + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { + /* Taking a virtual abort clears HCR_EL2.VSE */ + env->cp15.hcr_el2 &=3D ~HCR_VSE; + cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); + goto found; + } + } return false; =20 found: @@ -681,6 +698,25 @@ void arm_cpu_update_vfiq(ARMCPU *cpu) } } =20 +void arm_cpu_update_vserr(ARMCPU *cpu) +{ + /* + * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. + */ + CPUARMState *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); + + bool new_state =3D env->cp15.hcr_el2 & HCR_VSE; + + if (new_state !=3D ((cs->interrupt_request & CPU_INTERRUPT_VSERR) !=3D= 0)) { + if (new_state) { + cpu_interrupt(cs, CPU_INTERRUPT_VSERR); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); + } + } +} + #ifndef CONFIG_USER_ONLY static void arm_cpu_set_irq(void *opaque, int irq, int level) { diff --git a/target/arm/helper.c b/target/arm/helper.c index aa05a15e5c..c29409f060 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1873,7 +1873,12 @@ static uint64_t isr_read(CPUARMState *env, const ARM= CPRegInfo *ri) } } =20 - /* External aborts are not possible in QEMU so A bit is always clear */ + if (hcr_el2 & HCR_AMO) { + if (cs->interrupt_request & CPU_INTERRUPT_VSERR) { + ret |=3D CPSR_A; + } + } + return ret; } =20 @@ -5338,6 +5343,7 @@ static void do_hcr_write(CPUARMState *env, uint64_t v= alue, uint64_t valid_mask) g_assert(qemu_mutex_iothread_locked()); arm_cpu_update_virq(cpu); arm_cpu_update_vfiq(cpu); + arm_cpu_update_vserr(cpu); } =20 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) @@ -9527,6 +9533,7 @@ void arm_log_exception(CPUState *cs) [EXCP_LSERR] =3D "v8M LSERR UsageFault", [EXCP_UNALIGNED] =3D "v7M UNALIGNED UsageFault", [EXCP_DIVBYZERO] =3D "v7M DIVBYZERO UsageFault", + [EXCP_VSERR] =3D "Virtual SERR", }; =20 if (idx >=3D 0 && idx < ARRAY_SIZE(excnames)) { @@ -10039,6 +10046,31 @@ static void arm_cpu_do_interrupt_aarch32(CPUState = *cs) mask =3D CPSR_A | CPSR_I | CPSR_F; offset =3D 4; break; + case EXCP_VSERR: + { + /* + * Note that this is reported as a data abort, but the DFAR + * has an UNKNOWN value. Construct the SError syndrome from + * AET and ExT fields. + */ + ARMMMUFaultInfo fi =3D { .type =3D ARMFault_AsyncExternal, }; + + if (extended_addresses_enabled(env)) { + env->exception.fsr =3D arm_fi_to_lfsc(&fi); + } else { + env->exception.fsr =3D arm_fi_to_sfsc(&fi); + } + env->exception.fsr |=3D env->cp15.vsesr_el2 & 0xd000; + A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); + qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x\n", + env->exception.fsr); + + new_mode =3D ARM_CPU_MODE_ABT; + addr =3D 0x10; + mask =3D CPSR_A | CPSR_I; + offset =3D 8; + } + break; case EXCP_SMC: new_mode =3D ARM_CPU_MODE_MON; addr =3D 0x08; @@ -10259,6 +10291,12 @@ static void arm_cpu_do_interrupt_aarch64(CPUState = *cs) case EXCP_VFIQ: addr +=3D 0x100; break; + case EXCP_VSERR: + addr +=3D 0x180; + /* Construct the SError syndrome from IDS and ISS fields. */ + env->exception.syndrome =3D syn_serror(env->cp15.vsesr_el2 & 0x1ff= ffff); + env->cp15.esr_el[new_el] =3D env->exception.syndrome; + break; default: cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); } --=20 2.25.1 From nobody Mon Feb 9 17:10:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1649725011372204.00386398329874; Mon, 11 Apr 2022 17:56:51 -0700 (PDT) Received: from localhost ([::1]:37700 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ne4pu-0003eg-Ag for importer@patchew.org; Mon, 11 Apr 2022 20:56:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58778) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ne4Tc-0001vC-GU for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:51 -0400 Received: from mail-pj1-x102f.google.com ([2607:f8b0:4864:20::102f]:40837) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ne4TW-0001s1-T3 for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:45 -0400 Received: by mail-pj1-x102f.google.com with SMTP id md20-20020a17090b23d400b001cb70ef790dso948074pjb.5 for ; Mon, 11 Apr 2022 17:33:42 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id g15-20020a056a0023cf00b004e17e11cb17sm38346669pfc.111.2022.04.11.17.33.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 17:33:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JoBBg/kSFjOXyAKcvYGCO5ADafkL/tC3ktVRL7z4yew=; b=WXsxxoBZj4APndTyi5P7xAxjtSreYBr+yzse7Wh2aMGYn00MFyGrcGokp/WIMQrObv DBov/cIUfpPNQmzoPU/odYQh4MKIYjbxvLjf6A0ydbt4RW0N7aaluSNlBSMbKYt07cqR 4FfA+VYUpYWVwo6EKHRk6IsixFeDikL3xhsOtqAdPRzj/DlZ3jFa+3fnaj/HlERCofcx hVt6giRgjf5ycYpx6sICskzYSgovHDiOpcB7Y7bK/gNwpklWSTNpJrGl65QWOGXiVlQp R0gpPBCGfoDg3pJsUA9xifSbwX5W8Sw1H6J7qInb7zTx2y55OmVc1UqVv/1ZGr0/yDAA XnNQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JoBBg/kSFjOXyAKcvYGCO5ADafkL/tC3ktVRL7z4yew=; b=cX/jGWTnx1OXYFJBhS+igBb/vBOp8ACgChbZbZrA6aJdF7Rkt9xZXE7IzvOsiiO5ii 8N8ql+brWYjUwO/vfRQ4P4NVnc4xoouw9A32HPYIIx4vIhuupl6rbyY9s3fKUlMprSAC 6RjSGJ+6sVDFuRhmb8eWfzR7DBzgP5sYiI+gIZ9TPIea2xBvhIMO12TT4G6u/2/4SeIj PSWfRm0psBh7zOd+Ry4XMi6h2kY6vrgR+WnIZa4/sT3HF7u0q0AHxtoi8PIps2qHqLDa cUjYfv0ScXs1Z8FDdw12QQcUG+Jh5++CQgN9ZsCKI9IN4GSKHWNevrWbNlizA3e9FyH1 kXrA== X-Gm-Message-State: AOAM5336VYIqejXvjHDQpxZ9yreC3PN6tqhVHmTw8aq31mcjBzPYJ6yi ULI9IKcXTrJENH5sjIstEHElpHpDCKylIQ== X-Google-Smtp-Source: ABdhPJyHtoj4yFrJZfgBRTtd1BwiFhbPfOM7GvqzzrLPz74/EjVvVzl+POjbfWtNvvvZ1cEDs6W4AA== X-Received: by 2002:a17:903:186:b0:154:3606:7a73 with SMTP id z6-20020a170903018600b0015436067a73mr35276656plg.89.1649723621412; Mon, 11 Apr 2022 17:33:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 15/24] target/arm: Implement ESB instruction Date: Mon, 11 Apr 2022 17:33:17 -0700 Message-Id: <20220412003326.588530-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220412003326.588530-1-richard.henderson@linaro.org> References: <20220412003326.588530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1649725012488100001 Content-Type: text/plain; charset="utf-8" Check for and defer any pending virtual SError. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Retain m-profile check; improve comments. --- target/arm/helper.h | 1 + target/arm/a32.decode | 16 ++++++++------ target/arm/t32.decode | 18 ++++++++-------- target/arm/op_helper.c | 43 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 17 +++++++++++++++ target/arm/translate.c | 23 ++++++++++++++++++++ 6 files changed, 103 insertions(+), 15 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index b463d9343b..b1334e0c42 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -54,6 +54,7 @@ DEF_HELPER_1(wfe, void, env) DEF_HELPER_1(yield, void, env) DEF_HELPER_1(pre_hvc, void, env) DEF_HELPER_2(pre_smc, void, env, i32) +DEF_HELPER_1(vesb, void, env) =20 DEF_HELPER_3(cpsr_write, void, env, i32, i32) DEF_HELPER_2(cpsr_write_eret, void, env, i32) diff --git a/target/arm/a32.decode b/target/arm/a32.decode index fcd8cd4f7d..f2ca480949 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -187,13 +187,17 @@ SMULTT .... 0001 0110 .... 0000 .... 1110 .= ... @rd0mn =20 { { - YIELD ---- 0011 0010 0000 1111 ---- 0000 0001 - WFE ---- 0011 0010 0000 1111 ---- 0000 0010 - WFI ---- 0011 0010 0000 1111 ---- 0000 0011 + [ + YIELD ---- 0011 0010 0000 1111 ---- 0000 0001 + WFE ---- 0011 0010 0000 1111 ---- 0000 0010 + WFI ---- 0011 0010 0000 1111 ---- 0000 0011 =20 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 - # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 + # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 + + ESB ---- 0011 0010 0000 1111 ---- 0001 0000 + ] =20 # The canonical nop ends in 00000000, but the whole of the # rest of the space executes as nop if otherwise unsupported. diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 78fadef9d6..f21ad0167a 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -364,17 +364,17 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .= ... @rdm [ # Hints, and CPS { - YIELD 1111 0011 1010 1111 1000 0000 0000 0001 - WFE 1111 0011 1010 1111 1000 0000 0000 0010 - WFI 1111 0011 1010 1111 1000 0000 0000 0011 + [ + YIELD 1111 0011 1010 1111 1000 0000 0000 0001 + WFE 1111 0011 1010 1111 1000 0000 0000 0010 + WFI 1111 0011 1010 1111 1000 0000 0000 0011 =20 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV 1111 0011 1010 1111 1000 0000 0000 0100 - # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1111 0011 1010 1111 1000 0000 0000 0100 + # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 =20 - # For M-profile minimal-RAS ESB can be a NOP, which is the - # default behaviour since it is in the hint space. - # ESB 1111 0011 1010 1111 1000 0000 0001 0000 + ESB 1111 0011 1010 1111 1000 0000 0001 0000 + ] =20 # The canonical nop ends in 0000 0000, but the whole rest # of the space is "reserved hint, behaves as nop". diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 70b42b55fd..13076ee885 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -972,3 +972,46 @@ void HELPER(probe_access)(CPUARMState *env, target_ulo= ng ptr, access_type, mmu_idx, ra); } } + +/* + * This function corresponds to AArch64.vESBOperation(). + * Note that the AArch32 version is not functionally different. + */ +void HELPER(vesb)(CPUARMState *env) +{ + /* + * The EL2Enabled() check is done inside arm_hcr_el2_eff, + * and will return HCR_EL2.VSE =3D=3D 0, so nothing happens. + */ + uint64_t hcr =3D arm_hcr_el2_eff(env); + bool enabled =3D !(hcr & HCR_TGE) && (hcr & HCR_AMO); + bool pending =3D enabled && (hcr & HCR_VSE); + bool masked =3D (env->daif & PSTATE_A); + + /* If VSE pending and masked, defer the exception. */ + if (pending && masked) { + uint32_t syndrome; + + if (arm_el_is_aa64(env, 1)) { + /* Copy across IDS and ISS from VSESR. */ + syndrome =3D env->cp15.vsesr_el2 & 0x1ffffff; + } else { + ARMMMUFaultInfo fi =3D { .type =3D ARMFault_AsyncExternal }; + + if (extended_addresses_enabled(env)) { + syndrome =3D arm_fi_to_lfsc(&fi); + } else { + syndrome =3D arm_fi_to_sfsc(&fi); + } + /* Copy across AET and ExT from VSESR. */ + syndrome |=3D env->cp15.vsesr_el2 & 0xd000; + } + + /* Set VDISR_EL2.A along with the syndrome. */ + env->cp15.vdisr_el2 =3D syndrome | (1u << 31); + + /* Clear pending virtual SError */ + env->cp15.hcr_el2 &=3D ~HCR_VSE; + cpu_reset_interrupt(env_cpu(env), CPU_INTERRUPT_VSERR); + } +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9333d7be41..4fc31807ff 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1469,6 +1469,23 @@ static void handle_hint(DisasContext *s, uint32_t in= sn, gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); } break; + case 0b10000: /* ESB */ + /* Without RAS, we must implement this as NOP. */ + if (dc_isar_feature(aa64_ras, s)) { + /* + * QEMU does not have a source of physical SErrors, + * so we are only concerned with virtual SErrors. + * The pseudocode in the ARM for this case is + * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then + * AArch64.vESBOperation(); + * Most of the condition can be evaluated at translation time. + * Test for EL2 present, and defer test for SEL2 to runtime. + */ + if (s->current_el <=3D 1 && arm_dc_feature(s, ARM_FEATURE_EL2)= ) { + gen_helper_vesb(cpu_env); + } + } + break; case 0b11000: /* PACIAZ */ if (s->pauth_active) { gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], diff --git a/target/arm/translate.c b/target/arm/translate.c index bf2196b9e2..fa34b0ad4d 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6275,6 +6275,29 @@ static bool trans_WFI(DisasContext *s, arg_WFI *a) return true; } =20 +static bool trans_ESB(DisasContext *s, arg_ESB *a) +{ + /* + * For M-profile, minimal-RAS ESB can be a NOP. + * Without RAS, we must implement this as NOP. + */ + if (!arm_dc_feature(s, ARM_FEATURE_M) && dc_isar_feature(aa32_ras, s))= { + /* + * QEMU does not have a source of physical SErrors, + * so we are only concerned with virtual SErrors. + * The pseudocode in the ARM for this case is + * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then + * AArch32.vESBOperation(); + * Most of the condition can be evaluated at translation time. + * Test for EL2 present, and defer test for SEL2 to runtime. + */ + if (s->current_el <=3D 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) { + gen_helper_vesb(cpu_env); + } + } + return true; +} + static bool trans_NOP(DisasContext *s, arg_NOP *a) { return true; --=20 2.25.1 From nobody Mon Feb 9 17:10:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1649724761520458.52892204885825; Mon, 11 Apr 2022 17:52:41 -0700 (PDT) Received: from localhost ([::1]:56616 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ne4ls-0005Tl-Hp for importer@patchew.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1649724763585100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update emulation.rst --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 1 + 3 files changed, 3 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index c89c344de1..35b6f7d4de 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -41,6 +41,7 @@ the following architecture extensions: - FEAT_PMULL (PMULL, PMULL2 instructions) - FEAT_PMUv3p1 (PMU Extensions v3.1) - FEAT_PMUv3p4 (PMU Extensions v3.4) +- FEAT_RAS (Reliability, availability, and serviceability) - FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions) - FEAT_RNG (Random number generator) - FEAT_SB (Speculation Barrier) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 9bed76342f..3525aba610 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -744,6 +744,7 @@ static void aarch64_max_initfn(Object *obj) t =3D cpu->isar.id_aa64pfr0; t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, RAS, 1); /* FEAT_RAS */ t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 4ff4f30e89..4aa2eb0841 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -68,6 +68,7 @@ void arm32_max_features(ARMCPU *cpu) =20 t =3D cpu->isar.id_pfr0; t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ + t =3D FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ cpu->isar.id_pfr0 =3D t; =20 t =3D cpu->isar.id_pfr2; --=20 2.25.1 From nobody Mon Feb 9 17:10:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id g15-20020a056a0023cf00b004e17e11cb17sm38346669pfc.111.2022.04.11.17.33.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 17:33:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=T0NCGCLb0/jnRMpSTq7CEyTx8JltKRBy1weeZ4yC0a0=; b=TEzj9Fzg0ZrGdKmzZGeqDQbJM4phOLbTeoo6oJAuEPgbFgXqsA7ROtv6YdPz5Y+SIG b5cQCcNvtu88ghO1jK5dhjFlL7PlwsfjsMtTBY18FUf0OTryUhryD4uyaqh0dKiVBZ/J efNMesSBLhIFfOKo8yhp6E/daTVl4U3lxB+h0qxvLqMMGx+TxxaJqwO1nuuGoC2cHYwL 6+GyQZHjHr3LdKg5D4Bm7LQPk1Ovib3IAY+HchfNvjXUcZYGbSZlNza+FCNfbSX8+SH4 c6UCdKnDe6L7Cex30bwFdJbCFJ/r7oEMScE3eCidXRDvEJxzZwyn+cWcWiEA81tsu5Ue l1oQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=T0NCGCLb0/jnRMpSTq7CEyTx8JltKRBy1weeZ4yC0a0=; b=OPFjhVP6MLNVMoWZC3Jhk1i4ESoQJ4fo9+lw3kSQB+orBJwbepBQjKwceMBqERjAHl VQD+dJ+b731ujqKZFmg7UuRBaSe1x94csGY+IOU97HLm3rg6+cGaF9TJDAwxq2/PSsJn QEN2cxT0D5bnZ3L6Z7gXjGg3SfeFn97vWH+8vTTSRt56D4R0ZR3TgbfVKsod8eyfcW3d 3E8V4feUZUIMWamWtEqBQjvfjdntPaHrkfccx6Z1/SbdUR54fO2eYdU7M/NgNNf1gqoA erPc24/Jt2P+mWdgMa9gKFOMbwPiGIQ9a58De85SecybY3n4OVxnpIdkTzQ3KHt2NPVh g5Hw== X-Gm-Message-State: AOAM530UcBpur+8JitMIe4GCcv0odgp00kh4N/P6jcqYO/gsmAbhaN1Z tNrEBmaA+YgnHa7aOF8O3sm7bWVkonU+vA== X-Google-Smtp-Source: ABdhPJwmkcZV4UpeTvEZZ/vxVBGeEkUXQ9MSkrfcUZIA9mf9SzD5gIaA2ZQD3IpC4N+rL8fh50FXlg== X-Received: by 2002:a65:604b:0:b0:398:ebeb:ad8f with SMTP id a11-20020a65604b000000b00398ebebad8fmr29161043pgp.89.1649723623253; Mon, 11 Apr 2022 17:33:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 17/24] target/arm: Enable FEAT_IESB for -cpu max Date: Mon, 11 Apr 2022 17:33:19 -0700 Message-Id: <20220412003326.588530-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220412003326.588530-1-richard.henderson@linaro.org> References: <20220412003326.588530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1649724595299100001 Content-Type: text/plain; charset="utf-8" This feature is AArch64 only, and applies to physical SErrors, which QEMU does not implement, thus the feature is a nop. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update emulation.rst --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + 2 files changed, 2 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 35b6f7d4de..ebd9e418cc 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -24,6 +24,7 @@ the following architecture extensions: - FEAT_FlagM2 (Enhancements to flag manipulation instructions) - FEAT_HPDS (Hierarchical permission disables) - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions) +- FEAT_IESB (Implicit error synchronization event) - FEAT_JSCVT (JavaScript conversion instructions) - FEAT_LOR (Limited ordering regions) - FEAT_LPA (Large Physical Address space) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 3525aba610..c91528a12e 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -781,6 +781,7 @@ static void aarch64_max_initfn(Object *obj) t =3D cpu->isar.id_aa64mmfr2; t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ t =3D FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ cpu->isar.id_aa64mmfr2 =3D t; --=20 2.25.1 From nobody Mon Feb 9 17:10:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1649725269904979.438097295024; Mon, 11 Apr 2022 18:01:09 -0700 (PDT) Received: from localhost ([::1]:46738 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ne4u4-0001rE-Tp for importer@patchew.org; Mon, 11 Apr 2022 21:01:08 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58918) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ne4Tg-0001wC-AE for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:54 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]:45971) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ne4Tc-0001t4-5S for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:51 -0400 Received: by mail-pf1-x430.google.com with SMTP id s8so15994521pfk.12 for ; Mon, 11 Apr 2022 17:33:45 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id g15-20020a056a0023cf00b004e17e11cb17sm38346669pfc.111.2022.04.11.17.33.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 17:33:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vvaSAF9dWxfTutPcPK5woK3fG4aF2EnUyhQgs/BQ6VM=; b=j0P8wQkANITMz6s+rLKNO/c13jUInPdSaGN6UzVbkCX0Je09sfssCiYTAHdZeyZy2w SUGnijSNCR4yikcT93Mb14nANpKEhIDUFZnXiVeY0UhMWJ8ypiGK1HphFZi3SwGBhknp jgIplE+vv7sZWoqsznZscMKzFa9uw6XbPnjaJQdd27VByHHMxBsd/bpTfWBjePqAUVFi YpMrJi+lGf8letoVPF/cgfI3Ym+qWK/XeF8gaCPPz55E14xgDjjlD/Ija6HHWH3JD5Jr WdHXD2SEg5ntOcJ59j/KN2V2Om1Hk8+L/eb7FF3t6g84RTA7vjwnV8QJa1P5NFG59+0q 4+Jg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vvaSAF9dWxfTutPcPK5woK3fG4aF2EnUyhQgs/BQ6VM=; b=nG30ozVTkYefUO18FgVJhuTBp1FJHTwd6Io2GqKOa7mhdErJR8R57ML8UEl4Kt3OT5 kDbDwA8Ku7uad5A2jLMJfHcrxYG8d0bmAey8AuSLMkvz0UEDO5BA4KqYB68YnOmoF0Vs io8KKxBIatFlrrdZZM4l/sX2pOBcsmhWKjoLhkatk9wi+RYMcC7iHh0q6KHA5VlYEINJ jxbU/rVDvfdSOyF7l0+04CJYOVbaLY472eocc9eUo4tgD25xJ5L1v88+t+iMvudc4aof KNqXqFOWhQCHIf8uGv/RY6uHAys7qaNfD86XHs8M/s9nsNEE4fczjRq+car591DVAKaz yMlA== X-Gm-Message-State: AOAM530vDlVQKoDQ85zRKoMKQjikf1sl5jQlPBJi7z6JRM0UrEh8KP+4 dqknrX6n1kYouttSmVjSoVqdnZ4ONenpow== X-Google-Smtp-Source: ABdhPJyLxdAnPfvh2JzyS6zV4tpnz7SPl0Z6B8RP49RnynUt47Yojbt/VS0KiWrb6jMFH4oWFE8HkQ== X-Received: by 2002:a05:6a00:16cd:b0:4e1:366:7ee8 with SMTP id l13-20020a056a0016cd00b004e103667ee8mr35414150pfc.9.1649723624360; Mon, 11 Apr 2022 17:33:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 18/24] target/arm: Enable FEAT_CSV2 for -cpu max Date: Mon, 11 Apr 2022 17:33:20 -0700 Message-Id: <20220412003326.588530-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220412003326.588530-1-richard.henderson@linaro.org> References: <20220412003326.588530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1649725271856100001 Content-Type: text/plain; charset="utf-8" This extension concerns branch speculation, which TCG does not implement. Thus we can trivially enable this feature. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update emulation.rst --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 1 + 3 files changed, 3 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index ebd9e418cc..91fb06c579 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -11,6 +11,7 @@ the following architecture extensions: - FEAT_AES (AESD and AESE instructions) - FEAT_BF16 (AArch64 BFloat16 instructions) - FEAT_BTI (Branch Target Identification) +- FEAT_CSV2 (Cache speculation variant 2) - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) - FEAT_Debugv8p2 (Debug changes for v8.2) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index c91528a12e..eb4bcd8e80 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -748,6 +748,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ + t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */ cpu->isar.id_aa64pfr0 =3D t; =20 t =3D cpu->isar.id_aa64pfr1; diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 4aa2eb0841..7775a84575 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -67,6 +67,7 @@ void arm32_max_features(ARMCPU *cpu) cpu->isar.id_mmfr4 =3D t; =20 t =3D cpu->isar.id_pfr0; + t =3D FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */ t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ t =3D FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ cpu->isar.id_pfr0 =3D t; --=20 2.25.1 From nobody Mon Feb 9 17:10:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1649724952679523.1835444314187; Mon, 11 Apr 2022 17:55:52 -0700 (PDT) Received: from localhost ([::1]:35906 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ne4ox-0002Lc-49 for importer@patchew.org; Mon, 11 Apr 2022 20:55:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58972) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ne4Th-0001xl-F2 for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:54 -0400 Received: from mail-pj1-x102c.google.com ([2607:f8b0:4864:20::102c]:52811) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ne4Te-0001tG-Hx for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:53 -0400 Received: by mail-pj1-x102c.google.com with SMTP id 2so16791761pjw.2 for ; Mon, 11 Apr 2022 17:33:46 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id g15-20020a056a0023cf00b004e17e11cb17sm38346669pfc.111.2022.04.11.17.33.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 17:33:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YGfVz/mtd/7TyEjQ5MUVLAJWvuqAaTmixj5X4q+cSZw=; b=cncMBZNvZgstyTU2HLsZBc55Pi7sFE9kREpXjCAjwmgPKdcduh+OUtsGgL1N5dC/YB eI6H0vP0MYabYeuUVYffDJTPg83sn3KwRpIq3Y0MSD+DOURG0YSRMgwtzBway9tv0J/y Dv7w0xyhNExiAd3uI1a5JxqEgrFc5J5kXDIhRmjX3QtFtEZYepNNmRGuJ3BniBmw3dEp pDO+9iglHhG5meyv9caEivIpz1kTfVZL6wEnchkYEVHdV/A8ByagzUgtdbO5C7yP59d3 SUM16FALn6/rB1Vxyt3TmDiqv9neefw/zFXBQ6A7rj3ZockbwF2HyGJ90wymkxBfsB5n VfAQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YGfVz/mtd/7TyEjQ5MUVLAJWvuqAaTmixj5X4q+cSZw=; b=nRLiseUmmghZfATyBX+hTiO4AaZdQ0VSwH1ZJe35aPKBkrnaPZ5//G2mM6jnvE3XUs 9HaIKeLB0xfJgRsaz/8AmjB4eJVuMwgsMGteNZuus/o/v0V10itHFGvwildwDvQelAQ/ i5AwVp8cxYkErRCorGQvRpUSXMw2Q18xC88aFJq2GihiAxk7zz5y/rSjOorqK+x2hqYM 5SHqc0iOLwntmDoOrXQItqC6uRpwrxhs7SurBCPeG8q1mM0xHY3+jksNe2/SONhfa7K8 GkbVGVxDFrMyo1fCLUd5HQS1YpRcjMa1gsObUXoOoylDbK9JSp9xcL1xmnPyHoMXDS5Z +kDw== X-Gm-Message-State: AOAM532pFA0yxNit0sfccJdYDYea+r3imvNYBk27CmjfwC7Kf44cz0rG qsBscoedKNBb2+WCtnmxn37rfTXY4aoqdw== X-Google-Smtp-Source: ABdhPJxVL6Q76W3rgDbHlG2tId36+ihhivhHoaY9rpuvcUSG8bvFXwOzfjwvrfSp+pqcc3nslsAXRQ== X-Received: by 2002:a17:902:c94c:b0:154:45c6:fbea with SMTP id i12-20020a170902c94c00b0015445c6fbeamr35243771pla.117.1649723625210; Mon, 11 Apr 2022 17:33:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 19/24] target/arm: Update ISAR fields for ARMv8.8 Date: Mon, 11 Apr 2022 17:33:21 -0700 Message-Id: <20220412003326.588530-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220412003326.588530-1-richard.henderson@linaro.org> References: <20220412003326.588530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102c; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1649724954243100001 Content-Type: text/plain; charset="utf-8" Update isar fields per ARM DDI0487 H.a. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Add ID_AA64DFR0.HPMN0 --- target/arm/cpu.h | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7ca2463e17..6793336b5e 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1940,6 +1940,7 @@ FIELD(ID_MMFR4, CCIDX, 24, 4) FIELD(ID_MMFR4, EVT, 28, 4) =20 FIELD(ID_MMFR5, ETS, 0, 4) +FIELD(ID_MMFR5, NTLBPA, 4, 4) =20 FIELD(ID_PFR0, STATE0, 0, 4) FIELD(ID_PFR0, STATE1, 4, 4) @@ -1992,6 +1993,16 @@ FIELD(ID_AA64ISAR1, SPECRES, 40, 4) FIELD(ID_AA64ISAR1, BF16, 44, 4) FIELD(ID_AA64ISAR1, DGH, 48, 4) FIELD(ID_AA64ISAR1, I8MM, 52, 4) +FIELD(ID_AA64ISAR1, XS, 56, 4) +FIELD(ID_AA64ISAR1, LS64, 60, 4) + +FIELD(ID_AA64ISAR2, WFXT, 0, 4) +FIELD(ID_AA64ISAR2, RPRES, 4, 4) +FIELD(ID_AA64ISAR2, GPA3, 8, 4) +FIELD(ID_AA64ISAR2, APA3, 12, 4) +FIELD(ID_AA64ISAR2, MOPS, 16, 4) +FIELD(ID_AA64ISAR2, BC, 20, 4) +FIELD(ID_AA64ISAR2, PAC_FRAC, 24, 4) =20 FIELD(ID_AA64PFR0, EL0, 0, 4) FIELD(ID_AA64PFR0, EL1, 4, 4) @@ -2014,6 +2025,10 @@ FIELD(ID_AA64PFR1, SSBS, 4, 4) FIELD(ID_AA64PFR1, MTE, 8, 4) FIELD(ID_AA64PFR1, RAS_FRAC, 12, 4) FIELD(ID_AA64PFR1, MPAM_FRAC, 16, 4) +FIELD(ID_AA64PFR1, SME, 24, 4) +FIELD(ID_AA64PFR1, RNDR_TRAP, 28, 4) +FIELD(ID_AA64PFR1, CSV2_FRAC, 32, 4) +FIELD(ID_AA64PFR1, NMI, 36, 4) =20 FIELD(ID_AA64MMFR0, PARANGE, 0, 4) FIELD(ID_AA64MMFR0, ASIDBITS, 4, 4) @@ -2040,6 +2055,11 @@ FIELD(ID_AA64MMFR1, SPECSEI, 24, 4) FIELD(ID_AA64MMFR1, XNX, 28, 4) FIELD(ID_AA64MMFR1, TWED, 32, 4) FIELD(ID_AA64MMFR1, ETS, 36, 4) +FIELD(ID_AA64MMFR1, HCX, 40, 4) +FIELD(ID_AA64MMFR1, AFP, 44, 4) +FIELD(ID_AA64MMFR1, NTLBPA, 48, 4) +FIELD(ID_AA64MMFR1, TIDCP1, 52, 4) +FIELD(ID_AA64MMFR1, CMOW, 56, 4) =20 FIELD(ID_AA64MMFR2, CNP, 0, 4) FIELD(ID_AA64MMFR2, UAO, 4, 4) @@ -2066,7 +2086,10 @@ FIELD(ID_AA64DFR0, CTX_CMPS, 28, 4) FIELD(ID_AA64DFR0, PMSVER, 32, 4) FIELD(ID_AA64DFR0, DOUBLELOCK, 36, 4) FIELD(ID_AA64DFR0, TRACEFILT, 40, 4) +FIELD(ID_AA64DFR0, TRACEBUFFER, 44, 4) FIELD(ID_AA64DFR0, MTPMU, 48, 4) +FIELD(ID_AA64DFR0, BRBE, 52, 4) +FIELD(ID_AA64DFR0, HPMN0, 60, 4) =20 FIELD(ID_AA64ZFR0, SVEVER, 0, 4) FIELD(ID_AA64ZFR0, AES, 4, 4) @@ -2088,6 +2111,7 @@ FIELD(ID_DFR0, PERFMON, 24, 4) FIELD(ID_DFR0, TRACEFILT, 28, 4) =20 FIELD(ID_DFR1, MTPMU, 0, 4) +FIELD(ID_DFR1, HPMN0, 4, 4) =20 FIELD(DBGDIDR, SE_IMP, 12, 1) FIELD(DBGDIDR, NSUHD_IMP, 14, 1) --=20 2.25.1 From nobody Mon Feb 9 17:10:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1649725148; cv=none; d=zohomail.com; s=zohoarc; b=N96GWEizflRfAyNa7Hrf0eap5d6Fr4Aq2o0LHtmfFB518GmcmtCcKCkkaPk9L6BMa1GKQD9lNNbYKKeDdyBEULUs80/ZjU5S2uU4y5eiqH8TpLXqS+zp/03kZREk+LgxWw+SiwasvkKZkQDLxbP7O7UUfS92E9ELg/X19gzZCcg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649725148; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OgPG6q9N2Hh+dSzUOr7wF3dwYy5RnDPQT3Bvmp/3SMY=; b=OgdUhf3EEpVBb8aVV/qVJD1/va5Zxg4MODhLj2gUYWF9YEmgt1ifkpT1laUoi57lB3rifIKzy5nS54A3bUjzrop3THqy936O+Vl9LT3R/IaiNLB6y+yaH4m4hAHICgqVkQCGHuaKX5dhfCksQ0y4IP5xZ4tiuOEnp50Qj40ikzo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1649725148466445.7204091040726; Mon, 11 Apr 2022 17:59:08 -0700 (PDT) Received: from localhost ([::1]:42204 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ne4s7-0006kK-0e for importer@patchew.org; Mon, 11 Apr 2022 20:59:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58922) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ne4Tg-0001wI-9O for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:54 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:50926) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ne4Tc-0001tO-61 for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:51 -0400 Received: by mail-pj1-x1031.google.com with SMTP id o5so4251151pjr.0 for ; Mon, 11 Apr 2022 17:33:46 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id g15-20020a056a0023cf00b004e17e11cb17sm38346669pfc.111.2022.04.11.17.33.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 17:33:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OgPG6q9N2Hh+dSzUOr7wF3dwYy5RnDPQT3Bvmp/3SMY=; b=tAVNYCMRUy8C/aQmHkGrDV2dGlgiRv27ZXO7zr/1/9kIHyEdQFlxolbN2UeYnv6RmH Zx+RCoq4LEC+5jWuKYgFwvndxU69YDE4QgPHSpvII83LKagpGL59IZtlqSFOSh5yR8+r ziTN2JPIOIRFfq/mN0/XQ6GpykUMJ36gkfKaHIGe1o6MXeAGCepIl9QwtTJCHUsPxYUu 727EgyAiKmD18b8RiU2GIdYNE9aDaO/5ye2/mLOKrcZX831E1Gb/n+9tqN8kQntGQ4U9 tHH0AQU81bi47Dt9mTIi6UwxtjRansEh4sBn8NgzL6UTyidi98bD67b7VlKnGa2abdA0 HhPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OgPG6q9N2Hh+dSzUOr7wF3dwYy5RnDPQT3Bvmp/3SMY=; b=02+tONJ6ZtnwMMIvzCS3RpJsa/sHjnQxcXkD1+GysoO3T7Fi3zN4eb2dcj4Ryps3oC 3NMM75K+H9LsO21W3PFgD2B5uU22G2r8Ita6hNUTwx0MDBkxrYu65Ll9jdUIYuamLQKA kGIPh0SSjtEtuRBXGm73/adqz+f7SBWBcxbBfqtD4QVDqcPIv6HbGmnssEGRnrZ+KjEK qFuK2pM3A2zBKbEtNPLIoYEUf6r+jHI74xy3Nyx8wd7nI1o2zhcGxyaaympUMJ+cwa5+ wDhaTp+hsD40TBXAn7830LirtBYgY9nCaK5D16ZSlza2FJSdF4utNyBTo0N4f0jk895n pIxQ== X-Gm-Message-State: AOAM532l4/U2whlJy4H3FpYkIF93afRZSc87XJChNw/PJLnpRXN8VMCJ 58F0JknXVkszbQTLFzv6dUYAEZp6IUPPSg== X-Google-Smtp-Source: ABdhPJxmQDhJFeCeEu6DqTk5SHsCSSSIytALMzSRWKMHHYbQ6IZYnT3aKQfSo7S29RFewSNINtUHJg== X-Received: by 2002:a17:902:8f94:b0:154:839b:809f with SMTP id z20-20020a1709028f9400b00154839b809fmr34390318plo.150.1649723625921; Mon, 11 Apr 2022 17:33:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 20/24] target/arm: Enable FEAT_CSV2_2 for -cpu max Date: Mon, 11 Apr 2022 17:33:22 -0700 Message-Id: <20220412003326.588530-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220412003326.588530-1-richard.henderson@linaro.org> References: <20220412003326.588530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1649725148974100001 Content-Type: text/plain; charset="utf-8" There is no branch prediction in TCG, therefore there is no need to actually include the context number into the predictor. Therefore all we need to do is add the state for SCXTNUM_ELx. Signed-off-by: Richard Henderson --- v2: Update emulation.rst; clear CSV2_FRAC; use decimal; tidy access_scxtnum. --- docs/system/arm/emulation.rst | 3 ++ target/arm/cpu.h | 16 +++++++++ target/arm/cpu64.c | 3 +- target/arm/helper.c | 67 ++++++++++++++++++++++++++++++++++- 4 files changed, 87 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 91fb06c579..aebe3be1ba 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -12,6 +12,9 @@ the following architecture extensions: - FEAT_BF16 (AArch64 BFloat16 instructions) - FEAT_BTI (Branch Target Identification) - FEAT_CSV2 (Cache speculation variant 2) +- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) +- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) +- FEAT_CSV2_2 (Cache speculation variant 2, version 2) - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) - FEAT_Debugv8p2 (Debug changes for v8.2) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 6793336b5e..4b3b537fff 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -687,6 +687,8 @@ typedef struct CPUArchState { ARMPACKey apdb; ARMPACKey apga; } keys; + + uint64_t scxtnum_el[4]; #endif =20 #if defined(CONFIG_USER_ONLY) @@ -1210,6 +1212,7 @@ void pmu_init(ARMCPU *cpu); #define SCTLR_WXN (1U << 19) #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ +#define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ @@ -4368,6 +4371,19 @@ static inline bool isar_feature_aa64_dit(const ARMIS= ARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) !=3D 0; } =20 +static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) +{ + int key =3D FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); + if (key >=3D 2) { + return true; /* FEAT_CSV2_2 */ + } + if (key =3D=3D 1) { + key =3D FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); + return key >=3D 2; /* FEAT_CSV2_1p2 */ + } + return false; +} + static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) !=3D 0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index eb4bcd8e80..98fc3ace1f 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -748,7 +748,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ - t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ cpu->isar.id_aa64pfr0 =3D t; =20 t =3D cpu->isar.id_aa64pfr1; @@ -760,6 +760,7 @@ static void aarch64_max_initfn(Object *obj) * we do for EL2 with the virtualization=3Don property. */ t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ + t =3D FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ cpu->isar.id_aa64pfr1 =3D t; =20 t =3D cpu->isar.id_aa64mmfr0; diff --git a/target/arm/helper.c b/target/arm/helper.c index c29409f060..0291666c03 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1780,6 +1780,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_mte, cpu)) { valid_mask |=3D SCR_ATA; } + if (cpu_isar_feature(aa64_scxtnum, cpu)) { + valid_mask |=3D SCR_ENSCXT; + } } else { valid_mask &=3D ~(SCR_RW | SCR_ST); if (cpu_isar_feature(aa32_ras, cpu)) { @@ -5312,6 +5315,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t v= alue, uint64_t valid_mask) if (cpu_isar_feature(aa64_mte, cpu)) { valid_mask |=3D HCR_ATA | HCR_DCT | HCR_TID5; } + if (cpu_isar_feature(aa64_scxtnum, cpu)) { + valid_mask |=3D HCR_ENSCXT; + } } =20 /* Clear RES0 bits. */ @@ -5965,6 +5971,10 @@ static void define_arm_vh_e2h_redirects_aliases(ARMC= PU *cpu) { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0), "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte }, =20 + { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7), + "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12", + isar_feature_aa64_scxtnum }, + /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ }; @@ -7432,7 +7442,58 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = =3D { REGINFO_SENTINEL }; =20 -#endif +static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo = *ri, + bool isread) +{ + int el =3D arm_current_el(env); + + if (el =3D=3D 0) { + uint64_t hcr =3D arm_hcr_el2_eff(env); + if ((hcr & (HCR_TGE | HCR_E2H)) !=3D (HCR_TGE | HCR_E2H)) { + if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) { + if (hcr & HCR_TGE) { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_TRAP; + } + if (arm_is_el2_enabled(env) && !(hcr & HCR_ENSCXT)) { + return CP_ACCESS_TRAP_EL2; + } + goto no_sctlr_el2; + } + } + if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) { + return CP_ACCESS_TRAP_EL2; + } + no_sctlr_el2: + if (el < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_ENSCXT)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo scxtnum_reginfo[] =3D { + { .name =3D "SCXTNUM_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, + .access =3D PL0_RW, .accessfn =3D access_scxtnum, + .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[0]) }, + { .name =3D "SCXTNUM_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, + .access =3D PL1_RW, .accessfn =3D access_scxtnum, + .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[1]) }, + { .name =3D "SCXTNUM_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, + .access =3D PL2_RW, .accessfn =3D access_scxtnum, + .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[2]) }, + { .name =3D "SCXTNUM_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, + .access =3D PL3_RW, + .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[3]) }, + REGINFO_SENTINEL +}; +#endif /* TARGET_AARCH64 */ =20 static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo = *ri, bool isread) @@ -8632,6 +8693,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, mte_tco_ro_reginfo); define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); } + + if (cpu_isar_feature(aa64_scxtnum, cpu)) { + define_arm_cp_regs(cpu, scxtnum_reginfo); + } #endif =20 if (cpu_isar_feature(any_predinv, cpu)) { --=20 2.25.1 From nobody Mon Feb 9 17:10:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164972538455674.1582101049662; Mon, 11 Apr 2022 18:03:04 -0700 (PDT) Received: from localhost ([::1]:49546 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ne4vv-0004QQ-JL for importer@patchew.org; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id g15-20020a056a0023cf00b004e17e11cb17sm38346669pfc.111.2022.04.11.17.33.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 17:33:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0Bp2AEYW6PnMq5QzYwmOeueQXF8b6aBC6y++J377950=; b=uYd/ckj2P59vXk7M5UnUbi9bbrNaAmc+2Z+/zJa5vc9gKdadjBOr5XtGvn3fDpObGj 2HFTUN+4ArnshAt4lYrRrn1gy1Pg8+5W0Hs2bJoOVgsOEDZH1UWbABfjXSdbpJ0S5Hu4 hJR2GbDWXJdTMDAmV5x5wNrhBQzivevpzjEoMZbPAYYbVFmLkkC3GosstbVeftmWvW8G ugSFWMXMwbk6qsF8N+p7hJgiCjnDWYh6V5yb57eXnsuqhB5QYRGfF+j4E42/tsin/2SC cYd9btq7tErbUvKnjXY8L1zT71YGGj3vsplgPnLQCE8UryvaMp7UIp21Ik6gZc/5ojUB x67A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0Bp2AEYW6PnMq5QzYwmOeueQXF8b6aBC6y++J377950=; b=326RMm4lPc+E67C1Bs6jRlNDKdj8+q0/CfmZhIuU0/x+AsUkYpHCO6iqSjLP9e7IDO 7ECsLIpXWhb3OMhH6OiWZAVASDqk/qTSlQEpu93PrGCyDWeEro7DayS1+r5lZ19XHm7s N8V2iK9MmANRbi09APLrppQCPgMlb3R9z0tMWblk+GIoUCUKp0jfQR+XLk8xnTdF0FT2 RjDk8sAQCUwNNwLJ8HDdZMaoqQjYm9eXwusoAma9xUV98SdVPyAOcR3qpGrOptO39W2z vvlBixOVrgWNblo7EtePF2TGMgEXQ90HjaCVAWc4WOap4mFSLv8PkVCeOxnft1FaPMx4 AvKA== X-Gm-Message-State: AOAM531LC2YmyynzxWGznseKSkI3TBWnDTvK31Ci0p5miYaNoV1Xpg4g bELbCYTYYKJTdC2jWXSnX4lQhU0/lzfPmw== X-Google-Smtp-Source: ABdhPJwJNjxCGWzh8x77POBK69TkdSBGhu7WpinWlqbPlnCciefZ7r2LyO65d1cDQ1YgpgTXbl8fIg== X-Received: by 2002:a05:6a00:a26:b0:4fd:f9dd:549c with SMTP id p38-20020a056a000a2600b004fdf9dd549cmr35308176pfh.42.1649723626814; Mon, 11 Apr 2022 17:33:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 21/24] target/arm: Enable FEAT_CSV3 for -cpu max Date: Mon, 11 Apr 2022 17:33:23 -0700 Message-Id: <20220412003326.588530-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220412003326.588530-1-richard.henderson@linaro.org> References: <20220412003326.588530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1649725386036100001 Content-Type: text/plain; charset="utf-8" This extension concerns cache speculation, which TCG does not implement. Thus we can trivially enable this feature. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update emulation.rst --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 1 + 3 files changed, 3 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index aebe3be1ba..f75f0fc110 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -15,6 +15,7 @@ the following architecture extensions: - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) - FEAT_CSV2_2 (Cache speculation variant 2, version 2) +- FEAT_CSV3 (Cache speculation variant 3) - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) - FEAT_Debugv8p2 (Debug changes for v8.2) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 98fc3ace1f..2b6b9afd76 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -749,6 +749,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ cpu->isar.id_aa64pfr0 =3D t; =20 t =3D cpu->isar.id_aa64pfr1; diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 7775a84575..2592d7008a 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -73,6 +73,7 @@ void arm32_max_features(ARMCPU *cpu) cpu->isar.id_pfr0 =3D t; =20 t =3D cpu->isar.id_pfr2; + t =3D FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */ t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ cpu->isar.id_pfr2 =3D t; =20 --=20 2.25.1 From nobody Mon Feb 9 17:10:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1649724517553849.5222315077602; Mon, 11 Apr 2022 17:48:37 -0700 (PDT) Received: from localhost ([::1]:48032 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ne4hw-0007G8-AP for importer@patchew.org; Mon, 11 Apr 2022 20:48:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:58966) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ne4Th-0001xk-BU for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:54 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:41681) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ne4Te-0001td-IJ for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:53 -0400 Received: by mail-pj1-x1031.google.com with SMTP id e8-20020a17090a118800b001cb13402ea2so1087026pja.0 for ; Mon, 11 Apr 2022 17:33:48 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id g15-20020a056a0023cf00b004e17e11cb17sm38346669pfc.111.2022.04.11.17.33.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 17:33:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9MdMCTNBx9cByysiLT0tBOtkhuq/SFnwgPJW7sLNEiM=; b=lUu8DYA5dHNEOkMefLoeaC702/XxU8AgEAuDP61DzTsTAFMGlccE5WL8qoPfv3lLxI 7W4rx2K20tO5oneDsR48E+NVturoka51R2ZuHjZFmn/Q2ttPIja3MFWr62McCZwKg2Ih 9TGKbSRhDoVaCZuq3yKuNYkVu32XeEeO3nm7/k2UYQqc5QfIcIb8PK6hWL0bOu86cmqN UsdXtOJjW4Sc9GJn85Hy7n3Jpuj5oXyzXrZD5vAwlJSrpzXo3KlnPbuKNMAOjivYSUsH XK8NHlS05gxtmJ/2gQEIbRN5mDAtNVpR2+DVADM5dnZFKq4ZU+M08EFbK7TmDFhaSQim /G0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9MdMCTNBx9cByysiLT0tBOtkhuq/SFnwgPJW7sLNEiM=; b=uHRa/fIsRX4C7/slTZOSbnSwntjBSYrKTd/DGWPHzIGJF2hGb7ZVxrUO5eOJUZ5gdx JKNdY27k11EHCwfriMGUl0hy4u/AwfrcbN4NAgDJY41jlbXgND6mO+3Ltaqqhvt7OUSK FLgVndsgczbHe/4Fa8uxyTKYIzn3dG77J+l78B4yDqgU5lmJmspaFJkmpJQbGJPJipKe DhGK5uJ01kI2yfZXlnTPRwbLIljg5y32Ok6dgH7JjsY616bouWL+fG8mTlK7+p6V2/kS IrzRMkycrBoVFkeNqLhrwK7DarA0NeoLfaI6dLDXNJbCns2R76Y+rPPDnOnbVJeJCWsr PouQ== X-Gm-Message-State: AOAM530O4fobGPu0iBcji0h+/deO8ODGTr3ezbGfy3qB/Ga0jU3R1tuf ++3/lL8crHfu+TUGiP1e869vpPirStQUlA== X-Google-Smtp-Source: ABdhPJx3V/VZ38I6CJiSfjH22D4kn/RB6fT9S0NXb0VLm7xx4sO0C7n1UhcIoPH6lwLNZsNRVbla1g== X-Received: by 2002:a17:902:e74d:b0:156:9d3c:4271 with SMTP id p13-20020a170902e74d00b001569d3c4271mr34600442plf.79.1649723627710; Mon, 11 Apr 2022 17:33:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 22/24] target/arm: Enable FEAT_DGH for -cpu max Date: Mon, 11 Apr 2022 17:33:24 -0700 Message-Id: <20220412003326.588530-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220412003326.588530-1-richard.henderson@linaro.org> References: <20220412003326.588530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1649724519191100001 Content-Type: text/plain; charset="utf-8" This extension concerns not merging memory access, which TCG does not implement. Thus we can trivially enable this feature. Add a comment to handle_hint for the DGH instruction, but no code. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update emulation.rst --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + target/arm/translate-a64.c | 1 + 3 files changed, 3 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index f75f0fc110..bc9cdda75a 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -16,6 +16,7 @@ the following architecture extensions: - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) - FEAT_CSV2_2 (Cache speculation variant 2, version 2) - FEAT_CSV3 (Cache speculation variant 3) +- FEAT_DGH (Data gathering hint) - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) - FEAT_Debugv8p2 (Debug changes for v8.2) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 2b6b9afd76..8934ced19a 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -738,6 +738,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ cpu->isar.id_aa64isar1 =3D t; =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 4fc31807ff..0adfa1d22c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1442,6 +1442,7 @@ static void handle_hint(DisasContext *s, uint32_t ins= n, break; case 0b00100: /* SEV */ case 0b00101: /* SEVL */ + case 0b00110: /* DGH */ /* we treat all as NOP at least for now */ break; case 0b00111: /* XPACLRI */ --=20 2.25.1 From nobody Mon Feb 9 17:10:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1649724777; cv=none; d=zohomail.com; s=zohoarc; b=UMJsFnlS2K8+FM44A9quq7tFpkavfoyq1+s4R7q/0CX145RfAMtFEUBYDctvUYdRbAw0OYdMk0PYaSKzyzLHo0J50REM0DtiYk0pGyyQbWhZanCKwfaM6pFZWw64rLZBLhwUKK+A1MYRS32AsEWiFH1sPsDyk5YmBYHBTjbZRMk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649724777; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=W7VvkB9bLVbaUbeLnPbB0Uk8wr20FyjkQ0TwGkR7VjI=; b=YIO00Gg5K5YCliT9yWPBfKq2U7MkAaY7NxaaVtnvRpgeRCmIq6GvWsCcpQrGL5HXEeOoE11KRcZI5bp+6SlbcpQNIBtQGzf7Ofp01GFA785xcKkxgV/6faD87CzuE6DSBRBRi2jA/spkNgJLPJrXQriNwximx6WJkt3STRqnDcg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1649724777359415.43406313658295; Mon, 11 Apr 2022 17:52:57 -0700 (PDT) Received: from localhost ([::1]:57776 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ne4m8-0006NA-C2 for importer@patchew.org; Mon, 11 Apr 2022 20:52:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59032) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ne4Ti-0001zb-Qy for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:55 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]:54860) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ne4Tf-0001uC-Sb for qemu-devel@nongnu.org; Mon, 11 Apr 2022 20:33:54 -0400 Received: by mail-pj1-x102e.google.com with SMTP id md4so8487690pjb.4 for ; Mon, 11 Apr 2022 17:33:49 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id g15-20020a056a0023cf00b004e17e11cb17sm38346669pfc.111.2022.04.11.17.33.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 17:33:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=W7VvkB9bLVbaUbeLnPbB0Uk8wr20FyjkQ0TwGkR7VjI=; b=UgFYTgsv9kPehH+ybmMxo3hYV1Pc3vPdmGFw4wIfGf4CObZecSASfRNjgap1nXtCaY RibDbOnVyf5yhgHvq3RO8qTyrV5CeCwaNORd+PZbjQjFnVYVPAKJebMMxXnuMQvsktGn wYLIP7Xo6/SakfGGGWUM+1+XoXmT1Fa2nT6oQAUC7QOfkfZwhoM8LrUBG/HzBTf8Jlq7 jyJSawAdxw2MDzF9XpmZv3wvKkpnJPbBtzCFaNKJ2fvvlPr+9OL4nra1yoDGgdOluhMx pYTpxQsrTz3oVGyFZAGl59sbMPQWYGnU7KWzN25qxFLsfVT+9W+uXYkfVUKDtXlnPEHE Rj0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=W7VvkB9bLVbaUbeLnPbB0Uk8wr20FyjkQ0TwGkR7VjI=; b=lL9+X30YBR75HJ8mDzshPCGY0x/HnhyphaVClHwjuXlyAY6wVuaRosvQr9/0rY+UQ4 xSnb2Tcc54mszCWqhv2bv3sX8/2qE315he0EiszdA4ThrPJtLHtU1ZeWaUHDD6v7JaVI mGmH+tpR04Jram6IyxEBSMUT0Jss43CTfzQet/It0/Vdc8vcTZCBHGk6+9pyDImYsE9O M6jB4c6HkMc71k5zhmPNEmn7DD+a1XUw1TYrdLgfML1PNDlymnNI7VWWnx9yud/3j2iW 97yqK0np2lblP07gYMsbKdTvwjJZvyYALCYVpcE+kog8w66/02fbuvuw1vMNIyt5Lufh xaKA== X-Gm-Message-State: AOAM531BZzXXVcisfXimNmtPny8BG5aNZBpS9HFpGV5ReSC+ic2Mx03a KfpxtQfEnT4aIIruebMTuMv5zYsWqP6KSA== X-Google-Smtp-Source: ABdhPJxsfaSPL7JJlLZrhIJOqxxt0m9IJmi+KDw2/VkHvYw7uPppuNm0fuFR2WVdz/L3ALtEeJtQHQ== X-Received: by 2002:a17:902:e809:b0:158:553c:3592 with SMTP id u9-20020a170902e80900b00158553c3592mr9638100plg.151.1649723628534; Mon, 11 Apr 2022 17:33:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 23/24] target/arm: Define cortex-a76 Date: Mon, 11 Apr 2022 17:33:25 -0700 Message-Id: <20220412003326.588530-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220412003326.588530-1-richard.henderson@linaro.org> References: <20220412003326.588530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1649724779456100001 Content-Type: text/plain; charset="utf-8" Enable the a76 for virt and sbsa board use. Signed-off-by: Richard Henderson --- docs/system/arm/virt.rst | 1 + hw/arm/sbsa-ref.c | 1 + hw/arm/virt.c | 1 + target/arm/cpu64.c | 66 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 69 insertions(+) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index 1544632b67..e9ff81aa21 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -55,6 +55,7 @@ Supported guest CPU types: - ``cortex-a53`` (64-bit) - ``cortex-a57`` (64-bit) - ``cortex-a72`` (64-bit) +- ``cortex-a76`` (64-bit) - ``a64fx`` (64-bit) - ``host`` (with KVM only) - ``max`` (same as ``host`` for KVM; best possible emulation with TCG) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 2387401963..2ddde88f5e 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -145,6 +145,7 @@ static const int sbsa_ref_irqmap[] =3D { static const char * const valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), + ARM_CPU_TYPE_NAME("cortex-a76"), ARM_CPU_TYPE_NAME("max"), }; =20 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index d2e5ecd234..ce15c36a7f 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -202,6 +202,7 @@ static const char *valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a53"), ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), + ARM_CPU_TYPE_NAME("cortex-a76"), ARM_CPU_TYPE_NAME("a64fx"), ARM_CPU_TYPE_NAME("host"), ARM_CPU_TYPE_NAME("max"), diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 8934ced19a..7dbd649b0c 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -194,6 +194,71 @@ static void aarch64_a72_initfn(Object *obj) define_cortex_a72_a57_a53_cp_reginfo(cpu); } =20 +static void aarch64_a76_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a76"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* Ordered by B2.4 AArch64 registers by functional group */ + cpu->clidr =3D 0x82000023; + cpu->ctr =3D 0x8444C004; + cpu->dcz_blocksize =3D 4; + cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; + cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; + cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; + cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; + cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; + cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; + cpu->isar.id_aa64pfr0 =3D 0x1100000010111112ull; /* GIC filled in lat= er */ + cpu->isar.id_aa64pfr1 =3D 0x0000000000000010ull; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_dfr0 =3D 0x04010088; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00010142; + cpu->isar.id_isar5 =3D 0x01011121; + cpu->isar.id_isar6 =3D 0x00000010; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02122211; + cpu->isar.id_mmfr4 =3D 0x00021110; + cpu->isar.id_pfr0 =3D 0x10010131; + cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ + cpu->isar.id_pfr2 =3D 0x00000011; + cpu->midr =3D 0x414fd0b1; /* r4p1 */ + cpu->revidr =3D 0; + + /* From B2.18 CCSIDR_EL1 */ + cpu->ccsidr[0] =3D 0x701fe01a; /* 64KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe01a; /* 64KB L1 icache */ + cpu->ccsidr[2] =3D 0x707fe03a; /* 512KB L2 cache */ + + /* From B2.93 SCTLR_EL3 */ + cpu->reset_sctlr =3D 0x30c50838; + + /* From B4.23 ICH_VTR_EL2 */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + + /* From B5.1 AdvSIMD AArch64 register summary */ + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x13211111; + cpu->isar.mvfr2 =3D 0x00000043; +} + void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { /* @@ -879,6 +944,7 @@ static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a57", .initfn =3D aarch64_a57_initfn }, { .name =3D "cortex-a53", .initfn =3D aarch64_a53_initfn }, { .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn }, + { .name =3D "cortex-a76", .initfn =3D aarch64_a76_initfn }, { .name =3D "a64fx", .initfn =3D aarch64_a64fx_initfn }, { .name =3D "max", .initfn =3D aarch64_max_initfn }, #if defined(CONFIG_KVM) || defined(CONFIG_HVF) --=20 2.25.1 From nobody Mon Feb 9 17:10:19 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id g15-20020a056a0023cf00b004e17e11cb17sm38346669pfc.111.2022.04.11.17.33.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 11 Apr 2022 17:33:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qbIU9/oJJWMiAyeUILBM2EtZ8CbZd4LnV/Fwi7z9ycI=; b=aduO0cpRzVGFObzgvuu2nUKS8tQsf4RUWl5DF0CZwTvzCt1TI4DQmQOYFYGXqTAHq4 KTUWwHFnb0xvi1AWusqfgA+mG4a/Z7cIfxO/s6X1NZrbaXQQf6ivmySGqrCNUyWmOfTM ZRPY26uC1t7qtX/AmKnk8BUAV7o9dAOae/Y4lyXtEYj7N3PuHRyh+j68432SwbWW0bON L5Zq/pze9GKCJ76IORidfU2Ag3Vf0a6UBscTFOQvsfyBTcQW1xlls/4fWcfdBpaIDwKU IQZD31uXFL6cDfPV8cMmeBjgUY3b03GhHoaGz5BcmDR081qsPrdM+9p4cizRy8IYyQ1K VVaw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qbIU9/oJJWMiAyeUILBM2EtZ8CbZd4LnV/Fwi7z9ycI=; b=cDCqCtDi6p9RmRJxGD94HQvT7Jq1kTdcoN1mJX7ryar092lSvNBC5LoFUdAjcAj1eS P7vst3JB8Xhi3Rxfo43pdty0iOINzWQQ+ziJfyvrMNb88mIgfS2VRARkZe9nvWXiHxtH r2CAjHCExuKTyBBa3mtxXjNePv11L+OUQfwUhwWoAlf5BTDw5zFqI35uPIXbzdlxxFVL mkkc9ruw69DSHVEvG7VazTDLz5aC0k5FD7v6K0B6u+EYMPn44TJdnqMvIENlCCYno1i6 vhrb6xYNZggGHoGQDWNBG5TQvbgnUKcAfnO/kK2qkoJVhLMctXdPqtMDxPS/jAtdLMbd GAXA== X-Gm-Message-State: AOAM533iMJz+ZaMhrQJJdLIUEEL20M/gafBPF5EceAn/WutY60SbI7kW U9ES8fC/Nr007EQkpRkyCYm6NIk4t1mvIg== X-Google-Smtp-Source: ABdhPJy+XEz6FTjKuWZZhOpOWriXqgYq4k359E6ssEPovDjNnd+E+gxLIF4GK05Ne0eEexjdhvd2wA== X-Received: by 2002:a17:903:234d:b0:158:5c45:7e19 with SMTP id c13-20020a170903234d00b001585c457e19mr8721078plh.27.1649723629371; Mon, 11 Apr 2022 17:33:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 24/24] target/arm: Define neoverse-n1 Date: Mon, 11 Apr 2022 17:33:26 -0700 Message-Id: <20220412003326.588530-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220412003326.588530-1-richard.henderson@linaro.org> References: <20220412003326.588530-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1649725478475100001 Content-Type: text/plain; charset="utf-8" Enable the n1 for virt and sbsa board use. Signed-off-by: Richard Henderson --- docs/system/arm/virt.rst | 1 + hw/arm/sbsa-ref.c | 1 + hw/arm/virt.c | 1 + target/arm/cpu64.c | 66 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 69 insertions(+) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index e9ff81aa21..e8e851a15b 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -58,6 +58,7 @@ Supported guest CPU types: - ``cortex-a76`` (64-bit) - ``a64fx`` (64-bit) - ``host`` (with KVM only) +- ``neoverse-n1`` (64-bit) - ``max`` (same as ``host`` for KVM; best possible emulation with TCG) =20 Note that the default is ``cortex-a15``, so for an AArch64 guest you must diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 2ddde88f5e..dac8860f2d 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -146,6 +146,7 @@ static const char * const valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), ARM_CPU_TYPE_NAME("cortex-a76"), + ARM_CPU_TYPE_NAME("neoverse-n1"), ARM_CPU_TYPE_NAME("max"), }; =20 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index ce15c36a7f..82dd934de6 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -204,6 +204,7 @@ static const char *valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a72"), ARM_CPU_TYPE_NAME("cortex-a76"), ARM_CPU_TYPE_NAME("a64fx"), + ARM_CPU_TYPE_NAME("neoverse-n1"), ARM_CPU_TYPE_NAME("host"), ARM_CPU_TYPE_NAME("max"), }; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 7dbd649b0c..4bfa8af833 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -259,6 +259,71 @@ static void aarch64_a76_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; } =20 +static void aarch64_neoverse_n1_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,neoverse-n1"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* Ordered by B2.4 AArch64 registers by functional group */ + cpu->clidr =3D 0x82000023; + cpu->ctr =3D 0x8444c004; + cpu->dcz_blocksize =3D 4; + cpu->isar.id_aa64dfr0 =3D 0x0000000110305408ull; + cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; + cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; + cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; + cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; + cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; + cpu->isar.id_aa64pfr0 =3D 0x1100000010111112ull; /* GIC filled in lat= er */ + cpu->isar.id_aa64pfr1 =3D 0x0000000000000020ull; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_dfr0 =3D 0x04010088; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00010142; + cpu->isar.id_isar5 =3D 0x01011121; + cpu->isar.id_isar6 =3D 0x00000010; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02122211; + cpu->isar.id_mmfr4 =3D 0x00021110; + cpu->isar.id_pfr0 =3D 0x10010131; + cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ + cpu->isar.id_pfr2 =3D 0x00000011; + cpu->midr =3D 0x414fd0c1; /* r4p1 */ + cpu->revidr =3D 0; + + /* From B2.23 CCSIDR_EL1 */ + cpu->ccsidr[0] =3D 0x701fe01a; /* 64KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe01a; /* 64KB L1 icache */ + cpu->ccsidr[2] =3D 0x70ffe03a; /* 1MB L2 cache */ + + /* From B2.98 SCTLR_EL3 */ + cpu->reset_sctlr =3D 0x30c50838; + + /* From B4.23 ICH_VTR_EL2 */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + + /* From B5.1 AdvSIMD AArch64 register summary */ + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x13211111; + cpu->isar.mvfr2 =3D 0x00000043; +} + void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { /* @@ -946,6 +1011,7 @@ static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn }, { .name =3D "cortex-a76", .initfn =3D aarch64_a76_initfn }, { .name =3D "a64fx", .initfn =3D aarch64_a64fx_initfn }, + { .name =3D "neoverse-n1", .initfn =3D aarch64_neoverse_n1_init= fn }, { .name =3D "max", .initfn =3D aarch64_max_initfn }, #if defined(CONFIG_KVM) || defined(CONFIG_HVF) { .name =3D "host", .initfn =3D aarch64_host_initfn }, --=20 2.25.1