From nobody Mon Feb 9 06:50:28 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164966069371163.93190111170827; Mon, 11 Apr 2022 00:04:53 -0700 (PDT) Received: from localhost ([::1]:47048 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ndo6U-000332-RT for importer@patchew.org; Mon, 11 Apr 2022 03:04:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43352) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ndo0y-0008FZ-LC for qemu-devel@nongnu.org; Mon, 11 Apr 2022 02:59:08 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]:28181) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ndo0w-00076P-Rj for qemu-devel@nongnu.org; Mon, 11 Apr 2022 02:59:08 -0400 Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-533-yjngtxPoOpycc_5cz9oYhA-1; Mon, 11 Apr 2022 02:59:00 -0400 Received: from smtp.corp.redhat.com (int-mx09.intmail.prod.int.rdu2.redhat.com [10.11.54.9]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 3BBDC101A52C; Mon, 11 Apr 2022 06:59:00 +0000 (UTC) Received: from gshan.redhat.com (ovpn-12-73.pek2.redhat.com [10.72.12.73]) by smtp.corp.redhat.com (Postfix) with ESMTP id D681C4029AD; Mon, 11 Apr 2022 06:58:55 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1649660346; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=q785mq9ApuEsWrBluYEOnSDLZoBJxtoDzrY7DWxqW7g=; b=Lymc1AJhU/tgpROXDyP1nOI0AGu5RHdG3GMLigGyAEh95T/8EcqJuoXxY9q0Sdvq1FI+cK WbL4fnA/T8GzJODEaNFUCnjZ2Kp8OVC+lwhDW+u4djo9h1fOukB88pfVNnezaHO1HUe3Sx psb1hWq7Pcrz6FmY3LVJsehnqPJe6g0= X-MC-Unique: yjngtxPoOpycc_5cz9oYhA-1 From: Gavin Shan To: qemu-arm@nongnu.org Subject: [PATCH 1/5] target/arm/tcg: Indirect addressing for coprocessor register storage Date: Mon, 11 Apr 2022 14:58:38 +0800 Message-Id: <20220411065842.63880-2-gshan@redhat.com> In-Reply-To: <20220411065842.63880-1-gshan@redhat.com> References: <20220411065842.63880-1-gshan@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.85 on 10.11.54.9 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=gshan@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=gshan@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, richard.henderson@linaro.org, qemu-devel@nongnu.org, eric.auger@redhat.com, agraf@csgraf.de, shan.gavin@gmail.com, pbonzini@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1649660694667100001 Content-Type: text/plain; charset="utf-8" Currently, there is an array used as the storage for the coprocessor registers. Each element in the array occupies for 8 bytes. It means we have the assumption that the size of coprocessor can't exceed 8 bytes. The storage mechanism is used by KVM either. Unfortunately, the assumption is conflicting with KVM's pseudo firmware registers, whose sizes can be variable and exceeding 8 bytes. So the storage scheme isn't working for KVM's pseudo firmware registers. This introduces another array (@cpreg_value_indexes) to track the storage location in @cpreg_values for the corresponding coprocessor register. @cpreg_value_array_len is also added to track the total storage size for all coprocessor registers. After that, the storage is addressed indirectly by @cpreg_values[cpreg_value_indexes[i]]. For TCG case, each coprocessor register still has fixed 8 bytes storage space. So the old direct addressing mechanism and new indirect addressing mechanism can co-exist and interchangeable, even in migration circumstance. Signed-off-by: Gavin Shan --- target/arm/cpu.h | 12 ++++++++++-- target/arm/helper.c | 27 +++++++++++++++++++-------- 2 files changed, 29 insertions(+), 10 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 23879de5fa..0129791b3f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -795,17 +795,25 @@ struct ArchCPU { * 64 bit indexes, not CPRegInfo 32 bit indexes) */ uint64_t *cpreg_indexes; - /* Values of the registers (cpreg_indexes[i]'s value is cpreg_values[i= ]) */ + /* + * Values of the registers + * (cpreg_indexes[i]'s value is cpreg_values[cpreg_value_indexes[i]]) + */ + uint32_t *cpreg_value_indexes; uint64_t *cpreg_values; - /* Length of the indexes, values, reset_values arrays */ + /* Length of the indexes, value indexes and values arrays */ int32_t cpreg_array_len; + int32_t cpreg_value_array_len; + /* These are used only for migration: incoming data arrives in * these fields and is sanity checked in post_load before copying * to the working data structures above. */ uint64_t *cpreg_vmstate_indexes; + uint32_t *cpreg_vmstate_value_indexes; uint64_t *cpreg_vmstate_values; int32_t cpreg_vmstate_array_len; + int32_t cpreg_vmstate_value_array_len; =20 DynamicGDBXMLInfo dyn_sysreg_xml; DynamicGDBXMLInfo dyn_svereg_xml; diff --git a/target/arm/helper.c b/target/arm/helper.c index 7d14650615..e8cb4a9edb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -163,7 +163,7 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync) * item in the list, we just recheck "does the raw write we mu= st * have made in write_list_to_cpustate() read back OK" here. */ - uint64_t oldval =3D cpu->cpreg_values[i]; + uint64_t oldval =3D cpu->cpreg_values[cpu->cpreg_value_indexes= [i]]; =20 if (oldval =3D=3D newval) { continue; @@ -176,7 +176,7 @@ bool write_cpustate_to_list(ARMCPU *cpu, bool kvm_sync) =20 write_raw_cp_reg(&cpu->env, ri, newval); } - cpu->cpreg_values[i] =3D newval; + cpu->cpreg_values[cpu->cpreg_value_indexes[i]] =3D newval; } return ok; } @@ -188,7 +188,7 @@ bool write_list_to_cpustate(ARMCPU *cpu) =20 for (i =3D 0; i < cpu->cpreg_array_len; i++) { uint32_t regidx =3D kvm_to_cpreg_id(cpu->cpreg_indexes[i]); - uint64_t v =3D cpu->cpreg_values[i]; + uint64_t v =3D cpu->cpreg_values[cpu->cpreg_value_indexes[i]]; const ARMCPRegInfo *ri; =20 ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); @@ -222,8 +222,12 @@ static void add_cpreg_to_list(gpointer key, gpointer o= paque) =20 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { cpu->cpreg_indexes[cpu->cpreg_array_len] =3D cpreg_to_kvm_id(regid= x); + cpu->cpreg_value_indexes[cpu->cpreg_array_len] =3D + cpu->cpreg_value_array_len; + /* The value array need not be initialized at this point */ cpu->cpreg_array_len++; + cpu->cpreg_value_array_len++; } } =20 @@ -238,6 +242,7 @@ static void count_cpreg(gpointer key, gpointer opaque) =20 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { cpu->cpreg_array_len++; + cpu->cpreg_value_array_len++; } } =20 @@ -261,26 +266,32 @@ void init_cpreg_list(ARMCPU *cpu) * Note that we require cpreg_tuples[] to be sorted by key ID. */ GList *keys; - int arraylen; + int arraylen, value_arraylen; =20 keys =3D g_hash_table_get_keys(cpu->cp_regs); keys =3D g_list_sort(keys, cpreg_key_compare); =20 cpu->cpreg_array_len =3D 0; - + cpu->cpreg_value_array_len =3D 0; g_list_foreach(keys, count_cpreg, cpu); =20 arraylen =3D cpu->cpreg_array_len; + value_arraylen =3D cpu->cpreg_value_array_len; cpu->cpreg_indexes =3D g_new(uint64_t, arraylen); - cpu->cpreg_values =3D g_new(uint64_t, arraylen); + cpu->cpreg_value_indexes =3D g_new(uint32_t, arraylen); + cpu->cpreg_values =3D g_new(uint64_t, value_arraylen); cpu->cpreg_vmstate_indexes =3D g_new(uint64_t, arraylen); - cpu->cpreg_vmstate_values =3D g_new(uint64_t, arraylen); + cpu->cpreg_vmstate_value_indexes =3D g_new(uint32_t, arraylen); + cpu->cpreg_vmstate_values =3D g_new(uint64_t, value_arraylen); cpu->cpreg_vmstate_array_len =3D cpu->cpreg_array_len; - cpu->cpreg_array_len =3D 0; + cpu->cpreg_vmstate_value_array_len =3D cpu->cpreg_value_array_len; =20 + cpu->cpreg_array_len =3D 0; + cpu->cpreg_value_array_len =3D 0; g_list_foreach(keys, add_cpreg_to_list, cpu); =20 assert(cpu->cpreg_array_len =3D=3D arraylen); + assert(cpu->cpreg_value_array_len =3D=3D value_arraylen); =20 g_list_free(keys); } --=20 2.23.0 From nobody Mon Feb 9 06:50:28 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1649661003116918.3290435210582; Mon, 11 Apr 2022 00:10:03 -0700 (PDT) Received: from localhost ([::1]:53308 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ndoBV-0007Pa-Sp for importer@patchew.org; Mon, 11 Apr 2022 03:10:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43374) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ndo11-0008OL-V3 for qemu-devel@nongnu.org; Mon, 11 Apr 2022 02:59:11 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]:33205) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ndo10-00076s-AJ for qemu-devel@nongnu.org; Mon, 11 Apr 2022 02:59:11 -0400 Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-108-wsi95zUcNcqt7nTWpmNhhw-1; Mon, 11 Apr 2022 02:59:05 -0400 Received: from smtp.corp.redhat.com (int-mx09.intmail.prod.int.rdu2.redhat.com [10.11.54.9]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 2CA703C14101; Mon, 11 Apr 2022 06:59:05 +0000 (UTC) Received: from gshan.redhat.com (ovpn-12-73.pek2.redhat.com [10.72.12.73]) by smtp.corp.redhat.com (Postfix) with ESMTP id ED4824029AD; Mon, 11 Apr 2022 06:59:00 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1649660349; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=AvDhijDYqHS0XYn4GNOx/lJXFpjH0PMuUN97yxxGGRY=; b=JKgM0RureOa/rGOyVcqiPDI2HkYa/yGKI6xYjL651meD8G//0a90Nr9CL6M/ZmdYKreSbB zDF9LPVLDJO6ch9LnR/+f41kUuxV55rT0PjEWKvulCGmMKZXQpQmI9dDlG/ULpUIspWCig dYcIrvsqhAPyZO4Klu9/4j2EKPmznn8= X-MC-Unique: wsi95zUcNcqt7nTWpmNhhw-1 From: Gavin Shan To: qemu-arm@nongnu.org Subject: [PATCH 2/5] target/arm/hvf: Indirect addressing for coprocessor register storage Date: Mon, 11 Apr 2022 14:58:39 +0800 Message-Id: <20220411065842.63880-3-gshan@redhat.com> In-Reply-To: <20220411065842.63880-1-gshan@redhat.com> References: <20220411065842.63880-1-gshan@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.85 on 10.11.54.9 Authentication-Results: relay.mimecast.com; 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charset="utf-8" Similar to what we did for TCG, this uses @cpreg_value_indexes[] to track the storage space for the corresponding coprocessor register. As all coprocessor register have fixed 8 bytes storage space, so the indirect and direct addressing mechanisms can co-exist and interchangeable, even in migration circumstance. Signed-off-by: Gavin Shan --- target/arm/hvf/hvf.c | 20 +++++++++++++++++--- 1 file changed, 17 insertions(+), 3 deletions(-) diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index 8c34f86792..8cca26a59c 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -334,6 +334,7 @@ int hvf_get_registers(CPUState *cpu) ARMCPU *arm_cpu =3D ARM_CPU(cpu); CPUARMState *env =3D &arm_cpu->env; hv_return_t ret; + uint32_t value_index; uint64_t val; hv_simd_fp_uchar16_t fpval; int i; @@ -373,7 +374,8 @@ int hvf_get_registers(CPUState *cpu) ret =3D hv_vcpu_get_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, &= val); assert_hvf_ok(ret); =20 - arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx] =3D val; + value_index =3D arm_cpu->cpreg_value_indexes[hvf_sreg_match[i].cp_= idx]; + arm_cpu->cpreg_values[value_index] =3D val; } assert(write_list_to_cpustate(arm_cpu)); =20 @@ -387,6 +389,7 @@ int hvf_put_registers(CPUState *cpu) ARMCPU *arm_cpu =3D ARM_CPU(cpu); CPUARMState *env =3D &arm_cpu->env; hv_return_t ret; + uint32_t value_index; uint64_t val; hv_simd_fp_uchar16_t fpval; int i; @@ -421,7 +424,8 @@ int hvf_put_registers(CPUState *cpu) continue; } =20 - val =3D arm_cpu->cpreg_values[hvf_sreg_match[i].cp_idx]; + value_index =3D arm_cpu->cpreg_value_indexes[hvf_sreg_match[i].cp_= idx]; + val =3D arm_cpu->cpreg_values[value_index]; ret =3D hv_vcpu_set_sys_reg(cpu->hvf->fd, hvf_sreg_match[i].reg, v= al); assert_hvf_ok(ret); } @@ -573,12 +577,18 @@ int hvf_arch_init_vcpu(CPUState *cpu) sregs_match_len); arm_cpu->cpreg_values =3D g_renew(uint64_t, arm_cpu->cpreg_values, sregs_match_len); + arm_cpu->cpreg_value_indexes =3D + g_renew(uint32_t, arm_cpu->cpreg_value_indexes, + sregs_match_len); arm_cpu->cpreg_vmstate_indexes =3D g_renew(uint64_t, arm_cpu->cpreg_vmstate_indexe= s, sregs_match_len); arm_cpu->cpreg_vmstate_values =3D g_renew(uint64_t, arm_cpu->cpreg_vmstate_values, sregs_match_len); + arm_cpu->cpreg_vmstate_value_indexes =3D + g_renew(uint32_t, arm_cpu->cpreg_vmstate_value_indexes, + sregs_match_len); =20 memset(arm_cpu->cpreg_values, 0, sregs_match_len * sizeof(uint64_t)); =20 @@ -591,13 +601,17 @@ int hvf_arch_init_vcpu(CPUState *cpu) if (ri) { assert(!(ri->type & ARM_CP_NO_RAW)); hvf_sreg_match[i].cp_idx =3D sregs_cnt; - arm_cpu->cpreg_indexes[sregs_cnt++] =3D cpreg_to_kvm_id(key); + arm_cpu->cpreg_indexes[sregs_cnt] =3D cpreg_to_kvm_id(key); + arm_cpu->cpreg_value_indexes[sregs_cnt] =3D sregs_cnt; + sregs_cnt++; } else { hvf_sreg_match[i].cp_idx =3D -1; } } arm_cpu->cpreg_array_len =3D sregs_cnt; + arm_cpu->cpreg_value_array_len =3D sregs_cnt; arm_cpu->cpreg_vmstate_array_len =3D sregs_cnt; + arm_cpu->cpreg_vmstate_value_array_len =3D sregs_cnt; =20 assert(write_cpustate_to_list(arm_cpu, false)); =20 --=20 2.23.0 From nobody Mon Feb 9 06:50:28 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Mon, 11 Apr 2022 02:59:10 -0400 Received: from smtp.corp.redhat.com (int-mx09.intmail.prod.int.rdu2.redhat.com [10.11.54.9]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 5F58D80005D; Mon, 11 Apr 2022 06:59:10 +0000 (UTC) Received: from gshan.redhat.com (ovpn-12-73.pek2.redhat.com [10.72.12.73]) by smtp.corp.redhat.com (Postfix) with ESMTP id 06CDF4029AD; Mon, 11 Apr 2022 06:59:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1649660354; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=gny9dwMz29Kkjo+gzDLlsFFvN9RIIvPV3i4WkFwjFKY=; b=T1gvel5lj8qlhWk3DwQLTkzGj7OJ9QqclwakRCl0KK+NjSoax8HVqpjQE0MCEmnllLYGKJ hcNh40KwB7HAXDPgKhC5Rt0am/BZjAp+3hh8FY0IugBASq1z4fgzBgl0zEV58Dk2YwNHWL aXBmLkaItgofBBfx+pQsyIkQNnlXxJU= X-MC-Unique: aIDmxVv2PrSbsIZfPOOHsA-1 From: Gavin Shan To: qemu-arm@nongnu.org Subject: [PATCH 3/5] target/arm/kvm: Indirect addressing for coprocessor register storage Date: Mon, 11 Apr 2022 14:58:40 +0800 Message-Id: <20220411065842.63880-4-gshan@redhat.com> In-Reply-To: <20220411065842.63880-1-gshan@redhat.com> References: <20220411065842.63880-1-gshan@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.85 on 10.11.54.9 Authentication-Results: relay.mimecast.com; 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charset="utf-8" Similar to what we did for TCG, this uses @cpreg_value_indexes[] to track the storage space for the corresponding coprocessor register. As all coprocessor register have fixed 8 bytes storage space, so the indirect and direct addressing mechanisms can co-exist and interchangeable, even in migration circumstance. Signed-off-by: Gavin Shan --- target/arm/kvm.c | 34 ++++++++++++++++++++++++---------- 1 file changed, 24 insertions(+), 10 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index bbf1ce7ba3..5d1ce431b0 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -429,12 +429,14 @@ static int compare_u64(const void *a, const void *b) static uint64_t *kvm_arm_get_cpreg_ptr(ARMCPU *cpu, uint64_t regidx) { uint64_t *res; + uint32_t value_index; =20 res =3D bsearch(®idx, cpu->cpreg_indexes, cpu->cpreg_array_len, sizeof(uint64_t), compare_u64); assert(res); =20 - return &cpu->cpreg_values[res - cpu->cpreg_indexes]; + value_index =3D cpu->cpreg_value_indexes[res - cpu->cpreg_indexes]; + return &cpu->cpreg_values[value_index]; } =20 /* Initialize the ARMCPU cpreg list according to the kernel's @@ -445,7 +447,7 @@ int kvm_arm_init_cpreg_list(ARMCPU *cpu) { struct kvm_reg_list rl; struct kvm_reg_list *rlp; - int i, ret, arraylen; + int i, ret, arraylen, value_arraylen; CPUState *cs =3D CPU(cpu); =20 rl.n =3D 0; @@ -464,7 +466,7 @@ int kvm_arm_init_cpreg_list(ARMCPU *cpu) */ qsort(&rlp->reg, rlp->n, sizeof(rlp->reg[0]), compare_u64); =20 - for (i =3D 0, arraylen =3D 0; i < rlp->n; i++) { + for (i =3D 0, arraylen =3D 0, value_arraylen =3D 0; i < rlp->n; i++) { if (!kvm_arm_reg_syncs_via_cpreg_list(rlp->reg[i])) { continue; } @@ -479,26 +481,36 @@ int kvm_arm_init_cpreg_list(ARMCPU *cpu) } =20 arraylen++; + value_arraylen++; } =20 cpu->cpreg_indexes =3D g_renew(uint64_t, cpu->cpreg_indexes, arraylen); - cpu->cpreg_values =3D g_renew(uint64_t, cpu->cpreg_values, arraylen); + cpu->cpreg_values =3D g_renew(uint64_t, cpu->cpreg_values, value_array= len); + cpu->cpreg_value_indexes =3D g_renew(uint32_t, cpu->cpreg_value_indexe= s, + arraylen); cpu->cpreg_vmstate_indexes =3D g_renew(uint64_t, cpu->cpreg_vmstate_in= dexes, arraylen); cpu->cpreg_vmstate_values =3D g_renew(uint64_t, cpu->cpreg_vmstate_val= ues, - arraylen); + value_arraylen); + cpu->cpreg_vmstate_value_indexes =3D + g_renew(uint32_t, cpu->cpreg_vmstate_value_indexes, arraylen); cpu->cpreg_array_len =3D arraylen; + cpu->cpreg_value_array_len =3D value_arraylen; cpu->cpreg_vmstate_array_len =3D arraylen; + cpu->cpreg_vmstate_value_array_len =3D value_arraylen; =20 - for (i =3D 0, arraylen =3D 0; i < rlp->n; i++) { + for (i =3D 0, arraylen =3D 0, value_arraylen =3D 0; i < rlp->n; i++) { uint64_t regidx =3D rlp->reg[i]; if (!kvm_arm_reg_syncs_via_cpreg_list(regidx)) { continue; } cpu->cpreg_indexes[arraylen] =3D regidx; + cpu->cpreg_value_indexes[arraylen] =3D value_arraylen; arraylen++; + value_arraylen++; } assert(cpu->cpreg_array_len =3D=3D arraylen); + assert(cpu->cpreg_value_array_len =3D=3D value_arraylen); =20 if (!write_kvmstate_to_list(cpu)) { /* Shouldn't happen unless kernel is inconsistent about @@ -533,11 +545,12 @@ bool write_kvmstate_to_list(ARMCPU *cpu) r.addr =3D (uintptr_t)&v32; ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); if (!ret) { - cpu->cpreg_values[i] =3D v32; + cpu->cpreg_values[cpu->cpreg_value_indexes[i]] =3D v32; } break; case KVM_REG_SIZE_U64: - r.addr =3D (uintptr_t)(cpu->cpreg_values + i); + r.addr =3D (uintptr_t)(cpu->cpreg_values + + cpu->cpreg_value_indexes[i]); ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); break; default: @@ -569,11 +582,12 @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level) r.id =3D regidx; switch (regidx & KVM_REG_SIZE_MASK) { case KVM_REG_SIZE_U32: - v32 =3D cpu->cpreg_values[i]; + v32 =3D cpu->cpreg_values[cpu->cpreg_value_indexes[i]]; r.addr =3D (uintptr_t)&v32; break; case KVM_REG_SIZE_U64: - r.addr =3D (uintptr_t)(cpu->cpreg_values + i); + r.addr =3D (uintptr_t)(cpu->cpreg_values + + cpu->cpreg_value_indexes[i]); break; default: abort(); --=20 2.23.0 From nobody Mon Feb 9 06:50:28 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1649661263742782.060442873471; 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Mon, 11 Apr 2022 06:59:17 +0000 (UTC) Received: from gshan.redhat.com (ovpn-12-73.pek2.redhat.com [10.72.12.73]) by smtp.corp.redhat.com (Postfix) with ESMTP id 27FA84029AD; Mon, 11 Apr 2022 06:59:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1649660361; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=aFEQw6TAiR8zpvoPxHD0fZ8/v2qfC8PwRKOENW9Vpg8=; b=PmkiMumnIwZauj1T7j8ERz1JXbXLvSZBcBTCLoH5VGTSRObyMB75v4K4dXx+Hg4IYpNpVw adXa60xfeG7FlUKKuh2gNgQ2IXG5FTGdfqz7WOJPhCvxU8UDmD34vaBz/LBHUSu3Ktq0+9 piiUjaMTYJnToj/NSM7HEFuhnu+ULF8= X-MC-Unique: ZEKaOB5JMVKmiL-XGO-ZDw-1 From: Gavin Shan To: qemu-arm@nongnu.org Subject: [PATCH 4/5] target/arm: Migrate coprocessor register indirect addressing information Date: Mon, 11 Apr 2022 14:58:41 +0800 Message-Id: <20220411065842.63880-5-gshan@redhat.com> In-Reply-To: <20220411065842.63880-1-gshan@redhat.com> References: <20220411065842.63880-1-gshan@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.85 on 10.11.54.9 Authentication-Results: relay.mimecast.com; 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charset="utf-8" This migrates @cpreg_value_array_len and @cpreg_value_indexes, which are used to indirectly addressing the storage space for the corresponding coprocessor register. Signed-off-by: Gavin Shan --- target/arm/machine.c | 30 ++++++++++++++++++++++++------ 1 file changed, 24 insertions(+), 6 deletions(-) diff --git a/target/arm/machine.c b/target/arm/machine.c index 135d2420b5..ce6f2599d8 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -677,10 +677,13 @@ static int cpu_pre_save(void *opaque) } =20 cpu->cpreg_vmstate_array_len =3D cpu->cpreg_array_len; + cpu->cpreg_vmstate_value_array_len =3D cpu->cpreg_value_array_len; memcpy(cpu->cpreg_vmstate_indexes, cpu->cpreg_indexes, cpu->cpreg_array_len * sizeof(uint64_t)); memcpy(cpu->cpreg_vmstate_values, cpu->cpreg_values, - cpu->cpreg_array_len * sizeof(uint64_t)); + cpu->cpreg_value_array_len * sizeof(uint64_t)); + memcpy(cpu->cpreg_vmstate_value_indexes, cpu->cpreg_value_indexes, + cpu->cpreg_array_len * sizeof(uint32_t)); =20 return 0; } @@ -719,7 +722,7 @@ static int cpu_post_load(void *opaque, int version_id) { ARMCPU *cpu =3D opaque; CPUARMState *env =3D &cpu->env; - int i, v; + int i, v, n; =20 /* * Handle migration compatibility from old QEMU which didn't @@ -757,8 +760,19 @@ static int cpu_post_load(void *opaque, int version_id) /* register in their list but not ours: fail migration */ return -1; } + /* matching register, copy the value over */ - cpu->cpreg_values[i] =3D cpu->cpreg_vmstate_values[v]; + if (v < cpu->cpreg_vmstate_array_len - 1) { + n =3D cpu->cpreg_vmstate_value_indexes[v + 1] - + cpu->cpreg_vmstate_value_indexes[v]; + } else { + n =3D cpu->cpreg_vmstate_value_array_len - + cpu->cpreg_vmstate_value_indexes[v]; + } + + memcpy(&cpu->cpreg_values[cpu->cpreg_value_indexes[i]], + &cpu->cpreg_vmstate_values[cpu->cpreg_vmstate_value_indexes= [v]], + n * sizeof(uint64_t)); v++; } =20 @@ -814,8 +828,8 @@ static int cpu_post_load(void *opaque, int version_id) =20 const VMStateDescription vmstate_arm_cpu =3D { .name =3D "cpu", - .version_id =3D 22, - .minimum_version_id =3D 22, + .version_id =3D 23, + .minimum_version_id =3D 23, .pre_save =3D cpu_pre_save, .post_save =3D cpu_post_save, .pre_load =3D cpu_pre_load, @@ -844,12 +858,16 @@ const VMStateDescription vmstate_arm_cpu =3D { * incoming data possibly overflowing the array. */ VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_array_len, ARMCPU), + VMSTATE_INT32_POSITIVE_LE(cpreg_vmstate_value_array_len, ARMCPU), VMSTATE_VARRAY_INT32(cpreg_vmstate_indexes, ARMCPU, cpreg_vmstate_array_len, 0, vmstate_info_uint64, uint64_t), VMSTATE_VARRAY_INT32(cpreg_vmstate_values, ARMCPU, - cpreg_vmstate_array_len, + cpreg_vmstate_value_array_len, 0, vmstate_info_uint64, uint64_t), + VMSTATE_VARRAY_INT32(cpreg_vmstate_value_indexes, ARMCPU, + cpreg_vmstate_array_len, + 0, vmstate_info_uint32, uint32_t), VMSTATE_UINT64(env.exclusive_addr, ARMCPU), VMSTATE_UINT64(env.exclusive_val, ARMCPU), VMSTATE_UINT64(env.exclusive_high, ARMCPU), --=20 2.23.0 From nobody Mon Feb 9 06:50:28 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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bh=1k22XN/WGANFpo8X0qRkJi3jP/iJeublxk7IYC0mwTM=; b=cfj6yiT6pmZtZ5yQXJFcEUu9HGOHzW3u+fc3gBkIgu4riy4Kc2RdUippOCSgCOFNosjcQt c+F4DNusRKWOGYZz0ZPPZIwFe9dzWwWchQBBppnn0duIAxsg1E9uAxTbHNxuT8MgNT0ZXA HkAsHRyF593ffiYmAyVF0vGg2zXh34A= X-MC-Unique: T9fqq_ivPeOiVHoqCPbUww-1 From: Gavin Shan To: qemu-arm@nongnu.org Subject: [PATCH 5/5] target/arm/kvm: Support coprocessor register with variable size Date: Mon, 11 Apr 2022 14:58:42 +0800 Message-Id: <20220411065842.63880-6-gshan@redhat.com> In-Reply-To: <20220411065842.63880-1-gshan@redhat.com> References: <20220411065842.63880-1-gshan@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.85 on 10.11.54.9 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=gshan@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=gshan@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: peter.maydell@linaro.org, drjones@redhat.com, richard.henderson@linaro.org, qemu-devel@nongnu.org, eric.auger@redhat.com, agraf@csgraf.de, shan.gavin@gmail.com, pbonzini@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1649661529667100001 Content-Type: text/plain; charset="utf-8" With the indirect addressing mechanism, we can support large-sized coprocessor registers. This calculates the length of @cpreg_values and allocate the storage space accordingly. @cpreg_value_indexes is also initialized according to the coprocessor register size. For those registers whose sizes are less than 8 bytes, we always reserve 8 bytes storage space for it, to gurantee the storage space address is aligned to 8 bytes. On the other hand, the storage space size for other registers are allocated based on their sizes. Signed-off-by: Gavin Shan --- target/arm/kvm.c | 55 ++++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 53 insertions(+), 2 deletions(-) diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 5d1ce431b0..71f602fd81 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -471,8 +471,18 @@ int kvm_arm_init_cpreg_list(ARMCPU *cpu) continue; } switch (rlp->reg[i] & KVM_REG_SIZE_MASK) { + case KVM_REG_SIZE_U8: + case KVM_REG_SIZE_U16: case KVM_REG_SIZE_U32: + value_arraylen++; + break; case KVM_REG_SIZE_U64: + case KVM_REG_SIZE_U128: + case KVM_REG_SIZE_U256: + case KVM_REG_SIZE_U512: + case KVM_REG_SIZE_U1024: + case KVM_REG_SIZE_U2048: + value_arraylen +=3D KVM_REG_SIZE(rlp->reg[i]) / sizeof(uint64_= t); break; default: fprintf(stderr, "Can't handle size of register in kernel list\= n"); @@ -481,7 +491,6 @@ int kvm_arm_init_cpreg_list(ARMCPU *cpu) } =20 arraylen++; - value_arraylen++; } =20 cpu->cpreg_indexes =3D g_renew(uint64_t, cpu->cpreg_indexes, arraylen); @@ -507,7 +516,13 @@ int kvm_arm_init_cpreg_list(ARMCPU *cpu) cpu->cpreg_indexes[arraylen] =3D regidx; cpu->cpreg_value_indexes[arraylen] =3D value_arraylen; arraylen++; - value_arraylen++; + + /* We validate the size just now and no need to do it again */ + if (KVM_REG_SIZE(rlp->reg[i]) < sizeof(uint64_t)) { + value_arraylen++; + } else { + value_arraylen +=3D KVM_REG_SIZE(rlp->reg[i]) / sizeof(uint64_= t); + } } assert(cpu->cpreg_array_len =3D=3D arraylen); assert(cpu->cpreg_value_array_len =3D=3D value_arraylen); @@ -535,12 +550,28 @@ bool write_kvmstate_to_list(ARMCPU *cpu) for (i =3D 0; i < cpu->cpreg_array_len; i++) { struct kvm_one_reg r; uint64_t regidx =3D cpu->cpreg_indexes[i]; + uint8_t v8; + uint16_t v16; uint32_t v32; int ret; =20 r.id =3D regidx; =20 switch (regidx & KVM_REG_SIZE_MASK) { + case KVM_REG_SIZE_U8: + r.addr =3D (uintptr_t)&v8; + ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); + if (!ret) { + cpu->cpreg_values[cpu->cpreg_value_indexes[i]] =3D v8; + } + break; + case KVM_REG_SIZE_U16: + r.addr =3D (uintptr_t)&v16; + ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); + if (!ret) { + cpu->cpreg_values[cpu->cpreg_value_indexes[i]] =3D v16; + } + break; case KVM_REG_SIZE_U32: r.addr =3D (uintptr_t)&v32; ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); @@ -549,6 +580,11 @@ bool write_kvmstate_to_list(ARMCPU *cpu) } break; case KVM_REG_SIZE_U64: + case KVM_REG_SIZE_U128: + case KVM_REG_SIZE_U256: + case KVM_REG_SIZE_U512: + case KVM_REG_SIZE_U1024: + case KVM_REG_SIZE_U2048: r.addr =3D (uintptr_t)(cpu->cpreg_values + cpu->cpreg_value_indexes[i]); ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); @@ -572,6 +608,8 @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level) for (i =3D 0; i < cpu->cpreg_array_len; i++) { struct kvm_one_reg r; uint64_t regidx =3D cpu->cpreg_indexes[i]; + uint8_t v8; + uint16_t v16; uint32_t v32; int ret; =20 @@ -581,11 +619,24 @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level) =20 r.id =3D regidx; switch (regidx & KVM_REG_SIZE_MASK) { + case KVM_REG_SIZE_U8: + v8 =3D cpu->cpreg_values[cpu->cpreg_value_indexes[i]]; + r.addr =3D (uintptr_t)&v8; + break; + case KVM_REG_SIZE_U16: + v16 =3D cpu->cpreg_values[cpu->cpreg_value_indexes[i]]; + r.addr =3D (uintptr_t)&v16; + break; case KVM_REG_SIZE_U32: v32 =3D cpu->cpreg_values[cpu->cpreg_value_indexes[i]]; r.addr =3D (uintptr_t)&v32; break; case KVM_REG_SIZE_U64: + case KVM_REG_SIZE_U128: + case KVM_REG_SIZE_U256: + case KVM_REG_SIZE_U512: + case KVM_REG_SIZE_U1024: + case KVM_REG_SIZE_U2048: r.addr =3D (uintptr_t)(cpu->cpreg_values + cpu->cpreg_value_indexes[i]); break; --=20 2.23.0