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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id t69-20020a637848000000b0039831d6dc23sm22073961pgc.94.2022.04.08.17.07.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 17:07:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=77IUNxzBr4CUo6OGOs42IJabOTHQjqxfs99nkKvtt9E=; b=SAsLnfpQTcLLx8E9ydD4RUjY6NH9oXP3sYX/r+DjhuMJS2HD1GcvacxRb9a+v5mdHs +PXYPDeSmYXCzxyTbx4FTgvdkovbTY0lwbLAjM3gjo41sBfaN0M98ib2yqlpf80HgHTV Kpg3RTs/ka42wzCJssrFISPIyW55mBSkYH7lErhLaAP1HxMaJs+7Mid2FoBIQckIqpSc hvJJQo2qxP3sEVLOKCfFE+z8wLgEBZrunHWRcBwV16qVluP4QYE96Jii8PnLt/Rl3PQD WUTFcrsMvBa9o1jf/1VK7TYvdgj/DeyIaFW8yLPirLjyuL12LvRdsuI67XmziQGIrUYl kq9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=77IUNxzBr4CUo6OGOs42IJabOTHQjqxfs99nkKvtt9E=; b=LLYP4In+mLJ6PvuJ3yOutdXWT46XRqg/yKwpIMzHtovLIlIiKwQsKPRn//3vWlqmIy SUn6hoOr6gyPFxK6sE7+GpLuOOUMJBrGT30EYWYygV5Kj6nJN0VsRjET7cg8olTPbfBe qZ1Yqde9RWeqUvzZaFJAaqZpo6utR4pcbqspkJTNtXMr69YuyHLqVX3J5peAlZ/JtW5m Unqims6XgxXYMepi2eFDBC9M5D0o5IW7MSuDpsS7/zrBQZwIVfLKvnf4WH/gOcWCOQIr oNqciwO6ok8e77D4DwkwkTS1GUm/5M2bfb2zUBMVC5Z5fLSLpN1M/O5B5qyd47g5GezP VmIw== X-Gm-Message-State: AOAM533r+oBfzLdoOGunBdhoKj0mtUHmpfbtJZBfwFeK1/kn6q1dEoqc 6g4zBBSXxVNBP96TBBRqXpU9hSYqIq68mQ== X-Google-Smtp-Source: ABdhPJxWHbyFsPK/+kf+TtLvzO7tYLUG7EX/rqWRlC3DrO2n03EsAXGbqtP8MUfKNPJXZ7imb7dcIA== X-Received: by 2002:a17:90a:5983:b0:1c9:ee11:76df with SMTP id l3-20020a17090a598300b001c9ee1176dfmr24727413pji.95.1649462869664; Fri, 08 Apr 2022 17:07:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 07/16] target/arm: Use field names for manipulating EL2 and EL3 modes Date: Fri, 8 Apr 2022 17:07:33 -0700 Message-Id: <20220409000742.293691-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220409000742.293691-1-richard.henderson@linaro.org> References: <20220409000742.293691-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1649463570697100001 Content-Type: text/plain; charset="utf-8" Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0 during arm_cpu_realizefn. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5d4ca7a227..6521f350f9 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1795,11 +1795,13 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) */ unset_feature(env, ARM_FEATURE_EL3); =20 - /* Disable the security extension feature bits in the processor fe= ature - * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12= ]. + /* + * Disable the security extension feature bits in the processor + * feature registers as well. */ - cpu->isar.id_pfr1 &=3D ~0xf0; - cpu->isar.id_aa64pfr0 &=3D ~0xf000; + cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECUR= ITY, 0); + cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, + ID_AA64PFR0, EL3, 0); } =20 if (!cpu->has_el2) { @@ -1830,12 +1832,14 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) } =20 if (!arm_feature(env, ARM_FEATURE_EL2)) { - /* Disable the hypervisor feature bits in the processor feature - * registers if we don't have EL2. These are id_pfr1[15:12] and - * id_aa64pfr0_el1[11:8]. + /* + * Disable the hypervisor feature bits in the processor feature + * registers if we don't have EL2. */ - cpu->isar.id_aa64pfr0 &=3D ~0xf00; - cpu->isar.id_pfr1 &=3D ~0xf000; + cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, + ID_AA64PFR0, EL2, 0); + cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, + ID_PFR1, VIRTUALIZATION, 0); } =20 #ifndef CONFIG_USER_ONLY --=20 2.25.1