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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id t69-20020a637848000000b0039831d6dc23sm22073961pgc.94.2022.04.08.17.07.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 17:07:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bsIZuuOFl21oF1yTY/+qyLzpHVhgT0vup4ac2EKKMU0=; b=f3tpx/2QeX/GaEjY0MjWWZiXHhYBkui0HWp6Z0QGU/Dev2qUABzf8PSIRbILQrECN6 gY3+929yIppa3fMB/14cm7PxWput/4WKAkpU4BXgthkxe/KkaVPmPAB0/Ujq6TMC42Pj pkT/7YWnQdarana54zRMB/Yy36CD2jlWVSrY8+pfcOf4f/Gof6X47tZnAbYqa7/f/aBo LMkQGwM1avrmBUeomQS3wM/QL6ZH6fLiEjXG3rZrqM5GQe8MAvxZNN99eWpzDPLde1np ch3TXSPONzjxm09D0ndyVu+0bh++6vzudopjjB8gzYeSEzFeqhA0d+zfEl5N5COWMGx4 fBfQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1649462979834100005 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 23879de5fa..9c456ff23a 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4026,6 +4026,11 @@ static inline bool isar_feature_aa32_ssbs(const ARMI= SARegisters *id) return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) !=3D 0; } =20 +static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >=3D 8; +} + /* * 64-bit feature tests via id registers. */ @@ -4332,6 +4337,11 @@ static inline bool isar_feature_aa64_ssbs(const ARMI= SARegisters *id) return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) !=3D 0; } =20 +static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >=3D 8; +} + static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) !=3D 0; @@ -4415,6 +4425,11 @@ static inline bool isar_feature_any_tts2uxn(const AR= MISARegisters *id) return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); } =20 +static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id) +{ + return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(= id); +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ --=20 2.25.1 From nobody Mon Feb 9 20:13:22 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id t69-20020a637848000000b0039831d6dc23sm22073961pgc.94.2022.04.08.17.07.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 17:07:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=VyFhrugTgFt58NiQM9eVPjxsvqh4sz6yt/2EjO+Xbh8=; b=GJNc3Mup4LvHeUDzJC453cGL0e3WGVarNSxaUmYytIMcurPaMuywUPgAjokRJRWCwN DkVnjTT35C4Ig5pE+udj02/sZyeZiEI2zuygx5eAgYk72AevXJ4euY0kqr3Z5402NlIf L9YTluALdqNTdg+Drmyzn5ooCwSSo813B5zkRDsBdACH2Fc26B2J3/l91vtMud+COfj4 wes5iJDrbX/hZQtGnWkQ6rWGSYnwDRAxCSn07aTRpoyPA023Qm0/TNkCjm/w9/DVye+l MtHblACloaKCixzzC0Dk0928VFkJfWWnZGqsN3RPQwG8FIcersInPhXVgccvvicWTXI6 qIXQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=VyFhrugTgFt58NiQM9eVPjxsvqh4sz6yt/2EjO+Xbh8=; b=IfSKRAcpYdbF7Q9Nvm7E+9JaEPIrcXQljk/muyETtz/ObZ/hpWkHk1b7kb6OuNXvSw OqoR9EvgMMbEbCLDl+O8Ywsx4VdVQAcjjA2yvrpFDJp4E6PK8VYJez5e/mAvQqccMbDy X/wNrloPnqfMGJjW9tktomVWjukscnGtFDBqhdzyCZ5Wj5vtW8Wc1EyYnFEmTawE9Pqg zxEA1b+BjiAwn3sJhRue8yGxxR7VgRpCnQOKtVu26u5HN6E5j7pvpIY6r/1PgrbS6/b8 U6SpsbpSJHhuch0Fe4EgQTWoHDHige/N5dEwtxnfP1IpLwZqo49f5XsMMS/VBj0qjhTE TzAg== X-Gm-Message-State: AOAM53158ASWSrkntINwoaRlgt90JZnsuGJAWTpADZhWNJmdlbA5l7M6 ctT5+bPBbx2atMLPWmGrG2F1hwnRxG6GlA== X-Google-Smtp-Source: ABdhPJwLGX3fFbaZSiaGrxoGrBKCr8S04f7FhKTvB+ag5NKxZPgWu/McuGbv9aG6uGXJ4Fa+Tzw97w== X-Received: by 2002:a17:902:cccf:b0:156:31a:736e with SMTP id z15-20020a170902cccf00b00156031a736emr21718756ple.76.1649462865172; Fri, 08 Apr 2022 17:07:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 02/16] target/arm: Adjust definition of CONTEXTIDR_EL2 Date: Fri, 8 Apr 2022 17:07:28 -0700 Message-Id: <20220409000742.293691-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220409000742.293691-1-richard.henderson@linaro.org> References: <20220409000742.293691-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1649462969991100001 Content-Type: text/plain; charset="utf-8" This register is present for either VHE or Debugv8p2, and is RES0 from EL3 when EL2 is not present. Move the definition out of vhe_reginfo and provide a fallback for missing EL2. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 25 +++++++++++++++++++++---- 1 file changed, 21 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 7d14650615..210c139818 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7443,11 +7443,20 @@ static const ARMCPRegInfo jazelle_regs[] =3D { REGINFO_SENTINEL }; =20 +static const ARMCPRegInfo contextidr_el2 =3D { + .name =3D "CONTEXTIDR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[2]) +}; + +static const ARMCPRegInfo contextidr_no_el2 =3D { + .name =3D "CONTEXTIDR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 +}; + static const ARMCPRegInfo vhe_reginfo[] =3D { - { .name =3D "CONTEXTIDR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, - .access =3D PL2_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[2]) }, { .name =3D "TTBR1_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, .access =3D PL2_RW, .writefn =3D vmsa_tcr_ttbr_el2_write, @@ -8443,6 +8452,14 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &ssbs_reginfo); } =20 + if (cpu_isar_feature(aa64_vh, cpu) || + cpu_isar_feature(aa64_debugv8p2, cpu)) { + if (arm_feature(env, ARM_FEATURE_EL2)) { + define_one_arm_cp_reg(cpu, &contextidr_el2); + } else { + define_one_arm_cp_reg(cpu, &contextidr_no_el2); + } + } if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= )) { define_arm_cp_regs(cpu, vhe_reginfo); } --=20 2.25.1 From nobody Mon Feb 9 20:13:22 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1649463210; cv=none; d=zohomail.com; s=zohoarc; b=HxuW5DD8wc68Yk6gvbNraOU5Tkp4lykOLLENwqfib3NWiPtra6kzFI7vLpqbjxTp8GrpIPwcKrRl7k1I+0/RKE9w1AEey7SA5QxTLT9um67k/XFP7esln65VCa6kMysj7Ys1CI1wHOIcHryaQpXLxDdsTtlb/WME2nR3HNeXVEE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649463210; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=kYlBQs73M0s8RmpgWsEfo4P2xw9UaQj0M1CIAVxBygs=; b=fyZdpTzrYg9le7H6cny+ExRcCoBZ2KP+fBfv5T6oWEwBStDhLS1WUjWFHEIBdkUXT/0YfdbJsspBdG81by0vDboSPAJY5YbsGNxakUYuzImwkJ4W9PhP64yvFmEAqLyxwDtmsAneQQSUweXKdPuJyW/Z9uLyPMz9KUO/pexlhbQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1649463210976937.2812428221797; Fri, 8 Apr 2022 17:13:30 -0700 (PDT) Received: from localhost ([::1]:44180 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ncyjJ-0001XH-W5 for importer@patchew.org; Fri, 08 Apr 2022 20:13:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46624) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ncydp-0008BS-NL for qemu-devel@nongnu.org; Fri, 08 Apr 2022 20:07:49 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]:33361) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ncydn-0003Q2-FW for qemu-devel@nongnu.org; Fri, 08 Apr 2022 20:07:49 -0400 Received: by mail-pl1-x636.google.com with SMTP id c23so9298613plo.0 for ; Fri, 08 Apr 2022 17:07:47 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id t69-20020a637848000000b0039831d6dc23sm22073961pgc.94.2022.04.08.17.07.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 17:07:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kYlBQs73M0s8RmpgWsEfo4P2xw9UaQj0M1CIAVxBygs=; b=ku8d76b2Wj+/2k6ZCWSEHAU2i8RuWBpfTZWEz6tedzulxBNIBl/NSCfCDJ2uCWy2Ni Zv3g0WegNss0MPEvLe46AnyWiS7E7fXue6Crd4STbB6Qwd1Ft3jkAWiWGuiDbD1pQs2L 4MVHLro35ZXCDqSEyyz6kwp/rDAIGEteWrjPf69KshwQJWc6LUEYa60xmG3ozBeoNpI3 l8qoj5aF8W/eYxplE5L9XQQV5+/A6UXBjd4xAuYdQN+qJk8ftzr3BDZMXH+JeRsnAePt CSztShXIxLRNH7KWLEJ1TsLyJC7xiCTPxjQfxqT9/zouudu3jgAqEBHgiJzQOfaDksts GM+A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kYlBQs73M0s8RmpgWsEfo4P2xw9UaQj0M1CIAVxBygs=; b=cBh6D3PCiyVLWNWmogM0rcniC4oge/Z2NwDjclzO4L+wbO4OQSfk3MhxoqbLmHWbP1 P+9Hj+WfcKDo/uM5hCd/pGpCe4Lo5SNt4Nf3yZSVhtarCbyu+ST1XF1HxmgSZ06x1Uds gwjrwdlAboHcALlnRmiXg4S7CIXao8Q8T4H/DFM5nlwc3S65R7Eup/F0wilJ89nqHXge mZ92wqdG0+vUdS2Zzd0t8ghbxK5lT6fCukDaFiePp1X1MAZVt6qkxQZNE2X5uzX2KaCf WHuoL0ClpU1Jw6teJ48MX+Ec1DDXGJ1G5egvNArc57SJx05XjxAYqDDbK5Xd/eppsmWx HsHQ== X-Gm-Message-State: AOAM531iAznTfKzS9qm6RXGNyb+2utw0WBrkbZcgX6/sdLNZPiikUWf5 s3Gsi6FB/xEZq+SbEPEpwbecI2locL7Uug== X-Google-Smtp-Source: ABdhPJwHz8qHOKcAyqqND1p4zioenT7hcdrW8NFR203fQ6tzzBkVpxB29H/1mDiJ6pnXdnSOR0PBvA== X-Received: by 2002:a17:902:e889:b0:151:a56d:eb8f with SMTP id w9-20020a170902e88900b00151a56deb8fmr21116042plg.142.1649462866110; Fri, 08 Apr 2022 17:07:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 03/16] target/arm: Update qemu-system-arm -cpu max to cortex-a57 Date: Fri, 8 Apr 2022 17:07:29 -0700 Message-Id: <20220409000742.293691-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220409000742.293691-1-richard.henderson@linaro.org> References: <20220409000742.293691-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1649463212967100001 Content-Type: text/plain; charset="utf-8" Instead of starting with cortex-a15 and adding v8 features to a v7 cpu, begin with a v8 cpu stripped of its aarch64 features. This fixes the long-standing to-do where we only enabled v8 features for user-only. Signed-off-by: Richard Henderson --- target/arm/cpu_tcg.c | 134 ++++++++++++++++++++++++++----------------- 1 file changed, 80 insertions(+), 54 deletions(-) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 13d0e9b195..43ac3e27fa 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -938,71 +938,97 @@ static void arm_v7m_class_init(ObjectClass *oc, void = *data) static void arm_max_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + uint32_t t; =20 - cortex_a15_initfn(obj); + /* aarch64_a57_initfn, advertising none of the aarch64 features */ + cpu->dtb_compatible =3D "arm,cortex-a57"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->midr =3D 0x411fd070; + cpu->revidr =3D 0x00000000; + cpu->reset_fpsid =3D 0x41034070; + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x12111111; + cpu->isar.mvfr2 =3D 0x00000043; + cpu->ctr =3D 0x8444c004; + cpu->reset_sctlr =3D 0x00c50838; + cpu->isar.id_pfr0 =3D 0x00000131; + cpu->isar.id_pfr1 =3D 0x00011011; + cpu->isar.id_dfr0 =3D 0x03010066; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x10101105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02102211; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00011142; + cpu->isar.id_isar5 =3D 0x00011121; + cpu->isar.id_isar6 =3D 0; + cpu->isar.dbgdidr =3D 0x3516d000; + cpu->clidr =3D 0x0a200023; + cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe012; /* 48KB L1 icache */ + cpu->ccsidr[2] =3D 0x70ffe07a; /* 2048KB L2 cache */ =20 - /* old-style VFP short-vector support */ + /* Break with true ARMv8 and add back old-style VFP short-vector suppo= rt */ cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); =20 -#ifdef CONFIG_USER_ONLY - /* - * We don't set these in system emulation mode for the moment, - * since we don't correctly set (all of) the ID registers to - * advertise them. - */ - set_feature(&cpu->env, ARM_FEATURE_V8); - { - uint32_t t; + /* Add additional features supported by QEMU */ + t =3D cpu->isar.id_isar5; + t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); + t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); + t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); + t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); + t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); + t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); + cpu->isar.id_isar5 =3D t; =20 - t =3D cpu->isar.id_isar5; - t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); - t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); - t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); - t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); - t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); - t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); - cpu->isar.id_isar5 =3D t; + t =3D cpu->isar.id_isar6; + t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); + t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); + t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); + t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); + t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); + cpu->isar.id_isar6 =3D t; =20 - t =3D cpu->isar.id_isar6; - t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); - t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); - t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); - t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); - t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); - cpu->isar.id_isar6 =3D t; + t =3D cpu->isar.mvfr1; + t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ + t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ + cpu->isar.mvfr1 =3D t; =20 - t =3D cpu->isar.mvfr1; - t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ - t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ - cpu->isar.mvfr1 =3D t; + t =3D cpu->isar.mvfr2; + t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ + t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ + cpu->isar.mvfr2 =3D t; =20 - t =3D cpu->isar.mvfr2; - t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ - t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ - cpu->isar.mvfr2 =3D t; + t =3D cpu->isar.id_mmfr3; + t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ + cpu->isar.id_mmfr3 =3D t; =20 - t =3D cpu->isar.id_mmfr3; - t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ - cpu->isar.id_mmfr3 =3D t; + t =3D cpu->isar.id_mmfr4; + t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ + t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ + t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ + cpu->isar.id_mmfr4 =3D t; =20 - t =3D cpu->isar.id_mmfr4; - t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ - t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ - t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ - cpu->isar.id_mmfr4 =3D t; + t =3D cpu->isar.id_pfr0; + t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); + cpu->isar.id_pfr0 =3D t; =20 - t =3D cpu->isar.id_pfr0; - t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); - cpu->isar.id_pfr0 =3D t; - - t =3D cpu->isar.id_pfr2; - t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); - cpu->isar.id_pfr2 =3D t; - } -#endif /* CONFIG_USER_ONLY */ + t =3D cpu->isar.id_pfr2; + t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); + cpu->isar.id_pfr2 =3D t; } #endif /* !TARGET_AARCH64 */ =20 --=20 2.25.1 From nobody Mon Feb 9 20:13:22 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1649463198; cv=none; d=zohomail.com; s=zohoarc; b=T2hTpVrVBhdgtasnzSPQPpBoLu4s4tf/izYTfd6JBv4fYwE7EJMasKzTZwYsBzbqYV+IDnf5U7dk14NUSS5cv5Flc5N/WgVhtJzsCKY6SJFuLNz19rjF48CnAho5dhz1cF3rHLwAOFpfOcLiPUtChB1LD380DH7tMbCXEhybiPE= ARC-Message-Signature: i=1; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id t69-20020a637848000000b0039831d6dc23sm22073961pgc.94.2022.04.08.17.07.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 17:07:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=d2bF5Nr0rwxv79nY64ioUunD/Z2b0emNBLOrA8/hvIQ=; b=dhtm9mZg0TIdFZEFeKCvOtc1WY2lqY3eZ0b1jp3xI+9KYfK5Hd8kT0iWhvGbBpHaoI ctJrRJXufe9HaQMbngSZuXG6LeylrxXNLH5/u5fS/yHd3oEwEVqN5RbX7WXeymeYaCvI opcYvUSa34+lvY4DyLOl3TNPSte66uXePCHTJDHyhxl7Z1kKgm97Geni7FfVtvoEgfvK 4ybrO7786w6dOHxsCNlYIO0oZkX/Y1COMpS/yycb0SbOY8DVyJcJRYmg1MySNet2WVVt EKQ7Z6oT4M5igS7myrCyXq3n+Rn/ocMBZ981CHXw5yU0ac5RuTsObAEJCy3IjeBf8ney jLrw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=d2bF5Nr0rwxv79nY64ioUunD/Z2b0emNBLOrA8/hvIQ=; b=1zU9Cl90LcVS8Fix1nuuN+5nGt5Hkdk2sxjkZrmY1/q6EdCmMeeqHV2sE5yIlL/hyn /1dAcgxlLqeYFQlgTnxSv2TXIZhSTqJ+W9AGVOfvdI2objo9e9K5BZEwR8n1G1d1ZpX3 PxXr/tw/J2l4DTSoQFfB8ztq94tJh8SnbxYypgmDwvrnCn0uVc4xU53m2zYtLfFcLpKL M3HVS4BaXh3Xu8kjjkwLQMcbgT8zhb6Qr2tY/GeRX1oZZaEFSr7xk4YUKLuD07AJlRzd FMxVRM1pljKbHoFdBEyoECnAwrMoxbKjfr3nnz7w4oLZLT2Sza8fy59PTv9k7TaOLWPQ Fbsw== X-Gm-Message-State: AOAM531drQARi9wbBO7XADuBY2Zf/J+Yp7Uewy5SrgJWeHRNr1Y4qpie 6/lNmkqdvdmgYFZb4gQQWjUBOdBSDHuwIA== X-Google-Smtp-Source: ABdhPJxC4PNj81OUMlq/bFSAi12408yAljYn0B2/AEV4R3lppp3RmOyxuwvjyTxwlgeVdCXPxJd15A== X-Received: by 2002:a05:6a00:985:b0:505:9b3b:3fd6 with SMTP id u5-20020a056a00098500b005059b3b3fd6mr797141pfg.30.1649462866894; Fri, 08 Apr 2022 17:07:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 04/16] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max Date: Fri, 8 Apr 2022 17:07:30 -0700 Message-Id: <20220409000742.293691-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220409000742.293691-1-richard.henderson@linaro.org> References: <20220409000742.293691-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1649463199093100001 Content-Type: text/plain; charset="utf-8" We set this for qemu-system-aarch64, but failed to do so for the strictly 32-bit emulation. Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'") Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu_tcg.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 43ac3e27fa..9569e496e0 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -1029,6 +1029,10 @@ static void arm_max_initfn(Object *obj) t =3D cpu->isar.id_pfr2; t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); cpu->isar.id_pfr2 =3D t; + + t =3D cpu->isar.id_dfr0; + t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ + cpu->isar.id_dfr0 =3D t; } #endif /* !TARGET_AARCH64 */ =20 --=20 2.25.1 From nobody Mon Feb 9 20:13:22 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1649463215; cv=none; d=zohomail.com; s=zohoarc; b=IJiijMIP0A2g1TXHEy5Ri3+A1++fpatoFOLrD2ioID8rGDPFLuwZQm/c9RL9q4yFbGop62GzG5i6IBbv6w0BwRiLRbL0oeLiMw/mUitPkg51pEHhhQ6gBhGIEOa9hL8pCTwTw6Ir1Trrs8FJd+0jBfuibtsuIixGTYsQ9CGM7ug= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649463215; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8JpR2Ocg8Fx42QQsZ4oj5FYsojYTBwIWUurppokMXyo=; b=i035EJlXObrvfA8BJedYXUD/d/HqddvJHxdSpyZNuafYOrAkY4xTfYN9+YwyzfsCJkIa/BS7JsmpibLAQXTDF1DhKv6/oQJQMVwfUsIdzDNrWNzhGD4r+Uyc7cAaaqeXxV5ZeWvjK+j0nMtFIKBH6QmV4XSZ66YJ848shWRgD+0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1649463215537441.3249404986183; Fri, 8 Apr 2022 17:13:35 -0700 (PDT) Received: from localhost ([::1]:44446 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ncyjO-0001if-5Q for importer@patchew.org; Fri, 08 Apr 2022 20:13:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46682) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ncydr-0008H5-HD for qemu-devel@nongnu.org; Fri, 08 Apr 2022 20:07:51 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:40957) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ncydp-0003Qs-6M for qemu-devel@nongnu.org; Fri, 08 Apr 2022 20:07:51 -0400 Received: by mail-pl1-x629.google.com with SMTP id t6so2905615plg.7 for ; Fri, 08 Apr 2022 17:07:48 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id t69-20020a637848000000b0039831d6dc23sm22073961pgc.94.2022.04.08.17.07.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 17:07:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8JpR2Ocg8Fx42QQsZ4oj5FYsojYTBwIWUurppokMXyo=; b=gRd8KWCzGqoak1CZL/ytekaK3xiaVNeoTLm1aNo+McCev/84zEJuhPwmN79KvImghO YJ4gELWHAob+BTEdEdjnBDFzf1IUgMi/mTxbnb6pc+TB1Ze7JKRHRKN/wjDb85hqNYV0 lqU5rKDlpqaJsY2XL4Ys9DwRQT+Htsn9GumBv3scAuRPcH0o1QbGTMm/tAad8VMRrQev poYmz/DLj2vAa5RM6dMAUdAKTNxe2lU1eNN4vxx/JBxcCb3kSguIRyY0gMA8OZa3Ngvg NyZW6R+UtjvRTn5SBt9xekZIdiPCcBlXQw4CfZzs57Y07AH7/3o6PuusYSMSvsft3DIU Xa5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8JpR2Ocg8Fx42QQsZ4oj5FYsojYTBwIWUurppokMXyo=; b=Zgux9vXzL9mAkOGI3AI+OEghVz8NX/TJsc78J5gbp4Fut0TfgZoyC9+ezrxTf6RC9I wbKeixgLu03EiOCqmNhbL449Z1NrTsEFQW5gVDNsudI6VNZSViu5rguTs+f6YSFIxLLU mK8LxXhAuvBoQ5PCATtgZuyKwWDO9yEgAuX79S6biFbyWRHxZRdXpI7T6eJBlmpN0Iwi eA3oZQUtB2oe0b7XJMMUV8P7M+XA6W6K6SBFFpAU/4vBAPtNIbHqKvufZujRKpuaPOrp MmLtlvWEwokS/CV7ioIPfgDxBwgF/x3aEObvvswmaGdmGP9BIklp3Y/ngYIJOg0E3/ds vsMQ== X-Gm-Message-State: AOAM533gj3xOWTDbhHnQ4bDE4L2bBZNYSGNhp2Mz7FjOjMC8IF15u6YX TK69VOwjbwzf8f5gUBeaJ+yO5s47fO9n4A== X-Google-Smtp-Source: ABdhPJzXY3UNE/8L4FTjHLa2V+E9iaX1dqcuf5r/aENFKNdqMHQJFKrF2/svKdM95xrSVLuqqPibWQ== X-Received: by 2002:a17:903:11cc:b0:151:71e4:dadc with SMTP id q12-20020a17090311cc00b0015171e4dadcmr21400095plh.78.1649462867830; Fri, 08 Apr 2022 17:07:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 05/16] target/arm: Split out arm32_max_features Date: Fri, 8 Apr 2022 17:07:31 -0700 Message-Id: <20220409000742.293691-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220409000742.293691-1-richard.henderson@linaro.org> References: <20220409000742.293691-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1649463216998100004 Content-Type: text/plain; charset="utf-8" Share the code to set AArch32 max features so that we no longer have code drift between qemu{-system,}-{arm,aarch64}. Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 + target/arm/cpu64.c | 51 +---------------- target/arm/cpu_tcg.c | 121 ++++++++++++++++++++++------------------- 3 files changed, 70 insertions(+), 104 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 7f696cd36a..596fd53619 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1295,4 +1295,6 @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteAr= ray *buf, int reg); int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg); #endif =20 +void arm32_max_features(ARMCPU *cpu); + #endif diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index eb44c05822..13621530bc 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -34,6 +34,7 @@ #include "hvf_arm.h" #include "qapi/visitor.h" #include "hw/qdev-properties.h" +#include "internals.h" =20 =20 #ifndef CONFIG_USER_ONLY @@ -738,7 +739,6 @@ static void aarch64_max_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); uint64_t t; - uint32_t u; =20 if (kvm_enabled() || hvf_enabled()) { /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */ @@ -853,57 +853,12 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); cpu->isar.id_aa64zfr0 =3D t; =20 - /* Replicate the same data to the 32-bit id registers. */ - u =3D cpu->isar.id_isar5; - u =3D FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ - u =3D FIELD_DP32(u, ID_ISAR5, SHA1, 1); - u =3D FIELD_DP32(u, ID_ISAR5, SHA2, 1); - u =3D FIELD_DP32(u, ID_ISAR5, CRC32, 1); - u =3D FIELD_DP32(u, ID_ISAR5, RDM, 1); - u =3D FIELD_DP32(u, ID_ISAR5, VCMA, 1); - cpu->isar.id_isar5 =3D u; - - u =3D cpu->isar.id_isar6; - u =3D FIELD_DP32(u, ID_ISAR6, JSCVT, 1); - u =3D FIELD_DP32(u, ID_ISAR6, DP, 1); - u =3D FIELD_DP32(u, ID_ISAR6, FHM, 1); - u =3D FIELD_DP32(u, ID_ISAR6, SB, 1); - u =3D FIELD_DP32(u, ID_ISAR6, SPECRES, 1); - u =3D FIELD_DP32(u, ID_ISAR6, BF16, 1); - u =3D FIELD_DP32(u, ID_ISAR6, I8MM, 1); - cpu->isar.id_isar6 =3D u; - - u =3D cpu->isar.id_pfr0; - u =3D FIELD_DP32(u, ID_PFR0, DIT, 1); - cpu->isar.id_pfr0 =3D u; - - u =3D cpu->isar.id_pfr2; - u =3D FIELD_DP32(u, ID_PFR2, SSBS, 1); - cpu->isar.id_pfr2 =3D u; - - u =3D cpu->isar.id_mmfr3; - u =3D FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ - cpu->isar.id_mmfr3 =3D u; - - u =3D cpu->isar.id_mmfr4; - u =3D FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */ - u =3D FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - u =3D FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */ - u =3D FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */ - cpu->isar.id_mmfr4 =3D u; - t =3D cpu->isar.id_aa64dfr0; t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ cpu->isar.id_aa64dfr0 =3D t; =20 - u =3D cpu->isar.id_dfr0; - u =3D FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ - cpu->isar.id_dfr0 =3D u; - - u =3D cpu->isar.mvfr1; - u =3D FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */ - u =3D FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ - cpu->isar.mvfr1 =3D u; + /* Replicate the same data to the 32-bit id registers. */ + arm32_max_features(cpu); =20 #ifdef CONFIG_USER_ONLY /* diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 9569e496e0..2a0f67f128 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -19,6 +19,70 @@ #include "hw/boards.h" #endif =20 +/* Share AArch32 -cpu max features with AArch64. */ +void arm32_max_features(ARMCPU *cpu) +{ + uint32_t t; + + /* Break with true ARMv8 and add back old-style VFP short-vector suppo= rt */ + t =3D cpu->isar.mvfr0; + t =3D FIELD_DP32(t, MVFR0, FPSHVEC, 1); + cpu->isar.mvfr0 =3D t; + + /* Add additional features supported by QEMU */ + t =3D cpu->isar.id_isar5; + t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); + t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); + t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); + t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); + t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); + t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); + cpu->isar.id_isar5 =3D t; + + t =3D cpu->isar.id_isar6; + t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); + t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); + t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); + t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); + t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); + cpu->isar.id_isar6 =3D t; + + t =3D cpu->isar.mvfr1; + t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ + t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ + cpu->isar.mvfr1 =3D t; + + t =3D cpu->isar.mvfr2; + t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ + t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ + cpu->isar.mvfr2 =3D t; + + t =3D cpu->isar.id_mmfr3; + t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ + cpu->isar.id_mmfr3 =3D t; + + t =3D cpu->isar.id_mmfr4; + t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ + t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ + t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ + cpu->isar.id_mmfr4 =3D t; + + t =3D cpu->isar.id_pfr0; + t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); + cpu->isar.id_pfr0 =3D t; + + t =3D cpu->isar.id_pfr2; + t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); + cpu->isar.id_pfr2 =3D t; + + t =3D cpu->isar.id_dfr0; + t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ + cpu->isar.id_dfr0 =3D t; +} + /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) =20 @@ -938,7 +1002,6 @@ static void arm_v7m_class_init(ObjectClass *oc, void *= data) static void arm_max_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); - uint32_t t; =20 /* aarch64_a57_initfn, advertising none of the aarch64 features */ cpu->dtb_compatible =3D "arm,cortex-a57"; @@ -978,61 +1041,7 @@ static void arm_max_initfn(Object *obj) cpu->ccsidr[1] =3D 0x201fe012; /* 48KB L1 icache */ cpu->ccsidr[2] =3D 0x70ffe07a; /* 2048KB L2 cache */ =20 - /* Break with true ARMv8 and add back old-style VFP short-vector suppo= rt */ - cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); - - /* Add additional features supported by QEMU */ - t =3D cpu->isar.id_isar5; - t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); - t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); - t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); - t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); - t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); - t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); - cpu->isar.id_isar5 =3D t; - - t =3D cpu->isar.id_isar6; - t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); - t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); - t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); - t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); - t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); - cpu->isar.id_isar6 =3D t; - - t =3D cpu->isar.mvfr1; - t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ - t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ - cpu->isar.mvfr1 =3D t; - - t =3D cpu->isar.mvfr2; - t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ - t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ - cpu->isar.mvfr2 =3D t; - - t =3D cpu->isar.id_mmfr3; - t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ - cpu->isar.id_mmfr3 =3D t; - - t =3D cpu->isar.id_mmfr4; - t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ - t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ - t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ - cpu->isar.id_mmfr4 =3D t; - - t =3D cpu->isar.id_pfr0; - t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); - cpu->isar.id_pfr0 =3D t; - - t =3D cpu->isar.id_pfr2; - t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); - cpu->isar.id_pfr2 =3D t; - - t =3D cpu->isar.id_dfr0; - t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ - cpu->isar.id_dfr0 =3D t; + arm32_max_features(cpu); } #endif /* !TARGET_AARCH64 */ =20 --=20 2.25.1 From nobody Mon Feb 9 20:13:22 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1649463438; cv=none; d=zohomail.com; s=zohoarc; b=BWQ/EcUW7Ig3eXocQOyb/FoxWdYLX5EwUp1Tu19Y/bT+bBeOn6Dd2wGnw6lOEuZPLXaUBXQOjtkRemeC559Qa6u7JTIN1/nh9TnpvWsznc6iuSPpFIchrs5tyJ6vi12wwcgBDoWEIE6rR/Lwkpy9Yjie7/1R7p057R8+TPSPtEM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649463438; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=EiSUwxUVBr+MZP6xo84L/+hbxJ6hM1BedSKXEDlnzmM=; b=FQ6DeQnYQbwDvx5dQDTHHUILSAa/S3eAgMZL3bYOsF0oGGTReY/W1AayOGvmdEbtmEszf4jhyypOcOI1yfm0bF4q+zm7m0Lqw3gaYk54g7iAaCwri+fjRIoBnipx5oYCV3f+P5nFRW055dOR0J+E9HOSSLeEi+ObWZmST7tnMmU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1649463438250578.37437392644; Fri, 8 Apr 2022 17:17:18 -0700 (PDT) Received: from localhost ([::1]:52250 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ncymy-00075C-Pu for importer@patchew.org; Fri, 08 Apr 2022 20:17:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46706) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ncyds-0008J5-8V for qemu-devel@nongnu.org; Fri, 08 Apr 2022 20:07:52 -0400 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:41501) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ncydq-0003RH-7Y for qemu-devel@nongnu.org; Fri, 08 Apr 2022 20:07:51 -0400 Received: by mail-pg1-x532.google.com with SMTP id t13so9088406pgn.8 for ; Fri, 08 Apr 2022 17:07:49 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id t69-20020a637848000000b0039831d6dc23sm22073961pgc.94.2022.04.08.17.07.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 17:07:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EiSUwxUVBr+MZP6xo84L/+hbxJ6hM1BedSKXEDlnzmM=; b=KVTXeMYgL1rUZ/5mL23tcmwHXkov4n5/cATxFWOzQ1KHFZZSkDntP4SpmRqIhAM1hl hRnyvRxYZJkmuhm7oRAyAukiJjNlaazJvtxI9HktffyZQaQHpbz1GWg3VNjr5KRIxWTa qhhDnK5V2iEjnV7224zWsOZ3nTWKw82ZS3iYW97gibxnXwrxSyG/IoNit8Kl+QYfHnUs JDoSsqhV2yUDto9amKhbsk2tWfb8TLXuS6Pxmt6rKe3d+YRfERKC14o4FgW1bu2tcV/n A1AsOpUoA1i1jNSK5zMtQ4e9SCdkNy3DuDIZXNafpb0pR4xNoZx1yd2c51p95SPEEQIL 0efQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EiSUwxUVBr+MZP6xo84L/+hbxJ6hM1BedSKXEDlnzmM=; b=EYGQ8Pq8pgyqMaqfS2ETX/lrMTtZWp+YqTkmoFPWu19571AeLDr0SSc9U01CvoVy+A BUv0F2HyVV+hsXeNZ4QSGSRgsJEslMk4HVCCjkgtKKwg9LlkRuMol3oOkyUMXmQfBudA 9hcLiZdcR0c97wxhahv1jDFlwIcMStyG/KcH+wCdi2T5Phs+/RZRR8bIGFTazsADN6vx 1Dv8o48UoKGQnKNm7MntzuC0+vxArdMnOBvkG5K+8BqFl/NQr+MHQx0yENJ8NQZYpwtc 4/L2iuR4fuTQM2lZJNYyF81ae1D7TIXl4lCS+s1zRfdDIZuhVa3XWbC+VAkSN1/KI+sg vY8g== X-Gm-Message-State: AOAM530omnVptqejbjR1FWNl5e2XMaS7LtBSKjwIjJOdkRlARHHUwhij LvfDUFk7DnO/kRIR7EyCDHgYdzPr24z07A== X-Google-Smtp-Source: ABdhPJx2roBNCHun7XwvzP14IdaTmZ1LhKdRoxcjBqsz58PKF6pdOjfv4b2Dshwvi4ppR1Be+a8fqQ== X-Received: by 2002:a62:6dc3:0:b0:505:895a:d38b with SMTP id i186-20020a626dc3000000b00505895ad38bmr5780558pfc.7.1649462868735; Fri, 08 Apr 2022 17:07:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 06/16] target/arm: Annotate arm_max_initfn with FEAT identifiers Date: Fri, 8 Apr 2022 17:07:32 -0700 Message-Id: <20220409000742.293691-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220409000742.293691-1-richard.henderson@linaro.org> References: <20220409000742.293691-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1649463440000100001 Content-Type: text/plain; charset="utf-8" Update the legacy feature names to the current names. Provide feature names for id changes that were not marked. Sort the field updates into increasing bitfield order. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu64.c | 96 ++++++++++++++++++++++---------------------- target/arm/cpu_tcg.c | 48 +++++++++++----------- 2 files changed, 72 insertions(+), 72 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 13621530bc..ae7114ea79 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -770,51 +770,51 @@ static void aarch64_max_initfn(Object *obj) cpu->midr =3D t; =20 t =3D cpu->isar.id_aa64isar0; - t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ t =3D FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); - t =3D FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */ cpu->isar.id_aa64isar0 =3D t; =20 t =3D cpu->isar.id_aa64isar1; - t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); - t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ cpu->isar.id_aa64isar1 =3D t; =20 t =3D cpu->isar.id_aa64pfr0; + t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); + t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ cpu->isar.id_aa64pfr0 =3D t; =20 t =3D cpu->isar.id_aa64pfr1; - t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); - t =3D FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); + t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */ + t =3D FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */ /* * Begin with full support for MTE. This will be downgraded to MTE=3D0 * during realize if the board provides no tag memory, much like * we do for EL2 with the virtualization=3Don property. */ - t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); + t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ cpu->isar.id_aa64pfr1 =3D t; =20 t =3D cpu->isar.id_aa64mmfr0; @@ -826,35 +826,35 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64mmfr0 =3D t; =20 t =3D cpu->isar.id_aa64mmfr1; - t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); - t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); - t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ cpu->isar.id_aa64mmfr1 =3D t; =20 t =3D cpu->isar.id_aa64mmfr2; - t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); - t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ cpu->isar.id_aa64mmfr2 =3D t; =20 t =3D cpu->isar.id_aa64zfr0; t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); + t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ cpu->isar.id_aa64zfr0 =3D t; =20 t =3D cpu->isar.id_aa64dfr0; - t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ + t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_aa64dfr0 =3D t; =20 /* Replicate the same data to the 32-bit id registers. */ diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 2a0f67f128..9d5cd6ea00 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -31,55 +31,55 @@ void arm32_max_features(ARMCPU *cpu) =20 /* Add additional features supported by QEMU */ t =3D cpu->isar.id_isar5; - t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); - t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); - t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); + t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ + t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ + t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); - t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); - t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); + t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ + t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ cpu->isar.id_isar5 =3D t; =20 t =3D cpu->isar.id_isar6; - t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); - t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); - t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); - t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); - t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); + t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ + t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ + t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ + t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */ + t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */ + t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */ + t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */ cpu->isar.id_isar6 =3D t; =20 t =3D cpu->isar.mvfr1; - t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ - t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ + t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */ + t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */ cpu->isar.mvfr1 =3D t; =20 t =3D cpu->isar.mvfr2; - t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ - t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ + t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ + t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ cpu->isar.mvfr2 =3D t; =20 t =3D cpu->isar.id_mmfr3; - t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ + t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ cpu->isar.id_mmfr3 =3D t; =20 t =3D cpu->isar.id_mmfr4; - t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ - t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ - t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ + t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* FEAT_AA32HPD */ + t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ + t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX*/ cpu->isar.id_mmfr4 =3D t; =20 t =3D cpu->isar.id_pfr0; - t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); + t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ cpu->isar.id_pfr0 =3D t; =20 t =3D cpu->isar.id_pfr2; - t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); + t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ cpu->isar.id_pfr2 =3D t; =20 t =3D cpu->isar.id_dfr0; - t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ + t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_dfr0 =3D t; } =20 --=20 2.25.1 From nobody Mon Feb 9 20:13:22 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id t69-20020a637848000000b0039831d6dc23sm22073961pgc.94.2022.04.08.17.07.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 17:07:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=77IUNxzBr4CUo6OGOs42IJabOTHQjqxfs99nkKvtt9E=; b=SAsLnfpQTcLLx8E9ydD4RUjY6NH9oXP3sYX/r+DjhuMJS2HD1GcvacxRb9a+v5mdHs +PXYPDeSmYXCzxyTbx4FTgvdkovbTY0lwbLAjM3gjo41sBfaN0M98ib2yqlpf80HgHTV Kpg3RTs/ka42wzCJssrFISPIyW55mBSkYH7lErhLaAP1HxMaJs+7Mid2FoBIQckIqpSc hvJJQo2qxP3sEVLOKCfFE+z8wLgEBZrunHWRcBwV16qVluP4QYE96Jii8PnLt/Rl3PQD WUTFcrsMvBa9o1jf/1VK7TYvdgj/DeyIaFW8yLPirLjyuL12LvRdsuI67XmziQGIrUYl kq9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=77IUNxzBr4CUo6OGOs42IJabOTHQjqxfs99nkKvtt9E=; b=LLYP4In+mLJ6PvuJ3yOutdXWT46XRqg/yKwpIMzHtovLIlIiKwQsKPRn//3vWlqmIy SUn6hoOr6gyPFxK6sE7+GpLuOOUMJBrGT30EYWYygV5Kj6nJN0VsRjET7cg8olTPbfBe qZ1Yqde9RWeqUvzZaFJAaqZpo6utR4pcbqspkJTNtXMr69YuyHLqVX3J5peAlZ/JtW5m Unqims6XgxXYMepi2eFDBC9M5D0o5IW7MSuDpsS7/zrBQZwIVfLKvnf4WH/gOcWCOQIr oNqciwO6ok8e77D4DwkwkTS1GUm/5M2bfb2zUBMVC5Z5fLSLpN1M/O5B5qyd47g5GezP VmIw== X-Gm-Message-State: AOAM533r+oBfzLdoOGunBdhoKj0mtUHmpfbtJZBfwFeK1/kn6q1dEoqc 6g4zBBSXxVNBP96TBBRqXpU9hSYqIq68mQ== X-Google-Smtp-Source: ABdhPJxWHbyFsPK/+kf+TtLvzO7tYLUG7EX/rqWRlC3DrO2n03EsAXGbqtP8MUfKNPJXZ7imb7dcIA== X-Received: by 2002:a17:90a:5983:b0:1c9:ee11:76df with SMTP id l3-20020a17090a598300b001c9ee1176dfmr24727413pji.95.1649462869664; Fri, 08 Apr 2022 17:07:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 07/16] target/arm: Use field names for manipulating EL2 and EL3 modes Date: Fri, 8 Apr 2022 17:07:33 -0700 Message-Id: <20220409000742.293691-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220409000742.293691-1-richard.henderson@linaro.org> References: <20220409000742.293691-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1649463570697100001 Content-Type: text/plain; charset="utf-8" Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0 during arm_cpu_realizefn. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 5d4ca7a227..6521f350f9 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1795,11 +1795,13 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) */ unset_feature(env, ARM_FEATURE_EL3); =20 - /* Disable the security extension feature bits in the processor fe= ature - * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12= ]. + /* + * Disable the security extension feature bits in the processor + * feature registers as well. */ - cpu->isar.id_pfr1 &=3D ~0xf0; - cpu->isar.id_aa64pfr0 &=3D ~0xf000; + cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECUR= ITY, 0); + cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, + ID_AA64PFR0, EL3, 0); } =20 if (!cpu->has_el2) { @@ -1830,12 +1832,14 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) } =20 if (!arm_feature(env, ARM_FEATURE_EL2)) { - /* Disable the hypervisor feature bits in the processor feature - * registers if we don't have EL2. These are id_pfr1[15:12] and - * id_aa64pfr0_el1[11:8]. + /* + * Disable the hypervisor feature bits in the processor feature + * registers if we don't have EL2. */ - cpu->isar.id_aa64pfr0 &=3D ~0xf00; - cpu->isar.id_pfr1 &=3D ~0xf000; + cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, + ID_AA64PFR0, EL2, 0); + cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, + ID_PFR1, VIRTUALIZATION, 0); } =20 #ifndef CONFIG_USER_ONLY --=20 2.25.1 From nobody Mon Feb 9 20:13:22 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1649463486; cv=none; d=zohomail.com; s=zohoarc; b=HKvs0t0c4bZu+B7z7kqYF+J7bcI2Hk8llEjBtQrvXtzSSicH+12tvt+VW4Z0WZbiBsjWlyvalFEE1lCue5x7yNX9maTbUb0PV7pAGExR0TB0J5BtwJoWn4Kf3zAYUQGYsiHrik4OUp0y30V6SHC0oF6hovWrDYMvF9lc5UMNyq0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649463486; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=p80D0OL7NSD8A+1/4lXOPXEHHEGV8jpE8kk94fCxKzs=; b=Qth1ZdgEJGVWt7i9Jt13aWfoioM36Hcd0B/y6JYqkL+VmiGKnsM89BWIWdvBC5+PHMLJZCB4/lU2VQQlid9wfqgsYslzUc60pwhmRRhPwSknNfH9vdrzLt7pWG3/T1aTo7tYb36tv3X3E6GBDyrlqrAq0MyiAK/yOHSTxV7z4IU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1649463486347635.2715767642845; Fri, 8 Apr 2022 17:18:06 -0700 (PDT) Received: from localhost ([::1]:55044 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ncynl-0000d1-9c for importer@patchew.org; Fri, 08 Apr 2022 20:18:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46764) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ncydt-0008MC-Sp for qemu-devel@nongnu.org; Fri, 08 Apr 2022 20:07:53 -0400 Received: from mail-pl1-x62f.google.com ([2607:f8b0:4864:20::62f]:33355) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ncyds-0003T4-7n for qemu-devel@nongnu.org; Fri, 08 Apr 2022 20:07:53 -0400 Received: by mail-pl1-x62f.google.com with SMTP id c23so9298704plo.0 for ; Fri, 08 Apr 2022 17:07:51 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id t69-20020a637848000000b0039831d6dc23sm22073961pgc.94.2022.04.08.17.07.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 17:07:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=p80D0OL7NSD8A+1/4lXOPXEHHEGV8jpE8kk94fCxKzs=; b=t/cS+X8psQfXZyFIGb4ptdmrq9rhwsdZx5SfZbeg+hj0Puggb0OaRYphK0UQUD4Au5 9jbFkSg7ua3QuuCMxfvTZw77eBUtJfTxLRLIZT3ocfSoQkzD1kmYHD8Ahbd4cdIR3Bcb 8pHay8QfvZOxKyk+h+QSgR3sCQIBYezvgKJUQLDFMrj1jBqs6QVK027cm2WYM8+h3WFC MIwZQ8l7VoinVtWsNiyOkMAyr7m3ic4vcW0/yT2AmvJGl8w/oxBBkbu5GeOAp5/yZ+5E S10eGm99rxhpbxt3dZBPkTZ6XYK2/w3hSCzjUudSwTCfD3VdzQjW0WuG9Cw2CnWIa90P AwBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=p80D0OL7NSD8A+1/4lXOPXEHHEGV8jpE8kk94fCxKzs=; b=4MrELf4TUdMY6nFuDayYXabzpdzhLfgax3/s11DM9Z7BlNtlMm+NNaINf/fDveyGok NLu6V1M4jNCZ2enIgEMxIKGFHwzYuqBiTdaHUPG/ahzoUbejtirvUnsrG+K51A4Xj8Dc ZLDlPhmlXob0BY+xOxchWm1YxwKmF7Yioc828R2EViHg5XEnj/buCkWb21Y0CYFNU920 kOEWwtOyFoD1r3fuSbRHzWdyboZFk8Jz5JKAx62uRzJdphJK2D2SvzESH8SCsvOAV1PD 7rF/5OarBNIKu4+S5773kZv7liqn5M6PnfrCtM/IxTEJQDDLnojw/PRy3vWc8kPPWQtE X8XQ== X-Gm-Message-State: AOAM532vO06d9rdceSizXjZ1hKAxVOC5l3BdJvf5BMN41YQ/wE3+5rEa /qb40vBYrJLQQvS82G0YPQJr1L17PO4nuA== X-Google-Smtp-Source: ABdhPJw4RN7HFJf3VXPoevDrmst3jQW7UUy72uTt9jitsaZ75P/+aCNTrK+Tvr2j/UdobccagD39Fw== X-Received: by 2002:a17:902:8309:b0:156:486f:35d8 with SMTP id bd9-20020a170902830900b00156486f35d8mr22003569plb.143.1649462870713; Fri, 08 Apr 2022 17:07:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 08/16] target/arm: Enable FEAT_Debugv8p2 for -cpu max Date: Fri, 8 Apr 2022 17:07:34 -0700 Message-Id: <20220409000742.293691-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220409000742.293691-1-richard.henderson@linaro.org> References: <20220409000742.293691-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1649463488146100001 Content-Type: text/plain; charset="utf-8" The only portion of FEAT_Debugv8p2 that is relevant to QEMU is CONTEXTIDR_EL2, which is also conditionally implemented with FEAT_VHE. The rest of the debug extension concerns the External debug interface, which is outside the scope of QEMU. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.c | 1 + target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 2 ++ 3 files changed, 4 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6521f350f9..d815d3a397 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1800,6 +1800,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * feature registers as well. */ cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECUR= ITY, 0); + cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSD= BG, 0); cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, EL3, 0); } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index ae7114ea79..6b6422070d 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -854,6 +854,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64zfr0 =3D t; =20 t =3D cpu->isar.id_aa64dfr0; + t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */ t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_aa64dfr0 =3D t; =20 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 9d5cd6ea00..ac91bbea9b 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -79,6 +79,8 @@ void arm32_max_features(ARMCPU *cpu) cpu->isar.id_pfr2 =3D t; =20 t =3D cpu->isar.id_dfr0; + t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */ + t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */ t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_dfr0 =3D t; } --=20 2.25.1 From nobody Mon Feb 9 20:13:22 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1649463832; cv=none; d=zohomail.com; s=zohoarc; b=TJaTCeMOTQf3ABB7vLPCBErP+C3Kio0ZBBXri2/Y/soaZTff0NCIbgwZ6vVQ+mYCwEyXQgrdWD8tGXPTOQm3OVGy8nrqFbzT3JwA/uzY6OmejZRj5SURP96TjwBjNfYscXiIoaEdz7kTtRjrb+uet+OhF4fu2xW8WHAyRIV2S/Y= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649463832; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=MNTGLvkJnkedUMp8qlCzOgaMtMY1y27pusQZ1n5mN5U=; b=V/vtnia/VF+HM0tQqRGZBTuM95fgfNsh4K0xQtwFL26ZVdFhbIdPvwi/xGx44RCfxWgzrMcGZkst7biaItRNfCnsL4ZJtsLX7WdgB6/MgCKbVkToxXcJz1ifGvDkoYZJ+FvoIasIYHsFmA/tB1w+l3i9ZnRE2QvOe58mYrV3QkY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1649463832226795.3057145582666; Fri, 8 Apr 2022 17:23:52 -0700 (PDT) Received: from localhost ([::1]:38454 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ncytL-0000YT-1A for importer@patchew.org; Fri, 08 Apr 2022 20:23:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46806) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ncydu-0008PO-VI for qemu-devel@nongnu.org; Fri, 08 Apr 2022 20:07:55 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:44721) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ncydt-0003Tb-8M for qemu-devel@nongnu.org; Fri, 08 Apr 2022 20:07:54 -0400 Received: by mail-pl1-x629.google.com with SMTP id j8so9234336pll.11 for ; Fri, 08 Apr 2022 17:07:52 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id t69-20020a637848000000b0039831d6dc23sm22073961pgc.94.2022.04.08.17.07.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 17:07:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MNTGLvkJnkedUMp8qlCzOgaMtMY1y27pusQZ1n5mN5U=; b=oKGhXehssyQgfEXYL3XAvFG4i5rWVMrdA50LWDpEhoW8BywZYpbFCmIlsgSytpoV8K 2Ts4pN3cO+Cs1nW6tJ/1oaaw0AvBiYtJaBkcc31ZnlYYjy3hCzFdDASF1SC7NAU04S3b 80etyrWF8FP9BZVcSITs3AZRGzOIuL38H7WWz6e99bxdAzi3W7mwIYr2vnY5pNUy4XxW KGoDopiCP/uC2et8LN11/rD2sASyHjPpNUUg2oZFMSqixryANqRjp84S1OeBNol9/AFq KYCKvHEQniHrrEUZGimJAPpaVHxUBjVm6ziflKAFxAKZxqbPA0JOuHT9QTRBiIJvtv7o T7Jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MNTGLvkJnkedUMp8qlCzOgaMtMY1y27pusQZ1n5mN5U=; b=3lRXDB3nEhR82ZvX9cDy7O5qHJfdPxaqE8eAXuLZEI+HLeGNvPwFu1LmDp/BQwyC+z HejeCHfbUltw5OVCdS/7eSQidTySC5ZWevz+aPm9STJthbQaOwsG9y6sVu1aJqUxL+ze AKNBTYxKHCi+t1B7/ByIzk3idu6DwZc5RLfFr3hYOM3nSEzuEGU5s24gE1B6RY2gT0GK aK0C/FBpd7JZZdT4OnxPS9FOpkItvWZctzf01spHF8vBIvkiFejjRsul4g3CuuzOQAEx khYX+fVMJ/HTELMoW+9rHPaSG579a5asAuL980//VcUgbDa7OEqs//Z2xixAcuniIMYL EX4g== X-Gm-Message-State: AOAM530LJjG903RJccmG1lX4Qs++K6a1iQFQnM1iu2Lwpn1YlA3fbaT1 T+C4TQtODjIanR8dAqfNAJojoO7RlLSXjA== X-Google-Smtp-Source: ABdhPJwYqNmCHb/0G6i9Ld8VZAEx8NZMMhGOESRDjF6YTvKlqVG7Vu7AargdGK/OK+ET1IPZe7e6ew== X-Received: by 2002:a17:90a:f01:b0:1c7:ea40:93e7 with SMTP id 1-20020a17090a0f0100b001c7ea4093e7mr24794823pjy.30.1649462871809; Fri, 08 Apr 2022 17:07:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 09/16] target/arm: Enable FEAT_Debugv8p4 for -cpu max Date: Fri, 8 Apr 2022 17:07:35 -0700 Message-Id: <20220409000742.293691-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220409000742.293691-1-richard.henderson@linaro.org> References: <20220409000742.293691-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1649463833682100001 Content-Type: text/plain; charset="utf-8" This extension concerns changes to the External Debug interface, with Secure and Non-secure access to the debug registers, and all of it is outside the scope of QEMU. Indicating support for this is mandatory with FEAT_SEL2, which we do implement. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu64.c | 2 +- target/arm/cpu_tcg.c | 4 ++-- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 6b6422070d..f20fb6d9e1 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -854,7 +854,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64zfr0 =3D t; =20 t =3D cpu->isar.id_aa64dfr0; - t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */ + t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */ t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_aa64dfr0 =3D t; =20 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index ac91bbea9b..a443e8c48a 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -79,8 +79,8 @@ void arm32_max_features(ARMCPU *cpu) cpu->isar.id_pfr2 =3D t; =20 t =3D cpu->isar.id_dfr0; - t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */ - t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */ + t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */ + t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */ t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_dfr0 =3D t; } --=20 2.25.1 From nobody Mon Feb 9 20:13:22 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1649463636; cv=none; d=zohomail.com; s=zohoarc; b=P+lzmeua9znB6+y23RXjtHUX56EzDDpc6fa4iO2zw04Bs5IqGX8gkZ+Ulk3o/jmFSzT0fiHIfwcrYLg4hVL12IAdVhECEDbAQbfyXwR/RGeCiD0dPklYCAzsSQyI11qNj+l/VCck2U7bUqSmh3LEbeX8CevFnMQcH6tYhrtnWJs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649463636; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SSn6XnYEyRgUaQ5RFjGEN5zTQZu0eCBb7h/2LLfdbHk=; b=dITGNaPoU4+YFXGjjlJEWk56pTXJFjNJpnB4lvodZ/hAWjkhAfxm/QjDLpXfE89ZUUG46XoLV7S8Om7bAhVi0dHyR6g/8949DctrvFLAnER9K/cN1gPyarolhjh6JEoDgvdmdPicSd0FDS8+GTesX/bYPW9cSrSIfnnL676sP3A= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1649463636629103.22903308138393; Fri, 8 Apr 2022 17:20:36 -0700 (PDT) Received: from localhost ([::1]:34306 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ncyqB-0005t6-Af for importer@patchew.org; Fri, 08 Apr 2022 20:20:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46834) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ncydv-0008Se-Pb for qemu-devel@nongnu.org; Fri, 08 Apr 2022 20:07:55 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:40524) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ncydu-0003Tx-4b for qemu-devel@nongnu.org; Fri, 08 Apr 2022 20:07:55 -0400 Received: by mail-pj1-x1029.google.com with SMTP id ms15-20020a17090b234f00b001cb61350f05so651398pjb.5 for ; Fri, 08 Apr 2022 17:07:53 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id t69-20020a637848000000b0039831d6dc23sm22073961pgc.94.2022.04.08.17.07.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 17:07:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=SSn6XnYEyRgUaQ5RFjGEN5zTQZu0eCBb7h/2LLfdbHk=; b=KuWG4ENa+In6mc7edeh+l6ChPSrqCT3X2p5wtlGpgLd6EokE6ecXXbVFYdJTdcWrjN 7IA2GBJZ/D/gMaW48MQjfeGSe4QI2J+HqIBMDeUHlVzCqB61csMz5Xj1XpVhuKLc+OLS wNWMA6SCNTh3jQ3D2Y8F+7nWn1SRKdYXVP16x/0Avj4Gt67ACvAO/7xQm3nY1ZyPDWnM AwF3SorI8QEMvqTleZaIIy8e+UPhOAK2uERRQTyTbtYAY9JZ83TPi30REI9oY3d8IdSB 21me4PDeQ/3VofzyDfSazfW2HwGIpNlmr16a+lFkQ+9HXTvSTHAQF0cFutlbWZ+tLvO7 9T8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SSn6XnYEyRgUaQ5RFjGEN5zTQZu0eCBb7h/2LLfdbHk=; b=EnlXi4YEw1DVv2wJcbVAK4gZyaFR1VUon4EdNztUCl+wPmimQMLVWpFfzQWyQRYBvD xBJa8SBhj6+FUuQyos6K0VJ0O377qw0uAPLv+FS6oHZ5N4yi8/N1S1ohra4BplT3SC0i hyqpj4+4pBsikYGM52/Q9uq8dJZXE8WjJnlJAr27qmlNfEW0jsn7AZF1pbmgORgqv3se I5yvCgrY7CszTGJel31rEy6FBdCIF8wT7Lx1NCp0XRIcgnVASKtb5oj7Qs6Y0CrtGqML fuoAZF8ckH3+N1O+SNuwS/crQ67YYzq00t94EVuc7kR4hguk24qtzaQyE7IznNftWAie jiWw== X-Gm-Message-State: AOAM531UPdWPIH8MzCVAnTa3zbMeJeE3RQymNtlRb6NXQJrw/dd5l/4x TWm71d6yuCTd/h0BUViVHbDmG7CLsugM8Q== X-Google-Smtp-Source: ABdhPJxmrbVWaN1hLhe1DpEawelMr4uX3y5SKeTv57Sq42091GyIxJJGFm3ikJ0G4KHnFVBPJjMPtQ== X-Received: by 2002:a17:902:f545:b0:156:b8ae:d4c with SMTP id h5-20020a170902f54500b00156b8ae0d4cmr21532619plf.171.1649462872744; Fri, 08 Apr 2022 17:07:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 10/16] target/arm: Add isar_feature_{aa64,any}_ras Date: Fri, 8 Apr 2022 17:07:36 -0700 Message-Id: <20220409000742.293691-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220409000742.293691-1-richard.henderson@linaro.org> References: <20220409000742.293691-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1649463638722100001 Content-Type: text/plain; charset="utf-8" Add the aa64 predicate for detecting RAS support from id registers. We already have the aa32 version from the M-profile work. Add the 'any' predicate for testing both aa64 and aa32. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9c456ff23a..890001f26b 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4208,6 +4208,11 @@ static inline bool isar_feature_aa64_aa32_el1(const = ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >=3D 2; } =20 +static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) !=3D 0; +} + static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) !=3D 0; @@ -4430,6 +4435,11 @@ static inline bool isar_feature_any_debugv8p2(const = ARMISARegisters *id) return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(= id); } =20 +static inline bool isar_feature_any_ras(const ARMISARegisters *id) +{ + return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id); +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ --=20 2.25.1 From nobody Mon Feb 9 20:13:22 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1649463471; cv=none; d=zohomail.com; s=zohoarc; b=AZHbzdk2k3bo9Dc3riLam0O2J4SGcO4ZbZKHleYXP5Rs+QnpKBoVr9GJSqrC0M68gSPZV3SckAJjy+rDRDrpRhWihsaQIUh9LFGD/pn9BHf+cTdGovfqBfHpMyZqeFaO91S6r0N9eZp/Bv7Cn2HtZRiTmyJwgzeqCbsePhB68eU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649463471; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6rBOq0Nv8/vTaxT5E/RtnNmWUY7SzIzq03s+HMA2Ob4=; b=YiNxN9Uu8O2Nxq73BftFdMZ8wjvykcOJCPHUFqVmx7iWUeqCEFHK1tisUVsp5mAYHt7qYPack3SiH0VfLHaW0Fp8lXqStlHB4ySf4t0ATTilDWYOcAw4cFfR0H4crGD42VJU0qq0ZBcRyWe9IxaQmIHE6c4zDd6RCgivVjSaEA4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1649463471089138.38863362003156; Fri, 8 Apr 2022 17:17:51 -0700 (PDT) Received: from localhost ([::1]:53876 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ncynW-0008Cy-2N for importer@patchew.org; Fri, 08 Apr 2022 20:17:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46890) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ncydw-0008UU-W3 for qemu-devel@nongnu.org; Fri, 08 Apr 2022 20:07:57 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:45820) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ncydv-0003UL-0U for qemu-devel@nongnu.org; Fri, 08 Apr 2022 20:07:56 -0400 Received: by mail-pl1-x62d.google.com with SMTP id k13so4039398plk.12 for ; Fri, 08 Apr 2022 17:07:54 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id t69-20020a637848000000b0039831d6dc23sm22073961pgc.94.2022.04.08.17.07.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 17:07:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6rBOq0Nv8/vTaxT5E/RtnNmWUY7SzIzq03s+HMA2Ob4=; b=biIoclTyfmv3tUiqGsSGzh1sEfoHF0/CK4ZRzQuJxEcZ4SSov70cbzjxs9v6vNcEt6 WAXjirgIi7C3JNms/QF4iYbd1OC9mBCocIL0cA8xlLPWdhICN22MnN4Au8ZPbhIOKrSk pelOrqx9APQUcID569kpfXmLnILgihAUkSR7Ieub8tcQ5UrJWUtVQt/8yjCpIHkGDwI8 wedO5SMSu+6nlgS78IFlPWw1nB951zY2t5XsXueId5qNWckkJ6elDdHVU7XARA3drevG g1LUHWgJRUqlg0cX10kNP6R+PwuytCnEJIGNIdWtDlyMQ1NSIOk1GS+PrvZ36u8Ppack NMdw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6rBOq0Nv8/vTaxT5E/RtnNmWUY7SzIzq03s+HMA2Ob4=; b=Qzs/+KkCwMoMxGrflqePE8Ourt7EJnu/q6jxKusgN8WhdTttEWYPuYeQUqWVBxXiw5 5x6TsxrhuLqT1M6ES5bqQfV4MForCcZQ10EyiObrNUKrvxl+c5nQgxNFS99O/RAiV/UF 80wCkZXc2h7tp/8mrF2wyTIJ+v5iihU/k0c9s2DBHkxX5KYMKBD/it7S9rGrD9M6jd53 HZHDBH6yl/fJ2AVpkr04wZhab/euo3MV/wVZYcmeXtVlU3ZVYiWArOG8V+Xn0XjavPpt qrFz/LAkSQ6hBRYUn/X+WlZhRcIrgyISZQ+bxyiBwPWcxOz8MUeFa1e4PEuCWvJCiq2e F5ew== X-Gm-Message-State: AOAM530Yg4yBsNq3x122T3DMkSyBxKz2ZIBDC9kLiIXORyyHlfl9QnDF Y81NOjErIB2aFJIry4iGPE05PaaKR6QI7A== X-Google-Smtp-Source: ABdhPJxkl3YOm33Pt1+ASAf3YXUcniNjMJfFWEqxLa8nUX8dM/9ihs+rB+Y2QFnCC1ZoLqVNGWDSRg== X-Received: by 2002:a17:90a:fac:b0:1ca:5eb8:f3b2 with SMTP id 41-20020a17090a0fac00b001ca5eb8f3b2mr24878076pjz.37.1649462873563; Fri, 08 Apr 2022 17:07:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 11/16] target/arm: Add minimal RAS registers Date: Fri, 8 Apr 2022 17:07:37 -0700 Message-Id: <20220409000742.293691-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220409000742.293691-1-richard.henderson@linaro.org> References: <20220409000742.293691-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1649463472071100001 Content-Type: text/plain; charset="utf-8" Add only the system registers required to implement zero error records. This means we need to save state for ERRSELR, but all values are out of range, so none of the indexed error record registers need be implemented. Add the EL2 registers required for injecting virtual SError. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 6 +++ target/arm/helper.c | 107 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 113 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 890001f26b..66becc47f2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -524,6 +524,12 @@ typedef struct CPUArchState { uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ uint64_t gcr_el1; uint64_t rgsr_el1; + + /* Minimal RAS registers */ + uint64_t disr_el1; + uint64_t errselr_el1; + uint64_t vdisr_el2; + uint64_t vsesr_el2; } cp15; =20 struct { diff --git a/target/arm/helper.c b/target/arm/helper.c index 210c139818..01f8558fca 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6147,6 +6147,104 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = =3D { REGINFO_SENTINEL }; =20 +/* + * Check for traps to RAS registers, which are controlled + * by HCR_EL2.TERR and SCR_EL3.TERR. + */ +static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el =3D arm_current_el(env); + + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + int el =3D arm_current_el(env); + + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { + return env->cp15.vdisr_el2; + } + if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { + return 0; /* RAZ/WI */ + } + return env->cp15.disr_el1; +} + +static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = val) +{ + int el =3D arm_current_el(env); + + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { + env->cp15.vdisr_el2 =3D val; + return; + } + if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { + return; /* RAZ/WI */ + } + env->cp15.disr_el1 =3D val; +} + +/* + * Minimal RAS implementation with no Error Records. + * Which means that all of the Error Record registers: + * ERXADDR_EL1 + * ERXCTLR_EL1 + * ERXFR_EL1 + * ERXMISC0_EL1 + * ERXMISC1_EL1 + * ERXMISC2_EL1 + * ERXMISC3_EL1 + * ERXPFGCDN_EL1 (RASv1p1) + * ERXPFGCTL_EL1 (RASv1p1) + * ERXPFGF_EL1 (RASv1p1) + * ERXSTATUS_EL1 + * may generate UNDEFINED, which is the effect we get by not + * listing them at all. + */ +static const ARMCPRegInfo minimal_ras_reginfo_el1[] =3D { + { .name =3D "DISR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 0xc, .crm =3D 1, .opc2 =3D 1, + .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.disr= _el1), + .readfn =3D disr_read, .writefn =3D disr_write, .raw_writefn =3D raw= _write }, + { .name =3D "ERRIDR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 3, .opc2 =3D 0, + .access =3D PL1_R, .accessfn =3D access_terr, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "ERRSELR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 3, .opc2 =3D 1, + .access =3D PL1_RW, .accessfn =3D access_terr, + .fieldoffset =3D offsetof(CPUARMState, cp15.errselr_el1) }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo minimal_ras_reginfo_el2[] =3D { + { .name =3D "VDISR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0xc, .crm =3D 1, .opc2 =3D 1, + .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.vdis= r_el2) }, + { .name =3D "VSESR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 2, .opc2 =3D 3, + .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.vses= r_el2) }, + REGINFO_SENTINEL +}; + +static const ARMCPRegInfo minimal_ras_reginfo_no_el2[] =3D { + { .name =3D "VDISR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0xc, .crm =3D 1, .opc2 =3D 1, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "VSESR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 2, .opc2 =3D 3, + .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + REGINFO_SENTINEL +}; + /* Return the exception level to which exceptions should be taken * via SVEAccessTrap. If an exception should be routed through * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should @@ -8452,6 +8550,15 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &ssbs_reginfo); } =20 + if (cpu_isar_feature(any_ras, cpu)) { + define_arm_cp_regs(cpu, minimal_ras_reginfo_el1); + if (arm_feature(env, ARM_FEATURE_EL2)) { + define_arm_cp_regs(cpu, minimal_ras_reginfo_el2); + } else { + define_arm_cp_regs(cpu, minimal_ras_reginfo_no_el2); + } + } + if (cpu_isar_feature(aa64_vh, cpu) || cpu_isar_feature(aa64_debugv8p2, cpu)) { if (arm_feature(env, ARM_FEATURE_EL2)) { --=20 2.25.1 From nobody Mon Feb 9 20:13:22 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1649462983; cv=none; d=zohomail.com; s=zohoarc; b=TrA5pTvr0tcas+pUVytERsSgKYK+GWC0J40ElJBUhzns3hYzVKp4sRkDQxjbzu7MSVonoeb91xN1d9hyylGWqnd9KzG0AtAgXzBQcDrxILBLDnI3YDmUf7vap0gOWqpoXRdWYHOe3EKrmiUX7KGGdzXRd2sSy87zotuV/ryHE2g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649462983; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NUApV7x1eW6JanJ9cXe7CSNy/ZAx/ZG1Cq9BgRTELmQ=; b=dCJKGNblbAOGrkpSwrRkO40QHi9LSzQDgzQPyJ2qtLS1VoLgSRGf0npr9iSGjg+tzOgLFA+prhtlOey13gNQUsZIUz70XqjzDX9Vi2LPK/wEjWsKAonA+ZmCdo0773ebRUV6gKGWskI79ec2PjedNZa+VQRON5DwV5CkoqTdTw0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164946298329373.68034436449022; Fri, 8 Apr 2022 17:09:43 -0700 (PDT) Received: from localhost ([::1]:34832 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ncyfe-0003d5-9u for importer@patchew.org; Fri, 08 Apr 2022 20:09:42 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46906) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ncydx-0008Ub-9P for qemu-devel@nongnu.org; Fri, 08 Apr 2022 20:07:58 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:43976) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ncydv-0003Ue-OM for qemu-devel@nongnu.org; Fri, 08 Apr 2022 20:07:57 -0400 Received: by mail-pj1-x1029.google.com with SMTP id b2-20020a17090a010200b001cb0c78db57so7966677pjb.2 for ; Fri, 08 Apr 2022 17:07:55 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id t69-20020a637848000000b0039831d6dc23sm22073961pgc.94.2022.04.08.17.07.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 17:07:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NUApV7x1eW6JanJ9cXe7CSNy/ZAx/ZG1Cq9BgRTELmQ=; b=Gt2CXFXF30KiLt0/W5zjehS0Fj4PnPoedIauhr9xKRoUZIwlbJfzN92cCyTwlfDwHo ZHRFx4eRyrvuiGphqaCcKto5ZypyMhMHNrDd9Faswm/xLvyrdrlNQ7c+OIJi4oXWxxyP MXU9qv4rJyGWRITqwFsJ91rSDjKUuvmMdLbxUCqKWY0VoRRuRfh5ygAV7gbN3WEbPhnU PpQqHGTLzIOVlljhBRnD92AFmKp33D9Tq1zkbk6dA4Zoy7vpsykGlUZUGvGOoUC4H6/2 fkCm8LkUj19zQ786Afj18EVrFwnHw+MSqziRHGGsCX77iEhXlTosEMjxlAHGYFSpDtER XM5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NUApV7x1eW6JanJ9cXe7CSNy/ZAx/ZG1Cq9BgRTELmQ=; b=H0ycOXs21u8Y8FmAHXtXRt8988Ybk/pCEqaN6PY6/qp/HSDLXuE1V71OKm/4KAqRHj kEBYb6CGBrIy1YwTvkWBi3atSgziCvXqZ9rVWv+RBJAkM6Zj1mOuwh54Xp/T8HS+EbBO nzQMup/kTagzfV6rW7oYMyeI22K6JJYZPvlGpCeCtaUkrmvtGzzwlinNJIUJzhbwVbDB hLuxYdH8cDMc2vrMSgRFKuYZ7810euGiKeqUqYzHT08QIMULf31ZPx6KZX8pC7hqZarP k6hKjh6U2UIlSbnXzSikVBXkkb+pvjjGXZKCC4Zvtih6gA76nF7BviO3KbGfpXWnp5we SBVQ== X-Gm-Message-State: AOAM533gIlB54dgi3S0FAQk3xdH/hNjBGaOfPsGL3H03rtWIJaF3hdbI xzO5HNs8gi4+ljqHxBqH1+7dcHjDjL6T7Q== X-Google-Smtp-Source: ABdhPJwgmbEjhur16T5nlp/4TP7ai2JIfx3HsURvRhCkIhnDJoBaTvXCS7cLl28N8lWxMxP4IVWCNA== X-Received: by 2002:a17:903:4052:b0:155:fc0b:48fb with SMTP id n18-20020a170903405200b00155fc0b48fbmr21514473pla.27.1649462874409; Fri, 08 Apr 2022 17:07:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 12/16] target/arm: Enable SCR and HCR bits for RAS Date: Fri, 8 Apr 2022 17:07:38 -0700 Message-Id: <20220409000742.293691-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220409000742.293691-1-richard.henderson@linaro.org> References: <20220409000742.293691-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1649462983598100001 Content-Type: text/plain; charset="utf-8" Enable writes to the TERR and TEA bits when RAS is enabled. These bits are otherwise RES0. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 01f8558fca..2f6b02af7e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1765,6 +1765,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) } valid_mask &=3D ~SCR_NET; =20 + if (cpu_isar_feature(aa64_ras, cpu)) { + valid_mask |=3D SCR_TERR; + } if (cpu_isar_feature(aa64_lor, cpu)) { valid_mask |=3D SCR_TLOR; } @@ -1779,6 +1782,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) } } else { valid_mask &=3D ~(SCR_RW | SCR_ST); + if (cpu_isar_feature(aa32_ras, cpu)) { + valid_mask |=3D SCR_TERR; + } } =20 if (!arm_feature(env, ARM_FEATURE_EL2)) { @@ -5289,6 +5295,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t v= alue, uint64_t valid_mask) if (cpu_isar_feature(aa64_vh, cpu)) { valid_mask |=3D HCR_E2H; } + if (cpu_isar_feature(aa64_ras, cpu)) { + valid_mask |=3D HCR_TERR | HCR_TEA; + } if (cpu_isar_feature(aa64_lor, cpu)) { valid_mask |=3D HCR_TLOR; } --=20 2.25.1 From nobody Mon Feb 9 20:13:22 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1649463968; cv=none; d=zohomail.com; s=zohoarc; b=BM1l25YntA1LxKvmVPOItPZvZ41pA+Oqe7gCeoNMmXsh8vMXnfcVBDufp3QXOFb6hW4ER1TvTXtP1lV/LrAVNcjK973VVid9qHA7MfKhWwI6IskISkGWJ9tCCfWjPXsyVr1NX1Ml0UC7bXlqBKP1L631h1E0aCOjOlCqHcGaI3E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649463968; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ift/JdXJdiUN1/9UO2Y1HJ2r6G0V4xUYKPjDXLj7jTI=; b=fXrFRuoH7Plmyy/nmaH7xJ3cxwLBFFUsQBHpK5hpEGL5I9AjrhcqlBbC/xXQYgJS4hQ5YROSXnK3zQVclrDWkOmK1XRx/OETvqxs/s3ONl1Mx0MasLHmcDBemTuNqmikmT9PBYiBr8DslWQnWXWica2DLzFhU6HPqCnJuXDBORc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1649463968494301.99847539855693; Fri, 8 Apr 2022 17:26:08 -0700 (PDT) Received: from localhost ([::1]:41476 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ncyvX-0002la-H5 for importer@patchew.org; Fri, 08 Apr 2022 20:26:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:46958) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ncydy-0008WU-Ub for qemu-devel@nongnu.org; Fri, 08 Apr 2022 20:07:59 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]:45832) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ncydx-0003V3-1N for qemu-devel@nongnu.org; Fri, 08 Apr 2022 20:07:58 -0400 Received: by mail-pj1-x102e.google.com with SMTP id a16-20020a17090a6d9000b001c7d6c1bb13so11160552pjk.4 for ; Fri, 08 Apr 2022 17:07:56 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id t69-20020a637848000000b0039831d6dc23sm22073961pgc.94.2022.04.08.17.07.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 17:07:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ift/JdXJdiUN1/9UO2Y1HJ2r6G0V4xUYKPjDXLj7jTI=; b=Lm2AKhZtyXLF8PyBlGCGNV3tUkzaBj0canAptmRvTyzjZ6wNWGD6Q4yuJaoYmfXl/K XB498e48LfRfhqmAeD9sqzZ3/8tYxE1Ndqh20Y75ddyFoeDFvl0NMK6B9qaCywjRYDcw avPv3/QhijmZev6ETcRfxuquy5hJAJK5HbZMsRbttaafLeTjDM/dbHfnyvenH1L103wX f1CCQZ84v+mnvniI+0yE+lZ8kMNzt0qGFy//ShLZ0fXUbaVCv+YPxUYS5AMh+yn3IdVy vIAl4Zd5CxkonhPZuKoIxNHTGRhApIN79XXcoPdrelWHhLXdzrHxV/o8H4fwx/nrExwg aDWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ift/JdXJdiUN1/9UO2Y1HJ2r6G0V4xUYKPjDXLj7jTI=; b=CR+q5D0BdH7cy5LlRJ86pYGs12WsCgQeaeYl48qYLZqgqNqFIhUqKa+1+zLkCMiXx4 XkVC7uom+LfGPb5thgmZzIsozWQ/RkRTItx6DRjcpXPk3wNyul21qGXuq3u3oU61sGV+ l6EfyYQPKkPo6E2HWRAC9CWjMtroQrWMC9FBJGqYVSLNoOVF6fD64JBFNJN7ORRIyrux 73ExhnDjqefONRYPYm46u6J4T1kQ+lsgmKK7EZQYrSe3Tlf2Idg0sVLdQPxnhn3EqddE GvDPmdZkB3BUApE+0zGw+gNs/nPimOJeUO3D/EpkGiT7SGm333gIv2WwXvz11MERWplq rRgg== X-Gm-Message-State: AOAM532fEbWG/AUfUn7dJwyL1iTQjGgSdkwDSxBDHl0eAis8V00jArbk MTpQ/+5szb++oS7q87KH/kPr7aBZuh7Y6g== X-Google-Smtp-Source: ABdhPJwHHiJi2igKkF/rd9dVfYZAaPlif4hEvvdmPWtEMNnKBNSG997dffm89im0JozPWcsGnNuPjg== X-Received: by 2002:a17:90b:4c44:b0:1c7:1326:ec90 with SMTP id np4-20020a17090b4c4400b001c71326ec90mr24350025pjb.87.1649462875452; Fri, 08 Apr 2022 17:07:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 13/16] target/arm: Implement virtual SError exceptions Date: Fri, 8 Apr 2022 17:07:39 -0700 Message-Id: <20220409000742.293691-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220409000742.293691-1-richard.henderson@linaro.org> References: <20220409000742.293691-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1649463970338100001 Content-Type: text/plain; charset="utf-8" Virtual SError exceptions are raised by setting HCR_EL2.VSE, and are routed to EL1 just like other virtual exceptions. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 2 ++ target/arm/internals.h | 8 ++++++++ target/arm/syndrome.h | 5 +++++ target/arm/cpu.c | 38 +++++++++++++++++++++++++++++++++++++- target/arm/helper.c | 29 ++++++++++++++++++++++++++++- 5 files changed, 80 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 66becc47f2..eb8cb738b5 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -55,6 +55,7 @@ #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ +#define EXCP_VSERR 24 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ =20 #define ARMV7M_EXCP_RESET 1 @@ -88,6 +89,7 @@ enum { #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 +#define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 =20 /* The usual mapping for an AArch64 system register to its AArch32 * counterpart is for the 32 bit world to have access to the lower diff --git a/target/arm/internals.h b/target/arm/internals.h index 596fd53619..25ff9628f6 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -935,6 +935,14 @@ void arm_cpu_update_virq(ARMCPU *cpu); */ void arm_cpu_update_vfiq(ARMCPU *cpu); =20 +/** + * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit + * + * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request, + * following a change to the HCR_EL2.VSE bit. + */ +void arm_cpu_update_vserr(ARMCPU *cpu); + /** * arm_mmu_idx_el: * @env: The cpu environment diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 8cde8e7243..0cb26dde7d 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -287,4 +287,9 @@ static inline uint32_t syn_pcalignment(void) return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; } =20 +static inline uint32_t syn_serror(uint32_t extra) +{ + return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra; +} + #endif /* TARGET_ARM_SYNDROME_H */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d815d3a397..1a1b1612a8 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -84,7 +84,7 @@ static bool arm_cpu_has_work(CPUState *cs) return (cpu->power_state !=3D PSCI_OFF) && cs->interrupt_request & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD - | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ + | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR | CPU_INTERRUPT_EXITTB); } =20 @@ -508,6 +508,12 @@ static inline bool arm_excp_unmasked(CPUState *cs, uns= igned int excp_idx, return false; } return !(env->daif & PSTATE_I); + case EXCP_VSERR: + if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { + /* VIRQs are only taken when hypervized. */ + return false; + } + return !(env->daif & PSTATE_A); default: g_assert_not_reached(); } @@ -629,6 +635,17 @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int i= nterrupt_request) goto found; } } + if (interrupt_request & CPU_INTERRUPT_VSERR) { + excp_idx =3D EXCP_VSERR; + target_el =3D 1; + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { + /* Taking a virtual abort clears HCR_EL2.VSE */ + env->cp15.hcr_el2 &=3D ~HCR_VSE; + cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); + goto found; + } + } return false; =20 found: @@ -681,6 +698,25 @@ void arm_cpu_update_vfiq(ARMCPU *cpu) } } =20 +void arm_cpu_update_vserr(ARMCPU *cpu) +{ + /* + * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. + */ + CPUARMState *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); + + bool new_state =3D env->cp15.hcr_el2 & HCR_VSE; + + if (new_state !=3D ((cs->interrupt_request & CPU_INTERRUPT_VSERR) !=3D= 0)) { + if (new_state) { + cpu_interrupt(cs, CPU_INTERRUPT_VSERR); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); + } + } +} + #ifndef CONFIG_USER_ONLY static void arm_cpu_set_irq(void *opaque, int irq, int level) { diff --git a/target/arm/helper.c b/target/arm/helper.c index 2f6b02af7e..bd1c8e01cb 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1873,7 +1873,12 @@ static uint64_t isr_read(CPUARMState *env, const ARM= CPRegInfo *ri) } } =20 - /* External aborts are not possible in QEMU so A bit is always clear */ + if (hcr_el2 & HCR_AMO) { + if (cs->interrupt_request & CPU_INTERRUPT_VSERR) { + ret |=3D CPSR_A; + } + } + return ret; } =20 @@ -5338,6 +5343,7 @@ static void do_hcr_write(CPUARMState *env, uint64_t v= alue, uint64_t valid_mask) g_assert(qemu_mutex_iothread_locked()); arm_cpu_update_virq(cpu); arm_cpu_update_vfiq(cpu); + arm_cpu_update_vserr(cpu); } =20 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) @@ -9529,6 +9535,7 @@ void arm_log_exception(CPUState *cs) [EXCP_LSERR] =3D "v8M LSERR UsageFault", [EXCP_UNALIGNED] =3D "v7M UNALIGNED UsageFault", [EXCP_DIVBYZERO] =3D "v7M DIVBYZERO UsageFault", + [EXCP_VSERR] =3D "Virtual SERR", }; =20 if (idx >=3D 0 && idx < ARRAY_SIZE(excnames)) { @@ -10041,6 +10048,20 @@ static void arm_cpu_do_interrupt_aarch32(CPUState = *cs) mask =3D CPSR_A | CPSR_I | CPSR_F; offset =3D 4; break; + case EXCP_VSERR: + { + /* Construct the SError syndrome from AET and ExT fields. */ + ARMMMUFaultInfo fi =3D { .type =3D ARMFault_AsyncExternal, }; + env->exception.fsr =3D arm_fi_to_sfsc(&fi); + env->exception.fsr |=3D env->cp15.vsesr_el2 & 0xd000; + A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); + + new_mode =3D ARM_CPU_MODE_ABT; + addr =3D 0x10; + mask =3D CPSR_A | CPSR_I; + offset =3D 8; + } + break; case EXCP_SMC: new_mode =3D ARM_CPU_MODE_MON; addr =3D 0x08; @@ -10261,6 +10282,12 @@ static void arm_cpu_do_interrupt_aarch64(CPUState = *cs) case EXCP_VFIQ: addr +=3D 0x100; break; + case EXCP_VSERR: + addr +=3D 0x180; + /* Construct the SError syndrome from IDS and ISS fields. */ + env->exception.syndrome =3D syn_serror(env->cp15.vsesr_el2 & 0x1ff= ffff); + env->cp15.esr_el[new_el] =3D env->exception.syndrome; + break; default: cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); } --=20 2.25.1 From nobody Mon Feb 9 20:13:22 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1649463621; cv=none; d=zohomail.com; s=zohoarc; b=haSGg7WNaWWxrJGaOAGPePOntAvyWa7ibmmQWcwJJQP4F1YVDykdyPH1ajm+sltKec0FW29C5S5ED3zc4iBmorp8tvJzTuFpUwhohBCw9LAeGsuSj1+E/vXvTw45bAubfrHaS2ky3KTwvt0EpR4Y8I6WoyhVQZF18+2eeeQH/6E= ARC-Message-Signature: i=1; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id t69-20020a637848000000b0039831d6dc23sm22073961pgc.94.2022.04.08.17.07.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 17:07:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cIY+bgtJHMt/2+Zrm+Ge6EoREEHsHthKWWaUH9R3MJM=; b=dCQgfZbI/0AdGP5jpMZI4VnCvpf8UOWXDkBs8466lC0gyWQ6j+LhtUgrzy/DXL0ESb lG8OlU/m2fF6sutFCgeh16Ap7zOBCdV9wyD1Vop4+p9mUOlLzBA2Rjf+cp+V/9jAh9O0 M2fHHOFuOiaGoHbqjuCAtIgFmtgYxjZbxmfFE62ODErrYbFEzZdrtFiIyRJjc30DL/l7 H04Vkq1u01IMqpZ9DhXNCqqS3pl3oP7P7qdSwdaNlMMu0O9JyljBXaXmaze6F89wD4BU uQv43cLYOw5bjqUhuS/S5eInPf9k58W703TySPkyL6hJ5voPJ7iTWKFTJVknosRfIzVu yxXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cIY+bgtJHMt/2+Zrm+Ge6EoREEHsHthKWWaUH9R3MJM=; b=FXSuZV3O3OznWAN8gvI5p155Sq4l5d9BhSkjxlS2GGcU6DuiIzBcHQa67dptt7e+sO KaXeCRoZw9v9+GlsOWTF3IH+zRRZc94n7C0vW7L3mbixAdJ/9dW9gW5dH/KfL4xIAmwa VP+KkddGVSnHrgl80f03yim8BcPtve6fID2qbhFf3edh2RFC3k+WS1TkGO6i4uAK3xki hBYocEN9Zmlp9SiBszXUD4K0Y+UePzDyFSZ6f80CL8WVWZlGXpLuhx8psUP7SbfCIHhe XT3/TwEzaq1LWUbXjw6jXp0xMaa17InZ45NbyFB/4ZhtM8hwttJu2DO620TBE6xz8ejm TijQ== X-Gm-Message-State: AOAM531LLPIShkXfYjyu+k2TVn7ZkN2znnQWNzZ9wk74N62iR+8DQmee ZPKbbLgiapRa9y1LxtWRPXVtgJSYI79Nig== X-Google-Smtp-Source: ABdhPJzUoP9NCllir3g1MlfJmPa9zVIS5Dg6/25d33PpDtTjFxpJe+q05hWIjA39lwiRRgKPmu0vPQ== X-Received: by 2002:a17:902:da8e:b0:158:2837:7fe8 with SMTP id j14-20020a170902da8e00b0015828377fe8mr4246489plx.64.1649462876435; Fri, 08 Apr 2022 17:07:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 14/16] target/arm: Implement ESB instruction Date: Fri, 8 Apr 2022 17:07:40 -0700 Message-Id: <20220409000742.293691-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220409000742.293691-1-richard.henderson@linaro.org> References: <20220409000742.293691-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1649463622957100001 Content-Type: text/plain; charset="utf-8" Check for and defer any pending virtual SError. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.h | 1 + target/arm/a32.decode | 16 +++++++++----- target/arm/t32.decode | 18 +++++++-------- target/arm/op_helper.c | 45 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 7 ++++++ target/arm/translate.c | 10 +++++++++ 6 files changed, 82 insertions(+), 15 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index b463d9343b..bb7f901668 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -54,6 +54,7 @@ DEF_HELPER_1(wfe, void, env) DEF_HELPER_1(yield, void, env) DEF_HELPER_1(pre_hvc, void, env) DEF_HELPER_2(pre_smc, void, env, i32) +DEF_HELPER_1(esb, void, env) =20 DEF_HELPER_3(cpsr_write, void, env, i32, i32) DEF_HELPER_2(cpsr_write_eret, void, env, i32) diff --git a/target/arm/a32.decode b/target/arm/a32.decode index fcd8cd4f7d..f2ca480949 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -187,13 +187,17 @@ SMULTT .... 0001 0110 .... 0000 .... 1110 .= ... @rd0mn =20 { { - YIELD ---- 0011 0010 0000 1111 ---- 0000 0001 - WFE ---- 0011 0010 0000 1111 ---- 0000 0010 - WFI ---- 0011 0010 0000 1111 ---- 0000 0011 + [ + YIELD ---- 0011 0010 0000 1111 ---- 0000 0001 + WFE ---- 0011 0010 0000 1111 ---- 0000 0010 + WFI ---- 0011 0010 0000 1111 ---- 0000 0011 =20 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 - # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 + # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 + + ESB ---- 0011 0010 0000 1111 ---- 0001 0000 + ] =20 # The canonical nop ends in 00000000, but the whole of the # rest of the space executes as nop if otherwise unsupported. diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 78fadef9d6..f21ad0167a 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -364,17 +364,17 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .= ... @rdm [ # Hints, and CPS { - YIELD 1111 0011 1010 1111 1000 0000 0000 0001 - WFE 1111 0011 1010 1111 1000 0000 0000 0010 - WFI 1111 0011 1010 1111 1000 0000 0000 0011 + [ + YIELD 1111 0011 1010 1111 1000 0000 0000 0001 + WFE 1111 0011 1010 1111 1000 0000 0000 0010 + WFI 1111 0011 1010 1111 1000 0000 0000 0011 =20 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV 1111 0011 1010 1111 1000 0000 0000 0100 - # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1111 0011 1010 1111 1000 0000 0000 0100 + # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 =20 - # For M-profile minimal-RAS ESB can be a NOP, which is the - # default behaviour since it is in the hint space. - # ESB 1111 0011 1010 1111 1000 0000 0001 0000 + ESB 1111 0011 1010 1111 1000 0000 0001 0000 + ] =20 # The canonical nop ends in 0000 0000, but the whole rest # of the space is "reserved hint, behaves as nop". diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 70b42b55fd..f50424b301 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -972,3 +972,48 @@ void HELPER(probe_access)(CPUARMState *env, target_ulo= ng ptr, access_type, mmu_idx, ra); } } + +void HELPER(esb)(CPUARMState *env) +{ + /* + * QEMU does not have a source of physical SErrors, so we are + * only concerned with virtual SErrors. + * + * During translation, we have already checked: RAS enabled, + * EL2 present (enabled check done in arm_hcr_el2_eff), and + * PSTATE.EL in {EL0, EL1}. This function corresponds to + * AArch64.vESBOperation(), noting that the AArch32 version + * is not functionally different. + */ + uint64_t hcr =3D arm_hcr_el2_eff(env); + bool enabled =3D !(hcr & HCR_TGE) && (hcr & HCR_AMO); + bool pending =3D enabled && (hcr & HCR_VSE); + bool masked =3D (env->daif & PSTATE_A); + + /* If VSE pending and masked, defer the exception. */ + if (pending && masked) { + uint32_t syndrome; + + if (arm_el_is_aa64(env, 1)) { + /* Copy across IDS and ISS from VSESR. */ + syndrome =3D env->cp15.vsesr_el2 & 0x1ffffff; + } else { + ARMMMUFaultInfo fi =3D { .type =3D ARMFault_AsyncExternal }; + + if (extended_addresses_enabled(env)) { + syndrome =3D arm_fi_to_lfsc(&fi); + } else { + syndrome =3D arm_fi_to_sfsc(&fi); + } + /* Copy across AET and ExT from VSESR. */ + syndrome |=3D env->cp15.vsesr_el2 & 0xd000; + } + + /* Set VDISR_EL2.A along with the syndrome. */ + env->cp15.vdisr_el2 =3D syndrome | (1u << 31); + + /* Clear pending virtual SError */ + env->cp15.hcr_el2 &=3D ~HCR_VSE; + cpu_reset_interrupt(env_cpu(env), CPU_INTERRUPT_VSERR); + } +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 9333d7be41..cc54dff83c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1469,6 +1469,13 @@ static void handle_hint(DisasContext *s, uint32_t in= sn, gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); } break; + case 0b10000: /* ESB */ + if (dc_isar_feature(aa64_ras, s) && + arm_dc_feature(s, ARM_FEATURE_EL2) && + s->current_el <=3D 1) { + gen_helper_esb(cpu_env); + } + break; case 0b11000: /* PACIAZ */ if (s->pauth_active) { gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], diff --git a/target/arm/translate.c b/target/arm/translate.c index bf2196b9e2..b42ca53d99 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6275,6 +6275,16 @@ static bool trans_WFI(DisasContext *s, arg_WFI *a) return true; } =20 +static bool trans_ESB(DisasContext *s, arg_ESB *a) +{ + if (dc_isar_feature(aa32_ras, s) && + arm_dc_feature(s, ARM_FEATURE_EL2) && + s->current_el <=3D 1) { + gen_helper_esb(cpu_env); + } + return true; +} + static bool trans_NOP(DisasContext *s, arg_NOP *a) { return true; --=20 2.25.1 From nobody Mon Feb 9 20:13:22 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1649463216; cv=none; d=zohomail.com; s=zohoarc; b=jcNEQuWW+BFqgKpTuKayHgOIpKtr1o0PIz6VjPgKi4QGYTZ8SEOXRrI8rOOEI1sQ6jXInh7K8Z+jmwsEYUEsysaRMJdNiXIu7AAoW/0ikKDq6gAfoAPOFxgpP/9b3dAj5sRZd6O460y0PRKxqFsKR2bPN+Cwer4ELjbmU6LurKc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649463216; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=e+gf4njBlT4aculnG55HysMJzlBG+wUfm2aGsCO3sRk=; b=B7h72ey1kpeVirqAcftSQ/K7XK1AxMr0xMRCsbcXoTLfpw6DJabeygJNT3tlOzs+XKs9hBYkeFMzEuS6n02rusV37YAqVwadpB1dkGawZ6SOq77JkFwihWV18bYskiv8zjWo+/IlBnJJehiwfBm7PbPv0s6Ki2jVmd6hjNB404o= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1649463216480562.8519539626595; Fri, 8 Apr 2022 17:13:36 -0700 (PDT) Received: from localhost ([::1]:44720 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ncyjP-0001sr-FO for importer@patchew.org; Fri, 08 Apr 2022 20:13:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:47010) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1ncye1-00005g-50 for qemu-devel@nongnu.org; Fri, 08 Apr 2022 20:08:01 -0400 Received: from mail-pg1-x532.google.com ([2607:f8b0:4864:20::532]:33346) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1ncydz-0003Vp-O0 for qemu-devel@nongnu.org; Fri, 08 Apr 2022 20:08:00 -0400 Received: by mail-pg1-x532.google.com with SMTP id k14so9132559pga.0 for ; Fri, 08 Apr 2022 17:07:58 -0700 (PDT) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id t69-20020a637848000000b0039831d6dc23sm22073961pgc.94.2022.04.08.17.07.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 17:07:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=e+gf4njBlT4aculnG55HysMJzlBG+wUfm2aGsCO3sRk=; b=zqS+U8QkUzgNwKxjFsjN6LoAxPPFoVnxUIRUOF/cV3VLDTShiR5ODafF83uydhHuiD MBkJnIURFf1eh+ELCQWRPCXfUviOSEmlRoU8FvcKgaMNECKgeIWQ9xYVaVQUt1oOQ+TW f/9wulUGrZRWZmHJSBSUX8r6yfhEKEjLqo3LsipQxkPpZo5emmZt+d+M4GbKO36M7Hz0 HhXstYx2XzPinK+9k8zkKOdKBBnxXPYmSEawy/UVa0GmYHofzus2rrHP6TlBB5WkxJHR bjMm8JqwZQ6Q/K4bwtO3ePIE4R7KmppJWw2KSl76qC9WckvprB1IDEc7r2WJqUMB0utP E5MQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1649463216992100003 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 1 + 2 files changed, 2 insertions(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index f20fb6d9e1..03c6707111 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -801,6 +801,7 @@ static void aarch64_max_initfn(Object *obj) t =3D cpu->isar.id_aa64pfr0; t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, RAS, 1); /* FEAT_RAS */ t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index a443e8c48a..5cce9116d0 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -72,6 +72,7 @@ void arm32_max_features(ARMCPU *cpu) =20 t =3D cpu->isar.id_pfr0; t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ + t =3D FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ cpu->isar.id_pfr0 =3D t; =20 t =3D cpu->isar.id_pfr2; --=20 2.25.1 From nobody Mon Feb 9 20:13:22 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id t69-20020a637848000000b0039831d6dc23sm22073961pgc.94.2022.04.08.17.07.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 17:07:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=q+NlwqyQSZalosOWPHcbsVEejz0bpldPcXN2ZslQ7DA=; b=PKZRZPekTT/IhFJLLRCM4HPB5ZkgsadpgzFEc/j8fwlhSrNrvmdaV92OBPSnVFjUqV 5ExHf2CFiJFhl6BY7brKRF69WCAMI10Ba1XK4Jobh5fh7e5dSQm/JfwHHWz7mPqbVTss s/jxwxyQc1sTayj/05iHD8KxDJkki5AgYayG8KPJYU3EYmoWvOZIKezhywC3BrVpw5Qc RC5OnYn2P+T+d65OwbCQcl5fQccNP3/yYn2SfiD41blHkqw8rf+nAy5TK1aBrHBi35Yp r3EHR1jk2fi+8X84YntnEqyivhQZbRcilDMTqvruLWdqEDAepCXakkNjZZIM1XRej8wT +hSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=q+NlwqyQSZalosOWPHcbsVEejz0bpldPcXN2ZslQ7DA=; b=C9YyfFaC7rVq/r17fSyE3PIePewrZ2HZmCb4EJjz7E8tlXvChmeg2GdxuYK9/nR5de mNAY1hMAZZ7RqrMiUCp3xA588yybnK2F6Cg5RBZSIL8hHWOf1wDBHygy2j0R7/vOGgis I0kHV6Bdjrl4wR4OjJTgDvv2MYQkcaXJ/b50sLUQtZq6WMiowDO2wdoDrT1myAgyDtma +1254m4B3tLcbt45ncV41NsvDeD0pW2pb2mt2BfqDXheI84X1k3c15GbI1Cxnjvq0f4m g6bxyUL9nFt8mVR463vNi86CBESktFL2c80+B6aTmIxTJ6v6E+oiLHNCA7wj+wmTg2Mk QttQ== X-Gm-Message-State: AOAM533nJipH1Epv3l0Bt+37ccn3f4QSiUP6tWgNb0JjRwSeZ8cuKT7m T+KcL+cdG/8x0m1FY1Kg/r+o4O3E4COHyQ== X-Google-Smtp-Source: ABdhPJxxMzkQLO1QiDicw65+vvX3ldUgvzajX37CblgvTPqnp09TrpIfS+9ec8NiZyuP0BgpZp2ArQ== X-Received: by 2002:a17:90a:4604:b0:1bc:8bdd:4a63 with SMTP id w4-20020a17090a460400b001bc8bdd4a63mr24613194pjg.147.1649462878511; Fri, 08 Apr 2022 17:07:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 16/16] target/arm: Enable FEAT_IESB for -cpu max Date: Fri, 8 Apr 2022 17:07:42 -0700 Message-Id: <20220409000742.293691-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220409000742.293691-1-richard.henderson@linaro.org> References: <20220409000742.293691-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1649464118940100001 Content-Type: text/plain; charset="utf-8" This feature is AArch64 only, and applies to physical SErrors, which QEMU does not implement, thus the feature is a nop. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu64.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 03c6707111..def0f1fdcb 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -838,6 +838,7 @@ static void aarch64_max_initfn(Object *obj) t =3D cpu->isar.id_aa64mmfr2; t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ t =3D FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ cpu->isar.id_aa64mmfr2 =3D t; --=20 2.25.1