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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id i3-20020adffc03000000b0020616ee90dbsm11498849wrr.42.2022.04.08.07.16.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 08 Apr 2022 07:16:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QiNb/fWTGwmLaiD1DUdHdEATfanLil6GCXqbm2UfHKk=; b=yVHLooKaPmkQsaX+sIyiO3+MAUYHyaYySYKjxQbGPel7pHs/FzES2952urnlI6VWzb FwUvn1MnsUmlskMH/n907h3ULItBwdn9Tf8QJ7+mwxpsMrAgTYlJoxZkjUdzwnwYX+qA 61Eykp33mRGMn/yFTy+sj/S4NNcHIedQvguMdcZeXL7noC6nMuzR23HfkxGDL7COBsHm 6Avs/ng+6IJUHGRSmuY7YOZrW5ob1lWdYWEh3nmV6YSUO20YsHFu/NMAEXm8FV4y2o7N eZ0g/5R32PQ8xTevVwpL8FMYWAjNmzggnNwkRdrsMLumMfL9WUaWTt98r/n2Uw/mZiU6 greA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QiNb/fWTGwmLaiD1DUdHdEATfanLil6GCXqbm2UfHKk=; b=CeLRm0DI26sU8DeE5x7YN6CiJKiRR+cVacph8U9wUUaah+UxIRxLSHNOVTS4pLvP+f dLsyXc+hIuBCM3kXtHybyRyH0NpNkQMwndz/qc4rXvUb1yIzq31q7nsbA6wAzlYgaZpc NTQ1MQuvDmFk/D/w153G+ua/3TCyk4NFtRmk0rUjViZy1TlU2dE/WoOIEAv8V0quB9Vi lgSZyVG2zet/N5qglne2rlUsKo7ZKBoSR/bRioAQBH086eMkQtKXWCykXi8pKbgFfljl AWV84SdlhD4bthgKBKLfkQMisoyk3mOxWi9hQasqso6KSZToxR9izAss96kZCy0I8tMc e9lA== X-Gm-Message-State: AOAM531jSHUg17aUGHOgF36EVA8kJxnG6MjVIpvltlyFTxlKVwFauVNQ mp1EdrAfRlJFRxy3uDumgfmePQ== X-Google-Smtp-Source: ABdhPJxaQK9/ZrsILM6j9lOaHQy8JMaZkpjP5iyKmzTymHt2AZCja+5jQGdjekNAkOMhQLBaTNnuqw== X-Received: by 2002:a7b:cb4b:0:b0:38e:9c4c:9120 with SMTP id v11-20020a7bcb4b000000b0038e9c4c9120mr5266668wmj.76.1649427390881; Fri, 08 Apr 2022 07:16:30 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 41/41] hw/arm/virt: Support TCG GICv4 Date: Fri, 8 Apr 2022 15:15:50 +0100 Message-Id: <20220408141550.1271295-42-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220408141550.1271295-1-peter.maydell@linaro.org> References: <20220408141550.1271295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Marc Zyngier Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1649429683303100001 Content-Type: text/plain; charset="utf-8" Add support for the TCG GICv4 to the virt board. For the board, the GICv4 is very similar to the GICv3, with the only difference being the size of the redistributor frame. The changes here are thus: * calculating virt_redist_capacity correctly for GICv4 * changing various places which were "if GICv3" to be "if not GICv2" * the commandline option handling Note that using GICv4 reduces the maximum possible number of CPUs on the virt board from 512 to 317, because we can now only fit half as many redistributors into the redistributor regions we have defined. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- docs/system/arm/virt.rst | 5 ++- include/hw/arm/virt.h | 12 +++++-- hw/arm/virt.c | 70 ++++++++++++++++++++++++++++++---------- 3 files changed, 67 insertions(+), 20 deletions(-) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index 1544632b674..5d13ec2798a 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -99,11 +99,14 @@ gic-version GICv2 ``3`` GICv3 + ``4`` + GICv4 (requires ``virtualization`` to be ``on``) ``host`` Use the same GIC version the host provides, when using KVM ``max`` Use the best GIC version possible (same as host when using KVM; - currently same as ``3``` for TCG, but this may change in future) + with TCG this is currently ``3`` if ``virtualization`` is ``off`` and + ``4`` if ``virtualization`` is ``on``, but this may change in future) =20 its Set ``on``/``off`` to enable/disable ITS instantiation. The default is `= `on`` diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h index 360463e6bfb..15feabac63d 100644 --- a/include/hw/arm/virt.h +++ b/include/hw/arm/virt.h @@ -113,6 +113,7 @@ typedef enum VirtGICType { VIRT_GIC_VERSION_HOST, VIRT_GIC_VERSION_2, VIRT_GIC_VERSION_3, + VIRT_GIC_VERSION_4, VIRT_GIC_VERSION_NOSEL, } VirtGICType; =20 @@ -188,7 +189,14 @@ bool virt_is_acpi_enabled(VirtMachineState *vms); /* Return number of redistributors that fit in the specified region */ static uint32_t virt_redist_capacity(VirtMachineState *vms, int region) { - return vms->memmap[region].size / GICV3_REDIST_SIZE; + uint32_t redist_size; + + if (vms->gic_version =3D=3D VIRT_GIC_VERSION_3) { + redist_size =3D GICV3_REDIST_SIZE; + } else { + redist_size =3D GICV4_REDIST_SIZE; + } + return vms->memmap[region].size / redist_size; } =20 /* Return the number of used redistributor regions */ @@ -196,7 +204,7 @@ static inline int virt_gicv3_redist_region_count(VirtMa= chineState *vms) { uint32_t redist0_capacity =3D virt_redist_capacity(vms, VIRT_GIC_REDIS= T); =20 - assert(vms->gic_version =3D=3D VIRT_GIC_VERSION_3); + assert(vms->gic_version !=3D VIRT_GIC_VERSION_2); =20 return (MACHINE(vms)->smp.cpus > redist0_capacity && vms->highmem_redists) ? 2 : 1; diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 577c1e65188..dfedc6b22ee 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -522,7 +522,7 @@ static void fdt_add_gic_node(VirtMachineState *vms) qemu_fdt_setprop_cell(ms->fdt, nodename, "#address-cells", 0x2); qemu_fdt_setprop_cell(ms->fdt, nodename, "#size-cells", 0x2); qemu_fdt_setprop(ms->fdt, nodename, "ranges", NULL, 0); - if (vms->gic_version =3D=3D VIRT_GIC_VERSION_3) { + if (vms->gic_version !=3D VIRT_GIC_VERSION_2) { int nb_redist_regions =3D virt_gicv3_redist_region_count(vms); =20 qemu_fdt_setprop_string(ms->fdt, nodename, "compatible", @@ -708,6 +708,9 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) case VIRT_GIC_VERSION_3: revision =3D 3; break; + case VIRT_GIC_VERSION_4: + revision =3D 4; + break; default: g_assert_not_reached(); } @@ -722,7 +725,7 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) qdev_prop_set_bit(vms->gic, "has-security-extensions", vms->secure= ); } =20 - if (vms->gic_version =3D=3D VIRT_GIC_VERSION_3) { + if (vms->gic_version !=3D VIRT_GIC_VERSION_2) { uint32_t redist0_capacity =3D virt_redist_capacity(vms, VIRT_GIC_R= EDIST); uint32_t redist0_count =3D MIN(smp_cpus, redist0_capacity); =20 @@ -756,7 +759,7 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) gicbusdev =3D SYS_BUS_DEVICE(vms->gic); sysbus_realize_and_unref(gicbusdev, &error_fatal); sysbus_mmio_map(gicbusdev, 0, vms->memmap[VIRT_GIC_DIST].base); - if (vms->gic_version =3D=3D VIRT_GIC_VERSION_3) { + if (vms->gic_version !=3D VIRT_GIC_VERSION_2) { sysbus_mmio_map(gicbusdev, 1, vms->memmap[VIRT_GIC_REDIST].base); if (nb_redist_regions =3D=3D 2) { sysbus_mmio_map(gicbusdev, 2, @@ -794,7 +797,7 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) ppibase + timer_irq[irq= ])); } =20 - if (vms->gic_version =3D=3D VIRT_GIC_VERSION_3) { + if (vms->gic_version !=3D VIRT_GIC_VERSION_2) { qemu_irq irq =3D qdev_get_gpio_in(vms->gic, ppibase + ARCH_GIC_MAINT_IRQ); qdev_connect_gpio_out_named(cpudev, "gicv3-maintenance-interru= pt", @@ -820,7 +823,7 @@ static void create_gic(VirtMachineState *vms, MemoryReg= ion *mem) =20 fdt_add_gic_node(vms); =20 - if (vms->gic_version =3D=3D VIRT_GIC_VERSION_3 && vms->its) { + if (vms->gic_version !=3D VIRT_GIC_VERSION_2 && vms->its) { create_its(vms); } else if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) { create_v2m(vms); @@ -1672,10 +1675,10 @@ static uint64_t virt_cpu_mp_affinity(VirtMachineSta= te *vms, int idx) * purposes are to make TCG consistent (with 64-bit KVM hosts) * and to improve SGI efficiency. */ - if (vms->gic_version =3D=3D VIRT_GIC_VERSION_3) { - clustersz =3D GICV3_TARGETLIST_BITS; - } else { + if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) { clustersz =3D GIC_TARGETLIST_BITS; + } else { + clustersz =3D GICV3_TARGETLIST_BITS; } } return arm_cpu_mp_affinity(idx, clustersz); @@ -1808,6 +1811,10 @@ static void finalize_gic_version(VirtMachineState *v= ms) error_report( "gic-version=3D3 is not supported with kernel-irqchip= =3Doff"); exit(1); + case VIRT_GIC_VERSION_4: + error_report( + "gic-version=3D4 is not supported with kernel-irqchip= =3Doff"); + exit(1); } } =20 @@ -1845,6 +1852,9 @@ static void finalize_gic_version(VirtMachineState *vm= s) case VIRT_GIC_VERSION_2: case VIRT_GIC_VERSION_3: break; + case VIRT_GIC_VERSION_4: + error_report("gic-version=3D4 is not supported with KVM"); + exit(1); } =20 /* Check chosen version is effectively supported by the host */ @@ -1868,7 +1878,12 @@ static void finalize_gic_version(VirtMachineState *v= ms) case VIRT_GIC_VERSION_MAX: if (module_object_class_by_name("arm-gicv3")) { /* CONFIG_ARM_GICV3_TCG was set */ - vms->gic_version =3D VIRT_GIC_VERSION_3; + if (vms->virt) { + /* GICv4 only makes sense if CPU has EL2 */ + vms->gic_version =3D VIRT_GIC_VERSION_4; + } else { + vms->gic_version =3D VIRT_GIC_VERSION_3; + } } else { vms->gic_version =3D VIRT_GIC_VERSION_2; } @@ -1876,6 +1891,12 @@ static void finalize_gic_version(VirtMachineState *v= ms) case VIRT_GIC_VERSION_HOST: error_report("gic-version=3Dhost requires KVM"); exit(1); + case VIRT_GIC_VERSION_4: + if (!vms->virt) { + error_report("gic-version=3D4 requires virtualization enabled"= ); + exit(1); + } + break; case VIRT_GIC_VERSION_2: case VIRT_GIC_VERSION_3: break; @@ -2043,14 +2064,16 @@ static void machvirt_init(MachineState *machine) vms->psci_conduit =3D QEMU_PSCI_CONDUIT_HVC; } =20 - /* The maximum number of CPUs depends on the GIC version, or on how - * many redistributors we can fit into the memory map. + /* + * The maximum number of CPUs depends on the GIC version, or on how + * many redistributors we can fit into the memory map (which in turn + * depends on whether this is a GICv3 or v4). */ - if (vms->gic_version =3D=3D VIRT_GIC_VERSION_3) { + if (vms->gic_version =3D=3D VIRT_GIC_VERSION_2) { + virt_max_cpus =3D GIC_NCPU; + } else { virt_max_cpus =3D virt_redist_capacity(vms, VIRT_GIC_REDIST) + virt_redist_capacity(vms, VIRT_HIGH_GIC_REDIST2); - } else { - virt_max_cpus =3D GIC_NCPU; } =20 if (max_cpus > virt_max_cpus) { @@ -2431,8 +2454,19 @@ static void virt_set_mte(Object *obj, bool value, Er= ror **errp) static char *virt_get_gic_version(Object *obj, Error **errp) { VirtMachineState *vms =3D VIRT_MACHINE(obj); - const char *val =3D vms->gic_version =3D=3D VIRT_GIC_VERSION_3 ? "3" := "2"; + const char *val; =20 + switch (vms->gic_version) { + case VIRT_GIC_VERSION_4: + val =3D "4"; + break; + case VIRT_GIC_VERSION_3: + val =3D "3"; + break; + default: + val =3D "2"; + break; + } return g_strdup(val); } =20 @@ -2440,7 +2474,9 @@ static void virt_set_gic_version(Object *obj, const c= har *value, Error **errp) { VirtMachineState *vms =3D VIRT_MACHINE(obj); =20 - if (!strcmp(value, "3")) { + if (!strcmp(value, "4")) { + vms->gic_version =3D VIRT_GIC_VERSION_4; + } else if (!strcmp(value, "3")) { vms->gic_version =3D VIRT_GIC_VERSION_3; } else if (!strcmp(value, "2")) { vms->gic_version =3D VIRT_GIC_VERSION_2; @@ -2898,7 +2934,7 @@ static void virt_machine_class_init(ObjectClass *oc, = void *data) virt_set_gic_version); object_class_property_set_description(oc, "gic-version", "Set GIC version. " - "Valid values are 2, 3, host and= max"); + "Valid values are 2, 3, 4, host = and max"); =20 object_class_property_add_str(oc, "iommu", virt_get_iommu, virt_set_io= mmu); object_class_property_set_description(oc, "iommu", --=20 2.25.1