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b=EgNkKFhfcX7qS30TeygmIdkHlGRTB/ahBUIwYOely9n6b3xwoCv91MEfyqW9ouzziQ55 JJTcftJ9G86a9+9nn0ESWMDC1fhLTklrP127AtaiL5rXVnnDycR3jz/nrI3Eo0branqG 0gfAOkQu24HHerZKXBdj9u6VrKGGOWRlJ3F+7yGsIQGWuFBscMtU5iHRt2VBeiDbMxp+ sWdshEKpiJJjk1FV83Fua/UoKkHAAcoIYIaPZfgDPBSXYYy5hSGBHXuxbbLpP9PdOC95 SGkKDyI5BdfJd+1p6pwtPBQmmrBNsm7MUfRdkQuHaSd0F5y8Ia+4EHHTNt1gMzTHn0uk Xw== From: Frederic Barrat To: clg@kaod.org, danielhb413@gmail.com, mst@redhat.com, marcel.apfelbaum@gmail.com, qemu-ppc@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH v2 1/2] pcie: Don't try triggering a LSI when not defined Date: Fri, 8 Apr 2022 15:13:02 +0200 Message-Id: <20220408131303.147840-2-fbarrat@linux.ibm.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220408131303.147840-1-fbarrat@linux.ibm.com> References: <20220408131303.147840-1-fbarrat@linux.ibm.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-TM-AS-GCONF: 00 X-Proofpoint-ORIG-GUID: xBUf1XDwVvAVDgIiFmo3D5a0I9xXHU8d X-Proofpoint-GUID: gREDzRddZxQmSDRknk0fviy9-jjprRPx X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.425,FMLib:17.11.64.514 definitions=2022-04-08_04,2022-04-08_01,2022-02-23_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 mlxlogscore=615 bulkscore=0 spamscore=0 malwarescore=0 impostorscore=0 clxscore=1015 lowpriorityscore=0 mlxscore=0 priorityscore=1501 phishscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.12.0-2202240000 definitions=main-2204080067 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=148.163.156.1; envelope-from=fbarrat@linux.ibm.com; helo=mx0a-001b2d01.pphosted.com X-Spam_score_int: -19 X-Spam_score: -2.0 X-Spam_bar: -- X-Spam_report: (-2.0 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ibm.com) X-ZM-MESSAGEID: 1649423717487100001 Content-Type: text/plain; charset="utf-8" This patch skips [de]asserting a LSI interrupt if the device doesn't have any LSI defined. Doing so would trigger an assert in pci_irq_handler(). The PCIE root port implementation in qemu requests a LSI (INTA), but a subclass may want to change that behavior since it's a valid configuration. For example on the POWER8/POWER9/POWER10 systems, the root bridge doesn't request any LSI. Signed-off-by: Frederic Barrat Reviewed-by: Daniel Henrique Barboza Reviewed-by: Michael S. Tsirkin --- hw/pci/pcie.c | 5 +++-- hw/pci/pcie_aer.c | 2 +- 2 files changed, 4 insertions(+), 3 deletions(-) diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index 67a5d67372..68a62da0b5 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -353,7 +353,7 @@ static void hotplug_event_notify(PCIDevice *dev) msix_notify(dev, pcie_cap_flags_get_vector(dev)); } else if (msi_enabled(dev)) { msi_notify(dev, pcie_cap_flags_get_vector(dev)); - } else { + } else if (pci_intx(dev) !=3D -1) { pci_set_irq(dev, dev->exp.hpev_notified); } } @@ -361,7 +361,8 @@ static void hotplug_event_notify(PCIDevice *dev) static void hotplug_event_clear(PCIDevice *dev) { hotplug_event_update_event_status(dev); - if (!msix_enabled(dev) && !msi_enabled(dev) && !dev->exp.hpev_notified= ) { + if (!msix_enabled(dev) && !msi_enabled(dev) && pci_intx(dev) !=3D -1 && + !dev->exp.hpev_notified) { pci_irq_deassert(dev); } } diff --git a/hw/pci/pcie_aer.c b/hw/pci/pcie_aer.c index e1a8a88c8c..92bd0530dd 100644 --- a/hw/pci/pcie_aer.c +++ b/hw/pci/pcie_aer.c @@ -290,7 +290,7 @@ static void pcie_aer_root_notify(PCIDevice *dev) msix_notify(dev, pcie_aer_root_get_vector(dev)); } else if (msi_enabled(dev)) { msi_notify(dev, pcie_aer_root_get_vector(dev)); - } else { + } else if (pci_intx(dev) !=3D -1) { pci_irq_assert(dev); } } --=20 2.35.1