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Tue, 05 Apr 2022 15:38:04 -0700 (PDT) Date: Tue, 5 Apr 2022 15:36:34 -0700 In-Reply-To: <20220405223640.2595730-1-wuhaotsh@google.com> Message-Id: <20220405223640.2595730-6-wuhaotsh@google.com> Mime-Version: 1.0 References: <20220405223640.2595730-1-wuhaotsh@google.com> X-Mailer: git-send-email 2.35.1.1094.g7c7d902a7c-goog Subject: [PATCH for-7.1 05/11] hw/misc: Store DRAM size in NPCM8XX GCR Module From: Hao Wu To: peter.maydell@linaro.org Cc: qemu-arm@nongnu.org, qemu-devel@nongnu.org, wuhaotsh@google.com, venture@google.com, Avi.Fishman@nuvoton.com, kfting@nuvoton.com, hskinnemoen@google.com, Uri.Trichter@nuvoton.com, Vishal.Soni@microsoft.com, titusr@google.com Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1049; envelope-from=3zMRMYggKCqEXVIBPUTIHPPHMF.DPNRFNV-EFWFMOPOHOV.PSH@flex--wuhaotsh.bounces.google.com; helo=mail-pj1-x1049.google.com X-Spam_score_int: -95 X-Spam_score: -9.6 X-Spam_bar: --------- X-Spam_report: (-9.6 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_MED=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, USER_IN_DEF_DKIM_WL=-7.5 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @google.com) X-ZM-MESSAGEID: 1649198905307100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" NPCM8XX boot block stores the DRAM size in SCRPAD_B register in GCR module. Since we don't simulate a detailed memory controller, we need to store this information directly similar to the NPCM7XX's INCTR3 register. Signed-off-by: Hao Wu Reviwed-by: Titus Rwantare Reviewed-by: Peter Maydell --- hw/misc/npcm_gcr.c | 33 ++++++++++++++++++++++++++++++--- include/hw/misc/npcm_gcr.h | 1 + 2 files changed, 31 insertions(+), 3 deletions(-) diff --git a/hw/misc/npcm_gcr.c b/hw/misc/npcm_gcr.c index 2349949599..14c298602a 100644 --- a/hw/misc/npcm_gcr.c +++ b/hw/misc/npcm_gcr.c @@ -267,7 +267,7 @@ static const struct MemoryRegionOps npcm_gcr_ops =3D { }, }; =20 -static void npcm_gcr_enter_reset(Object *obj, ResetType type) +static void npcm7xx_gcr_enter_reset(Object *obj, ResetType type) { NPCMGCRState *s =3D NPCM_GCR(obj); NPCMGCRClass *c =3D NPCM_GCR_GET_CLASS(obj); @@ -283,6 +283,23 @@ static void npcm_gcr_enter_reset(Object *obj, ResetTyp= e type) } } =20 +static void npcm8xx_gcr_enter_reset(Object *obj, ResetType type) +{ + NPCMGCRState *s =3D NPCM_GCR(obj); + NPCMGCRClass *c =3D NPCM_GCR_GET_CLASS(obj); + + switch (type) { + case RESET_TYPE_COLD: + memcpy(s->regs, c->cold_reset_values, c->nr_regs * sizeof(uint32_t= )); + /* These 3 registers are at the same location in both 7xx and 8xx.= */ + s->regs[NPCM8XX_GCR_PWRON] =3D s->reset_pwron; + s->regs[NPCM8XX_GCR_MDLR] =3D s->reset_mdlr; + s->regs[NPCM8XX_GCR_INTCR3] =3D s->reset_intcr3; + s->regs[NPCM8XX_GCR_SCRPAD_B] =3D s->reset_scrpad_b; + break; + } +} + static void npcm_gcr_realize(DeviceState *dev, Error **errp) { ERRP_GUARD(); @@ -326,6 +343,14 @@ static void npcm_gcr_realize(DeviceState *dev, Error *= *errp) * https://github.com/Nuvoton-Israel/u-boot/blob/2aef993bd2aafeb5408db= aad0f3ce099ee40c4aa/board/nuvoton/poleg/poleg.c#L244 */ s->reset_intcr3 |=3D ctz64(dram_size / NPCM7XX_GCR_MIN_DRAM_SIZE) << 8; + + /* + * The boot block starting from 0.0.6 for NPCM8xx SoCs stores the DRAM= size + * in the SCRPAD2 registers. We need to set this field correctly since + * the initialization is skipped as we mentioned above. + * https://github.com/Nuvoton-Israel/u-boot/blob/npcm8mnx-v2019.01_tmp= /board/nuvoton/arbel/arbel.c#L737 + */ + s->reset_scrpad_b =3D dram_size; } =20 static void npcm_gcr_init(Object *obj) @@ -355,12 +380,10 @@ static Property npcm_gcr_properties[] =3D { =20 static void npcm_gcr_class_init(ObjectClass *klass, void *data) { - ResettableClass *rc =3D RESETTABLE_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); =20 dc->realize =3D npcm_gcr_realize; dc->vmsd =3D &vmstate_npcm_gcr; - rc->phases.enter =3D npcm_gcr_enter_reset; =20 device_class_set_props(dc, npcm_gcr_properties); } @@ -369,24 +392,28 @@ static void npcm7xx_gcr_class_init(ObjectClass *klass= , void *data) { NPCMGCRClass *c =3D NPCM_GCR_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 QEMU_BUILD_BUG_ON(NPCM7XX_GCR_REGS_END > NPCM_GCR_MAX_NR_REGS); QEMU_BUILD_BUG_ON(NPCM7XX_GCR_REGS_END !=3D NPCM7XX_GCR_NR_REGS); dc->desc =3D "NPCM7xx System Global Control Registers"; c->nr_regs =3D NPCM7XX_GCR_NR_REGS; c->cold_reset_values =3D npcm7xx_cold_reset_values; + rc->phases.enter =3D npcm7xx_gcr_enter_reset; } =20 static void npcm8xx_gcr_class_init(ObjectClass *klass, void *data) { NPCMGCRClass *c =3D NPCM_GCR_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); =20 QEMU_BUILD_BUG_ON(NPCM8XX_GCR_REGS_END > NPCM_GCR_MAX_NR_REGS); QEMU_BUILD_BUG_ON(NPCM8XX_GCR_REGS_END !=3D NPCM8XX_GCR_NR_REGS); dc->desc =3D "NPCM8xx System Global Control Registers"; c->nr_regs =3D NPCM8XX_GCR_NR_REGS; c->cold_reset_values =3D npcm8xx_cold_reset_values; + rc->phases.enter =3D npcm8xx_gcr_enter_reset; } =20 static const TypeInfo npcm_gcr_info[] =3D { diff --git a/include/hw/misc/npcm_gcr.h b/include/hw/misc/npcm_gcr.h index ac3d781c2e..bd69199d51 100644 --- a/include/hw/misc/npcm_gcr.h +++ b/include/hw/misc/npcm_gcr.h @@ -39,6 +39,7 @@ typedef struct NPCMGCRState { uint32_t reset_pwron; uint32_t reset_mdlr; uint32_t reset_intcr3; + uint32_t reset_scrpad_b; } NPCMGCRState; =20 typedef struct NPCMGCRClass { --=20 2.35.1.1094.g7c7d902a7c-goog