From nobody Wed Sep 3 02:19:27 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1649086889; cv=none; d=zohomail.com; s=zohoarc; b=BFK141+vfnjCpCNs19Ql1vXLs3b81g8obUs+HecEOl1nusHYWkUcvX40NA+qr/srWyPJrKEmG6/L0ngsLpgqPdc2L3IfpKYz5YGtfahQ2fiDMHVXKsZY6ruhCAAgotaHt4vO+r+k9xaOK6rXVzgIAruBGpHuaZC1T/xRq21LTQk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649086889; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=wqa46+Zw7Wfm9gX6oWA85gVuPzR0AkHrLhQA+YdvPhM=; b=CO9jE4119n8tkDKIeABqgYeWWs2d2fCuWMQBeRspf2ZPhxr03YGobUYhfq1r/+dF3xjDcRu5UQ+7FEDDIY1YwG8ylTnQKuEYKmrKlrJW7GR2qljLCeRf3FyWkBWkD7q+pMYIC4S/XOk+zpEl/SUVPx/Km+plQMRQyTBvFesBLNI= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164908688963741.63981043095032; Mon, 4 Apr 2022 08:41:29 -0700 (PDT) Received: from localhost ([::1]:51100 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nbOpc-0001VH-Ae for importer@patchew.org; Mon, 04 Apr 2022 11:41:28 -0400 Received: from eggs.gnu.org ([209.51.188.92]:40838) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nbOfg-0005AQ-FX for qemu-devel@nongnu.org; Mon, 04 Apr 2022 11:31:13 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]:2499) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nbOfe-0006Wd-Eo for qemu-devel@nongnu.org; Mon, 04 Apr 2022 11:31:12 -0400 Received: from fraeml712-chm.china.huawei.com (unknown [172.18.147.206]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4KXF721kTlz685FB; Mon, 4 Apr 2022 23:29:02 +0800 (CST) Received: from lhreml710-chm.china.huawei.com (10.201.108.61) by fraeml712-chm.china.huawei.com (10.206.15.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Mon, 4 Apr 2022 17:31:02 +0200 Received: from SecurePC-101-06.china.huawei.com (10.122.247.231) by lhreml710-chm.china.huawei.com (10.201.108.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Mon, 4 Apr 2022 16:31:01 +0100 To: , , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Marcel Apfelbaum , "Michael S . Tsirkin" , Igor Mammedov , Markus Armbruster , "Mark Cave-Ayland" , Adam Manzanares CC: , Ben Widawsky , "Peter Maydell" , Shameerali Kolothum Thodi , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Xu , David Hildenbrand , Paolo Bonzini , Saransh Gupta1 , Shreyas Shah , Chris Browy , "Samarth Saxena" , Dan Williams , "k . jensen @ samsung . com" , Tong Zhang , , Alison Schofield Subject: [PATCH v9 32/45] mem/cxl_type3: Add read and write functions for associated hostmem. Date: Mon, 4 Apr 2022 16:14:32 +0100 Message-ID: <20220404151445.10955-33-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220404151445.10955-1-Jonathan.Cameron@huawei.com> References: <20220404151445.10955-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.247.231] X-ClientProxiedBy: lhreml717-chm.china.huawei.com (10.201.108.68) To lhreml710-chm.china.huawei.com (10.201.108.61) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Jonathan Cameron From: Jonathan Cameron via X-ZM-MESSAGEID: 1649086891560100001 Content-Type: text/plain; charset="utf-8" From: Jonathan Cameron Once a read or write reaches a CXL type 3 device, the HDM decoders on the device are used to establish the Device Physical Address which should be accessed. These functions peform the required maths and then use a device specific address space to access the hostmem->mr to fullfil the actual operation. Note that failed writes are silent, but failed reads return poison. Note this is based loosely on: https://lore.kernel.org/qemu-devel/20200817161853.593247-6-f4bug@amsat.org/ [RFC PATCH 0/9] hw/misc: Add support for interleaved memory accesses Only lightly tested so far. More complex test cases yet to be written. Signed-off-by: Jonathan Cameron --- hw/mem/cxl_type3.c | 91 +++++++++++++++++++++++++++++++++++++ include/hw/cxl/cxl_device.h | 6 +++ 2 files changed, 97 insertions(+) diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 9578e72576..53fd57579b 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -95,7 +95,9 @@ static void ct3d_reg_write(void *opaque, hwaddr offset, u= int64_t value, =20 static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp) { + DeviceState *ds =3D DEVICE(ct3d); MemoryRegion *mr; + char *name; =20 if (!ct3d->hostmem) { error_setg(errp, "memdev property must be set"); @@ -110,6 +112,15 @@ static bool cxl_setup_memory(CXLType3Dev *ct3d, Error = **errp) memory_region_set_nonvolatile(mr, true); memory_region_set_enabled(mr, true); host_memory_backend_set_mapped(ct3d->hostmem, true); + + if (ds->id) { + name =3D g_strdup_printf("cxl-type3-dpa-space:%s", ds->id); + } else { + name =3D g_strdup("cxl-type3-dpa-space"); + } + address_space_init(&ct3d->hostmem_as, mr, name); + g_free(name); + ct3d->cxl_dstate.pmem_size =3D ct3d->hostmem->size; =20 if (!ct3d->lsa) { @@ -165,6 +176,86 @@ static void ct3_exit(PCIDevice *pci_dev) ComponentRegisters *regs =3D &cxl_cstate->crb; =20 g_free(regs->special_ops); + address_space_destroy(&ct3d->hostmem_as); +} + +/* TODO: Support multiple HDM decoders and DPA skip */ +static bool cxl_type3_dpa(CXLType3Dev *ct3d, hwaddr host_addr, uint64_t *d= pa) +{ + uint32_t *cache_mem =3D ct3d->cxl_cstate.crb.cache_mem_registers; + uint64_t decoder_base, decoder_size, hpa_offset; + uint32_t hdm0_ctrl; + int ig, iw; + + decoder_base =3D (((uint64_t)cache_mem[R_CXL_HDM_DECODER0_BASE_HI] << = 32) | + cache_mem[R_CXL_HDM_DECODER0_BASE_LO]); + if ((uint64_t)host_addr < decoder_base) { + return false; + } + + hpa_offset =3D (uint64_t)host_addr - decoder_base; + + decoder_size =3D ((uint64_t)cache_mem[R_CXL_HDM_DECODER0_SIZE_HI] << 3= 2) | + cache_mem[R_CXL_HDM_DECODER0_SIZE_LO]; + if (hpa_offset >=3D decoder_size) { + return false; + } + + hdm0_ctrl =3D cache_mem[R_CXL_HDM_DECODER0_CTRL]; + iw =3D FIELD_EX32(hdm0_ctrl, CXL_HDM_DECODER0_CTRL, IW); + ig =3D FIELD_EX32(hdm0_ctrl, CXL_HDM_DECODER0_CTRL, IG); + + *dpa =3D (MAKE_64BIT_MASK(0, 8 + ig) & hpa_offset) | + ((MAKE_64BIT_MASK(8 + ig + iw, 64 - 8 - ig - iw) & hpa_offset) >> = iw); + + return true; +} + +MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data, + unsigned size, MemTxAttrs attrs) +{ + CXLType3Dev *ct3d =3D CXL_TYPE3(d); + uint64_t dpa_offset; + MemoryRegion *mr; + + /* TODO support volatile region */ + mr =3D host_memory_backend_get_memory(ct3d->hostmem); + if (!mr) { + return MEMTX_ERROR; + } + + if (!cxl_type3_dpa(ct3d, host_addr, &dpa_offset)) { + return MEMTX_ERROR; + } + + if (dpa_offset > int128_get64(mr->size)) { + return MEMTX_ERROR; + } + + return address_space_read(&ct3d->hostmem_as, dpa_offset, attrs, data, = size); +} + +MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host_addr, uint64_t data, + unsigned size, MemTxAttrs attrs) +{ + CXLType3Dev *ct3d =3D CXL_TYPE3(d); + uint64_t dpa_offset; + MemoryRegion *mr; + + mr =3D host_memory_backend_get_memory(ct3d->hostmem); + if (!mr) { + return MEMTX_OK; + } + + if (!cxl_type3_dpa(ct3d, host_addr, &dpa_offset)) { + return MEMTX_OK; + } + + if (dpa_offset > int128_get64(mr->size)) { + return MEMTX_OK; + } + return address_space_write(&ct3d->hostmem_as, dpa_offset, attrs, + &data, size); } =20 static void ct3d_reset(DeviceState *dev) diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h index 4285fbda08..1e141b6621 100644 --- a/include/hw/cxl/cxl_device.h +++ b/include/hw/cxl/cxl_device.h @@ -239,6 +239,7 @@ struct CXLType3Dev { HostMemoryBackend *lsa; =20 /* State */ + AddressSpace hostmem_as; CXLComponentState cxl_cstate; CXLDeviceState cxl_dstate; }; @@ -259,4 +260,9 @@ struct CXLType3Class { uint64_t offset); }; =20 +MemTxResult cxl_type3_read(PCIDevice *d, hwaddr host_addr, uint64_t *data, + unsigned size, MemTxAttrs attrs); +MemTxResult cxl_type3_write(PCIDevice *d, hwaddr host_addr, uint64_t data, + unsigned size, MemTxAttrs attrs); + #endif --=20 2.32.0