From nobody Wed Sep 3 02:17:47 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1649086380; cv=none; d=zohomail.com; s=zohoarc; b=GmyRXkrtW0czwyyk89yy9U/7binJ29IrUm3nEBGsIQZdy+q2VxMrTlHm/VNS7HbhcBgedOQf6JCIg3DynFHjgU2LnBc2eDirEB7AG2PsrrUP4XYt/lWQvSO6642SCNKu4tARpKU7d+GetkVhJlickf287jQbQ3vrTFK4jfBB9hI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649086380; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=Md/O4Or6zo/1flW9mppPXq2pAtPOiq1odnk7pfuE1y8=; b=Le8RzBTXncukZ0riF9BYkHnwOKVrKPedEJegMwA7COP24eoSxDzVihyYBUjKdGqn1u906ainZ/IoFiKqr9TiCd++jK03ja001ZmN/OmPbUhLEPSZgKA+4xs8wMP9SgNqOqxlBxoKe26cpD3z/gibyGsJW1FgGjYQ4ZP0eI81gRI= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1649086380083904.1543378776314; Mon, 4 Apr 2022 08:33:00 -0700 (PDT) Received: from localhost ([::1]:50724 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nbOhO-0007Xr-PG for importer@patchew.org; Mon, 04 Apr 2022 11:32:58 -0400 Received: from eggs.gnu.org ([209.51.188.92]:39704) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nbOab-0003SQ-5d for qemu-devel@nongnu.org; Mon, 04 Apr 2022 11:25:57 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]:2489) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nbOaZ-0005oH-4N for qemu-devel@nongnu.org; Mon, 04 Apr 2022 11:25:56 -0400 Received: from fraeml745-chm.china.huawei.com (unknown [172.18.147.200]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4KXF054vZyz683DB; Mon, 4 Apr 2022 23:23:01 +0800 (CST) Received: from lhreml710-chm.china.huawei.com (10.201.108.61) by fraeml745-chm.china.huawei.com (10.206.15.226) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Mon, 4 Apr 2022 17:25:53 +0200 Received: from SecurePC-101-06.china.huawei.com (10.122.247.231) by lhreml710-chm.china.huawei.com (10.201.108.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Mon, 4 Apr 2022 16:25:52 +0100 To: , , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Marcel Apfelbaum , "Michael S . Tsirkin" , Igor Mammedov , Markus Armbruster , "Mark Cave-Ayland" , Adam Manzanares CC: , Ben Widawsky , "Peter Maydell" , Shameerali Kolothum Thodi , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Xu , David Hildenbrand , Paolo Bonzini , Saransh Gupta1 , Shreyas Shah , Chris Browy , "Samarth Saxena" , Dan Williams , "k . jensen @ samsung . com" , Tong Zhang , , Alison Schofield Subject: [PATCH v9 22/45] qtests/cxl: Add initial root port and CXL type3 tests Date: Mon, 4 Apr 2022 16:14:22 +0100 Message-ID: <20220404151445.10955-23-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220404151445.10955-1-Jonathan.Cameron@huawei.com> References: <20220404151445.10955-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.247.231] X-ClientProxiedBy: lhreml717-chm.china.huawei.com (10.201.108.68) To lhreml710-chm.china.huawei.com (10.201.108.61) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Jonathan Cameron From: Jonathan Cameron via X-ZM-MESSAGEID: 1649086381209100001 At this stage we can boot configurations with host bridges, root ports and type 3 memory devices, so add appropriate tests. Signed-off-by: Jonathan Cameron Reviewed-by: Alex Benn=C3=A9e --- tests/qtest/cxl-test.c | 126 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 126 insertions(+) diff --git a/tests/qtest/cxl-test.c b/tests/qtest/cxl-test.c index 1006c8ae4e..5f0794e816 100644 --- a/tests/qtest/cxl-test.c +++ b/tests/qtest/cxl-test.c @@ -8,6 +8,54 @@ #include "qemu/osdep.h" #include "libqtest-single.h" =20 +#define QEMU_PXB_CMD "-machine q35,cxl=3Don " \ + "-device pxb-cxl,id=3Dcxl.0,bus=3Dpcie.0,bus_nr=3D52 " + +#define QEMU_2PXB_CMD "-machine q35,cxl=3Don " \ + "-device pxb-cxl,id=3Dcxl.0,bus=3Dpcie.0,bus_nr=3D52= " \ + "-device pxb-cxl,id=3Dcxl.1,bus=3Dpcie.0,bus_nr=3D53= " + +#define QEMU_RP "-device cxl-rp,id=3Drp0,bus=3Dcxl.0,chassis=3D0,slot=3D0 " + +/* Dual ports on first pxb */ +#define QEMU_2RP "-device cxl-rp,id=3Drp0,bus=3Dcxl.0,chassis=3D0,slot=3D0= " \ + "-device cxl-rp,id=3Drp1,bus=3Dcxl.0,chassis=3D0,slot=3D1= " + +/* Dual ports on each of the pxb instances */ +#define QEMU_4RP "-device cxl-rp,id=3Drp0,bus=3Dcxl.0,chassis=3D0,slot=3D0= " \ + "-device cxl-rp,id=3Drp1,bus=3Dcxl.0,chassis=3D0,slot=3D1= " \ + "-device cxl-rp,id=3Drp2,bus=3Dcxl.1,chassis=3D0,slot=3D2= " \ + "-device cxl-rp,id=3Drp3,bus=3Dcxl.1,chassis=3D0,slot=3D3= " + +#define QEMU_T3D "-object memory-backend-file,id=3Dcxl-mem0,mem-path=3D%s,= size=3D256M " \ + "-object memory-backend-file,id=3Dlsa0,mem-path=3D%s,size= =3D256M " \ + "-device cxl-type3,bus=3Drp0,memdev=3Dcxl-mem0,lsa=3Dlsa0= ,id=3Dcxl-pmem0 " + +#define QEMU_2T3D "-object memory-backend-file,id=3Dcxl-mem0,mem-path=3D%s= ,size=3D256M " \ + "-object memory-backend-file,id=3Dlsa0,mem-path=3D%s,siz= e=3D256M " \ + "-device cxl-type3,bus=3Drp0,memdev=3Dcxl-mem0,lsa=3Dlsa= 0,id=3Dcxl-pmem0 " \ + "-object memory-backend-file,id=3Dcxl-mem1,mem-path=3D%s= ,size=3D256M " \ + "-object memory-backend-file,id=3Dlsa1,mem-path=3D%s,siz= e=3D256M " \ + "-device cxl-type3,bus=3Drp1,memdev=3Dcxl-mem1,lsa=3Dlsa= 1,id=3Dcxl-pmem1 " + +#define QEMU_4T3D "-object memory-backend-file,id=3Dcxl-mem0,mem-path=3D%s= ,size=3D256M " \ + "-object memory-backend-file,id=3Dlsa0,mem-path=3D%s,siz= e=3D256M " \ + "-device cxl-type3,bus=3Drp0,memdev=3Dcxl-mem0,lsa=3Dlsa= 0,id=3Dcxl-pmem0 " \ + "-object memory-backend-file,id=3Dcxl-mem1,mem-path=3D%s= ,size=3D256M " \ + "-object memory-backend-file,id=3Dlsa1,mem-path=3D%s,siz= e=3D256M " \ + "-device cxl-type3,bus=3Drp1,memdev=3Dcxl-mem1,lsa=3Dlsa= 1,id=3Dcxl-pmem1 " \ + "-object memory-backend-file,id=3Dcxl-mem2,mem-path=3D%s= ,size=3D256M " \ + "-object memory-backend-file,id=3Dlsa2,mem-path=3D%s,siz= e=3D256M " \ + "-device cxl-type3,bus=3Drp2,memdev=3Dcxl-mem2,lsa=3Dlsa= 2,id=3Dcxl-pmem2 " \ + "-object memory-backend-file,id=3Dcxl-mem3,mem-path=3D%s= ,size=3D256M " \ + "-object memory-backend-file,id=3Dlsa3,mem-path=3D%s,siz= e=3D256M " \ + "-device cxl-type3,bus=3Drp3,memdev=3Dcxl-mem3,lsa=3Dlsa= 3,id=3Dcxl-pmem3 " + +static void cxl_basic_hb(void) +{ + qtest_start("-machine q35,cxl=3Don"); + qtest_end(); +} =20 static void cxl_basic_pxb(void) { @@ -15,9 +63,87 @@ static void cxl_basic_pxb(void) qtest_end(); } =20 +static void cxl_pxb_with_window(void) +{ + qtest_start(QEMU_PXB_CMD); + qtest_end(); +} + +static void cxl_2pxb_with_window(void) +{ + qtest_start(QEMU_2PXB_CMD); + qtest_end(); +} + +static void cxl_root_port(void) +{ + qtest_start(QEMU_PXB_CMD QEMU_RP); + qtest_end(); +} + +static void cxl_2root_port(void) +{ + qtest_start(QEMU_PXB_CMD QEMU_2RP); + qtest_end(); +} + +static void cxl_t3d(void) +{ + g_autoptr(GString) cmdline =3D g_string_new(NULL); + char template[] =3D "/tmp/cxl-test-XXXXXX"; + const char *tmpfs; + + tmpfs =3D mkdtemp(template); + + g_string_printf(cmdline, QEMU_PXB_CMD QEMU_RP QEMU_T3D, tmpfs, tmpfs); + + qtest_start(cmdline->str); + qtest_end(); +} + +static void cxl_1pxb_2rp_2t3d(void) +{ + g_autoptr(GString) cmdline =3D g_string_new(NULL); + char template[] =3D "/tmp/cxl-test-XXXXXX"; + const char *tmpfs; + + tmpfs =3D mkdtemp(template); + + g_string_printf(cmdline, QEMU_PXB_CMD QEMU_2RP QEMU_2T3D, + tmpfs, tmpfs, tmpfs, tmpfs); + + qtest_start(cmdline->str); + qtest_end(); +} + +static void cxl_2pxb_4rp_4t3d(void) +{ + g_autoptr(GString) cmdline =3D g_string_new(NULL); + char template[] =3D "/tmp/cxl-test-XXXXXX"; + const char *tmpfs; + + tmpfs =3D mkdtemp(template); + + g_string_printf(cmdline, QEMU_2PXB_CMD QEMU_4RP QEMU_4T3D, + tmpfs, tmpfs, tmpfs, tmpfs, tmpfs, tmpfs, + tmpfs, tmpfs); + + qtest_start(cmdline->str); + qtest_end(); +} + int main(int argc, char **argv) { g_test_init(&argc, &argv, NULL); + + qtest_add_func("/pci/cxl/basic_hostbridge", cxl_basic_hb); qtest_add_func("/pci/cxl/basic_pxb", cxl_basic_pxb); + qtest_add_func("/pci/cxl/pxb_with_window", cxl_pxb_with_window); + qtest_add_func("/pci/cxl/pxb_x2_with_window", cxl_2pxb_with_window); + qtest_add_func("/pci/cxl/rp", cxl_root_port); + qtest_add_func("/pci/cxl/rp_x2", cxl_2root_port); + qtest_add_func("/pci/cxl/type3_device", cxl_t3d); + qtest_add_func("/pci/cxl/rp_x2_type3_x2", cxl_1pxb_2rp_2t3d); + qtest_add_func("/pci/cxl/pxb_x2_root_port_x4_type3_x4", cxl_2pxb_4rp_4= t3d); return g_test_run(); } --=20 2.32.0