From nobody Wed Sep 3 02:28:39 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1649086029; cv=none; d=zohomail.com; s=zohoarc; b=nB3H4wr8XHBTvzH/RORSrx61HXZZn27dkrmkfgYC1Vk7Weecb3m7O7AWxZpz1DtS4jXv/OOuROTU4Sj+NOBi8oM7IGRgNgpqhvuewzqDOf/x1qd6QGa9pNuRx1v+MW5yiT98nMHe/nypR2LJFoajJPDzRhcbsxGK+VYELViu+bo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649086029; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=qY/aXlghEvu4TXVnbkrC0XwD9l0ZhgW4cL56Tsps37E=; b=FkAoOjEUraXEKQlK6grNZWfL1atCoytN8TLfFllTeEOAbZjbdC+We1VU8i+uqhxLvNKfe2M3S6T7fNYc/59XV9eNcuVikwaJ6Su/d5ov2uwzNje27KV3G+/9E+IaBlJOjLgbtscfGUpyzF6GLdjaEZWvsfAF/wudKQW0wyhxaBg= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1649086029531649.5409011369054; Mon, 4 Apr 2022 08:27:09 -0700 (PDT) Received: from localhost ([::1]:33164 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nbObk-00043h-Ha for importer@patchew.org; Mon, 04 Apr 2022 11:27:08 -0400 Received: from eggs.gnu.org ([209.51.188.92]:39250) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nbOYb-0007I8-M7 for qemu-devel@nongnu.org; Mon, 04 Apr 2022 11:23:54 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]:2485) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nbOYZ-0005PC-Qa for qemu-devel@nongnu.org; Mon, 04 Apr 2022 11:23:53 -0400 Received: from fraeml706-chm.china.huawei.com (unknown [172.18.147.207]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4KXDxk2GVqz67J5f; Mon, 4 Apr 2022 23:20:58 +0800 (CST) Received: from lhreml710-chm.china.huawei.com (10.201.108.61) by fraeml706-chm.china.huawei.com (10.206.15.55) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2375.24; Mon, 4 Apr 2022 17:23:49 +0200 Received: from SecurePC-101-06.china.huawei.com (10.122.247.231) by lhreml710-chm.china.huawei.com (10.201.108.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Mon, 4 Apr 2022 16:23:49 +0100 To: , , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Marcel Apfelbaum , "Michael S . Tsirkin" , Igor Mammedov , Markus Armbruster , "Mark Cave-Ayland" , Adam Manzanares CC: , Ben Widawsky , "Peter Maydell" , Shameerali Kolothum Thodi , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Xu , David Hildenbrand , Paolo Bonzini , Saransh Gupta1 , Shreyas Shah , Chris Browy , "Samarth Saxena" , Dan Williams , "k . jensen @ samsung . com" , Tong Zhang , , Alison Schofield Subject: [PATCH v9 18/45] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12) Date: Mon, 4 Apr 2022 16:14:18 +0100 Message-ID: <20220404151445.10955-19-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220404151445.10955-1-Jonathan.Cameron@huawei.com> References: <20220404151445.10955-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.247.231] X-ClientProxiedBy: lhreml717-chm.china.huawei.com (10.201.108.68) To lhreml710-chm.china.huawei.com (10.201.108.61) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Jonathan Cameron From: Jonathan Cameron via X-ZM-MESSAGEID: 1649086031656100001 From: Ben Widawsky A device's volatile and persistent memory are known Host Defined Memory (HDM) regions. The mechanism by which the device is programmed to claim the addresses associated with those regions is through dedicated logic known as the HDM decoder. In order to allow the OS to properly program the HDMs, the HDM decoders must be modeled. There are two ways the HDM decoders can be implemented, the legacy mechanism is through the PCIe DVSEC programming from CXL 1.1 (8.1.3.8), and MMIO is found in 8.2.5.12 of the spec. For now, 8.1.3.8 is not implemented. Much of CXL device logic is implemented in cxl-utils. The HDM decoder however is implemented directly by the device implementation. Whilst the implementation currently does no validity checks on the encoder set up, future work will add sanity checking specific to the type of cxl component. Signed-off-by: Ben Widawsky Co-developed-by: Jonathan Cameron Signed-off-by: Jonathan Cameron Reviewed-by: Alex Benn=C3=A9e --- hw/mem/cxl_type3.c | 55 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 55 insertions(+) diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index 329a6ea2a9..5c93fbbd9b 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -50,6 +50,48 @@ static void build_dvsecs(CXLType3Dev *ct3d) GPF_DEVICE_DVSEC_REVID, dvsec); } =20 +static void hdm_decoder_commit(CXLType3Dev *ct3d, int which) +{ + ComponentRegisters *cregs =3D &ct3d->cxl_cstate.crb; + uint32_t *cache_mem =3D cregs->cache_mem_registers; + + assert(which =3D=3D 0); + + /* TODO: Sanity checks that the decoder is possible */ + ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMIT, 0); + ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, ERR, 0); + + ARRAY_FIELD_DP32(cache_mem, CXL_HDM_DECODER0_CTRL, COMMITTED, 1); +} + +static void ct3d_reg_write(void *opaque, hwaddr offset, uint64_t value, + unsigned size) +{ + CXLComponentState *cxl_cstate =3D opaque; + ComponentRegisters *cregs =3D &cxl_cstate->crb; + CXLType3Dev *ct3d =3D container_of(cxl_cstate, CXLType3Dev, cxl_cstate= ); + uint32_t *cache_mem =3D cregs->cache_mem_registers; + bool should_commit =3D false; + int which_hdm =3D -1; + + assert(size =3D=3D 4); + g_assert(offset <=3D CXL2_COMPONENT_CM_REGION_SIZE); + + switch (offset) { + case A_CXL_HDM_DECODER0_CTRL: + should_commit =3D FIELD_EX32(value, CXL_HDM_DECODER0_CTRL, COMMIT); + which_hdm =3D 0; + break; + default: + break; + } + + stl_le_p((uint8_t *)cache_mem + offset, value); + if (should_commit) { + hdm_decoder_commit(ct3d, which_hdm); + } +} + static bool cxl_setup_memory(CXLType3Dev *ct3d, Error **errp) { MemoryRegion *mr; @@ -93,6 +135,9 @@ static void ct3_realize(PCIDevice *pci_dev, Error **errp) ct3d->cxl_cstate.pdev =3D pci_dev; build_dvsecs(ct3d); =20 + regs->special_ops =3D g_new0(MemoryRegionOps, 1); + regs->special_ops->write =3D ct3d_reg_write; + cxl_component_register_block_init(OBJECT(pci_dev), cxl_cstate, TYPE_CXL_TYPE3); =20 @@ -107,6 +152,15 @@ static void ct3_realize(PCIDevice *pci_dev, Error **er= rp) &ct3d->cxl_dstate.device_registers); } =20 +static void ct3_exit(PCIDevice *pci_dev) +{ + CXLType3Dev *ct3d =3D CXL_TYPE3(pci_dev); + CXLComponentState *cxl_cstate =3D &ct3d->cxl_cstate; + ComponentRegisters *regs =3D &cxl_cstate->crb; + + g_free(regs->special_ops); +} + static void ct3d_reset(DeviceState *dev) { CXLType3Dev *ct3d =3D CXL_TYPE3(dev); @@ -128,6 +182,7 @@ static void ct3_class_init(ObjectClass *oc, void *data) PCIDeviceClass *pc =3D PCI_DEVICE_CLASS(oc); =20 pc->realize =3D ct3_realize; + pc->exit =3D ct3_exit; pc->class_id =3D PCI_CLASS_STORAGE_EXPRESS; pc->vendor_id =3D PCI_VENDOR_ID_INTEL; pc->device_id =3D 0xd93; /* LVF for now */ --=20 2.32.0