From nobody Wed Sep 3 02:27:27 2025 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1649086391; cv=none; d=zohomail.com; s=zohoarc; b=g+mH1cPN4NORZLK0B0Ql96Aa9zjt08tpiS100Ba8WN3ajQ/lhc1okd0SSLDjPau36S5IH1FL2adhEr7ZVHkhsKnoHUV6iR9u3EFkJW1U0HhoVHDKI543VkyEFSst82gMJaQ03QQrcKjGPHtgV2O6XqUOUG2o/URJ79lSWjZmL0o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1649086391; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=ARN5DK01wyqK+kQb0IotmVU23CDu5ocTT1K7MRmv8V0=; b=Tp/k/4WGL8ADFXK/MvU193V8J+kZdPP8Z2KLly7x1M8FB+YmnbtZ7c8gldm42bEa54bY9JRnMaxYIb1iS6/YSdlcAW3H3kfadkjZJfzUhtMwn4lvqiMT3VQRGq6cCM5isqft0vySDJCFQ/UM+/SP66HD0BOrBplG4H78PO36jD4= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1649086391739750.2305799452802; Mon, 4 Apr 2022 08:33:11 -0700 (PDT) Received: from localhost ([::1]:51756 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nbOha-0008D4-Px for importer@patchew.org; Mon, 04 Apr 2022 11:33:10 -0400 Received: from eggs.gnu.org ([209.51.188.92]:38794) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nbOW7-0001zJ-Rj for qemu-devel@nongnu.org; Mon, 04 Apr 2022 11:21:19 -0400 Received: from frasgout.his.huawei.com ([185.176.79.56]:2480) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nbOW6-0005Da-1K for qemu-devel@nongnu.org; Mon, 04 Apr 2022 11:21:19 -0400 Received: from fraeml743-chm.china.huawei.com (unknown [172.18.147.200]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4KXDw644dzz67QFM; Mon, 4 Apr 2022 23:19:34 +0800 (CST) Received: from lhreml710-chm.china.huawei.com (10.201.108.61) by fraeml743-chm.china.huawei.com (10.206.15.224) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Mon, 4 Apr 2022 17:21:15 +0200 Received: from SecurePC-101-06.china.huawei.com (10.122.247.231) by lhreml710-chm.china.huawei.com (10.201.108.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2375.24; Mon, 4 Apr 2022 16:21:14 +0100 To: , , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Marcel Apfelbaum , "Michael S . Tsirkin" , Igor Mammedov , Markus Armbruster , "Mark Cave-Ayland" , Adam Manzanares CC: , Ben Widawsky , "Peter Maydell" , Shameerali Kolothum Thodi , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Peter Xu , David Hildenbrand , Paolo Bonzini , Saransh Gupta1 , Shreyas Shah , Chris Browy , "Samarth Saxena" , Dan Williams , "k . jensen @ samsung . com" , Tong Zhang , , Alison Schofield Subject: [PATCH v9 13/45] cxl: Machine level control on whether CXL support is enabled Date: Mon, 4 Apr 2022 16:14:13 +0100 Message-ID: <20220404151445.10955-14-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220404151445.10955-1-Jonathan.Cameron@huawei.com> References: <20220404151445.10955-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.247.231] X-ClientProxiedBy: lhreml717-chm.china.huawei.com (10.201.108.68) To lhreml710-chm.china.huawei.com (10.201.108.61) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Jonathan Cameron From: Jonathan Cameron via X-ZM-MESSAGEID: 1649086393264100001 From: Jonathan Cameron There are going to be some potential overheads to CXL enablement, for example the host bridge region reserved in memory maps. Add a machine level control so that CXL is disabled by default. Signed-off-by: Jonathan Cameron Reviewed-by: Alex Benn=C3=A9e --- hw/core/machine.c | 28 ++++++++++++++++++++++++++++ hw/i386/pc.c | 1 + include/hw/boards.h | 2 ++ include/hw/cxl/cxl.h | 4 ++++ 4 files changed, 35 insertions(+) diff --git a/hw/core/machine.c b/hw/core/machine.c index d856485cb4..6ff5dba64e 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -31,6 +31,7 @@ #include "sysemu/qtest.h" #include "hw/pci/pci.h" #include "hw/mem/nvdimm.h" +#include "hw/cxl/cxl.h" #include "migration/global_state.h" #include "migration/vmstate.h" #include "exec/confidential-guest-support.h" @@ -545,6 +546,20 @@ static void machine_set_nvdimm_persistence(Object *obj= , const char *value, nvdimms_state->persistence_string =3D g_strdup(value); } =20 +static bool machine_get_cxl(Object *obj, Error **errp) +{ + MachineState *ms =3D MACHINE(obj); + + return ms->cxl_devices_state->is_enabled; +} + +static void machine_set_cxl(Object *obj, bool value, Error **errp) +{ + MachineState *ms =3D MACHINE(obj); + + ms->cxl_devices_state->is_enabled =3D value; +} + void machine_class_allow_dynamic_sysbus_dev(MachineClass *mc, const char *= type) { QAPI_LIST_PREPEND(mc->allowed_dynamic_sysbus_devices, g_strdup(type)); @@ -777,6 +792,8 @@ static void machine_class_init(ObjectClass *oc, void *d= ata) mc->default_ram_size =3D 128 * MiB; mc->rom_file_has_mr =3D true; =20 + /* Few machines support CXL, so default to off */ + mc->cxl_supported =3D false; /* numa node memory size aligned on 8MB by default. * On Linux, each node's border has to be 8MB aligned */ @@ -922,6 +939,16 @@ static void machine_initfn(Object *obj) "Valid values are cpu, mem-ctrl"); } =20 + if (mc->cxl_supported) { + Object *obj =3D OBJECT(ms); + + ms->cxl_devices_state =3D g_new0(CXLState, 1); + object_property_add_bool(obj, "cxl", machine_get_cxl, machine_set_= cxl); + object_property_set_description(obj, "cxl", + "Set on/off to enable/disable " + "CXL instantiation"); + } + if (mc->cpu_index_to_instance_props && mc->get_default_cpu_node_id) { ms->numa_state =3D g_new0(NumaState, 1); object_property_add_bool(obj, "hmat", @@ -956,6 +983,7 @@ static void machine_finalize(Object *obj) g_free(ms->device_memory); g_free(ms->nvdimms_state); g_free(ms->numa_state); + g_free(ms->cxl_devices_state); } =20 bool machine_usb(MachineState *machine) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index fd55fc725c..e2849fc741 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1758,6 +1758,7 @@ static void pc_machine_class_init(ObjectClass *oc, vo= id *data) mc->default_cpu_type =3D TARGET_DEFAULT_CPU_TYPE; mc->nvdimm_supported =3D true; mc->smp_props.dies_supported =3D true; + mc->cxl_supported =3D true; mc->default_ram_id =3D "pc.ram"; =20 object_class_property_add(oc, PC_MACHINE_MAX_RAM_BELOW_4G, "size", diff --git a/include/hw/boards.h b/include/hw/boards.h index c92ac8815c..680718dafc 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -269,6 +269,7 @@ struct MachineClass { bool ignore_boot_device_suffixes; bool smbus_no_migration_support; bool nvdimm_supported; + bool cxl_supported; bool numa_mem_supported; bool auto_enable_numa; SMPCompatProps smp_props; @@ -360,6 +361,7 @@ struct MachineState { CPUArchIdList *possible_cpus; CpuTopology smp; struct NVDIMMState *nvdimms_state; + struct CXLState *cxl_devices_state; struct NumaState *numa_state; }; =20 diff --git a/include/hw/cxl/cxl.h b/include/hw/cxl/cxl.h index 554ad93b6b..31af92fd5e 100644 --- a/include/hw/cxl/cxl.h +++ b/include/hw/cxl/cxl.h @@ -17,4 +17,8 @@ #define CXL_COMPONENT_REG_BAR_IDX 0 #define CXL_DEVICE_REG_BAR_IDX 2 =20 +typedef struct CXLState { + bool is_enabled; +} CXLState; + #endif --=20 2.32.0