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[187.188.190.73]) by smtp.gmail.com with ESMTPSA id h6-20020a9d7986000000b005ce0d5433cdsm1066665otm.15.2022.04.01.05.59.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Apr 2022 05:59:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yF7C9gaOsw5q5PId/RPk9weVI8GZSE/i/UYTi79cArg=; b=Fv9EPnrAA2w7zGLj+VSTHip02aJ3WndToaz3PLpV8oCsH46TIH8cn5g6q7lLNb9R/Y 1wUh4QyIbv4fWeHrepGScG9nbBzw1zGeliONU3lVoU60wsxmt/QSoK5UCvh0CwPerYGi ccQLPNTXkg4G2hrV+XhpuZOaBEmh8d2S2faufns3maDyZPkfPyvIM4IsBL7hHYPBpCvQ EOtoGUVWrp4Y40Utqdmlw7TFNabUDba2PIcks01UeCVeWU2mQzyUxvFqCWwYllVQzGq3 br8B40lDZC6z6CYgjXRMbbEDWo7CfcFVWMFHbsqzoPrx9u1v+8vGKu1L61qT6kEUEMp0 Wuxg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yF7C9gaOsw5q5PId/RPk9weVI8GZSE/i/UYTi79cArg=; b=b7t4qZhOlX6CuBFtK9H15jiPYliI+w+bmZkTgVsDiiWSUo0hPGxr5hq89gmx2OynoS kE/UL3T4m7422nrJXTKtjvtT5IGY6slzIHDO4JLob1KgvFUI5eFYQe5X3IkZqcLk4vfJ dTY/r/n7A8inOfg/VJfB+5l5X7ypJoXC/chk5fNOZW1av/nfuP704jR7n2dBANHyyq7R iHIwccZJrvqecE4i+9KvivUPtQVCT+4fRK8sajMjVw5s3xBxn/b/WlLDqbtbbmndmVZc VMeu95PVMMAr9puP+XdhunpF/EZAw3KPQfetYbjxi+4VCG9Tt8qYH3C2amQK162T0jkA 2ZuA== X-Gm-Message-State: AOAM53177bxUc83EzAJ8GtApne00irSqLYeNXLrduvKofs2zn9yeAHCK CkS7169forj7aIqLfHpJFP+ljN4sOOwAqHQHGjY= X-Google-Smtp-Source: ABdhPJwa/Q6VsR8hj8hy8guj5P+ot4ujgW1DYefmfwYdd0LLOBXN16YcbXRVZiICt8fZsaugisOIRw== X-Received: by 2002:a4a:5510:0:b0:328:faf7:9ed9 with SMTP id e16-20020a4a5510000000b00328faf79ed9mr1806789oob.65.1648817992380; Fri, 01 Apr 2022 05:59:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 1/2] target/riscv: Use cpu_loop_exit_restore directly from mmu faults Date: Fri, 1 Apr 2022 06:59:47 -0600 Message-Id: <20220401125948.79292-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220401125948.79292-1-richard.henderson@linaro.org> References: <20220401125948.79292-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::c36 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c36; envelope-from=richard.henderson@linaro.org; helo=mail-oo1-xc36.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, bin.meng@windriver.com, alistair.francis@wdc.com, palmer@dabbelt.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1648818199567100001 Content-Type: text/plain; charset="utf-8" The riscv_raise_exception function stores its argument into exception_index and then exits to the main loop. When we have already set exception_index, we can just exit directly. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 1c60fb2e80..126251d5da 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1150,7 +1150,7 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, hw= addr physaddr, env->badaddr =3D addr; env->two_stage_lookup =3D riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(mmu_idx); - riscv_raise_exception(&cpu->env, cs->exception_index, retaddr); + cpu_loop_exit_restore(cs, retaddr); } =20 void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, @@ -1175,7 +1175,7 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, vadd= r addr, env->badaddr =3D addr; env->two_stage_lookup =3D riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(mmu_idx); - riscv_raise_exception(env, cs->exception_index, retaddr); + cpu_loop_exit_restore(cs, retaddr); } =20 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, @@ -1311,7 +1311,7 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, first_stage_error, riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(mmu_idx)); - riscv_raise_exception(env, cs->exception_index, retaddr); + cpu_loop_exit_restore(cs, retaddr); } =20 return true; --=20 2.25.1 From nobody Mon Feb 9 01:49:12 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1648818275966706.1850727339071; Fri, 1 Apr 2022 06:04:35 -0700 (PDT) Received: from localhost ([::1]:49256 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1naGx8-0003fC-SA for importer@patchew.org; Fri, 01 Apr 2022 09:04:34 -0400 Received: from eggs.gnu.org ([209.51.188.92]:46658) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1naGsf-0007So-4x for qemu-devel@nongnu.org; Fri, 01 Apr 2022 08:59:57 -0400 Received: from [2607:f8b0:4864:20::22f] (port=40511 helo=mail-oi1-x22f.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1naGsd-00037j-8l for qemu-devel@nongnu.org; Fri, 01 Apr 2022 08:59:56 -0400 Received: by mail-oi1-x22f.google.com with SMTP id i7so2717873oie.7 for ; Fri, 01 Apr 2022 05:59:54 -0700 (PDT) Received: from localhost.localdomain (fixed-187-188-190-73.totalplay.net. [187.188.190.73]) by smtp.gmail.com with ESMTPSA id h6-20020a9d7986000000b005ce0d5433cdsm1066665otm.15.2022.04.01.05.59.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 01 Apr 2022 05:59:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=remv68tyTQNbr4dsFhIspC7nRXHKrJg5z69/YnKTiFc=; b=kRVYuJIs+8mWT6jCkkkDH+qRo2vQYrYAmaOEacIkKWEAT0G7DpBxA6U/nCPYq5TYmL dP5vwQFNQ6cHeD3wmDwsOyzXxkPwLHCKoHz2cNBeVm0aIzXYDyYB9qeqGw7qmCPVJBGT xLI62D4Q8k1nCkpaX/4GGa3nVudKq4QNE5uje2AJhzAEdKd/YgbjLnVNFN1qv4rKL7s7 lUyxu5INQ0zwVsqlAhP12LYzfL+fBk0NDULmeg0PLMioFzMcMiP76p91yvvCkxaw/x6m B11tIkAsjgj/UshtmdJce36o/c7RIx9pbaEXs+p+ezh8AdRLjCqH53JVUlmMKbTNtzFO Rkyw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=remv68tyTQNbr4dsFhIspC7nRXHKrJg5z69/YnKTiFc=; b=uBTAPmDF3fetmoa7IauilcS/FR9YnNPX31Z4BYyJXB/tjRyxraWCpV7ETRSEwMbSTn HgxOxWV42p2jb1ErlCo7X21sal6oHpsHdV/ko1bubSfjwF2lMakmhWWi1gdnp0JkXUZ8 u93SnQl+vpWyLnjB1Jkrt2WuKK1K9J5MjTb7iP+HXMpDLguSm+rzHTRKAtxDLbD2v33L GuvN9p9NXBfrwzNblghxqxkhQMA8rjoU3TPZgY5n3fEQPGLaum4AN+FRk0ZznYw6aD/y OhdwNnvCcWd+gEW9GHMkkvWnMC+s4ns/51EVJGAabkwE/7oqHKqMDm6cA9PE3d29CRic iATQ== X-Gm-Message-State: AOAM531FaCzTRW4pwU1agcVFjLodeKSS+HucI3H8sc6UPde/ykh27aQW +riy1cc3rrO6sswa0xRNxbS/HVQ1wM6LtHKMEL4= X-Google-Smtp-Source: ABdhPJwnQp/Fajbrf8K7FM2oVslwCFZ9NDK2kAT+/nsoW0Pu53RUrYYZZ4h2WncuLA4wTw+mOvP6yA== X-Received: by 2002:a54:4092:0:b0:2d9:4715:dadf with SMTP id i18-20020a544092000000b002d94715dadfmr4563019oii.151.1648817994085; Fri, 01 Apr 2022 05:59:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH 2/2] target/riscv: Mark amo insns during translation Date: Fri, 1 Apr 2022 06:59:48 -0600 Message-Id: <20220401125948.79292-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220401125948.79292-1-richard.henderson@linaro.org> References: <20220401125948.79292-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::22f (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22f.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-riscv@nongnu.org, bin.meng@windriver.com, alistair.francis@wdc.com, palmer@dabbelt.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1648818276379100001 Content-Type: text/plain; charset="utf-8" Atomic memory operations perform both reads and writes as part of their implementation, but always raise write faults. Use TARGET_INSN_START_EXTRA_WORDS to mark amo insns in the opcode stream, and force the access type to write at the point of raising the exception. Signed-off-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h | 15 ++++++ target/riscv/cpu.c | 3 ++ target/riscv/cpu_helper.c | 62 +++++++++++++++++-------- target/riscv/translate.c | 9 ++++ target/riscv/insn_trans/trans_rva.c.inc | 11 ++++- 5 files changed, 79 insertions(+), 21 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c069fe85fa..3de4da3fa1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -290,6 +290,13 @@ struct CPUArchState { /* True if in debugger mode. */ bool debugger; =20 + /* + * True if unwinding through an amo insn. Used to transform a + * read fault into a store_amo fault; only valid immediately + * after cpu_restore_state(). + */ + bool unwind_amo; + /* * CSRs for PointerMasking extension */ @@ -517,6 +524,14 @@ FIELD(TB_FLAGS, XL, 20, 2) FIELD(TB_FLAGS, PM_MASK_ENABLED, 22, 1) FIELD(TB_FLAGS, PM_BASE_ENABLED, 23, 1) =20 +#ifndef CONFIG_USER_ONLY +/* + * RISC-V-specific extra insn start words: + * 1: True if the instruction is AMO, false otherwise. + */ +#define TARGET_INSN_START_EXTRA_WORDS 1 +#endif + #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) #else diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ddda4906ff..3818d5ba80 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -396,6 +396,9 @@ void restore_state_to_opc(CPURISCVState *env, Translati= onBlock *tb, } else { env->pc =3D data[0]; } +#ifndef CONFIG_USER_ONLY + env->unwind_amo =3D data[1]; +#endif } =20 static void riscv_cpu_reset(DeviceState *dev) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 126251d5da..b5bbe6fc39 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -1139,26 +1139,11 @@ void riscv_cpu_do_transaction_failed(CPUState *cs, = hwaddr physaddr, RISCVCPU *cpu =3D RISCV_CPU(cs); CPURISCVState *env =3D &cpu->env; =20 - if (access_type =3D=3D MMU_DATA_STORE) { - cs->exception_index =3D RISCV_EXCP_STORE_AMO_ACCESS_FAULT; - } else if (access_type =3D=3D MMU_DATA_LOAD) { - cs->exception_index =3D RISCV_EXCP_LOAD_ACCESS_FAULT; - } else { - cs->exception_index =3D RISCV_EXCP_INST_ACCESS_FAULT; + cpu_restore_state(cs, retaddr, true); + if (env->unwind_amo) { + access_type =3D MMU_DATA_STORE; } =20 - env->badaddr =3D addr; - env->two_stage_lookup =3D riscv_cpu_virt_enabled(env) || - riscv_cpu_two_stage_lookup(mmu_idx); - cpu_loop_exit_restore(cs, retaddr); -} - -void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, int mmu_idx, - uintptr_t retaddr) -{ - RISCVCPU *cpu =3D RISCV_CPU(cs); - CPURISCVState *env =3D &cpu->env; switch (access_type) { case MMU_INST_FETCH: cs->exception_index =3D RISCV_EXCP_INST_ADDR_MIS; @@ -1172,10 +1157,43 @@ void riscv_cpu_do_unaligned_access(CPUState *cs, va= ddr addr, default: g_assert_not_reached(); } + env->badaddr =3D addr; env->two_stage_lookup =3D riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(mmu_idx); - cpu_loop_exit_restore(cs, retaddr); + cpu_loop_exit(cs); +} + +void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, int mmu_idx, + uintptr_t retaddr) +{ + RISCVCPU *cpu =3D RISCV_CPU(cs); + CPURISCVState *env =3D &cpu->env; + + cpu_restore_state(cs, retaddr, true); + if (env->unwind_amo) { + access_type =3D MMU_DATA_STORE; + } + + switch (access_type) { + case MMU_INST_FETCH: + cs->exception_index =3D RISCV_EXCP_INST_ADDR_MIS; + break; + case MMU_DATA_LOAD: + cs->exception_index =3D RISCV_EXCP_LOAD_ADDR_MIS; + break; + case MMU_DATA_STORE: + cs->exception_index =3D RISCV_EXCP_STORE_AMO_ADDR_MIS; + break; + default: + g_assert_not_reached(); + } + + env->badaddr =3D addr; + env->two_stage_lookup =3D riscv_cpu_virt_enabled(env) || + riscv_cpu_two_stage_lookup(mmu_idx); + cpu_loop_exit(cs); } =20 bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size, @@ -1307,11 +1325,15 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address= , int size, } else if (probe) { return false; } else { + cpu_restore_state(cs, retaddr, true); + if (env->unwind_amo) { + access_type =3D MMU_DATA_STORE; + } raise_mmu_exception(env, address, access_type, pmp_violation, first_stage_error, riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(mmu_idx)); - cpu_loop_exit_restore(cs, retaddr); + cpu_loop_exit(cs); } =20 return true; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index fac998a6b5..ae4b0d1524 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -107,6 +107,10 @@ typedef struct DisasContext { /* PointerMasking extension */ bool pm_mask_enabled; bool pm_base_enabled; +#ifndef CONFIG_USER_ONLY + /* TCG op of the current insn_start. */ + TCGOp *insn_start; +#endif } DisasContext; =20 static inline bool has_ext(DisasContext *ctx, uint32_t ext) @@ -1105,7 +1109,12 @@ static void riscv_tr_insn_start(DisasContextBase *dc= base, CPUState *cpu) { DisasContext *ctx =3D container_of(dcbase, DisasContext, base); =20 +#ifdef CONFIG_USER_ONLY tcg_gen_insn_start(ctx->base.pc_next); +#else + tcg_gen_insn_start(ctx->base.pc_next, 0); + ctx->insn_start =3D tcg_last_op(); +#endif } =20 static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cp= u) diff --git a/target/riscv/insn_trans/trans_rva.c.inc b/target/riscv/insn_tr= ans/trans_rva.c.inc index 45db82c9be..66faa8f1da 100644 --- a/target/riscv/insn_trans/trans_rva.c.inc +++ b/target/riscv/insn_trans/trans_rva.c.inc @@ -37,6 +37,13 @@ static bool gen_lr(DisasContext *ctx, arg_atomic *a, Mem= Op mop) return true; } =20 +static void record_insn_start_amo(DisasContext *ctx) +{ +#ifndef CONFIG_USER_ONLY + tcg_set_insn_start_param(ctx->insn_start, 1, 1); +#endif +} + static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemOp mop) { TCGv dest, src1, src2; @@ -73,6 +80,7 @@ static bool gen_sc(DisasContext *ctx, arg_atomic *a, MemO= p mop) */ tcg_gen_movi_tl(load_res, -1); =20 + record_insn_start_amo(ctx); return true; } =20 @@ -85,8 +93,9 @@ static bool gen_amo(DisasContext *ctx, arg_atomic *a, TCGv src2 =3D get_gpr(ctx, a->rs2, EXT_NONE); =20 func(dest, src1, src2, ctx->mem_idx, mop); - gen_set_gpr(ctx, a->rd, dest); + + record_insn_start_amo(ctx); return true; } =20 --=20 2.25.1