From nobody Sat Feb 7 15:30:02 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1648803005793934.0882681024138; Fri, 1 Apr 2022 01:50:05 -0700 (PDT) Received: from localhost ([::1]:50584 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1naCyq-0001Ax-R4 for importer@patchew.org; Fri, 01 Apr 2022 04:50:04 -0400 Received: from eggs.gnu.org ([209.51.188.92]:51802) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1naCpR-0000Fc-Ia; Fri, 01 Apr 2022 04:40:22 -0400 Received: from twspam01.aspeedtech.com ([211.20.114.71]:49830) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1naCpN-0001Tz-6P; Fri, 01 Apr 2022 04:40:20 -0400 Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 2318Rpls030495; Fri, 1 Apr 2022 16:27:51 +0800 (GMT-8) (envelope-from jamin_lin@aspeedtech.com) Received: from localhost.localdomain (192.168.70.87) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Fri, 1 Apr 2022 16:38:52 +0800 From: Jamin Lin To: Alistair Francis , Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Andrew Jeffery , Joel Stanley , Cleber Rosa , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , "Wainer dos Santos Moschetta" , Beraldo Leal , "open list:STM32F205" , "open list:All patches CC here" Subject: [PATCH v5 2/9] aspeed/smc: Add AST1030 support Date: Fri, 1 Apr 2022 16:38:43 +0800 Message-ID: <20220401083850.15266-3-jamin_lin@aspeedtech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220401083850.15266-1-jamin_lin@aspeedtech.com> References: <20220401083850.15266-1-jamin_lin@aspeedtech.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [192.168.70.87] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 2318Rpls030495 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.71; envelope-from=jamin_lin@aspeedtech.com; helo=twspam01.aspeedtech.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jamin_lin@aspeedtech.com, troy_lee@aspeedtech.com, steven_lee@aspeedtech.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1648803007803100003 From: Steven Lee AST1030 spi controller's address decoding unit is 1MB that is identical to ast2600, but fmc address decoding unit is 512kb. Introduce seg_to_reg and reg_to_seg handlers for ast1030 fmc controller. In addition, add ast1030 fmc, spi1, and spi2 class init handler. Signed-off-by: Troy Lee Signed-off-by: Jamin Lin Signed-off-by: Steven Lee Reviewed-by: C=C3=A9dric Le Goater --- hw/ssi/aspeed_smc.c | 157 ++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 157 insertions(+) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 48305e1574..68aa697164 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -1696,6 +1696,160 @@ static const TypeInfo aspeed_2600_spi2_info =3D { .class_init =3D aspeed_2600_spi2_class_init, }; =20 +/* + * The FMC Segment Registers of the AST1030 have a 512KB unit. + * Only bits [27:19] are used for decoding. + */ +#define AST1030_SEG_ADDR_MASK 0x0ff80000 + +static uint32_t aspeed_1030_smc_segment_to_reg(const AspeedSMCState *s, + const AspeedSegments *seg) +{ + uint32_t reg =3D 0; + + /* Disabled segments have a nil register */ + if (!seg->size) { + return 0; + } + + reg |=3D (seg->addr & AST1030_SEG_ADDR_MASK) >> 16; /* start offset */ + reg |=3D (seg->addr + seg->size - 1) & AST1030_SEG_ADDR_MASK; /* end o= ffset */ + return reg; +} + +static void aspeed_1030_smc_reg_to_segment(const AspeedSMCState *s, + uint32_t reg, AspeedSegments *seg) +{ + uint32_t start_offset =3D (reg << 16) & AST1030_SEG_ADDR_MASK; + uint32_t end_offset =3D reg & AST1030_SEG_ADDR_MASK; + AspeedSMCClass *asc =3D ASPEED_SMC_GET_CLASS(s); + + if (reg) { + seg->addr =3D asc->flash_window_base + start_offset; + seg->size =3D end_offset + (512 * KiB) - start_offset; + } else { + seg->addr =3D asc->flash_window_base; + seg->size =3D 0; + } +} + +static const uint32_t aspeed_1030_fmc_resets[ASPEED_SMC_R_MAX] =3D { + [R_CONF] =3D (CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE0 | + CONF_FLASH_TYPE_SPI << CONF_FLASH_TYPE1), +}; + +static const AspeedSegments aspeed_1030_fmc_segments[] =3D { + { 0x0, 128 * MiB }, /* start address is readonly */ + { 128 * MiB, 128 * MiB }, /* default is disabled but needed for -kerne= l */ + { 0x0, 0 }, /* disabled */ +}; + +static void aspeed_1030_fmc_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedSMCClass *asc =3D ASPEED_SMC_CLASS(klass); + + dc->desc =3D "Aspeed 1030 FMC Controller"; + asc->r_conf =3D R_CONF; + asc->r_ce_ctrl =3D R_CE_CTRL; + asc->r_ctrl0 =3D R_CTRL0; + asc->r_timings =3D R_TIMINGS; + asc->nregs_timings =3D 2; + asc->conf_enable_w0 =3D CONF_ENABLE_W0; + asc->cs_num_max =3D 2; + asc->segments =3D aspeed_1030_fmc_segments; + asc->segment_addr_mask =3D 0x0ff80ff8; + asc->resets =3D aspeed_1030_fmc_resets; + asc->flash_window_base =3D 0x80000000; + asc->flash_window_size =3D 0x10000000; + asc->features =3D ASPEED_SMC_FEATURE_DMA; + asc->dma_flash_mask =3D 0x0FFFFFFC; + asc->dma_dram_mask =3D 0x000BFFFC; + asc->nregs =3D ASPEED_SMC_R_MAX; + asc->segment_to_reg =3D aspeed_1030_smc_segment_to_reg; + asc->reg_to_segment =3D aspeed_1030_smc_reg_to_segment; + asc->dma_ctrl =3D aspeed_2600_smc_dma_ctrl; +} + +static const TypeInfo aspeed_1030_fmc_info =3D { + .name =3D "aspeed.fmc-ast1030", + .parent =3D TYPE_ASPEED_SMC, + .class_init =3D aspeed_1030_fmc_class_init, +}; + +static const AspeedSegments aspeed_1030_spi1_segments[] =3D { + { 0x0, 128 * MiB }, /* start address is readonly */ + { 0x0, 0 }, /* disabled */ +}; + +static void aspeed_1030_spi1_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedSMCClass *asc =3D ASPEED_SMC_CLASS(klass); + + dc->desc =3D "Aspeed 1030 SPI1 Controller"; + asc->r_conf =3D R_CONF; + asc->r_ce_ctrl =3D R_CE_CTRL; + asc->r_ctrl0 =3D R_CTRL0; + asc->r_timings =3D R_TIMINGS; + asc->nregs_timings =3D 2; + asc->conf_enable_w0 =3D CONF_ENABLE_W0; + asc->cs_num_max =3D 2; + asc->segments =3D aspeed_1030_spi1_segments; + asc->segment_addr_mask =3D 0x0ff00ff0; + asc->flash_window_base =3D 0x90000000; + asc->flash_window_size =3D 0x10000000; + asc->features =3D ASPEED_SMC_FEATURE_DMA; + asc->dma_flash_mask =3D 0x0FFFFFFC; + asc->dma_dram_mask =3D 0x000BFFFC; + asc->nregs =3D ASPEED_SMC_R_MAX; + asc->segment_to_reg =3D aspeed_2600_smc_segment_to_reg; + asc->reg_to_segment =3D aspeed_2600_smc_reg_to_segment; + asc->dma_ctrl =3D aspeed_2600_smc_dma_ctrl; +} + +static const TypeInfo aspeed_1030_spi1_info =3D { + .name =3D "aspeed.spi1-ast1030", + .parent =3D TYPE_ASPEED_SMC, + .class_init =3D aspeed_1030_spi1_class_init, +}; +static const AspeedSegments aspeed_1030_spi2_segments[] =3D { + { 0x0, 128 * MiB }, /* start address is readonly */ + { 0x0, 0 }, /* disabled */ +}; + +static void aspeed_1030_spi2_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + AspeedSMCClass *asc =3D ASPEED_SMC_CLASS(klass); + + dc->desc =3D "Aspeed 1030 SPI2 Controller"; + asc->r_conf =3D R_CONF; + asc->r_ce_ctrl =3D R_CE_CTRL; + asc->r_ctrl0 =3D R_CTRL0; + asc->r_timings =3D R_TIMINGS; + asc->nregs_timings =3D 2; + asc->conf_enable_w0 =3D CONF_ENABLE_W0; + asc->cs_num_max =3D 2; + asc->segments =3D aspeed_1030_spi2_segments; + asc->segment_addr_mask =3D 0x0ff00ff0; + asc->flash_window_base =3D 0xb0000000; + asc->flash_window_size =3D 0x10000000; + asc->features =3D ASPEED_SMC_FEATURE_DMA; + asc->dma_flash_mask =3D 0x0FFFFFFC; + asc->dma_dram_mask =3D 0x000BFFFC; + asc->nregs =3D ASPEED_SMC_R_MAX; + asc->segment_to_reg =3D aspeed_2600_smc_segment_to_reg; + asc->reg_to_segment =3D aspeed_2600_smc_reg_to_segment; + asc->dma_ctrl =3D aspeed_2600_smc_dma_ctrl; +} + +static const TypeInfo aspeed_1030_spi2_info =3D { + .name =3D "aspeed.spi2-ast1030", + .parent =3D TYPE_ASPEED_SMC, + .class_init =3D aspeed_1030_spi2_class_init, +}; + static void aspeed_smc_register_types(void) { type_register_static(&aspeed_smc_flash_info); @@ -1709,6 +1863,9 @@ static void aspeed_smc_register_types(void) type_register_static(&aspeed_2600_fmc_info); type_register_static(&aspeed_2600_spi1_info); type_register_static(&aspeed_2600_spi2_info); + type_register_static(&aspeed_1030_fmc_info); + type_register_static(&aspeed_1030_spi1_info); + type_register_static(&aspeed_1030_spi2_info); } =20 type_init(aspeed_smc_register_types) --=20 2.17.1