From nobody Tue Feb 10 23:55:17 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1648740506103618.8852427481087; Thu, 31 Mar 2022 08:28:26 -0700 (PDT) Received: from localhost ([::1]:38340 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nZwim-0000Ek-NA for importer@patchew.org; Thu, 31 Mar 2022 11:28:24 -0400 Received: from eggs.gnu.org ([209.51.188.92]:56268) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nZwfa-0003d0-4S; Thu, 31 Mar 2022 11:25:06 -0400 Received: from [187.72.171.209] (port=51585 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nZwfY-0004ne-Aa; Thu, 31 Mar 2022 11:25:05 -0400 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Thu, 31 Mar 2022 12:24:02 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id D875880060F; Thu, 31 Mar 2022 11:58:42 -0300 (-03) From: Leandro Lupori To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [RFC PATCH v2 1/5] target/ppc: Add support for the Processor Attention instruction Date: Thu, 31 Mar 2022 11:58:09 -0300 Message-Id: <20220331145813.21719-2-leandro.lupori@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220331145813.21719-1-leandro.lupori@eldorado.org.br> References: <20220331145813.21719-1-leandro.lupori@eldorado.org.br> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 31 Mar 2022 15:24:02.0531 (UTC) FILETIME=[5A12DB30:01D84513] X-Host-Lookup-Failed: Reverse DNS lookup failed for 187.72.171.209 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=187.72.171.209; envelope-from=leandro.lupori@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.659, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Leandro Lupori , danielhb413@gmail.com, richard.henderson@linaro.org, groug@kaod.org, clg@kaod.org, pbonzini@redhat.com, alex.bennee@linaro.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1648740507887100001 From: C=C3=A9dric Le Goater Check the HID0 bit to send signal, currently modeled as a checkstop. The QEMU implementation adds an exit using the GPR[3] value (that's a hack for tests) Signed-off-by: C=C3=A9dric Le Goater Signed-off-by: Leandro Lupori --- target/ppc/cpu.h | 8 ++++++++ target/ppc/excp_helper.c | 27 +++++++++++++++++++++++++++ target/ppc/helper.h | 1 + target/ppc/translate.c | 14 ++++++++++++++ 4 files changed, 50 insertions(+) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 047b24ba50..12f9f3a880 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -173,6 +173,12 @@ enum { POWERPC_EXCP_PRIV_REG =3D 0x02, /* Privileged register exception= */ /* Trap = */ POWERPC_EXCP_TRAP =3D 0x40, + /* Processor Attention = */ + POWERPC_EXCP_ATTN =3D 0x100, + /* + * NOTE: POWERPC_EXCP_ATTN uses values from 0x100 to 0x1ff to return + * error codes. + */ }; =20 #define PPC_INPUT(env) ((env)->bus_model) @@ -2089,6 +2095,8 @@ void ppc_compat_add_property(Object *obj, const char = *name, #define HID0_DOZE (1 << 23) /* pre-2.06 */ #define HID0_NAP (1 << 22) /* pre-2.06 */ #define HID0_HILE PPC_BIT(19) /* POWER8 */ +#define HID0_ATTN PPC_BIT(31) /* Processor Attention */ +#define HID0_POWER9_ATTN PPC_BIT(3) #define HID0_POWER9_HILE PPC_BIT(4) =20 /*************************************************************************= ****/ diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index d3e2cfcd71..b0c629905c 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1379,6 +1379,9 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int e= xcp) } cs->halted =3D 1; cpu_interrupt_exittb(cs); + if ((env->error_code & ~0xff) =3D=3D POWERPC_EXCP_ATTN) { + exit(env->error_code & 0xff); + } } if (env->msr_mask & MSR_HVB) { /* @@ -1971,6 +1974,30 @@ void helper_pminsn(CPUPPCState *env, powerpc_pm_insn= _t insn) env->resume_as_sreset =3D (insn !=3D PPC_PM_STOP) || (env->spr[SPR_PSSCR] & PSSCR_EC); } + +/* + * Processor Attention instruction (Implementation dependent) + */ +void helper_attn(CPUPPCState *env, target_ulong r3) +{ + bool attn =3D false; + + if (env->excp_model =3D=3D POWERPC_EXCP_POWER8) { + attn =3D !!(env->spr[SPR_HID0] & HID0_ATTN); + } else if (env->excp_model =3D=3D POWERPC_EXCP_POWER9 || + env->excp_model =3D=3D POWERPC_EXCP_POWER10) { + attn =3D !!(env->spr[SPR_HID0] & HID0_POWER9_ATTN); + } + + if (attn) { + raise_exception_err(env, POWERPC_EXCP_MCHECK, + POWERPC_EXCP_ATTN | (r3 & 0xff)); + } else { + raise_exception_err_ra(env, POWERPC_EXCP_PROGRAM, + POWERPC_EXCP_INVAL | + POWERPC_EXCP_INVAL_INVAL, GETPC()); + } +} #endif /* defined(TARGET_PPC64) */ =20 static void do_rfi(CPUPPCState *env, target_ulong nip, target_ulong msr) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 57da11c77e..9a2497569b 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -14,6 +14,7 @@ DEF_HELPER_1(rfmci, void, env) #if defined(TARGET_PPC64) DEF_HELPER_2(scv, noreturn, env, i32) DEF_HELPER_2(pminsn, void, env, i32) +DEF_HELPER_2(attn, void, env, tl) DEF_HELPER_1(rfid, void, env) DEF_HELPER_1(rfscv, void, env) DEF_HELPER_1(hrfid, void, env) diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 408ae26173..5ace6f3a29 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -4123,6 +4123,19 @@ static void gen_rvwinkle(DisasContext *ctx) gen_exception_nip(ctx, EXCP_HLT, ctx->base.pc_next); #endif /* defined(CONFIG_USER_ONLY) */ } + +static void gen_attn(DisasContext *ctx) +{ + #if defined(CONFIG_USER_ONLY) + GEN_PRIV; +#else + CHK_SV; + + gen_helper_attn(cpu_env, cpu_gpr[3]); + ctx->base.is_jmp =3D DISAS_NORETURN; +#endif +} + #endif /* #if defined(TARGET_PPC64) */ =20 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip) @@ -6844,6 +6857,7 @@ GEN_HANDLER_E(nap, 0x13, 0x12, 0x0d, 0x03FFF801, PPC_= NONE, PPC2_PM_ISA206), GEN_HANDLER_E(sleep, 0x13, 0x12, 0x0e, 0x03FFF801, PPC_NONE, PPC2_PM_ISA20= 6), GEN_HANDLER_E(rvwinkle, 0x13, 0x12, 0x0f, 0x03FFF801, PPC_NONE, PPC2_PM_IS= A206), GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H), +GEN_HANDLER(attn, 0x0, 0x00, 0x8, 0xfffffdff, PPC_FLOW), #endif /* Top bit of opc2 corresponds with low bit of LEV, so use two handlers */ GEN_HANDLER(sc, 0x11, 0x11, 0xFF, 0x03FFF01D, PPC_FLOW), --=20 2.25.1