From nobody Wed Feb 11 00:56:42 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1648647993338460.74887101017; Wed, 30 Mar 2022 06:46:33 -0700 (PDT) Received: from localhost ([::1]:51414 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nZYed-00058L-K4 for importer@patchew.org; Wed, 30 Mar 2022 09:46:31 -0400 Received: from eggs.gnu.org ([209.51.188.92]:52100) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nZXtD-0008FX-U5; Wed, 30 Mar 2022 08:57:31 -0400 Received: from beetle.greensocs.com ([5.135.226.135]:41240) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nZXtC-0004bR-33; Wed, 30 Mar 2022 08:57:31 -0400 Received: from crumble.bar.greensocs.com (unknown [172.17.10.6]) by beetle.greensocs.com (Postfix) with ESMTPS id 80A8E21EDA; Wed, 30 Mar 2022 12:56:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1648645016; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=U6XTnSySc1VPFdO0j6fRlkKZ8C5bePQAqffOUVTjrec=; b=3N71HHKtlg8nGTnSpit5vmnXB+ZUX1rYBY5FFvQBXRZngq8R4AgyXeXumUScnOPY+CFHHQ bQkbUOnkFEenTuo1KKFVNhtIn7W42HTzgcKOB3MM1jhLSt+3JQWzM31uFjUzgwVgioX6t8 qTyq9S08zoOG9N/bvoDM8y+LVtQrciY= From: Damien Hedde To: qemu-devel@nongnu.org Subject: [RFC PATCH 16/18] hw/riscv: update remaining machines due to riscv_hart_array update Date: Wed, 30 Mar 2022 14:56:37 +0200 Message-Id: <20220330125639.201937-17-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220330125639.201937-1-damien.hedde@greensocs.com> References: <20220330125639.201937-1-damien.hedde@greensocs.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam: Yes Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.135.226.135; envelope-from=damien.hedde@greensocs.com; helo=beetle.greensocs.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Peter Maydell , Alistair Francis , Bin Meng , qemu-riscv@nongnu.org, Alistair Francis , mark.burton@greensocs.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , qemu-arm@nongnu.org, Palmer Dabbelt , Vijai Kumar K , "Edgar E. Iglesias" , =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1648647996138100001 Content-Type: text/plain; charset="utf-8" virt & spike machines have multiple sockets (but they still put all cpus in the same default cluster). For these 2 machines we disable the clustering in the array in order to keep the behavior. opentitan, sifive_e and shakti_c, were using the default cluster too. But we can use the embedded cluster as it is equivalent. Signed-off-by: Damien Hedde --- hw/riscv/opentitan.c | 4 ++-- hw/riscv/shakti_c.c | 4 ++-- hw/riscv/sifive_e.c | 4 ++-- hw/riscv/spike.c | 5 +++-- hw/riscv/virt.c | 5 +++-- 5 files changed, 12 insertions(+), 10 deletions(-) diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index 2eb7454d8a..4e90610f1d 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -132,10 +132,10 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev= _soc, Error **errp) =20 object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type, &error_abort); - object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, + object_property_set_int(OBJECT(&s->cpus), "num-cpus", ms->smp.cpus, &error_abort); object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x8080, &error_a= bort); - riscv_hart_array_realize(&s->cpus, &error_abort); + qdev_realize(DEVICE(&s->cpus), NULL, &error_abort); =20 /* Boot ROM */ memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.r= om", diff --git a/hw/riscv/shakti_c.c b/hw/riscv/shakti_c.c index 93e0c8dd68..5158ea6e8b 100644 --- a/hw/riscv/shakti_c.c +++ b/hw/riscv/shakti_c.c @@ -108,7 +108,7 @@ static void shakti_c_soc_state_realize(DeviceState *dev= , Error **errp) ShaktiCSoCState *sss =3D RISCV_SHAKTI_SOC(dev); MemoryRegion *system_memory =3D get_system_memory(); =20 - riscv_hart_array_realize(&sss->cpus, &error_abort); + qdev_realize(DEVICE(&sss->cpus), NULL, &error_abort); =20 sss->plic =3D sifive_plic_create(shakti_c_memmap[SHAKTI_C_PLIC].base, (char *)SHAKTI_C_PLIC_HART_CONFIG, ms->smp.cpus, 0, @@ -171,7 +171,7 @@ static void shakti_c_soc_instance_init(Object *obj) */ object_property_set_str(OBJECT(&sss->cpus), "cpu-type", TYPE_RISCV_CPU_SHAKTI_C, &error_abort); - object_property_set_int(OBJECT(&sss->cpus), "num-harts", 1, + object_property_set_int(OBJECT(&sss->cpus), "num-cpus", 1, &error_abort); } =20 diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 25ba0a8c85..c1e67c0f78 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -179,7 +179,7 @@ static void sifive_e_soc_init(Object *obj) SiFiveESoCState *s =3D RISCV_E_SOC(obj); =20 object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY); - object_property_set_int(OBJECT(&s->cpus), "num-harts", ms->smp.cpus, + object_property_set_int(OBJECT(&s->cpus), "num-cpus", ms->smp.cpus, &error_abort); object_property_set_int(OBJECT(&s->cpus), "resetvec", 0x1004, &error_a= bort); object_initialize_child(obj, "riscv.sifive.e.gpio0", &s->gpio, @@ -195,7 +195,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Erro= r **errp) =20 object_property_set_str(OBJECT(&s->cpus), "cpu-type", ms->cpu_type, &error_abort); - riscv_hart_array_realize(&s->cpus, &error_abort); + qdev_realize(DEVICE(&s->cpus), NULL, &error_abort); =20 /* Mask ROM */ memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom= ", diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index b75e3656e1..17bba3c7fa 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -228,9 +228,10 @@ static void spike_board_init(MachineState *machine) machine->cpu_type, &error_abort); object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", base_hartid, &error_abort); - object_property_set_int(OBJECT(&s->soc[i]), "num-harts", + object_property_set_int(OBJECT(&s->soc[i]), "num-cpus", hart_count, &error_abort); - riscv_hart_array_realize(&s->soc[i], &error_abort); + cpus_disable_clustering(CPUS(&s->soc[i])); + qdev_realize(DEVICE(&s->soc[i]), NULL, &error_abort); =20 /* Core Local Interruptor (timer and IPI) for each socket */ riscv_aclint_swi_create( diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 12036aa95b..c51b124330 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -1221,9 +1221,10 @@ static void virt_machine_init(MachineState *machine) machine->cpu_type, &error_abort); object_property_set_int(OBJECT(&s->soc[i]), "hartid-base", base_hartid, &error_abort); - object_property_set_int(OBJECT(&s->soc[i]), "num-harts", + object_property_set_int(OBJECT(&s->soc[i]), "num-cpus", hart_count, &error_abort); - riscv_hart_array_realize(&s->soc[i], &error_abort); + cpus_disable_clustering(CPUS(&s->soc[i])); + qdev_realize(DEVICE(&s->soc[i]), NULL, &error_abort); =20 if (!kvm_enabled()) { if (s->have_aclint) { --=20 2.35.1