From nobody Tue Feb 10 20:30:44 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1648647297708730.4501234256994; Wed, 30 Mar 2022 06:34:57 -0700 (PDT) Received: from localhost ([::1]:34580 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nZYTQ-0001Av-FG for importer@patchew.org; Wed, 30 Mar 2022 09:34:56 -0400 Received: from eggs.gnu.org ([209.51.188.92]:52102) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nZXtE-0008Fi-0B; Wed, 30 Mar 2022 08:57:32 -0400 Received: from beetle.greensocs.com ([5.135.226.135]:41204) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nZXtA-0004bK-Fg; Wed, 30 Mar 2022 08:57:31 -0400 Received: from crumble.bar.greensocs.com (unknown [172.17.10.6]) by beetle.greensocs.com (Postfix) with ESMTPS id C363B21ECF; Wed, 30 Mar 2022 12:56:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1648645015; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=nd0l66pK/eqKazwea3zL1B+q/z68d1eWANZjxDruLgA=; b=DpL7ux4Fho7/Trlxj2KjAch7Uqcq5FMCJGSF7ohDfZIa0Shqb7lvdRjxLocbRr9tOX0Dr4 DhZ8LfA0ddZP9EGvqxdgKowkIRxXQJMrVlC2UBZa8+2wSwiUBDocgP5kS7w8g+sM/CSXHk WdKvvqLl7PY+FkEbT6aDT8UELAe7WVg= From: Damien Hedde To: qemu-devel@nongnu.org Subject: [RFC PATCH 14/18] hw/riscv/riscv_hart: use cpus as base class Date: Wed, 30 Mar 2022 14:56:35 +0200 Message-Id: <20220330125639.201937-15-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220330125639.201937-1-damien.hedde@greensocs.com> References: <20220330125639.201937-1-damien.hedde@greensocs.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam: Yes Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.135.226.135; envelope-from=damien.hedde@greensocs.com; helo=beetle.greensocs.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Peter Maydell , Alistair Francis , Bin Meng , qemu-riscv@nongnu.org, Alistair Francis , mark.burton@greensocs.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , qemu-arm@nongnu.org, Palmer Dabbelt , Vijai Kumar K , "Edgar E. Iglesias" , =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1648647299663100001 Content-Type: text/plain; charset="utf-8" This is a drastic update: qom-path of riscv harts are changed by this patch from "/path/to/array/hart[n]" to "/path/to/array/cpu[n]". This object is now not anymore a SYS_BUS_DEVICE. Signed-off-by: Damien Hedde --- I expect it is an issue regarding migration of riscv machines. It is possible to keep an "hart[n]" alias to "cpu[n]" or even to be able to configure the cpu child basename to "hart". I'm not sure what we need to keep migration working: Does qom-path has to stay identical ? Or having aliases is ok ? Any ideas or comments ? Any of these changes could be fixed by adding support in the base class (child name, sysbus device, ...) if needed. --- include/hw/riscv/riscv_hart.h | 17 ++++++------ hw/riscv/riscv_hart.c | 49 ++++++++++++++--------------------- 2 files changed, 28 insertions(+), 38 deletions(-) diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h index 71747bf37c..65ac0d2bc4 100644 --- a/include/hw/riscv/riscv_hart.h +++ b/include/hw/riscv/riscv_hart.h @@ -21,7 +21,7 @@ #ifndef HW_RISCV_HART_H #define HW_RISCV_HART_H =20 -#include "hw/sysbus.h" +#include "hw/cpu/cpus.h" #include "target/riscv/cpu.h" #include "qom/object.h" =20 @@ -31,30 +31,29 @@ OBJECT_DECLARE_SIMPLE_TYPE(RISCVHartArrayState, RISCV_H= ART_ARRAY) =20 struct RISCVHartArrayState { /*< private >*/ - SysBusDevice parent_obj; + CpusState parent_obj; =20 /*< public >*/ - uint32_t num_harts; uint32_t hartid_base; - char *cpu_type; uint64_t resetvec; - RISCVCPU *harts; }; =20 /** * riscv_array_get_hart: + * Helper to get an hart from the container. */ -static inline RISCVCPU *riscv_array_get_hart(RISCVHartArrayState *harts, i= nt i) +static inline RISCVCPU *riscv_array_get_hart(RISCVHartArrayState *s, int i) { - return &harts->harts[i]; + return RISCV_CPU(CPUS(s)->cpus[i]); } =20 /** * riscv_array_get_num_harts: + * Helper to get the number of harts in the container. */ -static inline unsigned riscv_array_get_num_harts(RISCVHartArrayState *hart= s) +static inline unsigned riscv_array_get_num_harts(RISCVHartArrayState *s) { - return harts->num_harts; + return CPUS(s)->topology.cpus; } =20 /* Temporary function until we migrated the riscv hart array to simple dev= ice */ diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index 780fd3a59a..1b4ff7e3c6 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -22,67 +22,58 @@ #include "qapi/error.h" #include "qemu/module.h" #include "sysemu/reset.h" -#include "hw/sysbus.h" #include "target/riscv/cpu.h" #include "hw/qdev-properties.h" #include "hw/riscv/riscv_hart.h" +#include "hw/cpu/cpus.h" =20 void riscv_hart_array_realize(RISCVHartArrayState *state, Error **errp) { - sysbus_realize(SYS_BUS_DEVICE(state), errp); + /* disable the clustering */ + cpus_disable_clustering(CPUS(state)); + qdev_realize(DEVICE(state), NULL, errp); } =20 static Property riscv_harts_props[] =3D { - DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1), DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0), - DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type), DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec, DEFAULT_RSTVEC), DEFINE_PROP_END_OF_LIST(), }; =20 -static void riscv_harts_cpu_reset(void *opaque) +static void riscv_harts_configure_cpu(CpusState *base, CPUState *cpu, + unsigned i) { - RISCVCPU *cpu =3D opaque; - cpu_reset(CPU(cpu)); -} + RISCVHartArrayState *s =3D RISCV_HART_ARRAY(base); + DeviceState *cpudev =3D DEVICE(cpu); + CPURISCVState *cpuenv =3D cpu->env_ptr; =20 -static bool riscv_hart_realize(RISCVHartArrayState *s, int idx, - char *cpu_type, Error **errp) -{ - object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], cpu_typ= e); - qdev_prop_set_uint64(DEVICE(&s->harts[idx]), "resetvec", s->resetvec); - s->harts[idx].env.mhartid =3D s->hartid_base + idx; - qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]); - return qdev_realize(DEVICE(&s->harts[idx]), NULL, errp); + qdev_prop_set_uint64(cpudev, "resetvec", s->resetvec); + cpuenv->mhartid =3D s->hartid_base + i; } =20 -static void riscv_harts_realize(DeviceState *dev, Error **errp) +static void riscv_harts_init(Object *obj) { - RISCVHartArrayState *s =3D RISCV_HART_ARRAY(dev); - int n; - - s->harts =3D g_new0(RISCVCPU, s->num_harts); - - for (n =3D 0; n < s->num_harts; n++) { - if (!riscv_hart_realize(s, n, s->cpu_type, errp)) { - return; - } - } + /* add a temporary property to keep num-harts */ + object_property_add_alias(obj, "num-harts", obj, "num-cpus"); } =20 static void riscv_harts_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); + CpusClass *cc =3D CPUS_CLASS(klass); =20 device_class_set_props(dc, riscv_harts_props); - dc->realize =3D riscv_harts_realize; + + cc->base_cpu_type =3D TYPE_RISCV_CPU; + cc->configure_cpu =3D riscv_harts_configure_cpu; } =20 static const TypeInfo riscv_harts_info =3D { .name =3D TYPE_RISCV_HART_ARRAY, - .parent =3D TYPE_SYS_BUS_DEVICE, + .parent =3D TYPE_CPUS, .instance_size =3D sizeof(RISCVHartArrayState), + .instance_init =3D riscv_harts_init, .class_init =3D riscv_harts_class_init, }; =20 --=20 2.35.1