From nobody Tue Feb 10 07:57:32 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1648646617095819.2665735755011; Wed, 30 Mar 2022 06:23:37 -0700 (PDT) Received: from localhost ([::1]:49942 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nZYIR-0008AC-H2 for importer@patchew.org; Wed, 30 Mar 2022 09:23:35 -0400 Received: from eggs.gnu.org ([209.51.188.92]:52014) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nZXtA-00082g-BQ; Wed, 30 Mar 2022 08:57:28 -0400 Received: from beetle.greensocs.com ([5.135.226.135]:41118) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nZXt8-0004aL-OA; Wed, 30 Mar 2022 08:57:28 -0400 Received: from crumble.bar.greensocs.com (unknown [172.17.10.6]) by beetle.greensocs.com (Postfix) with ESMTPS id 7FBAE21EC6; Wed, 30 Mar 2022 12:56:51 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1648645011; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=OP2KACeS0PxZ1cbQpDRjk56f4TeAFjOJTUpHlmpiXfc=; b=OVTr74r2H1SGGg81PNbAotcOyG0vhNKotyLUFtZKSoRNmscrUSzencupPVJvnAMFhaNeju 2wPb/gokuOGkPlCtv1oqDkEMUDTSGeJ7o9f4GO2yy+aPKfZGK0u85KjH1K1JU6gHtq505n JZswpS2ELJUPLRqhSaK9i7Jb2NN+TKQ= From: Damien Hedde To: qemu-devel@nongnu.org Subject: [RFC PATCH 10/18] hw/riscv/riscv_hart: prepare transition to cpus Date: Wed, 30 Mar 2022 14:56:31 +0200 Message-Id: <20220330125639.201937-11-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220330125639.201937-1-damien.hedde@greensocs.com> References: <20220330125639.201937-1-damien.hedde@greensocs.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Spam: Yes Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.135.226.135; envelope-from=damien.hedde@greensocs.com; helo=beetle.greensocs.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Peter Maydell , Alistair Francis , Bin Meng , qemu-riscv@nongnu.org, Alistair Francis , mark.burton@greensocs.com, =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Yanan Wang , Eduardo Habkost , qemu-arm@nongnu.org, Palmer Dabbelt , Vijai Kumar K , "Edgar E. Iglesias" , =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1648646618759100001 Content-Type: text/plain; charset="utf-8" riscv_hart_array does not need to be a sysbus device: it does not have any mmio or sysbus irq. We want to make it inherit the new cpus class so we need a few tweaks: + a temporary helper realize so we can switch from sysbus_realize to qdev_realize (will be removed afer the transition is done). + a helper function to get an hart from the array (the current storage array field will be removed). + a helper function to get the number of harts in an array (the current field will be removed). Signed-off-by: Damien Hedde --- include/hw/riscv/riscv_hart.h | 19 +++++++++++++++++++ hw/riscv/riscv_hart.c | 5 +++++ 2 files changed, 24 insertions(+) diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h index bbc21cdc9a..71747bf37c 100644 --- a/include/hw/riscv/riscv_hart.h +++ b/include/hw/riscv/riscv_hart.h @@ -41,4 +41,23 @@ struct RISCVHartArrayState { RISCVCPU *harts; }; =20 +/** + * riscv_array_get_hart: + */ +static inline RISCVCPU *riscv_array_get_hart(RISCVHartArrayState *harts, i= nt i) +{ + return &harts->harts[i]; +} + +/** + * riscv_array_get_num_harts: + */ +static inline unsigned riscv_array_get_num_harts(RISCVHartArrayState *hart= s) +{ + return harts->num_harts; +} + +/* Temporary function until we migrated the riscv hart array to simple dev= ice */ +void riscv_hart_array_realize(RISCVHartArrayState *state, Error **errp); + #endif diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index 613ea2aaa0..780fd3a59a 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -27,6 +27,11 @@ #include "hw/qdev-properties.h" #include "hw/riscv/riscv_hart.h" =20 +void riscv_hart_array_realize(RISCVHartArrayState *state, Error **errp) +{ + sysbus_realize(SYS_BUS_DEVICE(state), errp); +} + static Property riscv_harts_props[] =3D { DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1), DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0), --=20 2.35.1