From nobody Sat Sep 28 15:35:26 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1648053380865647.6299433985031; Wed, 23 Mar 2022 09:36:20 -0700 (PDT) Received: from localhost ([::1]:43736 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nX3y7-0007Kr-OP for importer@patchew.org; Wed, 23 Mar 2022 12:36:19 -0400 Received: from eggs.gnu.org ([209.51.188.92]:39328) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nX3QZ-00064M-RB for qemu-devel@nongnu.org; Wed, 23 Mar 2022 12:01:41 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.129.124]:27995) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nX3QX-0005h1-L7 for qemu-devel@nongnu.org; Wed, 23 Mar 2022 12:01:39 -0400 Received: from mimecast-mx02.redhat.com (mimecast-mx02.redhat.com [66.187.233.88]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-133-emE5kjG1PMyURttWnSez8Q-1; Wed, 23 Mar 2022 12:01:33 -0400 Received: from smtp.corp.redhat.com (int-mx10.intmail.prod.int.rdu2.redhat.com [10.11.54.10]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 6635C899EE1; Wed, 23 Mar 2022 16:01:31 +0000 (UTC) Received: from localhost (unknown [10.39.208.32]) by smtp.corp.redhat.com (Postfix) with ESMTP id A9D7C401E36; Wed, 23 Mar 2022 16:01:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1648051296; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=FNWeXhVmSyFUF005KTrVBR4V46blkLYJSBcsUWzAiZY=; b=T2lRTNXWYi8aMNhg3sPOdGqd8j8SCY9MTqcihrJkGwfSW06X1q5HmK5Du7CnDTwpctSnXH SrIaSK119nZFbrfKi6n13YGcyyHxeySk82RgWB52bxppt1lXMf8yq36l6xeaTxd1kr8zK5 s2hV38qsei96+NhOjuouK2n9yJnWOxg= X-MC-Unique: emE5kjG1PMyURttWnSez8Q-1 From: marcandre.lureau@redhat.com To: qemu-devel@nongnu.org Subject: [PATCH 28/32] Move CPU softfloat unions to cpu-float.h Date: Wed, 23 Mar 2022 19:57:39 +0400 Message-Id: <20220323155743.1585078-29-marcandre.lureau@redhat.com> In-Reply-To: <20220323155743.1585078-1-marcandre.lureau@redhat.com> References: <20220323155743.1585078-1-marcandre.lureau@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.85 on 10.11.54.10 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=marcandre.lureau@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.129.124; envelope-from=marcandre.lureau@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , David Hildenbrand , Bin Meng , Mark Cave-Ayland , Max Filippov , Alistair Francis , "Edgar E. Iglesias" , Yoshinori Sato , Juan Quintela , Daniel Henrique Barboza , =?UTF-8?q?Marc-Andr=C3=A9=20Lureau?= , Artyom Tarasenko , Thomas Huth , Richard Henderson , "Dr. David Alan Gilbert" , Greg Kurz , "open list:S390 TCG CPUs" , "open list:ARM TCG CPUs" , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , "open list:PowerPC TCG CPUs" , Stafford Horne , David Gibson , "open list:RISC-V TCG CPUs" , Bastian Koppelmann , Cornelia Huck , Laurent Vivier , Palmer Dabbelt Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1648053382068100001 From: Marc-Andr=C3=A9 Lureau The types are no longer used in bswap.h since commit f930224fffe ("bswap.h: Remove unused float-access functions"), there isn't much sense in keeping it there and having a dependency on fpu/. Signed-off-by: Marc-Andr=C3=A9 Lureau Reviewed-by: Juan Quintela --- include/qemu/bswap.h | 60 ------------------------------------ include/qemu/cpu-float.h | 64 +++++++++++++++++++++++++++++++++++++++ target/alpha/cpu.h | 1 + target/arm/cpu.h | 1 + target/hppa/cpu.h | 1 + target/i386/cpu.h | 1 + target/m68k/cpu.h | 1 + target/microblaze/cpu.h | 2 +- target/openrisc/cpu.h | 1 + target/ppc/cpu.h | 1 + target/riscv/cpu.h | 2 +- target/rx/cpu.h | 1 + target/s390x/cpu.h | 1 + target/sh4/cpu.h | 1 + target/sparc/cpu.h | 1 + target/tricore/cpu.h | 1 + target/xtensa/cpu.h | 1 + migration/vmstate-types.c | 1 + 18 files changed, 80 insertions(+), 62 deletions(-) create mode 100644 include/qemu/cpu-float.h diff --git a/include/qemu/bswap.h b/include/qemu/bswap.h index 9dff7c7dbbc9..346d05f2aab3 100644 --- a/include/qemu/bswap.h +++ b/include/qemu/bswap.h @@ -19,8 +19,6 @@ extern "C" { #endif =20 -#include "fpu/softfloat-types.h" - #ifdef BSWAP_FROM_BYTESWAP static inline uint16_t bswap16(uint16_t x) { @@ -202,64 +200,6 @@ CPU_CONVERT(le, 64, uint64_t) # define const_le16(_x) (_x) #endif =20 -/* Unions for reinterpreting between floats and integers. */ - -typedef union { - float32 f; - uint32_t l; -} CPU_FloatU; - -typedef union { - float64 d; -#if HOST_BIG_ENDIAN - struct { - uint32_t upper; - uint32_t lower; - } l; -#else - struct { - uint32_t lower; - uint32_t upper; - } l; -#endif - uint64_t ll; -} CPU_DoubleU; - -typedef union { - floatx80 d; - struct { - uint64_t lower; - uint16_t upper; - } l; -} CPU_LDoubleU; - -typedef union { - float128 q; -#if HOST_BIG_ENDIAN - struct { - uint32_t upmost; - uint32_t upper; - uint32_t lower; - uint32_t lowest; - } l; - struct { - uint64_t upper; - uint64_t lower; - } ll; -#else - struct { - uint32_t lowest; - uint32_t lower; - uint32_t upper; - uint32_t upmost; - } l; - struct { - uint64_t lower; - uint64_t upper; - } ll; -#endif -} CPU_QuadU; - /* unaligned/endian-independent pointer access */ =20 /* diff --git a/include/qemu/cpu-float.h b/include/qemu/cpu-float.h new file mode 100644 index 000000000000..911099499ffb --- /dev/null +++ b/include/qemu/cpu-float.h @@ -0,0 +1,64 @@ +#ifndef QEMU_CPU_FLOAT_H_ +#define QEMU_CPU_FLOAT_H_ + +#include "fpu/softfloat-types.h" + +/* Unions for reinterpreting between floats and integers. */ + +typedef union { + float32 f; + uint32_t l; +} CPU_FloatU; + +typedef union { + float64 d; +#if HOST_BIG_ENDIAN + struct { + uint32_t upper; + uint32_t lower; + } l; +#else + struct { + uint32_t lower; + uint32_t upper; + } l; +#endif + uint64_t ll; +} CPU_DoubleU; + +typedef union { + floatx80 d; + struct { + uint64_t lower; + uint16_t upper; + } l; +} CPU_LDoubleU; + +typedef union { + float128 q; +#if HOST_BIG_ENDIAN + struct { + uint32_t upmost; + uint32_t upper; + uint32_t lower; + uint32_t lowest; + } l; + struct { + uint64_t upper; + uint64_t lower; + } ll; +#else + struct { + uint32_t lowest; + uint32_t lower; + uint32_t upper; + uint32_t upmost; + } l; + struct { + uint64_t lower; + uint64_t upper; + } ll; +#endif +} CPU_QuadU; + +#endif /* QEMU_CPU_FLOAT_H_ */ diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 58f00b7814fd..994a018b910d 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -22,6 +22,7 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "qemu/cpu-float.h" =20 /* Alpha processors have a weak memory model */ #define TCG_GUEST_DEFAULT_MO (0) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ccf635ac5cbc..cb5359a74702 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -21,6 +21,7 @@ #define ARM_CPU_H =20 #include "kvm-consts.h" +#include "qemu/cpu-float.h" #include "hw/registerfields.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 4cc936b6bfda..c43b93a68f14 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -22,6 +22,7 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "qemu/cpu-float.h" =20 /* PA-RISC 1.x processors have a strong memory model. */ /* ??? While we do not yet implement PA-RISC 2.0, those processors have diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 5124c1e307b5..796e2cf6d664 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -25,6 +25,7 @@ #include "kvm/hyperv-proto.h" #include "exec/cpu-defs.h" #include "qapi/qapi-types-common.h" +#include "qemu/cpu-float.h" =20 /* The x86 has a strong memory model with some store-after-load re-orderin= g */ #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 872e8ce63758..9b3bf7a44819 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -22,6 +22,7 @@ #define M68K_CPU_H =20 #include "exec/cpu-defs.h" +#include "qemu/cpu-float.h" #include "cpu-qom.h" =20 #define OS_BYTE 0 diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 0a0ce71b6a5c..67aa88b8db5b 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -22,7 +22,7 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" -#include "fpu/softfloat-types.h" +#include "qemu/cpu-float.h" =20 typedef struct CPUArchState CPUMBState; #if !defined(CONFIG_USER_ONLY) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index bdf29d2dc4c3..b9584f10d452 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -21,6 +21,7 @@ #define OPENRISC_CPU_H =20 #include "exec/cpu-defs.h" +#include "fpu/softfloat-types.h" #include "hw/core/cpu.h" #include "qom/object.h" =20 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 627e574127ba..473436a49eb5 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -21,6 +21,7 @@ #define PPC_CPU_H =20 #include "qemu/int128.h" +#include "qemu/cpu-float.h" #include "exec/cpu-defs.h" #include "cpu-qom.h" #include "qom/object.h" diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c069fe85fa1b..e1d976bdef06 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -23,7 +23,7 @@ #include "hw/core/cpu.h" #include "hw/registerfields.h" #include "exec/cpu-defs.h" -#include "fpu/softfloat-types.h" +#include "qemu/cpu-float.h" #include "qom/object.h" #include "qemu/int128.h" #include "cpu_bits.h" diff --git a/target/rx/cpu.h b/target/rx/cpu.h index b4abd90ccd1e..1c267f83bfd2 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -24,6 +24,7 @@ #include "cpu-qom.h" =20 #include "exec/cpu-defs.h" +#include "qemu/cpu-float.h" =20 /* PSW define */ REG32(PSW, 0) diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index c49c8466e74d..7d6d01325b2d 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -28,6 +28,7 @@ #include "cpu-qom.h" #include "cpu_models.h" #include "exec/cpu-defs.h" +#include "qemu/cpu-float.h" =20 #define ELF_MACHINE_UNAME "S390X" =20 diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index c72a30edfd41..14d490ac4705 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -22,6 +22,7 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "qemu/cpu-float.h" =20 /* CPU Subtypes */ #define SH_CPU_SH7750 (1 << 0) diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index abb38db6749d..dd9e2f5cdb6a 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -4,6 +4,7 @@ #include "qemu/bswap.h" #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "qemu/cpu-float.h" =20 #if !defined(TARGET_SPARC64) #define TARGET_DPREGS 16 diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 108d6b8288fb..3b9c533a7c3b 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -22,6 +22,7 @@ =20 #include "cpu-qom.h" #include "exec/cpu-defs.h" +#include "qemu/cpu-float.h" #include "tricore-defs.h" =20 struct tricore_boot_info; diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index f10cfabdc35c..71142ea8f453 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -29,6 +29,7 @@ #define XTENSA_CPU_H =20 #include "cpu-qom.h" +#include "qemu/cpu-float.h" #include "exec/cpu-defs.h" #include "xtensa-isa.h" =20 diff --git a/migration/vmstate-types.c b/migration/vmstate-types.c index bf4d440308ea..e83bfccb9ecf 100644 --- a/migration/vmstate-types.c +++ b/migration/vmstate-types.c @@ -11,6 +11,7 @@ */ =20 #include "qemu/osdep.h" +#include "qemu/cpu-float.h" #include "qemu-file.h" #include "migration.h" #include "migration/vmstate.h" --=20 2.35.1.273.ge6ebfd0e8cbb