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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=mchitale@ventanamicro.com; helo=mail-pg1-x531.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mayuresh Chitale , alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1647956921976100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" If smstateen is implemented then accesses to AIA registers CSRS, IMSIC CSRs and other IMSIC registers is controlled by setting of corresponding bits in mstateen/hstateen registers. Otherwise an illegal instruction trap or virtual instruction trap is generated. Signed-off-by: Mayuresh Chitale --- target/riscv/csr.c | 248 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 246 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5d7381c771..a8e17e4fe5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -68,6 +68,53 @@ static RISCVException smstateen_acc_ok(CPURISCVState *en= v, int mode, int bit) return RISCV_EXCP_NONE; } =20 +static RISCVException smstateen_aia_acc_ok(CPURISCVState *env, int csrno) +{ + int bit, mode; + + switch (csrno) { + case CSR_SSETEIPNUM: + case CSR_SCLREIPNUM: + case CSR_SSETEIENUM: + case CSR_SCLREIENUM: + case CSR_STOPEI: + case CSR_VSSETEIPNUM: + case CSR_VSCLREIPNUM: + case CSR_VSSETEIENUM: + case CSR_VSCLREIENUM: + case CSR_VSTOPEI: + case CSR_HSTATUS: + mode =3D PRV_S; + bit =3D SMSTATEEN0_IMSIC; + break; + + case CSR_SIEH: + case CSR_SIPH: + case CSR_HVIPH: + case CSR_HVICTL: + case CSR_HVIPRIO1: + case CSR_HVIPRIO2: + case CSR_HVIPRIO1H: + case CSR_HVIPRIO2H: + case CSR_VSIEH: + case CSR_VSIPH: + mode =3D PRV_S; + bit =3D SMSTATEEN0_AIA; + break; + + case CSR_SISELECT: + case CSR_VSISELECT: + mode =3D PRV_S; + bit =3D SMSTATEEN0_SVSLCT; + break; + + default: + return RISCV_EXCP_NONE; + } + + return smstateen_acc_ok(env, mode, bit); +} + static RISCVException fs(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) @@ -1402,6 +1449,13 @@ static int rmw_xiselect(CPURISCVState *env, int csrn= o, target_ulong *val, target_ulong new_val, target_ulong wr_mask) { target_ulong *iselect; + RISCVException ret; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } =20 /* Translate CSR number for VS-mode */ csrno =3D aia_xlate_vs_csrno(env, csrno); @@ -1484,7 +1538,9 @@ static int rmw_xireg(CPURISCVState *env, int csrno, t= arget_ulong *val, bool virt; uint8_t *iprio; int ret =3D -EINVAL; - target_ulong priv, isel, vgein; + target_ulong priv, isel, vgein =3D 0; + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); =20 /* Translate CSR number for VS-mode */ csrno =3D aia_xlate_vs_csrno(env, csrno); @@ -1513,11 +1569,20 @@ static int rmw_xireg(CPURISCVState *env, int csrno,= target_ulong *val, }; =20 /* Find the selected guest interrupt file */ - vgein =3D (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; + if (virt) { + if (!cpu->cfg.ext_smstateen || + (env->hstateen[0] & 1UL << SMSTATEEN0_IMSIC)) { + vgein =3D get_field(env->hstatus, HSTATUS_VGEIN); + } + } =20 if (ISELECT_IPRIO0 <=3D isel && isel <=3D ISELECT_IPRIO15) { /* Local interrupt priority registers not available for VS-mode */ if (!virt) { + if (priv =3D=3D PRV_S && cpu->cfg.ext_smstateen && + !(env->hstateen[0] & 1UL << SMSTATEEN0_AIA)) { + goto done; + } ret =3D rmw_iprio(riscv_cpu_mxl_bits(env), isel, iprio, val, new_val, wr_mask, (priv =3D=3D PRV_M) ? IRQ_M_EXT : IRQ_S_EXT); @@ -1551,6 +1616,13 @@ static int rmw_xsetclreinum(CPURISCVState *env, int = csrno, target_ulong *val, int ret =3D -EINVAL; bool set, pend, virt; target_ulong priv, isel, vgein, xlen, nval, wmask; + RISCVException excp; + + /* Check if smstateen is enabled and this access is allowed */ + excp =3D smstateen_aia_acc_ok(env, csrno); + if (excp !=3D RISCV_EXCP_NONE) { + return excp; + } =20 /* Translate CSR number for VS-mode */ csrno =3D aia_xlate_vs_csrno(env, csrno); @@ -1669,6 +1741,13 @@ static int rmw_xtopei(CPURISCVState *env, int csrno,= target_ulong *val, bool virt; int ret =3D -EINVAL; target_ulong priv, vgein; + RISCVException excp; + + /* Check if smstateen is enabled and this access is allowed */ + excp =3D smstateen_aia_acc_ok(env, csrno); + if (excp !=3D RISCV_EXCP_NONE) { + return excp; + } =20 /* Translate CSR number for VS-mode */ csrno =3D aia_xlate_vs_csrno(env, csrno); @@ -2013,6 +2092,12 @@ static RISCVException write_mstateen(CPURISCVState *= env, int csrno, wr_mask |=3D 1UL << SMSTATEEN0_FCSR; } =20 + if (riscv_feature(env, RISCV_FEATURE_AIA)) { + wr_mask |=3D (1UL << SMSTATEEN0_IMSIC) + | (1UL << SMSTATEEN0_AIA) + | (1UL << SMSTATEEN0_SVSLCT); + } + write_smstateen(env, reg, wr_mask, new_val); =20 return RISCV_EXCP_NONE; @@ -2040,6 +2125,12 @@ static RISCVException write_mstateenh(CPURISCVState = *env, int csrno, wr_mask |=3D 1UL << SMSTATEEN0_FCSR; } =20 + if (riscv_feature(env, RISCV_FEATURE_AIA)) { + wr_mask |=3D (1UL << SMSTATEEN0_IMSIC) + | (1UL << SMSTATEEN0_AIA) + | (1UL << SMSTATEEN0_SVSLCT); + } + write_smstateen(env, reg, wr_mask, val); =20 return RISCV_EXCP_NONE; @@ -2064,6 +2155,12 @@ static RISCVException write_hstateen(CPURISCVState *= env, int csrno, wr_mask |=3D 1UL << SMSTATEEN0_FCSR; } =20 + if (riscv_feature(env, RISCV_FEATURE_AIA)) { + wr_mask |=3D (1UL << SMSTATEEN0_IMSIC) + | (1UL << SMSTATEEN0_AIA) + | (1UL << SMSTATEEN0_SVSLCT); + } + reg =3D &env->hstateen[index]; wr_mask &=3D env->mstateen[index]; write_smstateen(env, reg, wr_mask, new_val); @@ -2091,6 +2188,12 @@ static RISCVException write_hstateenh(CPURISCVState = *env, int csrno, wr_mask |=3D 1UL << SMSTATEEN0_FCSR; } =20 + if (riscv_feature(env, RISCV_FEATURE_AIA)) { + wr_mask |=3D (1UL << SMSTATEEN0_IMSIC) + | (1UL << SMSTATEEN0_AIA) + | (1UL << SMSTATEEN0_SVSLCT); + } + reg =3D &env->hstateen[index]; val =3D (uint64_t)new_val << 32; val |=3D *reg & 0xFFFFFFFF; @@ -2284,6 +2387,12 @@ static RISCVException rmw_vsieh(CPURISCVState *env, = int csrno, uint64_t rval; RISCVException ret; =20 + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + ret =3D rmw_vsie64(env, csrno, &rval, ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); if (ret_val) { @@ -2338,6 +2447,12 @@ static RISCVException rmw_sieh(CPURISCVState *env, i= nt csrno, uint64_t rval; RISCVException ret; =20 + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + ret =3D rmw_sie64(env, csrno, &rval, ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); if (ret_val) { @@ -2500,6 +2615,12 @@ static RISCVException rmw_vsiph(CPURISCVState *env, = int csrno, uint64_t rval; RISCVException ret; =20 + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + ret =3D rmw_vsip64(env, csrno, &rval, ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); if (ret_val) { @@ -2554,6 +2675,12 @@ static RISCVException rmw_siph(CPURISCVState *env, i= nt csrno, uint64_t rval; RISCVException ret; =20 + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + ret =3D rmw_sip64(env, csrno, &rval, ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); if (ret_val) { @@ -2744,6 +2871,10 @@ static RISCVException read_hstatus(CPURISCVState *en= v, int csrno, static RISCVException write_hstatus(CPURISCVState *env, int csrno, target_ulong val) { + if (smstateen_aia_acc_ok(env, csrno) !=3D RISCV_EXCP_NONE) { + val &=3D ~HSTATUS_VGEIN; + } + env->hstatus =3D val; if (riscv_cpu_mxl(env) !=3D MXL_RV32 && get_field(val, HSTATUS_VSXL) != =3D 2) { qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN optio= ns."); @@ -2804,6 +2935,12 @@ static RISCVException rmw_hidelegh(CPURISCVState *en= v, int csrno, uint64_t rval; RISCVException ret; =20 + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + ret =3D rmw_hideleg64(env, csrno, &rval, ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); if (ret_val) { @@ -2850,6 +2987,12 @@ static RISCVException rmw_hviph(CPURISCVState *env, = int csrno, uint64_t rval; RISCVException ret; =20 + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + ret =3D rmw_hvip64(env, csrno, &rval, ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); if (ret_val) { @@ -2904,6 +3047,13 @@ static RISCVException write_hcounteren(CPURISCVState= *env, int csrno, static RISCVException read_hgeie(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + ret =3D smstateen_acc_ok(env, PRV_S, SMSTATEEN0_IMSIC); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + if (val) { *val =3D env->hgeie; } @@ -2913,6 +3063,13 @@ static RISCVException read_hgeie(CPURISCVState *env,= int csrno, static RISCVException write_hgeie(CPURISCVState *env, int csrno, target_ulong val) { + RISCVException ret; + + ret =3D smstateen_acc_ok(env, PRV_S, SMSTATEEN0_IMSIC); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + /* Only GEILEN:1 bits implemented and BIT0 is never implemented */ val &=3D ((((target_ulong)1) << env->geilen) - 1) << 1; env->hgeie =3D val; @@ -2952,6 +3109,13 @@ static RISCVException write_htinst(CPURISCVState *en= v, int csrno, static RISCVException read_hgeip(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + ret =3D smstateen_acc_ok(env, PRV_S, SMSTATEEN0_IMSIC); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + if (val) { *val =3D env->hgeip; } @@ -3022,12 +3186,28 @@ static RISCVException write_htimedeltah(CPURISCVSta= te *env, int csrno, =20 static int read_hvictl(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + *val =3D env->hvictl; return RISCV_EXCP_NONE; } =20 static int write_hvictl(CPURISCVState *env, int csrno, target_ulong val) { + RISCVException ret =3D RISCV_EXCP_NONE; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + env->hvictl =3D val & HVICTL_VALID_MASK; return RISCV_EXCP_NONE; } @@ -3086,41 +3266,105 @@ static int write_hvipriox(CPURISCVState *env, int = first_index, =20 static int read_hviprio1(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + return read_hvipriox(env, 0, env->hviprio, val); } =20 static int write_hviprio1(CPURISCVState *env, int csrno, target_ulong val) { + RISCVException ret; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + return write_hvipriox(env, 0, env->hviprio, val); } =20 static int read_hviprio1h(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + return read_hvipriox(env, 4, env->hviprio, val); } =20 static int write_hviprio1h(CPURISCVState *env, int csrno, target_ulong val) { + RISCVException ret; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + return write_hvipriox(env, 4, env->hviprio, val); } =20 static int read_hviprio2(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + return read_hvipriox(env, 8, env->hviprio, val); } =20 static int write_hviprio2(CPURISCVState *env, int csrno, target_ulong val) { + RISCVException ret; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + return write_hvipriox(env, 8, env->hviprio, val); } =20 static int read_hviprio2h(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + return read_hvipriox(env, 12, env->hviprio, val); } =20 static int write_hviprio2h(CPURISCVState *env, int csrno, target_ulong val) { + RISCVException ret; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + return write_hvipriox(env, 12, env->hviprio, val); } =20 --=20 2.17.1