From nobody Sat Sep 21 00:49:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1647956630; cv=none; d=zohomail.com; s=zohoarc; b=csVxdel33y6CMuwb1TCvm5qfej35Cc9Zq7oUI8Eohc7zKl6C3knmy/TQ20t566YljXHb5Y48zsfnB6U6HL1p9Hx6rIIUhWVZMk3fRMyvlLoS0BbHKOM8uwEWipuU7FYUeFLc5pN0APv5PD9E5UhtlLMhwm6ttFpA5mOV4AalhtY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1647956630; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=7MiFWbxn0OlxTDdKDRVVlxJUDcW9QG+46FFdHfSR7F0=; b=BbFktbrMMGGZX76fwWNCkeYO0oClE7mHFnjf2z76NPi9Uo1HlYNbapZvvqhndZSXIceO/rJapAltL8pdo2UEZIu07+3piMW1RBalqZk2h+bk1UMqspif0VO4Gnnh8a4TAeZwO1Sf32OT2Hr/10UZVKDguC+T2EbqUEZVT4tFT/k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1647956630188790.3459275280762; Tue, 22 Mar 2022 06:43:50 -0700 (PDT) Received: from localhost ([::1]:37986 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nWenc-0008Mv-E8 for importer@patchew.org; Tue, 22 Mar 2022 09:43:48 -0400 Received: from eggs.gnu.org ([209.51.188.92]:32800) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nWemT-0006nT-Es for qemu-devel@nongnu.org; Tue, 22 Mar 2022 09:42:37 -0400 Received: from [2607:f8b0:4864:20::631] (port=35361 helo=mail-pl1-x631.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nWemR-0006iH-CB for qemu-devel@nongnu.org; Tue, 22 Mar 2022 09:42:37 -0400 Received: by mail-pl1-x631.google.com with SMTP id n15so15504012plh.2 for ; Tue, 22 Mar 2022 06:42:35 -0700 (PDT) Received: from ThinkPad-T490.dc1.ventanamicro.com ([171.50.204.174]) by smtp.googlemail.com with ESMTPSA id ij17-20020a17090af81100b001c67c964d93sm3101216pjb.2.2022.03.22.06.42.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Mar 2022 06:42:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=7MiFWbxn0OlxTDdKDRVVlxJUDcW9QG+46FFdHfSR7F0=; b=F/aTP2/KIzdJhEB/+KU1jSBOXw+/WnMrq3kH03OflB7epJ5+ih5aPGCgx6hmvpBZj+ NDMw7L2JS5ujdlKV0ownymsPK6V5V+uUCKwaYvIXcd6BCSKPjB/hP+Ovz867IylIlIXd B3lTtN9kuWop7InMqaNn5LK4OOttbfsWCSYpZkUpvZQjAoWYyidw9qaQYX9UXQAvVtay PxA0EeG+f8R/NV5roWICClxVAwWJSJYxyGaHQifT+hShGu4eZDhhVYRsesY3WvoTrSKO NaGYiyWJPL8G2aWsR8PGZ61lcda1+IoYaf5DbAAi1nxBZf6wBeeG4AMhmuQvrT+vr9on aDjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=7MiFWbxn0OlxTDdKDRVVlxJUDcW9QG+46FFdHfSR7F0=; b=XGNL7ZeAtWLf11JVmD2M+hB8o79/Kt7bVywbbbF5wiZHAl76NzP2kz5lluZ/NrBtCQ 1V4Pzeuzft4eqCM6oZ+fxuwt76nDFFv3eMku7tCQRcmPAdWHxq2tvRiAHB23LZRPu9Hl WiFq1AFs+gF8XbYHLvKGNesdnQCS+GHeySNa7HEsdvGyzMhUzuML5Z+zuuCkBEYaCJIn xdixFRpO7FDlpa9B5LIE2Xrb8Qek8WRNZTDw0B9fu97ztMUAI+193B4cRf22Yo259x9y etHRd+7AAZCOntIYMTRosWWep7pjfCCgpmSUE6cd62KaPMDeKMejzNtf0Z+SGLKLBdN4 6XpA== X-Gm-Message-State: AOAM533Bp8dt91n+P9ECC0HjYZhdDQZnOhp6Kn2+NFKF1CyC0Yv6NC9+ P0DxixHuAzvKMYUwLgJ6xLPLXQ== X-Google-Smtp-Source: ABdhPJx03Kngp7+vs104H6LdTCrZoVXz7rCDI3CjihmhZ+NAw0/ELUNp3MC6O0/n38ZDcvwH5ABcRw== X-Received: by 2002:a17:902:9348:b0:14d:8ee9:329f with SMTP id g8-20020a170902934800b0014d8ee9329fmr18105826plp.80.1647956553733; Tue, 22 Mar 2022 06:42:33 -0700 (PDT) From: Mayuresh Chitale To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [RFC PATCH v1 1/4] target/riscv: Add smstateen support Date: Tue, 22 Mar 2022 19:12:15 +0530 Message-Id: <20220322134218.27322-2-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220322134218.27322-1-mchitale@ventanamicro.com> References: <20220322134218.27322-1-mchitale@ventanamicro.com> X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::631 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=mchitale@ventanamicro.com; helo=mail-pl1-x631.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mayuresh Chitale , alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1647956631741100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Smstateen extension specifies a mechanism to close the potential covert channels that could cause security issues. This patch adds the CSRs defined in the specification and the corresponding predicates and read/write functions. Signed-off-by: Mayuresh Chitale --- target/riscv/cpu.c | 2 + target/riscv/cpu.h | 4 + target/riscv/cpu_bits.h | 36 +++++++ target/riscv/csr.c | 210 ++++++++++++++++++++++++++++++++++++++++ target/riscv/machine.c | 22 ++++- 5 files changed, 273 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 8e338daf72..832602d91f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -807,6 +807,7 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true), DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true), DEFINE_PROP_BOOL("sstc", RISCVCPU, cfg.ext_sstc, true), + DEFINE_PROP_BOOL("smstateen", RISCVCPU, cfg.ext_smstateen, true), =20 DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec), DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec), @@ -970,6 +971,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char **= isa_str, int max_str_len) ISA_EDATA_ENTRY(svinval, ext_svinval), ISA_EDATA_ENTRY(svnapot, ext_svnapot), ISA_EDATA_ENTRY(svpbmt, ext_svpbmt), + ISA_EDATA_ENTRY(smstateen, ext_smstateen), }; =20 for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index ea23666e8e..8e61edca6f 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -338,6 +338,9 @@ struct CPURISCVState { =20 /* CSRs for execution enviornment configuration */ uint64_t menvcfg; + uint64_t mstateen[SMSTATEEN_MAX_COUNT]; + uint64_t hstateen[SMSTATEEN_MAX_COUNT]; + uint64_t sstateen[SMSTATEEN_MAX_COUNT]; target_ulong senvcfg; uint64_t henvcfg; #endif @@ -416,6 +419,7 @@ struct RISCVCPUConfig { bool ext_zve32f; bool ext_zve64f; bool ext_sscofpmf; + bool ext_smstateen; =20 /* Vendor-specific custom extensions */ bool ext_XVentanaCondOps; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 7454f4087f..66edb26686 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -205,6 +205,12 @@ /* Supervisor Configuration CSRs */ #define CSR_SENVCFG 0x10A =20 +/* Supervisor state CSRs */ +#define CSR_SSTATEEN0 0x10C +#define CSR_SSTATEEN1 0x10D +#define CSR_SSTATEEN2 0x10E +#define CSR_SSTATEEN3 0x10F + /* Supervisor Trap Handling */ #define CSR_SSCRATCH 0x140 #define CSR_SEPC 0x141 @@ -258,6 +264,16 @@ #define CSR_HENVCFG 0x60A #define CSR_HENVCFGH 0x61A =20 +/* Hypervisor state CSRs */ +#define CSR_HSTATEEN0 0x60C +#define CSR_HSTATEEN0H 0x61C +#define CSR_HSTATEEN1 0x60D +#define CSR_HSTATEEN1H 0x61D +#define CSR_HSTATEEN2 0x60E +#define CSR_HSTATEEN2H 0x61E +#define CSR_HSTATEEN3 0x60F +#define CSR_HSTATEEN3H 0x61F + /* Virtual CSRs */ #define CSR_VSSTATUS 0x200 #define CSR_VSIE 0x204 @@ -309,6 +325,26 @@ #define CSR_MENVCFG 0x30A #define CSR_MENVCFGH 0x31A =20 +/* Machine state CSRs */ +#define CSR_MSTATEEN0 0x30C +#define CSR_MSTATEEN0H 0x31C +#define CSR_MSTATEEN1 0x30D +#define CSR_MSTATEEN1H 0x31D +#define CSR_MSTATEEN2 0x30E +#define CSR_MSTATEEN2H 0x31E +#define CSR_MSTATEEN3 0x30F +#define CSR_MSTATEEN3H 0x31F + +/* Common defines for all smstateen */ +#define SMSTATEEN_MAX_COUNT 4 +#define SMSTATEEN0_CS 0 +#define SMSTATEEN0_FCSR 0 +#define SMSTATEEN0_IMSIC 58 +#define SMSTATEEN0_AIA 59 +#define SMSTATEEN0_SVSLCT 60 +#define SMSTATEEN0_HSENVCFG 62 +#define SMSTATEEN_STATEN 63 + /* Enhanced Physical Memory Protection (ePMP) */ #define CSR_MSECCFG 0x747 #define CSR_MSECCFGH 0x757 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d3d16d71de..215c8ecef1 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -265,6 +265,42 @@ static RISCVException hmode32(CPURISCVState *env, int = csrno) =20 } =20 +static RISCVException mstateen(CPURISCVState *env, int csrno) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + if (!cpu->cfg.ext_smstateen) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return any(env, csrno); +} + +static RISCVException hstateen(CPURISCVState *env, int csrno) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + if (!cpu->cfg.ext_smstateen) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return hmode(env, csrno); +} + +static RISCVException sstateen(CPURISCVState *env, int csrno) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + if (!cpu->cfg.ext_smstateen) { + return RISCV_EXCP_ILLEGAL_INST; + } + + return smode(env, csrno); +} + /* Checks if PointerMasking registers could be accessed */ static RISCVException pointer_masking(CPURISCVState *env, int csrno) { @@ -1882,6 +1918,129 @@ static RISCVException write_henvcfgh(CPURISCVState = *env, int csrno, return RISCV_EXCP_NONE; } =20 +static inline void write_smstateen(CPURISCVState *env, uint64_t *reg, + uint64_t wr_mask, uint64_t new_val) +{ + *reg =3D (*reg & ~wr_mask) | (new_val & wr_mask); +} + +static RISCVException read_mstateen(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->mstateen[csrno - CSR_MSTATEEN0]; + + return RISCV_EXCP_NONE; +} + +static RISCVException write_mstateen(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + uint64_t *reg; + uint64_t wr_mask =3D 1UL << SMSTATEEN_STATEN; + + reg =3D &env->mstateen[csrno - CSR_MSTATEEN0]; + write_smstateen(env, reg, wr_mask, new_val); + + return RISCV_EXCP_NONE; +} + +static RISCVException read_mstateenh(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->mstateen[csrno - CSR_MSTATEEN0H - 0x10] >> 32; + + return RISCV_EXCP_NONE; +} + +static RISCVException write_mstateenh(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + uint64_t *reg; + uint64_t val; + uint64_t wr_mask =3D 1UL << SMSTATEEN_STATEN; + + reg =3D &env->mstateen[csrno - CSR_MSTATEEN0H - 0x10]; + val =3D (uint64_t)new_val << 32; + val |=3D *reg & 0xFFFFFFFF; + write_smstateen(env, reg, wr_mask, val); + + return RISCV_EXCP_NONE; +} + +static RISCVException read_hstateen(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->hstateen[csrno - CSR_HSTATEEN0]; + + return RISCV_EXCP_NONE; +} + +static RISCVException write_hstateen(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + uint64_t *reg; + uint64_t wr_mask =3D 1UL << SMSTATEEN_STATEN; + int index =3D csrno - CSR_HSTATEEN0; + + reg =3D &env->hstateen[index]; + wr_mask &=3D env->mstateen[index]; + write_smstateen(env, reg, wr_mask, new_val); + + return RISCV_EXCP_NONE; +} + +static RISCVException read_hstateenh(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->hstateen[csrno - CSR_HSTATEEN0H - 0x10] >> 32; + + return RISCV_EXCP_NONE; +} + +static RISCVException write_hstateenh(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + uint64_t *reg; + uint64_t val; + uint64_t wr_mask =3D 1UL << SMSTATEEN_STATEN; + int index =3D csrno - CSR_HSTATEEN0H - 0x10; + + reg =3D &env->hstateen[index]; + val =3D (uint64_t)new_val << 32; + val |=3D *reg & 0xFFFFFFFF; + wr_mask &=3D env->mstateen[index]; + + write_smstateen(env, reg, wr_mask, val); + return RISCV_EXCP_NONE; +} + +static RISCVException read_sstateen(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->sstateen[csrno - CSR_SSTATEEN0]; + + return RISCV_EXCP_NONE; +} + +static RISCVException write_sstateen(CPURISCVState *env, int csrno, + target_ulong new_val) +{ + uint64_t *reg; + uint64_t wr_mask =3D 0; + int index =3D csrno - CSR_SSTATEEN0; + bool virt =3D riscv_cpu_virt_enabled(env); + + reg =3D &env->sstateen[index]; + if (virt) { + wr_mask &=3D env->mstateen[index]; + } else { + wr_mask &=3D env->hstateen[index]; + } + write_smstateen(env, reg, wr_mask, new_val); + + return RISCV_EXCP_NONE; +} + static RISCVException rmw_mip64(CPURISCVState *env, int csrno, uint64_t *ret_val, uint64_t new_val, uint64_t wr_mask) @@ -3664,6 +3823,57 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_HENVCFGH] =3D { "henvcfgh", hmode32, read_henvcfgh, write_henvcfg= h, .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, =20 + /* Smstateen extension CSRs */ + [CSR_MSTATEEN0] =3D { "mstateen0", mstateen, read_mstateen, write_msta= teen, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_MSTATEEN0H] =3D { "mstateen0h", mstateen, read_mstateenh, + write_mstateenh, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_MSTATEEN1] =3D { "mstateen1", mstateen, read_mstateen, write_msta= teen, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_MSTATEEN1H] =3D { "mstateen1h", mstateen, read_mstateenh, + write_mstateenh, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_MSTATEEN2] =3D { "mstateen2", mstateen, read_mstateen, write_msta= teen, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_MSTATEEN2H] =3D { "mstateen2h", mstateen, read_mstateenh, + write_mstateenh, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_MSTATEEN3] =3D { "mstateen3", mstateen, read_mstateen, write_msta= teen, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_MSTATEEN3H] =3D { "mstateen3h", mstateen, read_mstateenh, + write_mstateenh, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + + [CSR_HSTATEEN0] =3D { "hstateen0", hstateen, read_hstateen, write_hsta= teen, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_HSTATEEN0H] =3D { "hstateen0h", hstateen, read_hstateenh, + write_hstateenh, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_HSTATEEN1] =3D { "hstateen1", hstateen, read_hstateen, write_hsta= teen, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_HSTATEEN1H] =3D { "hstateen1h", hstateen, read_hstateenh, + write_hstateenh, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_HSTATEEN2] =3D { "hstateen2", hstateen, read_hstateen, write_hsta= teen, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_HSTATEEN2H] =3D { "hstateen2h", hstateen, read_hstateenh, + write_hstateenh, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_HSTATEEN3] =3D { "hstateen3", hstateen, read_hstateen, write_hsta= teen, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_HSTATEEN3H] =3D { "hstateen3h", hstateen, read_hstateenh, + write_hstateenh, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + + [CSR_SSTATEEN0] =3D { "sstateen0", sstateen, read_sstateen, write_ssta= teen, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_SSTATEEN1] =3D { "sstateen1", sstateen, read_sstateen, write_ssta= teen, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_SSTATEEN2] =3D { "sstateen2", sstateen, read_sstateen, write_ssta= teen, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_SSTATEEN3] =3D { "sstateen3", sstateen, read_sstateen, write_ssta= teen, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, /* Supervisor Trap Setup */ [CSR_SSTATUS] =3D { "sstatus", smode, read_sstatus, write_sst= atus, NULL, read_sstatus_i128 = }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index aa968dc29c..e376f82ca0 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -232,6 +232,26 @@ static int riscv_cpu_post_load(void *opaque, int versi= on_id) return 0; } =20 +static bool smstateen_needed(void *opaque) +{ + RISCVCPU *cpu =3D opaque; + + return cpu->cfg.ext_smstateen; +} + +static const VMStateDescription vmstate_smstateen =3D { + .name =3D "cpu/smtateen", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D smstateen_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64_ARRAY(env.mstateen, RISCVCPU, 4), + VMSTATE_UINT64_ARRAY(env.hstateen, RISCVCPU, 4), + VMSTATE_UINT64_ARRAY(env.sstateen, RISCVCPU, 4), + VMSTATE_END_OF_LIST() + } +}; + static bool envcfg_needed(void *opaque) { RISCVCPU *cpu =3D opaque; @@ -331,7 +351,6 @@ const VMStateDescription vmstate_riscv_cpu =3D { VMSTATE_UINT64(env.mtohost, RISCVCPU), VMSTATE_UINT64(env.mtimecmp, RISCVCPU), VMSTATE_UINT64(env.stimecmp, RISCVCPU), - VMSTATE_END_OF_LIST() }, .subsections =3D (const VMStateDescription * []) { @@ -342,6 +361,7 @@ const VMStateDescription vmstate_riscv_cpu =3D { &vmstate_rv128, &vmstate_kvmtimer, &vmstate_envcfg, + &vmstate_smstateen, NULL } }; --=20 2.17.1 From nobody Sat Sep 21 00:49:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1647956636; cv=none; d=zohomail.com; s=zohoarc; b=aKKEppkLToGCozI/aYYyo/b4yNIKB6uN5/P7z5hKopCK0c7vtZNULRtTuC/pTG3D/6CApKggylhTbdL1OFOTvnOXRAnZM+rZvcpUI+9G44ne6lUUFJmJACKqt48c5UjSbAWd8Gn/WfT1Nhop8QKlsjwLhLaj7eW0/TQZ2kez9QE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1647956636; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=kg/pKk30mbUxRLPDjKNWTsH4zz7r/mNxr+90O8Y2D9k=; b=SROgtLwQm8XEQHzTdUlnJg05URfudwq0P+kCnI9NoIv0xiwfLpWoCImJCO7GAQ7jJSZjkdL9JV20lyEGp9sLtj8ej32kK6GgW4huU8hAIxYh4XcDVBcQgGABvqw+YBf63urFICx3CgzDFcmEL+Eiaq+n9iL9rxByBp03Re/zD8Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1647956636816108.64694266300603; Tue, 22 Mar 2022 06:43:56 -0700 (PDT) Received: from localhost ([::1]:38460 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nWenj-0000Ew-Jv for importer@patchew.org; Tue, 22 Mar 2022 09:43:55 -0400 Received: from eggs.gnu.org ([209.51.188.92]:32870) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nWemY-0006qR-Ms for qemu-devel@nongnu.org; Tue, 22 Mar 2022 09:42:42 -0400 Received: from [2607:f8b0:4864:20::102e] (port=50909 helo=mail-pj1-x102e.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nWemU-0006ir-BA for qemu-devel@nongnu.org; Tue, 22 Mar 2022 09:42:39 -0400 Received: by mail-pj1-x102e.google.com with SMTP id m22so15729369pja.0 for ; Tue, 22 Mar 2022 06:42:37 -0700 (PDT) Received: from ThinkPad-T490.dc1.ventanamicro.com ([171.50.204.174]) by smtp.googlemail.com with ESMTPSA id ij17-20020a17090af81100b001c67c964d93sm3101216pjb.2.2022.03.22.06.42.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Mar 2022 06:42:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=kg/pKk30mbUxRLPDjKNWTsH4zz7r/mNxr+90O8Y2D9k=; b=ZhVm4Svo9Q9GA/y8NefPxJEqSXyNlCfJireDjAqSxGpiY39tlUjkXN6Y31Lb+eOb2/ O64zPD6tF82nRMiXxDmsgHZGjmUp/hNK+TQS8LIkQyQWjDHt06zNmlojHCKEEKReNVMi BKde+4IXPA7C4igE8VjdSN9E9zp4xONXUGyDdMVvS8fvvrsdOdC1p/vBP2XOGPBh3h9w fTrxG6FBCm7n2lSpz8ipwc7EeOwJCDQWZlkXwKI4o23xGTouAL3EbtcLwEQq0+R5bamb +dXzVt8hIMjdeCfz/46a2JftKU+TFRf5W7OhTv/MKy75FDiob8v9+tnPzM7BmAIV4kwd Wyvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=kg/pKk30mbUxRLPDjKNWTsH4zz7r/mNxr+90O8Y2D9k=; b=FFEXWgFoZ1XuzdKiFmifhLT9frk04d3Ru9pM+JI+eT0bkq4nxLZ/gf3mP9s2Mbxw0B 75Q4RWB8glZcK7F1K/vs4P7DgDNc8tYTixp/CQjkVNUSRWfV8ewVzqHZo5a16c8oAYtr np7aoI1NMn1sBl5TGI0+SmWsIvzKg0IBCWpRDX1NHiAVaf7v3h0RkG0H8J+iXCSz8VTP ukCeTHKwmsgx8119/MXndFXyFviWwwNvaXR0wlJYgCh+twhAsp5kfdHqgSd8GiKQ6sfr n2i7L2GqjBYi/ZuR11zpDJsnnxVJjnHCh3GMmIM0Fkaf4/t/Tjkw2IU4SMigZaqYueNO bBbw== X-Gm-Message-State: AOAM531NtuEuwPM2sZ7raLPDBn4C/reznrLcdJv/DRh1V5Y3umcEhrdE nuPYfLfXiOX9Qir9KUKXnCFcaA== X-Google-Smtp-Source: ABdhPJz92ohAFboe9dINHklh8iodg87zcl2ex0KQWYUhnxEqHfr01mHC4oj1OkGHlHtGAr1zfxWkWQ== X-Received: by 2002:a17:90a:4214:b0:1bf:6ae9:f62a with SMTP id o20-20020a17090a421400b001bf6ae9f62amr5140698pjg.64.1647956556974; Tue, 22 Mar 2022 06:42:36 -0700 (PDT) From: Mayuresh Chitale To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [RFC PATCH v1 2/4] target/riscv: smstateen check for h/senvcfg Date: Tue, 22 Mar 2022 19:12:16 +0530 Message-Id: <20220322134218.27322-3-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220322134218.27322-1-mchitale@ventanamicro.com> References: <20220322134218.27322-1-mchitale@ventanamicro.com> X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102e (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=mchitale@ventanamicro.com; helo=mail-pj1-x102e.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mayuresh Chitale , alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1647956637725100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Accesses to henvcfg, henvcfgh and senvcfg are allowed only if corresponding bit in mstateen0/hstateen0 is enabled. Otherwise an illegal instruction trap is generated. Signed-off-by: Mayuresh Chitale --- target/riscv/csr.c | 70 ++++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 68 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 215c8ecef1..46761a6fa8 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -39,6 +39,35 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *= ops) } =20 /* Predicates */ +static RISCVException smstateen_acc_ok(CPURISCVState *env, int mode, int b= it) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + bool virt =3D riscv_cpu_virt_enabled(env); + + if (!cpu->cfg.ext_smstateen) { + return RISCV_EXCP_NONE; + } + + if (!(env->mstateen[0] & 1UL << bit)) { + return RISCV_EXCP_ILLEGAL_INST; + } + + if (virt) { + if (!(env->hstateen[0] & 1UL << bit)) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + } + + if (mode =3D=3D PRV_U) { + if (!(env->sstateen[0] & 1UL << bit)) { + return RISCV_EXCP_ILLEGAL_INST; + } + } + + return RISCV_EXCP_NONE; +} + static RISCVException fs(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) @@ -1865,6 +1894,13 @@ static RISCVException write_menvcfgh(CPURISCVState *= env, int csrno, static RISCVException read_senvcfg(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + ret =3D smstateen_acc_ok(env, PRV_S, SMSTATEEN0_HSENVCFG); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + *val =3D env->senvcfg; return RISCV_EXCP_NONE; } @@ -1873,15 +1909,27 @@ static RISCVException write_senvcfg(CPURISCVState *= env, int csrno, target_ulong val) { uint64_t mask =3D SENVCFG_FIOM | SENVCFG_CBIE | SENVCFG_CBCFE | SENVCF= G_CBZE; + RISCVException ret; =20 - env->senvcfg =3D (env->senvcfg & ~mask) | (val & mask); + ret =3D smstateen_acc_ok(env, PRV_S, SMSTATEEN0_HSENVCFG); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } =20 + env->senvcfg =3D (env->senvcfg & ~mask) | (val & mask); return RISCV_EXCP_NONE; } =20 static RISCVException read_henvcfg(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + ret =3D smstateen_acc_ok(env, PRV_S, SMSTATEEN0_HSENVCFG); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + *val =3D env->henvcfg; return RISCV_EXCP_NONE; } @@ -1890,6 +1938,12 @@ static RISCVException write_henvcfg(CPURISCVState *e= nv, int csrno, target_ulong val) { uint64_t mask =3D HENVCFG_FIOM | HENVCFG_CBIE | HENVCFG_CBCFE | HENVCF= G_CBZE; + RISCVException ret; + + ret =3D smstateen_acc_ok(env, PRV_S, SMSTATEEN0_HSENVCFG); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } =20 if (riscv_cpu_mxl(env) =3D=3D MXL_RV64) { mask |=3D HENVCFG_PBMTE | HENVCFG_STCE; @@ -1903,6 +1957,13 @@ static RISCVException write_henvcfg(CPURISCVState *e= nv, int csrno, static RISCVException read_henvcfgh(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + ret =3D smstateen_acc_ok(env, PRV_S, SMSTATEEN0_HSENVCFG); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + *val =3D env->henvcfg >> 32; return RISCV_EXCP_NONE; } @@ -1912,9 +1973,14 @@ static RISCVException write_henvcfgh(CPURISCVState *= env, int csrno, { uint64_t mask =3D HENVCFG_PBMTE | HENVCFG_STCE; uint64_t valh =3D (uint64_t)val << 32; + RISCVException ret; =20 - env->henvcfg =3D (env->henvcfg & ~mask) | (valh & mask); + ret =3D smstateen_acc_ok(env, PRV_S, SMSTATEEN0_HSENVCFG); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } =20 + env->henvcfg =3D (env->henvcfg & ~mask) | (valh & mask); return RISCV_EXCP_NONE; } =20 --=20 2.17.1 From nobody Sat Sep 21 00:49:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1647956788; cv=none; d=zohomail.com; s=zohoarc; b=Adv/mRFepZh52QHKtX6sPF4uBBhxjj57/zxHzjq80kByyd/QkhC4ESJQuIWNsbzB85u8YBDMApCB6BJk7tFXIYCb4TLAY1HSR+SonV1miONIDZjO2zpwUxfuUGHIG7mmJsSz0czka/XGA6VRo4GBUb/hwYSZZD/U/bvYnBgpFtg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1647956788; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=21r0MTqTy6EW9WiBP4H36YUfZKCd0c+Ilx4FpjjR+bM=; b=BOdGbT+MMndNZ/tLDAhrsATM1/KoQAmK1wzG/Dlfkdm2cyxudre/2v4o34fprGpQBuWin3uRwidisLL/vK1R1DaMolnek2q1iCnPCj5k0LFSAtW0O77PZpTDf6QM8CgwqHR9/vN0gRCikLtsUnqGKiXGbPuqJLMpu993Sp7LjRU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1647956788080942.2416723852722; Tue, 22 Mar 2022 06:46:28 -0700 (PDT) Received: from localhost ([::1]:43338 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nWeqA-0003r3-NJ for importer@patchew.org; Tue, 22 Mar 2022 09:46:26 -0400 Received: from eggs.gnu.org ([209.51.188.92]:32906) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nWemZ-0006tC-SC for qemu-devel@nongnu.org; Tue, 22 Mar 2022 09:42:43 -0400 Received: from [2607:f8b0:4864:20::42f] (port=35624 helo=mail-pf1-x42f.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nWemY-0006jG-Cj for qemu-devel@nongnu.org; Tue, 22 Mar 2022 09:42:43 -0400 Received: by mail-pf1-x42f.google.com with SMTP id a5so18231648pfv.2 for ; Tue, 22 Mar 2022 06:42:41 -0700 (PDT) Received: from ThinkPad-T490.dc1.ventanamicro.com ([171.50.204.174]) by smtp.googlemail.com with ESMTPSA id ij17-20020a17090af81100b001c67c964d93sm3101216pjb.2.2022.03.22.06.42.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Mar 2022 06:42:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=21r0MTqTy6EW9WiBP4H36YUfZKCd0c+Ilx4FpjjR+bM=; b=LsZYHay1vLbAR8SI2Rj30PnLUa5jxVmhbxElnE/aUzv48U1Alku4cQgNoTo6NZChx8 Dl97ofpfL51ozRW8JVHy5pjGfDhFpff6/dyLJcpWO/mD19tIkWtrVXOVZtVU/PCPOtqo I0cqJC7sMPkdxD04/on/69s0ZdHAy42i47V5gp7m5yfVPyxsCEniEN0wQed1gRmVucb5 3IumG7L3If3btIF9W7geN3QDj2IWz7T3YlrCsD6a0Cje2A5pOKJeInX0t5GM4J2Q4vV3 CEEHze0X8NTbz8w7rc1pGJfr7jrTTF6SV3Z7NOmzQQpDpzkblIrWijsDFPFTOp2Qxy58 GVdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=21r0MTqTy6EW9WiBP4H36YUfZKCd0c+Ilx4FpjjR+bM=; b=ID8QKCeDrPnlTYRfbM9QjfxkoRgn+O8PNmdnL2MpE9u0EGkYPRiX2FUwfI2Dtu5ygt V43hKk97rJJ9t2B4uW8sqc4mtGHBnm1bisp2n2QmptmpO0a40L2RFiUVfpZy/lHJTWSb 7/0CY0s0wVSJ+LlrJCMiC75MlVsA6UyKAtWBX4VJVJTEzUVCNyuZKgh/6gBMLnxAu2Db F/9b0RbQ5Et2cooL854ggHOtln06M2hPROl5FFAz+dcRFkktNI4lt/185jJhi5Tqiuxz PVoN0HhxZLqTMasMkKJxnC31znZplq/H/6UejYT8dFSoL483Bc1Uakv5kkMrU68fFEgj MFXw== X-Gm-Message-State: AOAM5327VC29suYoDtI136T1FBKUAtReW5fWXKWafzBlC5rvQVNS09f+ JGiajzcdzh5BSyun6r9+s9/BxA== X-Google-Smtp-Source: ABdhPJzIT9P54TkWxtJDLib7vJbj7Vwnsn7EDEIoVCA/8BWcbe2MnGf6bvtG+u4Xg89A5ZbUOdGB+Q== X-Received: by 2002:a05:6a00:24cd:b0:4f7:2340:a6cf with SMTP id d13-20020a056a0024cd00b004f72340a6cfmr29243438pfv.36.1647956560270; Tue, 22 Mar 2022 06:42:40 -0700 (PDT) From: Mayuresh Chitale To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [RFC PATCH v1 3/4] target/riscv: smstateen check for fcsr Date: Tue, 22 Mar 2022 19:12:17 +0530 Message-Id: <20220322134218.27322-4-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220322134218.27322-1-mchitale@ventanamicro.com> References: <20220322134218.27322-1-mchitale@ventanamicro.com> X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42f (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=mchitale@ventanamicro.com; helo=mail-pf1-x42f.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mayuresh Chitale , alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1647956790452100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" If smstateen is implemented and sstateen0.fcsr is clear then the floating point operations must return illegal instruction exception. Signed-off-by: Mayuresh Chitale --- target/riscv/csr.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 46761a6fa8..5d7381c771 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -75,6 +75,10 @@ static RISCVException fs(CPURISCVState *env, int csrno) !RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { return RISCV_EXCP_ILLEGAL_INST; } + + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { + return smstateen_acc_ok(env, PRV_U, SMSTATEEN0_FCSR); + } #endif return RISCV_EXCP_NONE; } @@ -2005,6 +2009,10 @@ static RISCVException write_mstateen(CPURISCVState *= env, int csrno, uint64_t wr_mask =3D 1UL << SMSTATEEN_STATEN; =20 reg =3D &env->mstateen[csrno - CSR_MSTATEEN0]; + if (riscv_has_ext(env, RVF)) { + wr_mask |=3D 1UL << SMSTATEEN0_FCSR; + } + write_smstateen(env, reg, wr_mask, new_val); =20 return RISCV_EXCP_NONE; @@ -2028,6 +2036,10 @@ static RISCVException write_mstateenh(CPURISCVState = *env, int csrno, reg =3D &env->mstateen[csrno - CSR_MSTATEEN0H - 0x10]; val =3D (uint64_t)new_val << 32; val |=3D *reg & 0xFFFFFFFF; + if (riscv_has_ext(env, RVF)) { + wr_mask |=3D 1UL << SMSTATEEN0_FCSR; + } + write_smstateen(env, reg, wr_mask, val); =20 return RISCV_EXCP_NONE; @@ -2048,6 +2060,10 @@ static RISCVException write_hstateen(CPURISCVState *= env, int csrno, uint64_t wr_mask =3D 1UL << SMSTATEEN_STATEN; int index =3D csrno - CSR_HSTATEEN0; =20 + if (riscv_has_ext(env, RVF)) { + wr_mask |=3D 1UL << SMSTATEEN0_FCSR; + } + reg =3D &env->hstateen[index]; wr_mask &=3D env->mstateen[index]; write_smstateen(env, reg, wr_mask, new_val); @@ -2071,6 +2087,10 @@ static RISCVException write_hstateenh(CPURISCVState = *env, int csrno, uint64_t wr_mask =3D 1UL << SMSTATEEN_STATEN; int index =3D csrno - CSR_HSTATEEN0H - 0x10; =20 + if (riscv_has_ext(env, RVF)) { + wr_mask |=3D 1UL << SMSTATEEN0_FCSR; + } + reg =3D &env->hstateen[index]; val =3D (uint64_t)new_val << 32; val |=3D *reg & 0xFFFFFFFF; @@ -2096,6 +2116,10 @@ static RISCVException write_sstateen(CPURISCVState *= env, int csrno, int index =3D csrno - CSR_SSTATEEN0; bool virt =3D riscv_cpu_virt_enabled(env); =20 + if (riscv_has_ext(env, RVF)) { + wr_mask |=3D 1UL << SMSTATEEN0_FCSR; + } + reg =3D &env->sstateen[index]; if (virt) { wr_mask &=3D env->mstateen[index]; --=20 2.17.1 From nobody Sat Sep 21 00:49:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1647956920; cv=none; d=zohomail.com; s=zohoarc; b=C7G19nPUC8rIRnp+rGRYfGkYlHCPqMesXTjGp+XtiYh2iGLR5pgsHOYjpamCrkYbmPLWt9lbcz3hnKZ/nmwPmb0eXBJUqtAevRSmrQ9sfzNKQBFP/SlXhFrDbgFdlkG8isclFNJ2jin58lGX+j9FbQlzCe2GiYUfvS6WlFH8e1k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1647956920; h=Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:Message-ID:References:Sender:Subject:To; bh=wxiIghJm5dJyInlDoprjUmYOyP4DOAeg2GYrGLIcT6s=; b=HeDSYXvlez9K9DMT5w8wrcrkh66dKLmdW0lFvv3dDnBxySQmv898/55Ku0o6ALbOE/zv5zNjX+D+JVyzdmRM3Z2uD7huNdDIrpPtrjnYKNysdX8AGH5HG+NS1ZWaXi9iRWrF/Zarf57isu/oNzgs+OJYEbX3ilm+IxVRW2ZKXoE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1647956920371683.9019079603385; Tue, 22 Mar 2022 06:48:40 -0700 (PDT) Received: from localhost ([::1]:48596 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nWesI-0007UT-SL for importer@patchew.org; Tue, 22 Mar 2022 09:48:38 -0400 Received: from eggs.gnu.org ([209.51.188.92]:32950) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nWemc-0006xg-Rv for qemu-devel@nongnu.org; Tue, 22 Mar 2022 09:42:47 -0400 Received: from [2607:f8b0:4864:20::531] (port=40572 helo=mail-pg1-x531.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nWema-0006k6-Oj for qemu-devel@nongnu.org; Tue, 22 Mar 2022 09:42:46 -0400 Received: by mail-pg1-x531.google.com with SMTP id w21so8964830pgm.7 for ; Tue, 22 Mar 2022 06:42:44 -0700 (PDT) Received: from ThinkPad-T490.dc1.ventanamicro.com ([171.50.204.174]) by smtp.googlemail.com with ESMTPSA id ij17-20020a17090af81100b001c67c964d93sm3101216pjb.2.2022.03.22.06.42.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Mar 2022 06:42:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=wxiIghJm5dJyInlDoprjUmYOyP4DOAeg2GYrGLIcT6s=; b=ah3/XRRbEqjd6Gx4jDcS2ZCE/ri7kJyKBnLCEeFWOScyEuyNA17v3E4ejk+76y1vzm WdYQJqB/hpCh/GlRGIPRMwzVGNmi57zv60urNOjtUNKAv8rBUrVtc3zNvDOy7p7fNR6b rwzjbwnlxqeyEFdlaepU07GFL2+PfnmQqRfpoEVrNq7gDZGVPaej2Zw4tIgC//x7Faji 5hKNOawi1/JV+ipGbtDFwZ+5v7vl0JEl1iaCarli3ha8SgoxFLwHH8L+Bn6Tr0xBZd8q VG8dUmiAukiIkbndlqgJLn+refaKyxLXX15vEoO72Dj0LbiYaSADrwCTN/kC3/8b4WaA Vjcw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=wxiIghJm5dJyInlDoprjUmYOyP4DOAeg2GYrGLIcT6s=; b=UIHSgyE1fvs51+evTGV+oTZwQSHP/SPKGzrdzx09OPNtpRjCOpGdU9FGXkr9JyPNw/ uu779aITb2ytqE3KU9/gGNmOUWj6NKNB64t8wMBAyCSzHLOVnyThp+knt7H26K85q1pH a0Uf5/b55nFnYcS7PT+jipYHaN1ApO5aocCppNITpuovZiiLn1zBiGFUnjHoSXy8lyJa fRzcT7TIVNGlcwgadpa7ds9MVcebF2CYK3nasH8HD4UjJA08ZKH50phijqczPk+d62Fv nHr1Gp5YZk2bh131DRYl/9KP21Fa79wwLRR3J6R1QUPxJqQDugcoVKZmmYHTSiAIgaNc ndxA== X-Gm-Message-State: AOAM533hn6oTeZIM3CBgyvvd7LxD14g1S/rTxKJNCZuDrUHh4plVBKfY f44+tj4zwn7/UrsMmOOdnS5JhjegrS2oNPqD X-Google-Smtp-Source: ABdhPJwHsdSAYnVrGJjwSRCrkcZ6uSaE54EIYkDf/wH8QdoJ4NONvthh9C4MEc1n72LKROyH3yqMCw== X-Received: by 2002:a05:6a00:2290:b0:4fa:a99e:2e21 with SMTP id f16-20020a056a00229000b004faa99e2e21mr7741527pfe.20.1647956563392; Tue, 22 Mar 2022 06:42:43 -0700 (PDT) From: Mayuresh Chitale To: qemu-riscv@nongnu.org, qemu-devel@nongnu.org Subject: [RFC PATCH v1 4/4] target/riscv: smstateen check for AIA/IMSIC Date: Tue, 22 Mar 2022 19:12:18 +0530 Message-Id: <20220322134218.27322-5-mchitale@ventanamicro.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220322134218.27322-1-mchitale@ventanamicro.com> References: <20220322134218.27322-1-mchitale@ventanamicro.com> X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::531 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=mchitale@ventanamicro.com; helo=mail-pg1-x531.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mayuresh Chitale , alistair.francis@wdc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1647956921976100001 Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" If smstateen is implemented then accesses to AIA registers CSRS, IMSIC CSRs and other IMSIC registers is controlled by setting of corresponding bits in mstateen/hstateen registers. Otherwise an illegal instruction trap or virtual instruction trap is generated. Signed-off-by: Mayuresh Chitale --- target/riscv/csr.c | 248 ++++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 246 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 5d7381c771..a8e17e4fe5 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -68,6 +68,53 @@ static RISCVException smstateen_acc_ok(CPURISCVState *en= v, int mode, int bit) return RISCV_EXCP_NONE; } =20 +static RISCVException smstateen_aia_acc_ok(CPURISCVState *env, int csrno) +{ + int bit, mode; + + switch (csrno) { + case CSR_SSETEIPNUM: + case CSR_SCLREIPNUM: + case CSR_SSETEIENUM: + case CSR_SCLREIENUM: + case CSR_STOPEI: + case CSR_VSSETEIPNUM: + case CSR_VSCLREIPNUM: + case CSR_VSSETEIENUM: + case CSR_VSCLREIENUM: + case CSR_VSTOPEI: + case CSR_HSTATUS: + mode =3D PRV_S; + bit =3D SMSTATEEN0_IMSIC; + break; + + case CSR_SIEH: + case CSR_SIPH: + case CSR_HVIPH: + case CSR_HVICTL: + case CSR_HVIPRIO1: + case CSR_HVIPRIO2: + case CSR_HVIPRIO1H: + case CSR_HVIPRIO2H: + case CSR_VSIEH: + case CSR_VSIPH: + mode =3D PRV_S; + bit =3D SMSTATEEN0_AIA; + break; + + case CSR_SISELECT: + case CSR_VSISELECT: + mode =3D PRV_S; + bit =3D SMSTATEEN0_SVSLCT; + break; + + default: + return RISCV_EXCP_NONE; + } + + return smstateen_acc_ok(env, mode, bit); +} + static RISCVException fs(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) @@ -1402,6 +1449,13 @@ static int rmw_xiselect(CPURISCVState *env, int csrn= o, target_ulong *val, target_ulong new_val, target_ulong wr_mask) { target_ulong *iselect; + RISCVException ret; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } =20 /* Translate CSR number for VS-mode */ csrno =3D aia_xlate_vs_csrno(env, csrno); @@ -1484,7 +1538,9 @@ static int rmw_xireg(CPURISCVState *env, int csrno, t= arget_ulong *val, bool virt; uint8_t *iprio; int ret =3D -EINVAL; - target_ulong priv, isel, vgein; + target_ulong priv, isel, vgein =3D 0; + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); =20 /* Translate CSR number for VS-mode */ csrno =3D aia_xlate_vs_csrno(env, csrno); @@ -1513,11 +1569,20 @@ static int rmw_xireg(CPURISCVState *env, int csrno,= target_ulong *val, }; =20 /* Find the selected guest interrupt file */ - vgein =3D (virt) ? get_field(env->hstatus, HSTATUS_VGEIN) : 0; + if (virt) { + if (!cpu->cfg.ext_smstateen || + (env->hstateen[0] & 1UL << SMSTATEEN0_IMSIC)) { + vgein =3D get_field(env->hstatus, HSTATUS_VGEIN); + } + } =20 if (ISELECT_IPRIO0 <=3D isel && isel <=3D ISELECT_IPRIO15) { /* Local interrupt priority registers not available for VS-mode */ if (!virt) { + if (priv =3D=3D PRV_S && cpu->cfg.ext_smstateen && + !(env->hstateen[0] & 1UL << SMSTATEEN0_AIA)) { + goto done; + } ret =3D rmw_iprio(riscv_cpu_mxl_bits(env), isel, iprio, val, new_val, wr_mask, (priv =3D=3D PRV_M) ? IRQ_M_EXT : IRQ_S_EXT); @@ -1551,6 +1616,13 @@ static int rmw_xsetclreinum(CPURISCVState *env, int = csrno, target_ulong *val, int ret =3D -EINVAL; bool set, pend, virt; target_ulong priv, isel, vgein, xlen, nval, wmask; + RISCVException excp; + + /* Check if smstateen is enabled and this access is allowed */ + excp =3D smstateen_aia_acc_ok(env, csrno); + if (excp !=3D RISCV_EXCP_NONE) { + return excp; + } =20 /* Translate CSR number for VS-mode */ csrno =3D aia_xlate_vs_csrno(env, csrno); @@ -1669,6 +1741,13 @@ static int rmw_xtopei(CPURISCVState *env, int csrno,= target_ulong *val, bool virt; int ret =3D -EINVAL; target_ulong priv, vgein; + RISCVException excp; + + /* Check if smstateen is enabled and this access is allowed */ + excp =3D smstateen_aia_acc_ok(env, csrno); + if (excp !=3D RISCV_EXCP_NONE) { + return excp; + } =20 /* Translate CSR number for VS-mode */ csrno =3D aia_xlate_vs_csrno(env, csrno); @@ -2013,6 +2092,12 @@ static RISCVException write_mstateen(CPURISCVState *= env, int csrno, wr_mask |=3D 1UL << SMSTATEEN0_FCSR; } =20 + if (riscv_feature(env, RISCV_FEATURE_AIA)) { + wr_mask |=3D (1UL << SMSTATEEN0_IMSIC) + | (1UL << SMSTATEEN0_AIA) + | (1UL << SMSTATEEN0_SVSLCT); + } + write_smstateen(env, reg, wr_mask, new_val); =20 return RISCV_EXCP_NONE; @@ -2040,6 +2125,12 @@ static RISCVException write_mstateenh(CPURISCVState = *env, int csrno, wr_mask |=3D 1UL << SMSTATEEN0_FCSR; } =20 + if (riscv_feature(env, RISCV_FEATURE_AIA)) { + wr_mask |=3D (1UL << SMSTATEEN0_IMSIC) + | (1UL << SMSTATEEN0_AIA) + | (1UL << SMSTATEEN0_SVSLCT); + } + write_smstateen(env, reg, wr_mask, val); =20 return RISCV_EXCP_NONE; @@ -2064,6 +2155,12 @@ static RISCVException write_hstateen(CPURISCVState *= env, int csrno, wr_mask |=3D 1UL << SMSTATEEN0_FCSR; } =20 + if (riscv_feature(env, RISCV_FEATURE_AIA)) { + wr_mask |=3D (1UL << SMSTATEEN0_IMSIC) + | (1UL << SMSTATEEN0_AIA) + | (1UL << SMSTATEEN0_SVSLCT); + } + reg =3D &env->hstateen[index]; wr_mask &=3D env->mstateen[index]; write_smstateen(env, reg, wr_mask, new_val); @@ -2091,6 +2188,12 @@ static RISCVException write_hstateenh(CPURISCVState = *env, int csrno, wr_mask |=3D 1UL << SMSTATEEN0_FCSR; } =20 + if (riscv_feature(env, RISCV_FEATURE_AIA)) { + wr_mask |=3D (1UL << SMSTATEEN0_IMSIC) + | (1UL << SMSTATEEN0_AIA) + | (1UL << SMSTATEEN0_SVSLCT); + } + reg =3D &env->hstateen[index]; val =3D (uint64_t)new_val << 32; val |=3D *reg & 0xFFFFFFFF; @@ -2284,6 +2387,12 @@ static RISCVException rmw_vsieh(CPURISCVState *env, = int csrno, uint64_t rval; RISCVException ret; =20 + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + ret =3D rmw_vsie64(env, csrno, &rval, ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); if (ret_val) { @@ -2338,6 +2447,12 @@ static RISCVException rmw_sieh(CPURISCVState *env, i= nt csrno, uint64_t rval; RISCVException ret; =20 + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + ret =3D rmw_sie64(env, csrno, &rval, ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); if (ret_val) { @@ -2500,6 +2615,12 @@ static RISCVException rmw_vsiph(CPURISCVState *env, = int csrno, uint64_t rval; RISCVException ret; =20 + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + ret =3D rmw_vsip64(env, csrno, &rval, ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); if (ret_val) { @@ -2554,6 +2675,12 @@ static RISCVException rmw_siph(CPURISCVState *env, i= nt csrno, uint64_t rval; RISCVException ret; =20 + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + ret =3D rmw_sip64(env, csrno, &rval, ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); if (ret_val) { @@ -2744,6 +2871,10 @@ static RISCVException read_hstatus(CPURISCVState *en= v, int csrno, static RISCVException write_hstatus(CPURISCVState *env, int csrno, target_ulong val) { + if (smstateen_aia_acc_ok(env, csrno) !=3D RISCV_EXCP_NONE) { + val &=3D ~HSTATUS_VGEIN; + } + env->hstatus =3D val; if (riscv_cpu_mxl(env) !=3D MXL_RV32 && get_field(val, HSTATUS_VSXL) != =3D 2) { qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN optio= ns."); @@ -2804,6 +2935,12 @@ static RISCVException rmw_hidelegh(CPURISCVState *en= v, int csrno, uint64_t rval; RISCVException ret; =20 + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + ret =3D rmw_hideleg64(env, csrno, &rval, ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); if (ret_val) { @@ -2850,6 +2987,12 @@ static RISCVException rmw_hviph(CPURISCVState *env, = int csrno, uint64_t rval; RISCVException ret; =20 + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + ret =3D rmw_hvip64(env, csrno, &rval, ((uint64_t)new_val) << 32, ((uint64_t)wr_mask) << 32); if (ret_val) { @@ -2904,6 +3047,13 @@ static RISCVException write_hcounteren(CPURISCVState= *env, int csrno, static RISCVException read_hgeie(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + ret =3D smstateen_acc_ok(env, PRV_S, SMSTATEEN0_IMSIC); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + if (val) { *val =3D env->hgeie; } @@ -2913,6 +3063,13 @@ static RISCVException read_hgeie(CPURISCVState *env,= int csrno, static RISCVException write_hgeie(CPURISCVState *env, int csrno, target_ulong val) { + RISCVException ret; + + ret =3D smstateen_acc_ok(env, PRV_S, SMSTATEEN0_IMSIC); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + /* Only GEILEN:1 bits implemented and BIT0 is never implemented */ val &=3D ((((target_ulong)1) << env->geilen) - 1) << 1; env->hgeie =3D val; @@ -2952,6 +3109,13 @@ static RISCVException write_htinst(CPURISCVState *en= v, int csrno, static RISCVException read_hgeip(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + ret =3D smstateen_acc_ok(env, PRV_S, SMSTATEEN0_IMSIC); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + if (val) { *val =3D env->hgeip; } @@ -3022,12 +3186,28 @@ static RISCVException write_htimedeltah(CPURISCVSta= te *env, int csrno, =20 static int read_hvictl(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + *val =3D env->hvictl; return RISCV_EXCP_NONE; } =20 static int write_hvictl(CPURISCVState *env, int csrno, target_ulong val) { + RISCVException ret =3D RISCV_EXCP_NONE; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + env->hvictl =3D val & HVICTL_VALID_MASK; return RISCV_EXCP_NONE; } @@ -3086,41 +3266,105 @@ static int write_hvipriox(CPURISCVState *env, int = first_index, =20 static int read_hviprio1(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + return read_hvipriox(env, 0, env->hviprio, val); } =20 static int write_hviprio1(CPURISCVState *env, int csrno, target_ulong val) { + RISCVException ret; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + return write_hvipriox(env, 0, env->hviprio, val); } =20 static int read_hviprio1h(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + return read_hvipriox(env, 4, env->hviprio, val); } =20 static int write_hviprio1h(CPURISCVState *env, int csrno, target_ulong val) { + RISCVException ret; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + return write_hvipriox(env, 4, env->hviprio, val); } =20 static int read_hviprio2(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + return read_hvipriox(env, 8, env->hviprio, val); } =20 static int write_hviprio2(CPURISCVState *env, int csrno, target_ulong val) { + RISCVException ret; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + return write_hvipriox(env, 8, env->hviprio, val); } =20 static int read_hviprio2h(CPURISCVState *env, int csrno, target_ulong *val) { + RISCVException ret; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + return read_hvipriox(env, 12, env->hviprio, val); } =20 static int write_hviprio2h(CPURISCVState *env, int csrno, target_ulong val) { + RISCVException ret; + + /* Check if smstateen is enabled and this access is allowed */ + ret =3D smstateen_aia_acc_ok(env, csrno); + if (ret !=3D RISCV_EXCP_NONE) { + return ret; + } + return write_hvipriox(env, 12, env->hviprio, val); } =20 --=20 2.17.1