From nobody Sat Feb 7 07:11:24 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=redhat.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1647842617063686.3692208544539; Sun, 20 Mar 2022 23:03:37 -0700 (PDT) Received: from localhost ([::1]:47152 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nWB8h-0003rX-I9 for importer@patchew.org; Mon, 21 Mar 2022 02:03:35 -0400 Received: from eggs.gnu.org ([209.51.188.92]:42202) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nWB0J-0005Z7-B3 for qemu-devel@nongnu.org; Mon, 21 Mar 2022 01:54:56 -0400 Received: from us-smtp-delivery-124.mimecast.com ([170.10.133.124]:48372) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nWB0G-0005BS-1C for qemu-devel@nongnu.org; Mon, 21 Mar 2022 01:54:54 -0400 Received: from mimecast-mx02.redhat.com (mx3-rdu2.redhat.com [66.187.233.73]) by relay.mimecast.com with ESMTP with STARTTLS (version=TLSv1.2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id us-mta-402-4MWGjLlmPE6fUQp41H_dHA-1; Mon, 21 Mar 2022 01:54:41 -0400 Received: from smtp.corp.redhat.com (int-mx09.intmail.prod.int.rdu2.redhat.com [10.11.54.9]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mimecast-mx02.redhat.com (Postfix) with ESMTPS id 929B43811A20; Mon, 21 Mar 2022 05:54:41 +0000 (UTC) Received: from localhost.localdomain (ovpn-14-31.pek2.redhat.com [10.72.14.31]) by smtp.corp.redhat.com (Postfix) with ESMTP id DB8AB43248C; Mon, 21 Mar 2022 05:54:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=redhat.com; s=mimecast20190719; t=1647842085; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version:content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=nuQKGyXktdABV9piwLvU0lugbayOgI4dN/3b4EP6n2I=; b=GIHcxJbRH/lf3etiopSjzstCw8JLIJio59m42Yi8Aci6lTjkVLkkAZRObmN29s37aaWy8l 2hMmqAB3WWPcq48vKFyRQDmSoQrxETI3tsSeatWcCjUR/IjUtu/c09a3WBxSdSeCe7iVtZ lM2S8NsltxAlSLXYgAy76P4Hf9tM3mw= X-MC-Unique: 4MWGjLlmPE6fUQp41H_dHA-1 From: Jason Wang To: mst@redhat.com, peterx@redhat.com Subject: [PATCH V2 2/4] intel-iommu: drop VTDBus Date: Mon, 21 Mar 2022 13:54:27 +0800 Message-Id: <20220321055429.10260-3-jasowang@redhat.com> In-Reply-To: <20220321055429.10260-1-jasowang@redhat.com> References: <20220321055429.10260-1-jasowang@redhat.com> MIME-Version: 1.0 X-Scanned-By: MIMEDefang 2.85 on 10.11.54.9 Authentication-Results: relay.mimecast.com; auth=pass smtp.auth=CUSA124A263 smtp.mailfrom=jasowang@redhat.com X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=170.10.133.124; envelope-from=jasowang@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jason Wang , yi.l.liu@intel.com, yi.y.sun@linux.intel.com, qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1647842617606100001 Content-Type: text/plain; charset="utf-8" We introduce VTDBus structure as an intermediate step for searching the address space. This works well with SID based matching/lookup. But when we want to support SID plus PASID based address space lookup, this intermediate steps turns out to be a burden. So the patch simply drops the VTDBus structure and use the PCIBus and devfn as the key for the g_hash_table(). This simplifies the codes and the future PASID extension. To prevent being slower for past vtd_find_as_from_bus_num() callers, a vtd_as cache indexed by the bus number is introduced to store the last recent search result of a vtd_as belongs to a specific bus. Signed-off-by: Jason Wang Reviewed-by: Peter Xu --- hw/i386/intel_iommu.c | 238 +++++++++++++++++----------------- include/hw/i386/intel_iommu.h | 11 +- 2 files changed, 123 insertions(+), 126 deletions(-) diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 90964b201c..5851a17d0e 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -61,6 +61,16 @@ } = \ } =20 +/* + * PCI bus number (or SID) is not reliable since the device is usaully + * initalized before guest can configure the PCI bridge + * (SECONDARY_BUS_NUMBER). + */ +struct vtd_as_key { + PCIBus *bus; + uint8_t devfn; +}; + static void vtd_address_space_refresh_all(IntelIOMMUState *s); static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n); =20 @@ -210,6 +220,31 @@ static guint vtd_uint64_hash(gconstpointer v) return (guint)*(const uint64_t *)v; } =20 +static gboolean vtd_as_equal(gconstpointer v1, gconstpointer v2) +{ + const struct vtd_as_key *key1 =3D v1; + const struct vtd_as_key *key2 =3D v2; + + return (key1->bus =3D=3D key2->bus) && (key1->devfn =3D=3D key2->devfn= ); +} + +static inline uint16_t vtd_make_source_id(uint8_t bus_num, uint8_t devfn) +{ + return ((bus_num & 0xffUL) << 8) | (devfn & 0xffUL); +} + +/* + * Note that we use pointer to PCIBus as the key, so hashing/shifting + * based on the pointer value is intended. + */ +static guint vtd_as_hash(gconstpointer v) +{ + const struct vtd_as_key *key =3D v; + guint value =3D (guint)(uintptr_t)key->bus; + + return (guint)(value << 8 | key->devfn); +} + static gboolean vtd_hash_remove_by_domain(gpointer key, gpointer value, gpointer user_data) { @@ -248,22 +283,14 @@ static gboolean vtd_hash_remove_by_page(gpointer key,= gpointer value, static void vtd_reset_context_cache_locked(IntelIOMMUState *s) { VTDAddressSpace *vtd_as; - VTDBus *vtd_bus; - GHashTableIter bus_it; - uint32_t devfn_it; + GHashTableIter as_it; =20 trace_vtd_context_cache_reset(); =20 - g_hash_table_iter_init(&bus_it, s->vtd_as_by_busptr); + g_hash_table_iter_init(&as_it, s->vtd_as); =20 - while (g_hash_table_iter_next (&bus_it, NULL, (void**)&vtd_bus)) { - for (devfn_it =3D 0; devfn_it < PCI_DEVFN_MAX; ++devfn_it) { - vtd_as =3D vtd_bus->dev_as[devfn_it]; - if (!vtd_as) { - continue; - } - vtd_as->context_cache_entry.context_cache_gen =3D 0; - } + while (g_hash_table_iter_next (&as_it, NULL, (void**)&vtd_as)) { + vtd_as->context_cache_entry.context_cache_gen =3D 0; } s->context_cache_gen =3D 1; } @@ -993,32 +1020,6 @@ static bool vtd_slpte_nonzero_rsvd(uint64_t slpte, ui= nt32_t level) return slpte & rsvd_mask; } =20 -/* Find the VTD address space associated with a given bus number */ -static VTDBus *vtd_find_as_from_bus_num(IntelIOMMUState *s, uint8_t bus_nu= m) -{ - VTDBus *vtd_bus =3D s->vtd_as_by_bus_num[bus_num]; - GHashTableIter iter; - - if (vtd_bus) { - return vtd_bus; - } - - /* - * Iterate over the registered buses to find the one which - * currently holds this bus number and update the bus_num - * lookup table. - */ - g_hash_table_iter_init(&iter, s->vtd_as_by_busptr); - while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) { - if (pci_bus_num(vtd_bus->bus) =3D=3D bus_num) { - s->vtd_as_by_bus_num[bus_num] =3D vtd_bus; - return vtd_bus; - } - } - - return NULL; -} - /* Given the @iova, get relevant @slptep. @slpte_level will be the last le= vel * of the translation, can be used for deciding the size of large page. */ @@ -1634,24 +1635,13 @@ static bool vtd_switch_address_space(VTDAddressSpac= e *as) =20 static void vtd_switch_address_space_all(IntelIOMMUState *s) { + VTDAddressSpace *vtd_as; GHashTableIter iter; - VTDBus *vtd_bus; - int i; - - g_hash_table_iter_init(&iter, s->vtd_as_by_busptr); - while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_bus)) { - for (i =3D 0; i < PCI_DEVFN_MAX; i++) { - if (!vtd_bus->dev_as[i]) { - continue; - } - vtd_switch_address_space(vtd_bus->dev_as[i]); - } - } -} =20 -static inline uint16_t vtd_make_source_id(uint8_t bus_num, uint8_t devfn) -{ - return ((bus_num & 0xffUL) << 8) | (devfn & 0xffUL); + g_hash_table_iter_init(&iter, s->vtd_as); + while (g_hash_table_iter_next(&iter, NULL, (void **)&vtd_as)) { + vtd_switch_address_space(vtd_as); + } } =20 static const bool vtd_qualified_faults[] =3D { @@ -1688,18 +1678,39 @@ static inline bool vtd_is_interrupt_addr(hwaddr add= r) return VTD_INTERRUPT_ADDR_FIRST <=3D addr && addr <=3D VTD_INTERRUPT_A= DDR_LAST; } =20 +static gboolean vtd_find_as_by_sid(gpointer key, gpointer value, + gpointer user_data) +{ + struct vtd_as_key *as_key =3D (struct vtd_as_key *)key; + uint16_t target_sid =3D *(uint16_t *)user_data; + uint16_t sid =3D vtd_make_source_id(pci_bus_num(as_key->bus), + as_key->devfn); + return sid =3D=3D target_sid; +} + +static VTDAddressSpace *vtd_get_as_by_sid(IntelIOMMUState *s, uint16_t sid) +{ + uint8_t bus_num =3D sid >> 8; + VTDAddressSpace *vtd_as =3D s->vtd_as_cache[bus_num]; + + if (vtd_as && + (sid =3D=3D vtd_make_source_id(pci_bus_num(vtd_as->bus), + vtd_as->devfn))) { + return vtd_as; + } + + vtd_as =3D g_hash_table_find(s->vtd_as, vtd_find_as_by_sid, &sid); + s->vtd_as_cache[bus_num] =3D vtd_as; + + return vtd_as; +} + static void vtd_pt_enable_fast_path(IntelIOMMUState *s, uint16_t source_id) { - VTDBus *vtd_bus; VTDAddressSpace *vtd_as; bool success =3D false; =20 - vtd_bus =3D vtd_find_as_from_bus_num(s, VTD_SID_TO_BUS(source_id)); - if (!vtd_bus) { - goto out; - } - - vtd_as =3D vtd_bus->dev_as[VTD_SID_TO_DEVFN(source_id)]; + vtd_as =3D vtd_get_as_by_sid(s, source_id); if (!vtd_as) { goto out; } @@ -1907,11 +1918,10 @@ static void vtd_context_device_invalidate(IntelIOMM= UState *s, uint16_t source_id, uint16_t func_mask) { + GHashTableIter as_it; uint16_t mask; - VTDBus *vtd_bus; VTDAddressSpace *vtd_as; uint8_t bus_n, devfn; - uint16_t devfn_it; =20 trace_vtd_inv_desc_cc_devices(source_id, func_mask); =20 @@ -1934,32 +1944,31 @@ static void vtd_context_device_invalidate(IntelIOMM= UState *s, mask =3D ~mask; =20 bus_n =3D VTD_SID_TO_BUS(source_id); - vtd_bus =3D vtd_find_as_from_bus_num(s, bus_n); - if (vtd_bus) { - devfn =3D VTD_SID_TO_DEVFN(source_id); - for (devfn_it =3D 0; devfn_it < PCI_DEVFN_MAX; ++devfn_it) { - vtd_as =3D vtd_bus->dev_as[devfn_it]; - if (vtd_as && ((devfn_it & mask) =3D=3D (devfn & mask))) { - trace_vtd_inv_desc_cc_device(bus_n, VTD_PCI_SLOT(devfn_it), - VTD_PCI_FUNC(devfn_it)); - vtd_iommu_lock(s); - vtd_as->context_cache_entry.context_cache_gen =3D 0; - vtd_iommu_unlock(s); - /* - * Do switch address space when needed, in case if the - * device passthrough bit is switched. - */ - vtd_switch_address_space(vtd_as); - /* - * So a device is moving out of (or moving into) a - * domain, resync the shadow page table. - * This won't bring bad even if we have no such - * notifier registered - the IOMMU notification - * framework will skip MAP notifications if that - * happened. - */ - vtd_sync_shadow_page_table(vtd_as); - } + devfn =3D VTD_SID_TO_DEVFN(source_id); + + g_hash_table_iter_init(&as_it, s->vtd_as); + while (g_hash_table_iter_next(&as_it, NULL, (void**)&vtd_as)) { + if ((pci_bus_num(vtd_as->bus) =3D=3D bus_n) && + (vtd_as->devfn & mask) =3D=3D (devfn & mask)) { + trace_vtd_inv_desc_cc_device(bus_n, VTD_PCI_SLOT(vtd_as->devfn= ), + VTD_PCI_FUNC(vtd_as->devfn)); + vtd_iommu_lock(s); + vtd_as->context_cache_entry.context_cache_gen =3D 0; + vtd_iommu_unlock(s); + /* + * Do switch address space when needed, in case if the + * device passthrough bit is switched. + */ + vtd_switch_address_space(vtd_as); + /* + * So a device is moving out of (or moving into) a + * domain, resync the shadow page table. + * This won't bring bad even if we have no such + * notifier registered - the IOMMU notification + * framework will skip MAP notifications if that + * happened. + */ + vtd_sync_shadow_page_table(vtd_as); } } } @@ -2473,18 +2482,13 @@ static bool vtd_process_device_iotlb_desc(IntelIOMM= UState *s, { VTDAddressSpace *vtd_dev_as; IOMMUTLBEvent event; - struct VTDBus *vtd_bus; hwaddr addr; uint64_t sz; uint16_t sid; - uint8_t devfn; bool size; - uint8_t bus_num; =20 addr =3D VTD_INV_DESC_DEVICE_IOTLB_ADDR(inv_desc->hi); sid =3D VTD_INV_DESC_DEVICE_IOTLB_SID(inv_desc->lo); - devfn =3D sid & 0xff; - bus_num =3D sid >> 8; size =3D VTD_INV_DESC_DEVICE_IOTLB_SIZE(inv_desc->hi); =20 if ((inv_desc->lo & VTD_INV_DESC_DEVICE_IOTLB_RSVD_LO) || @@ -2495,12 +2499,11 @@ static bool vtd_process_device_iotlb_desc(IntelIOMM= UState *s, return false; } =20 - vtd_bus =3D vtd_find_as_from_bus_num(s, bus_num); - if (!vtd_bus) { - goto done; - } - - vtd_dev_as =3D vtd_bus->dev_as[devfn]; + /* + * Using sid is OK since the guest should have finished the + * initialization of both the bus and device. + */ + vtd_dev_as =3D vtd_get_as_by_sid(s, sid); if (!vtd_dev_as) { goto done; } @@ -3426,27 +3429,27 @@ static const MemoryRegionOps vtd_mem_ir_ops =3D { =20 VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, PCIBus *bus, int devf= n) { - uintptr_t key =3D (uintptr_t)bus; - VTDBus *vtd_bus =3D g_hash_table_lookup(s->vtd_as_by_busptr, &key); + /* + * We can't simply use sid here since the bus number might not be + * initialized by the guest. + */ + struct vtd_as_key key =3D { + .bus =3D bus, + .devfn =3D devfn, + }; VTDAddressSpace *vtd_dev_as; char name[128]; =20 - if (!vtd_bus) { - uintptr_t *new_key =3D g_malloc(sizeof(*new_key)); - *new_key =3D (uintptr_t)bus; - /* No corresponding free() */ - vtd_bus =3D g_malloc0(sizeof(VTDBus) + sizeof(VTDAddressSpace *) *= \ - PCI_DEVFN_MAX); - vtd_bus->bus =3D bus; - g_hash_table_insert(s->vtd_as_by_busptr, new_key, vtd_bus); - } + vtd_dev_as =3D g_hash_table_lookup(s->vtd_as, &key); + if (!vtd_dev_as) { + struct vtd_as_key *new_key =3D g_malloc(sizeof(*new_key)); =20 - vtd_dev_as =3D vtd_bus->dev_as[devfn]; + new_key->bus =3D bus; + new_key->devfn =3D devfn; =20 - if (!vtd_dev_as) { snprintf(name, sizeof(name), "vtd-%02x.%x", PCI_SLOT(devfn), PCI_FUNC(devfn)); - vtd_bus->dev_as[devfn] =3D vtd_dev_as =3D g_malloc0(sizeof(VTDAddr= essSpace)); + vtd_dev_as =3D g_malloc0(sizeof(VTDAddressSpace)); =20 vtd_dev_as->bus =3D bus; vtd_dev_as->devfn =3D (uint8_t)devfn; @@ -3502,6 +3505,8 @@ VTDAddressSpace *vtd_find_add_as(IntelIOMMUState *s, = PCIBus *bus, int devfn) &vtd_dev_as->nodmar, 0); =20 vtd_switch_address_space(vtd_dev_as); + + g_hash_table_insert(s->vtd_as, new_key, vtd_dev_as); } return vtd_dev_as; } @@ -3875,7 +3880,6 @@ static void vtd_realize(DeviceState *dev, Error **err= p) =20 QLIST_INIT(&s->vtd_as_with_notifiers); qemu_mutex_init(&s->iommu_lock); - memset(s->vtd_as_by_bus_num, 0, sizeof(s->vtd_as_by_bus_num)); memory_region_init_io(&s->csrmem, OBJECT(s), &vtd_mem_ops, s, "intel_iommu", DMAR_REG_SIZE); =20 @@ -3897,8 +3901,8 @@ static void vtd_realize(DeviceState *dev, Error **err= p) /* No corresponding destroy */ s->iotlb =3D g_hash_table_new_full(vtd_uint64_hash, vtd_uint64_equal, g_free, g_free); - s->vtd_as_by_busptr =3D g_hash_table_new_full(vtd_uint64_hash, vtd_uin= t64_equal, - g_free, g_free); + s->vtd_as =3D g_hash_table_new_full(vtd_as_hash, vtd_as_equal, + g_free, g_free); vtd_init(s); sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, Q35_HOST_BRIDGE_IOMMU_ADDR); pci_setup_iommu(bus, vtd_host_dma_iommu, dev); diff --git a/include/hw/i386/intel_iommu.h b/include/hw/i386/intel_iommu.h index 3b5ac869db..fa1bed353c 100644 --- a/include/hw/i386/intel_iommu.h +++ b/include/hw/i386/intel_iommu.h @@ -58,7 +58,6 @@ typedef struct VTDContextEntry VTDContextEntry; typedef struct VTDContextCacheEntry VTDContextCacheEntry; typedef struct VTDAddressSpace VTDAddressSpace; typedef struct VTDIOTLBEntry VTDIOTLBEntry; -typedef struct VTDBus VTDBus; typedef union VTD_IR_TableEntry VTD_IR_TableEntry; typedef union VTD_IR_MSIAddress VTD_IR_MSIAddress; typedef struct VTDPASIDDirEntry VTDPASIDDirEntry; @@ -111,12 +110,6 @@ struct VTDAddressSpace { IOVATree *iova_tree; /* Traces mapped IOVA ranges */ }; =20 -struct VTDBus { - PCIBus* bus; /* A reference to the bus to provide translation for */ - /* A table of VTDAddressSpace objects indexed by devfn */ - VTDAddressSpace *dev_as[]; -}; - struct VTDIOTLBEntry { uint64_t gfn; uint16_t domain_id; @@ -253,8 +246,8 @@ struct IntelIOMMUState { uint32_t context_cache_gen; /* Should be in [1,MAX] */ GHashTable *iotlb; /* IOTLB */ =20 - GHashTable *vtd_as_by_busptr; /* VTDBus objects indexed by PCIBus* r= eference */ - VTDBus *vtd_as_by_bus_num[VTD_PCI_BUS_MAX]; /* VTDBus objects indexed = by bus number */ + GHashTable *vtd_as; /* VTD address space indexed by source= id*/ + VTDAddressSpace *vtd_as_cache[VTD_PCI_BUS_MAX]; /* VTD address space c= ache */ /* list of registered notifiers */ QLIST_HEAD(, VTDAddressSpace) vtd_as_with_notifiers; =20 --=20 2.25.1