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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1647395955; x=1649987956; bh=JULuWU7jjd4v+41kv9 ixESO60ZWaWtvA4R2DIeLIsHk=; b=aW0iOks+rwYIHtq9CDbNMroI+pEl6RQR0n qb3k6IQgWTKK1G6+bhV9jXUhWoULhyFxS5f4UTWvTYw009mTlR3PT6hfN2QlajEV Vl/wkWcs5lxxjkE79BDxHkKtnjdQqZS63tUPTFRt1h6QAWYzBdZGRHrHUwOIcChU yaaw99ViOQ5wMw+cPhQTlAx+0SrmxXeXci7F2FFRGc2Z6sOmMG6Zm7CmFWn1YQPs xTayYw+3/VM0oEUAjWk8n6LfeCZ1FapkhXxRyt0auAgHPaZIMvNXUiKLBANVRrR/ fZ3YfIPn5Jd1SsFEQidSNBHhM+tnYknksC+WSX/W+Fp0g5CFzpPg== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org, qemu-riscv@nongnu.org Cc: bmeng.cn@gmail.com, Alistair Francis , Bin Meng , palmer@dabbelt.com, alistair23@gmail.com Subject: [PATCH v2 1/2] target/riscv: cpu: Fixup indentation Date: Wed, 16 Mar 2022 11:59:00 +1000 Message-Id: <20220316015901.3787779-2-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220316015901.3787779-1-alistair.francis@opensource.wdc.com> References: <20220316015901.3787779-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=0672150a7=alistair.francis@opensource.wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1647396091283100003 Content-Type: text/plain; charset="utf-8" From: Alistair Francis Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index ddda4906ff..41b757995d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -567,18 +567,18 @@ static void riscv_cpu_realize(DeviceState *dev, Error= **errp) if (cpu->cfg.ext_i && cpu->cfg.ext_e) { error_setg(errp, "I and E extensions are incompatible"); - return; - } + return; + } =20 if (!cpu->cfg.ext_i && !cpu->cfg.ext_e) { error_setg(errp, "Either I or E extension must be set"); - return; - } + return; + } =20 - if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & - cpu->cfg.ext_a & cpu->cfg.ext_f & - cpu->cfg.ext_d)) { + if (cpu->cfg.ext_g && !(cpu->cfg.ext_i & cpu->cfg.ext_m & + cpu->cfg.ext_a & cpu->cfg.ext_f & + cpu->cfg.ext_d)) { warn_report("Setting G will also set IMAFD"); cpu->cfg.ext_i =3D true; cpu->cfg.ext_m =3D true; @@ -709,11 +709,11 @@ static void riscv_cpu_set_irq(void *opaque, int irq, = int level) case IRQ_S_EXT: case IRQ_VS_EXT: case IRQ_M_EXT: - if (kvm_enabled()) { + if (kvm_enabled()) { kvm_riscv_set_irq(cpu, irq, level); - } else { + } else { riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); - } + } break; default: g_assert_not_reached(); --=20 2.35.1 From nobody Sat May 18 08:47:01 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=0672150a7=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1647396222572100001 Content-Type: text/plain; charset="utf-8" From: Alistair Francis The RISC-V specification states that: "Supervisor-level external interrupts are made pending based on the logical-OR of the software-writable SEIP bit and the signal from the external interrupt controller." We currently only allow either the interrupt controller or software to set the bit, which is incorrect. This patch removes the miclaim mask when writing MIP to allow M-mode software to inject interrupts, even with an interrupt controller. We then also need to keep track of which source is setting MIP_SEIP. The final value is a OR of both, so we add two bools and use that to keep track of the current state. This way either source can change without losing the correct value. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/904 Signed-off-by: Alistair Francis Reviewed-by: Bin Meng Reviewed-by: Richard Henderson --- target/riscv/cpu.h | 8 ++++++++ target/riscv/cpu.c | 10 +++++++++- target/riscv/csr.c | 8 ++++++-- 3 files changed, 23 insertions(+), 3 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c069fe85fa..05d40f8dbd 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -173,6 +173,14 @@ struct CPUArchState { uint64_t mstatus; =20 uint64_t mip; + /* + * MIP contains the software writable version of SEIP ORed with the + * external interrupt value. The MIP register is always up-to-date. + * To keep track of the current source, we also save booleans of the v= alues + * here. + */ + bool external_seip; + bool software_seip; =20 uint64_t miclaim; =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 41b757995d..68373b769c 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -706,7 +706,6 @@ static void riscv_cpu_set_irq(void *opaque, int irq, in= t level) case IRQ_VS_TIMER: case IRQ_M_TIMER: case IRQ_U_EXT: - case IRQ_S_EXT: case IRQ_VS_EXT: case IRQ_M_EXT: if (kvm_enabled()) { @@ -715,6 +714,15 @@ static void riscv_cpu_set_irq(void *opaque, int irq, i= nt level) riscv_cpu_update_mip(cpu, 1 << irq, BOOL_TO_MASK(level)); } break; + case IRQ_S_EXT: + if (kvm_enabled()) { + kvm_riscv_set_irq(cpu, irq, level); + } else { + env->external_seip =3D level; + riscv_cpu_update_mip(cpu, 1 << irq, + BOOL_TO_MASK(level | env->software_se= ip)); + } + break; default: g_assert_not_reached(); } diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 0606cd0ea8..48e78cf91e 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -1403,10 +1403,14 @@ static RISCVException rmw_mip64(CPURISCVState *env,= int csrno, uint64_t new_val, uint64_t wr_mask) { RISCVCPU *cpu =3D env_archcpu(env); - /* Allow software control of delegable interrupts not claimed by hardw= are */ - uint64_t old_mip, mask =3D wr_mask & delegable_ints & ~env->miclaim; + uint64_t old_mip, mask =3D wr_mask & delegable_ints; uint32_t gin; =20 + if (mask & MIP_SEIP) { + env->software_seip =3D new_val & MIP_SEIP; + } + new_val |=3D env->external_seip << IRQ_S_EXT; + if (mask) { old_mip =3D riscv_cpu_update_mip(cpu, mask, (new_val & mask)); } else { --=20 2.35.1