From nobody Fri May 17 23:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164733132136994.35280521725485; Tue, 15 Mar 2022 01:02:01 -0700 (PDT) Received: from localhost ([::1]:40442 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nU280-0003kB-3o for importer@patchew.org; Tue, 15 Mar 2022 04:02:00 -0400 Received: from eggs.gnu.org ([209.51.188.92]:32800) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nU24p-0000dJ-Q7; Tue, 15 Mar 2022 03:58:43 -0400 Received: from twspam01.aspeedtech.com ([211.20.114.71]:41108) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nU24m-0003kK-DC; Tue, 15 Mar 2022 03:58:43 -0400 Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 22F7loYr061296; Tue, 15 Mar 2022 15:47:51 +0800 (GMT-8) (envelope-from steven_lee@aspeedtech.com) Received: from localhost.localdomain (192.168.70.100) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 15 Mar 2022 15:57:56 +0800 From: Steven Lee To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" Subject: [PATCH v2 1/2] hw: aspeed_scu: Add AST2600 apb_freq and hpll calculation function Date: Tue, 15 Mar 2022 15:57:52 +0800 Message-ID: <20220315075753.8591-2-steven_lee@aspeedtech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220315075753.8591-1-steven_lee@aspeedtech.com> References: <20220315075753.8591-1-steven_lee@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.70.100] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 22F7loYr061296 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.71; envelope-from=steven_lee@aspeedtech.com; helo=twspam01.aspeedtech.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jamin_lin@aspeedtech.com, troy_lee@aspeedtech.com, steven_lee@aspeedtech.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1647331322792100001 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AST2600's HPLL register offset and bit definition are different from AST2500. Add a hpll calculation function and an apb frequency calculation function based on SCU200 register description in ast2600v11.pdf. Signed-off-by: Steven Lee Reviewed-by: C=C3=A9dric Le Goater --- hw/misc/aspeed_scu.c | 39 +++++++++++++++++++++++++++++++++++- include/hw/misc/aspeed_scu.h | 18 +++++++++++++++++ 2 files changed, 56 insertions(+), 1 deletion(-) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index d06e179a6e..d65f86df3d 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -213,6 +213,11 @@ static uint32_t aspeed_scu_get_random(void) } =20 uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s) +{ + return ASPEED_SCU_GET_CLASS(s)->get_apb(s); +} + +static uint32_t aspeed_2400_scu_get_apb_freq(AspeedSCUState *s) { AspeedSCUClass *asc =3D ASPEED_SCU_GET_CLASS(s); uint32_t hpll =3D asc->calc_hpll(s, s->regs[HPLL_PARAM]); @@ -221,6 +226,15 @@ uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s) / asc->apb_divider; } =20 +static uint32_t aspeed_2600_scu_get_apb_freq(AspeedSCUState *s) +{ + AspeedSCUClass *asc =3D ASPEED_SCU_GET_CLASS(s); + uint32_t hpll =3D asc->calc_hpll(s, s->regs[AST2600_HPLL_PARAM]); + + return hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[AST2600_CLK_SEL]) + 1) + / asc->apb_divider; +} + static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size) { AspeedSCUState *s =3D ASPEED_SCU(opaque); @@ -426,6 +440,26 @@ static uint32_t aspeed_2500_scu_calc_hpll(AspeedSCUSta= te *s, uint32_t hpll_reg) return clkin * multiplier; } =20 +static uint32_t aspeed_2600_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll= _reg) +{ + uint32_t multiplier =3D 1; + uint32_t clkin =3D aspeed_scu_get_clkin(s); + + if (hpll_reg & SCU_AST2600_H_PLL_OFF) { + return 0; + } + + if (!(hpll_reg & SCU_AST2600_H_PLL_BYPASS_EN)) { + uint32_t p =3D (hpll_reg >> 19) & 0xf; + uint32_t n =3D (hpll_reg >> 13) & 0x3f; + uint32_t m =3D hpll_reg & 0x1fff; + + multiplier =3D ((m + 1) / (n + 1)) / (p + 1); + } + + return clkin * multiplier; +} + static void aspeed_scu_reset(DeviceState *dev) { AspeedSCUState *s =3D ASPEED_SCU(dev); @@ -525,6 +559,7 @@ static void aspeed_2400_scu_class_init(ObjectClass *kla= ss, void *data) dc->desc =3D "ASPEED 2400 System Control Unit"; asc->resets =3D ast2400_a0_resets; asc->calc_hpll =3D aspeed_2400_scu_calc_hpll; + asc->get_apb =3D aspeed_2400_scu_get_apb_freq; asc->apb_divider =3D 2; asc->nr_regs =3D ASPEED_SCU_NR_REGS; asc->ops =3D &aspeed_ast2400_scu_ops; @@ -545,6 +580,7 @@ static void aspeed_2500_scu_class_init(ObjectClass *kla= ss, void *data) dc->desc =3D "ASPEED 2500 System Control Unit"; asc->resets =3D ast2500_a1_resets; asc->calc_hpll =3D aspeed_2500_scu_calc_hpll; + asc->get_apb =3D aspeed_2400_scu_get_apb_freq; asc->apb_divider =3D 4; asc->nr_regs =3D ASPEED_SCU_NR_REGS; asc->ops =3D &aspeed_ast2500_scu_ops; @@ -716,7 +752,8 @@ static void aspeed_2600_scu_class_init(ObjectClass *kla= ss, void *data) dc->desc =3D "ASPEED 2600 System Control Unit"; dc->reset =3D aspeed_ast2600_scu_reset; asc->resets =3D ast2600_a3_resets; - asc->calc_hpll =3D aspeed_2500_scu_calc_hpll; /* No change since AST25= 00 */ + asc->calc_hpll =3D aspeed_2600_scu_calc_hpll; + asc->get_apb =3D aspeed_2600_scu_get_apb_freq; asc->apb_divider =3D 4; asc->nr_regs =3D ASPEED_AST2600_SCU_NR_REGS; asc->ops =3D &aspeed_ast2600_scu_ops; diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index c14aff2bcb..6bf67589e8 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -56,6 +56,7 @@ struct AspeedSCUClass { =20 const uint32_t *resets; uint32_t (*calc_hpll)(AspeedSCUState *s, uint32_t hpll_reg); + uint32_t (*get_apb)(AspeedSCUState *s); uint32_t apb_divider; uint32_t nr_regs; const MemoryRegionOps *ops; @@ -316,4 +317,21 @@ uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s); SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \ SCU_AST2500_HW_STRAP_RESERVED1) =20 +/* SCU200 H-PLL Parameter Register (for Aspeed AST2600 SOC) + * + * 28:26 H-PLL Parameters + * 25 Enable H-PLL reset + * 24 Enable H-PLL bypass mode + * 23 Turn off H-PLL + * 22:19 H-PLL Post Divider (P) + * 18:13 H-PLL Numerator (M) + * 12:0 H-PLL Denumerator (N) + * + * (Output frequency) =3D CLKIN(25MHz) * [(M+1) / (N+1)] / (P+1) + * + * The default frequency is 1200Mhz when CLKIN =3D 25MHz + */ +#define SCU_AST2600_H_PLL_BYPASS_EN (0x1 << 24) +#define SCU_AST2600_H_PLL_OFF (0x1 << 23) + #endif /* ASPEED_SCU_H */ --=20 2.17.1 From nobody Fri May 17 23:07:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1647331307132834.0813934276798; Tue, 15 Mar 2022 01:01:47 -0700 (PDT) Received: from localhost ([::1]:39504 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nU27n-000376-As for importer@patchew.org; Tue, 15 Mar 2022 04:01:47 -0400 Received: from eggs.gnu.org ([209.51.188.92]:32788) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nU24p-0000dG-Q4; Tue, 15 Mar 2022 03:58:43 -0400 Received: from twspam01.aspeedtech.com ([211.20.114.71]:22718) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nU24m-0003jb-9i; Tue, 15 Mar 2022 03:58:43 -0400 Received: from mail.aspeedtech.com ([192.168.0.24]) by twspam01.aspeedtech.com with ESMTP id 22F7loYs061296; Tue, 15 Mar 2022 15:47:51 +0800 (GMT-8) (envelope-from steven_lee@aspeedtech.com) Received: from localhost.localdomain (192.168.70.100) by TWMBX02.aspeed.com (192.168.0.24) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Tue, 15 Mar 2022 15:57:56 +0800 From: Steven Lee To: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Peter Maydell , Andrew Jeffery , Joel Stanley , "open list:ASPEED BMCs" , "open list:All patches CC here" Subject: [PATCH v2 2/2] hw: aspeed_scu: Introduce clkin_25Mhz attribute Date: Tue, 15 Mar 2022 15:57:53 +0800 Message-ID: <20220315075753.8591-3-steven_lee@aspeedtech.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20220315075753.8591-1-steven_lee@aspeedtech.com> References: <20220315075753.8591-1-steven_lee@aspeedtech.com> MIME-Version: 1.0 X-Originating-IP: [192.168.70.100] X-ClientProxiedBy: TWMBX02.aspeed.com (192.168.0.24) To TWMBX02.aspeed.com (192.168.0.24) X-DNSRBL: X-MAIL: twspam01.aspeedtech.com 22F7loYs061296 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=211.20.114.71; envelope-from=steven_lee@aspeedtech.com; helo=twspam01.aspeedtech.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jamin_lin@aspeedtech.com, troy_lee@aspeedtech.com, steven_lee@aspeedtech.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1647331309787100002 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" AST2600 clkin is always 25MHz, introduce clkin_25Mhz attribute for aspeed_scu_get_clkin() to return the correct clkin for ast2600. Signed-off-by: Steven Lee Reviewed-by: C=C3=A9dric Le Goater --- hw/misc/aspeed_scu.c | 6 +++++- include/hw/misc/aspeed_scu.h | 1 + 2 files changed, 6 insertions(+), 1 deletion(-) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index d65f86df3d..150567f98a 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -371,7 +371,8 @@ static const MemoryRegionOps aspeed_ast2500_scu_ops =3D= { =20 static uint32_t aspeed_scu_get_clkin(AspeedSCUState *s) { - if (s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN) { + if (s->hw_strap1 & SCU_HW_STRAP_CLK_25M_IN || + ASPEED_SCU_GET_CLASS(s)->clkin_25Mhz) { return 25000000; } else if (s->hw_strap1 & SCU_HW_STRAP_CLK_48M_IN) { return 48000000; @@ -562,6 +563,7 @@ static void aspeed_2400_scu_class_init(ObjectClass *kla= ss, void *data) asc->get_apb =3D aspeed_2400_scu_get_apb_freq; asc->apb_divider =3D 2; asc->nr_regs =3D ASPEED_SCU_NR_REGS; + asc->clkin_25Mhz =3D false; asc->ops =3D &aspeed_ast2400_scu_ops; } =20 @@ -583,6 +585,7 @@ static void aspeed_2500_scu_class_init(ObjectClass *kla= ss, void *data) asc->get_apb =3D aspeed_2400_scu_get_apb_freq; asc->apb_divider =3D 4; asc->nr_regs =3D ASPEED_SCU_NR_REGS; + asc->clkin_25Mhz =3D false; asc->ops =3D &aspeed_ast2500_scu_ops; } =20 @@ -756,6 +759,7 @@ static void aspeed_2600_scu_class_init(ObjectClass *kla= ss, void *data) asc->get_apb =3D aspeed_2600_scu_get_apb_freq; asc->apb_divider =3D 4; asc->nr_regs =3D ASPEED_AST2600_SCU_NR_REGS; + asc->clkin_25Mhz =3D true; asc->ops =3D &aspeed_ast2600_scu_ops; } =20 diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index 6bf67589e8..fdc721846c 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -59,6 +59,7 @@ struct AspeedSCUClass { uint32_t (*get_apb)(AspeedSCUState *s); uint32_t apb_divider; uint32_t nr_regs; + bool clkin_25Mhz; const MemoryRegionOps *ops; }; =20 --=20 2.17.1