From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646912567341241.26121011147563; Thu, 10 Mar 2022 03:42:47 -0800 (PST) Received: from localhost ([::1]:58138 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHBu-00080Y-AW for importer@patchew.org; Thu, 10 Mar 2022 06:42:46 -0500 Received: from eggs.gnu.org ([209.51.188.92]:50466) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGx9-0004nP-Bd for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:31 -0500 Received: from [2607:f8b0:4864:20::102b] (port=35644 helo=mail-pj1-x102b.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGx7-0007tn-Ln for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:30 -0500 Received: by mail-pj1-x102b.google.com with SMTP id mg21-20020a17090b371500b001bef9e4657cso8014949pjb.0 for ; Thu, 10 Mar 2022 03:27:29 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.27.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:27:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NA9HskFqPeLh+02a0cXnYrdAXovGtw+F2Po8AxVhC7E=; b=DZUuX833jwyKf25fc16ZvWHBarUREFZrcPPZWxVd51RcBpv1SsMiqwtmWAM+VSSW6v ++FmquQQX8uKo/f33hbwCyCbF3YFC6Tsc2BQkxyV8ePOkV8yBNtNKWgGqoBzE6nd+aYi +MOqvYZGukQgsJgYD2+Hj6Df9M8AxZgFuiHONNkOt2gZoaVACXatJae755t841LnA6rl JdUqhGaTP8uaCjxViT6DHR1VVrx82CgRWATozFDVT7xqjJbHC5Huel7RVTfsUzgTc77Y VS3DqzvOvbJv1wwiZZKnJ/IMUj12T5EWMYn6t+SyvjS9oaMttM8tA/sLBME8QIupqsTn szxA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NA9HskFqPeLh+02a0cXnYrdAXovGtw+F2Po8AxVhC7E=; b=aYeAlP2byz3lWpueidM1j2FQPW8iRA8Km+VuM1g9/Zb43X4I56pZNpAynpMOcwtkdL AdltOXAkHSDweNm/wERuClh//uh00DgWtGNZhdRLUgVrj+yXDYAUT70UP1yfxsVIGfX+ VJqFwcEKxc1OXuq+A/nteSV5f8hJRPrVjkKNj+wjezjU8DXK3+yglEdSRxXiiD7ySvv6 zMM5T8ISImQf4lYsojhS4hbmwjLyu4XnkYvDTgOqzh41EEWdEngWSjxx0A+29S+SL2oY FX0RUUnrgY/8DGnUWQOeGJOdEeZf/cUvmPnYksmrd9UO5S59VxGKlvzPJLOg1Zwxeant jycA== X-Gm-Message-State: AOAM531znU9OEmqVRX5oqWXRtIIjRRX+PnmQl1dY8SFjUX/uJkCyckyk /Y8h7hc0YPWYc8RuslvhlIqI6dW1Wq0vog== X-Google-Smtp-Source: ABdhPJxpXIcZueN00DZa/PF7a+xeELRODICXUPMxx3tKrFbHMsvqYdr0V9E8hJC6iC5ngjGTpefs3g== X-Received: by 2002:a17:902:8491:b0:14e:dad4:5ce5 with SMTP id c17-20020a170902849100b0014edad45ce5mr4505167plo.76.1646911648371; Thu, 10 Mar 2022 03:27:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 01/48] target/nios2: Check supervisor on eret Date: Thu, 10 Mar 2022 03:26:38 -0800 Message-Id: <20220310112725.570053-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102b (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646912568233100001 Content-Type: text/plain; charset="utf-8" From: Amir Gonnen eret instruction is only allowed in supervisor mode. Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Signed-off-by: Amir Gonnen Message-Id: <20220303153906.2024748-2-amir.gonnen@neuroblade.ai> Signed-off-by: Richard Henderson --- target/nios2/translate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index f89271dbed..341f3a8273 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -384,6 +384,8 @@ static const Nios2Instruction i_type_instructions[] =3D= { */ static void eret(DisasContext *dc, uint32_t code, uint32_t flags) { + gen_check_supervisor(dc); + tcg_gen_mov_tl(cpu_R[CR_STATUS], cpu_R[CR_ESTATUS]); tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_EA]); =20 --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646913259247308.4319262883748; Thu, 10 Mar 2022 03:54:19 -0800 (PST) Received: from localhost ([::1]:60940 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHN4-000488-7S for importer@patchew.org; Thu, 10 Mar 2022 06:54:18 -0500 Received: from eggs.gnu.org ([209.51.188.92]:50508) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGxA-0004q0-LB for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:32 -0500 Received: from [2607:f8b0:4864:20::102b] (port=33650 helo=mail-pj1-x102b.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGx8-0007u6-Hp for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:32 -0500 Received: by mail-pj1-x102b.google.com with SMTP id v1-20020a17090a088100b001bf25f97c6eso6399331pjc.0 for ; Thu, 10 Mar 2022 03:27:30 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.27.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:27:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bz8zlZqp+XNpUuV3WS3uKIWPzFVnLucU6nOyII1L55M=; b=RquWEd/RQnz2t0dcU7OLl46wGO6Id2FuSV+LR37+8Q+hx+Wb5XQ1DXkwOkszsAMVIL 12iuxBODnyH9s1oIXx/N4sxSbRAD83q7ie7Xzg29F5k5hM8yVBzEUDZe33WhzV9cniHr awO0sle25OFlylGkmg1SKSfCV2c0leJcABisPvrCt3y0dbdw1quDBiIyKSSAQkb9bNpc 7Z8NRCa0Zng8wc++HXtSHqkE4SOlGWzXwB1Xw5jcnFRhKuL86mC+ll0gBgbZt3/16fb3 LFCQr/mFfR4AGblBFBugB+ko9v5qK4yLwW7HSif6zBNGLTei59r7pKwFIBeDjM4aDIYj sr9w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bz8zlZqp+XNpUuV3WS3uKIWPzFVnLucU6nOyII1L55M=; b=rvFbmD/7ZB9DJK32i73pUP7D8wxRP+KKLnsgjke5oF43f14XWyUa+svnwQjAky/m91 TqeIXvx/qvVHk+mpd/DISudsMvLh+M9JAQ7R2O/q7pWHKnnubSbHVPFkD4ta5UeVyP0a 5iAN1rSh/cEf/BpreXcxvaMvNmyelwrD05tMx2QyCZ04LTAU0X2pSwi35r6ETkvt1/hr qS4QvVF4JL+WOCSq7VUFSXeKqHl1WZsDhpCcfwZo9FihjTDxp6SUNiG+XFGY1NlsKxF4 UFsqfNiCaL2CiNTlSBhZUbh0wNRqj2eknDPo3pMvqgwTpYPPgM+E3l+HRv8DeouEMJPS vtRw== X-Gm-Message-State: AOAM530g+wnW1a2pEpB1PyyfwqwnRUpwwEIWisY/ZzFY/DVQlNyvKNRU 0UpHQwVyAqV5F5L6N976tf9eQcsctc0ZbQ== X-Google-Smtp-Source: ABdhPJyAIZUYT8bM1X7IdhppA2Wl+H94gLHixmSwJkjG+EPvYLB8xESVAQLzEApQh6oSsLGq5tromg== X-Received: by 2002:a17:902:c408:b0:153:176:19a4 with SMTP id k8-20020a170902c40800b00153017619a4mr4693416plk.18.1646911649276; Thu, 10 Mar 2022 03:27:29 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 02/48] target/nios2: Stop generating code if gen_check_supervisor fails Date: Thu, 10 Mar 2022 03:26:39 -0800 Message-Id: <20220310112725.570053-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102b (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646913259821100001 Content-Type: text/plain; charset="utf-8" Whether the cpu is in user-mode or not is something that we know at translation-time. We do not need to generate code after having raised an exception. Suggested-by: Peter Maydell Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/translate.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 341f3a8273..1e0ab686dc 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -169,12 +169,14 @@ static void gen_excp(DisasContext *dc, uint32_t code,= uint32_t flags) t_gen_helper_raise_exception(dc, flags); } =20 -static void gen_check_supervisor(DisasContext *dc) +static bool gen_check_supervisor(DisasContext *dc) { if (dc->base.tb->flags & CR_STATUS_U) { /* CPU in user mode, privileged instruction called, stop. */ t_gen_helper_raise_exception(dc, EXCP_SUPERI); + return false; } + return true; } =20 /* @@ -384,7 +386,9 @@ static const Nios2Instruction i_type_instructions[] =3D= { */ static void eret(DisasContext *dc, uint32_t code, uint32_t flags) { - gen_check_supervisor(dc); + if (!gen_check_supervisor(dc)) { + return; + } =20 tcg_gen_mov_tl(cpu_R[CR_STATUS], cpu_R[CR_ESTATUS]); tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_EA]); @@ -447,7 +451,9 @@ static void rdctl(DisasContext *dc, uint32_t code, uint= 32_t flags) { R_TYPE(instr, code); =20 - gen_check_supervisor(dc); + if (!gen_check_supervisor(dc)) { + return; + } =20 if (unlikely(instr.c =3D=3D R_ZERO)) { return; @@ -474,9 +480,13 @@ static void rdctl(DisasContext *dc, uint32_t code, uin= t32_t flags) /* ctlN <- rA */ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags) { - gen_check_supervisor(dc); + if (!gen_check_supervisor(dc)) { + return; + } =20 -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else R_TYPE(instr, code); TCGv v =3D load_gpr(dc, instr.a); =20 --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646912764307241.0651623356447; Thu, 10 Mar 2022 03:46:04 -0800 (PST) Received: from localhost ([::1]:38548 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHF5-0005R4-0s for importer@patchew.org; Thu, 10 Mar 2022 06:46:03 -0500 Received: from eggs.gnu.org ([209.51.188.92]:50526) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGxB-0004so-K3 for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:33 -0500 Received: from [2607:f8b0:4864:20::629] (port=38560 helo=mail-pl1-x629.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGxA-0007ug-1C for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:33 -0500 Received: by mail-pl1-x629.google.com with SMTP id n18so1911358plg.5 for ; Thu, 10 Mar 2022 03:27:31 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.27.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:27:29 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=tamfos1uvfrgy6OTL/hYTKA67kxVDj5ysduH3BCBsBo=; b=fzlO5ezHc+T+qu7VGgr9u06EGqUV5gVCp/LwBqeG8sXDfp3Er+vnfBg9wvxduT45P2 R/fUdwAGiW5csZDxdijov0r/Ec8jXJI1PZbqaEuxOILfCVitEd5L1Ye/Cl/SsJ+EQ0gi o8YW12wT27lTlUCWiKgSSS/zn9mBZEsfqwdm+8i2FKuNsijhKiLiAOCJRv2+XiI3aZKJ PVEjtQaH0rCL4ZcV/TXNEi1z24YB6YpYm3vxyb+Rp5EnQomD0oeQMkn59UT0KuGGSXIz gGczvDe37J1uAA44C+ApEKZUMhpC7WY+AKLRztNNk4MDNTuP+skvLcexpStZY1sVOKCY 5tOA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tamfos1uvfrgy6OTL/hYTKA67kxVDj5ysduH3BCBsBo=; b=WOWzvn+HwMB8eIHT4IY2+BDRb2RQTHmT6hm/DU7Zpj/5Navk8qHG4DOH/pyOkP3OsC Rw87mo5wsaGP4cr03HO5eQpjgGLBaD5ZzXpOH6AWdB8FQAp86YO9X9sR4+Lr17EvKjYl 4Cmo6m3ozV0une65KY0IK22+KrHGzkw992n5Oxzo5Zafc1bobca9umX4PQ/T01ixA0U3 9c6+XTZfIPMr4Mf1mcM9a4094CcrOxtbRqcfAzuqPEAwMYKd3Uzgntd1u1n3zZJIyQX9 R8p2RHCZ2H67GTYz9Z6WveF7a7tCW7WU6i39mhuXgjvx5y2r0Spr70j0M0vCS8uFtWB+ wg7Q== X-Gm-Message-State: AOAM532oxIyJzjFGLouJdwo3vC2SvYUOabGADGYDx2x0+4L26bOLgsLu msRZUXy1u8pgUCg8ubeX0M+X4d5PBnJKzg== X-Google-Smtp-Source: ABdhPJxkgnUqEEbPF3pIH/tNAuvp84zAlx/kbUotyapPVNtzFzkT5KHbmswpXPX2XmdUo0B9DF8C6A== X-Received: by 2002:a17:90a:da02:b0:1bf:3919:f2a with SMTP id e2-20020a17090ada0200b001bf39190f2amr15435804pjv.208.1646911650188; Thu, 10 Mar 2022 03:27:30 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 03/48] target/nios2: Add NUM_GP_REGS and NUM_CP_REGS Date: Thu, 10 Mar 2022 03:26:40 -0800 Message-Id: <20220310112725.570053-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::629 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646912765377100001 Content-Type: text/plain; charset="utf-8" From: Amir Gonnen Split NUM_CORE_REGS into components that can be used elsewhere. Reviewed-by: Peter Maydell Signed-off-by: Amir Gonnen Message-Id: <20220303153906.2024748-3-amir.gonnen@neuroblade.ai> [rth: Split out of a larger patch for shadow register sets.] Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index ca0f3420cd..adeb16377d 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -56,9 +56,11 @@ struct Nios2CPUClass { #define EXCEPTION_ADDRESS 0x00000004 #define FAST_TLB_MISS_ADDRESS 0x00000008 =20 +#define NUM_GP_REGS 32 +#define NUM_CR_REGS 32 =20 /* GP regs + CR regs + PC */ -#define NUM_CORE_REGS (32 + 32 + 1) +#define NUM_CORE_REGS (NUM_GP_REGS + NUM_CR_REGS + 1) =20 /* General purpose register aliases */ #define R_ZERO 0 @@ -79,7 +81,7 @@ struct Nios2CPUClass { #define R_RA 31 =20 /* Control register aliases */ -#define CR_BASE 32 +#define CR_BASE NUM_GP_REGS #define CR_STATUS (CR_BASE + 0) #define CR_STATUS_PIE (1 << 0) #define CR_STATUS_U (1 << 1) --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646913502653712.9203255798901; Thu, 10 Mar 2022 03:58:22 -0800 (PST) Received: from localhost ([::1]:43902 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHQz-0003cc-FT for importer@patchew.org; Thu, 10 Mar 2022 06:58:21 -0500 Received: from eggs.gnu.org ([209.51.188.92]:50582) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGxD-0004yF-Si for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:35 -0500 Received: from [2607:f8b0:4864:20::531] (port=43903 helo=mail-pg1-x531.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGxB-0007v2-EJ for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:35 -0500 Received: by mail-pg1-x531.google.com with SMTP id 27so4470814pgk.10 for ; Thu, 10 Mar 2022 03:27:33 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.27.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:27:31 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bkOrHFoETWid+QekyrDcDE4JYVn7YyGDinnjYK+GH7Y=; b=i1832pePtU73jPJ/DoibxbSu9+UqfhXHsoinv8bbOdZWpM4frjP1Uvsky3J3N2ZyhP LIfAnXZftEaXbfGAPH2i+cCbRxgY8o6uDFiiFrhWbDyx/dQ3tFglWediP9P6NmjAwAbB Q3cBf0F7NWCgLlEUnwvFS+BK7DrUgVJ7zHvimFseEKGTkEpZJwrFiPsXT/dL9bXepYD8 6/YboK3NrfmN5my6CWHxufEJkrMtQhKnyMxdgPt94AbZITJDNniwhf8tdHjottbRG5Xa BiCMNnLLraIJUvAnnD6GP/+aIadoyy/Lbq8elY5eQ0k0Sy+eG81mfgdVgpZ58WRWdKgx lBMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bkOrHFoETWid+QekyrDcDE4JYVn7YyGDinnjYK+GH7Y=; b=QyMb6uRn0hZMIhROWhp2ErDX1qpGbXbyr8B/YQnxmJqumfpG6zppgRI5AXn7oduiwk qPUYuXybJOF1YR95PpUP2gDwP1WWCl+Qrk5Ebe3KISp0+xvk6K/2vupLwYCza6qesXri nXHNenGF4PZFEHb+6TDJ/y1EDwV30fSgCFWX5z2C+fHOOJJhmlFfY68fMFNh9z6lazhJ KXamQreuBoYhNIfzuHan/gd29A4wtlnwHv/NiC1VMki/4oXjd1VRUIhwXytDogE7sVrz fevm5OnS7OuMcfXfuO0jw6X5Ba+BC2Ihpw8RtzFAE6lp7BrN4lKv6mG/hXgqfDQce7ut tSYQ== X-Gm-Message-State: AOAM530xGNaiCORD5hGFtqrzLhU1yfKqG7nCnfpYeCaOYS3l4pyCVidg t/V1ZoZCFVpKNRoCebg9AnxTiGNWgFrzIA== X-Google-Smtp-Source: ABdhPJw4HRJRTc48+JRJLNvBUgBsJ0SLH3aEyEPd8KSs5hkOXbBtnUQT6uQNpQQYWT/Of7GjpoUY9A== X-Received: by 2002:a63:85c8:0:b0:380:3444:d682 with SMTP id u191-20020a6385c8000000b003803444d682mr3651554pgd.163.1646911651864; Thu, 10 Mar 2022 03:27:31 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 04/48] target/nios2: Split PC out of env->regs[] Date: Thu, 10 Mar 2022 03:26:41 -0800 Message-Id: <20220310112725.570053-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::531 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646913503980100002 Content-Type: text/plain; charset="utf-8" It is cleaner to have a separate name for this variable. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 10 +++----- linux-user/elfload.c | 2 +- linux-user/nios2/cpu_loop.c | 17 ++++++------- linux-user/nios2/signal.c | 6 ++--- target/nios2/cpu.c | 8 +++--- target/nios2/helper.c | 51 +++++++++++++++++-------------------- target/nios2/translate.c | 29 +++++++++++---------- 7 files changed, 58 insertions(+), 65 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index adeb16377d..9be128d63a 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -59,8 +59,8 @@ struct Nios2CPUClass { #define NUM_GP_REGS 32 #define NUM_CR_REGS 32 =20 -/* GP regs + CR regs + PC */ -#define NUM_CORE_REGS (NUM_GP_REGS + NUM_CR_REGS + 1) +/* GP regs + CR regs */ +#define NUM_CORE_REGS (NUM_GP_REGS + NUM_CR_REGS) =20 /* General purpose register aliases */ #define R_ZERO 0 @@ -130,9 +130,6 @@ struct Nios2CPUClass { #define CR_MPUBASE (CR_BASE + 14) #define CR_MPUACC (CR_BASE + 15) =20 -/* Other registers */ -#define R_PC 64 - /* Exceptions */ #define EXCP_BREAK 0x1000 #define EXCP_RESET 0 @@ -158,6 +155,7 @@ struct Nios2CPUClass { =20 struct CPUArchState { uint32_t regs[NUM_CORE_REGS]; + uint32_t pc; =20 #if !defined(CONFIG_USER_ONLY) Nios2MMU mmu; @@ -241,7 +239,7 @@ typedef Nios2CPU ArchCPU; static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *= pc, target_ulong *cs_base, uint32_t *f= lags) { - *pc =3D env->regs[R_PC]; + *pc =3D env->pc; *cs_base =3D 0; *flags =3D (env->regs[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U)); } diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 9628a38361..23ff9659a5 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1170,7 +1170,7 @@ static void elf_core_copy_regs(target_elf_gregset_t *= regs, (*regs)[30] =3D -1; /* R_SSTATUS */ (*regs)[31] =3D tswapreg(env->regs[R_RA]); =20 - (*regs)[32] =3D tswapreg(env->regs[R_PC]); + (*regs)[32] =3D tswapreg(env->pc); =20 (*regs)[33] =3D -1; /* R_STATUS */ (*regs)[34] =3D tswapreg(env->regs[CR_ESTATUS]); diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index 1e93ef34e6..7b20c024db 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -56,25 +56,24 @@ void cpu_loop(CPUNios2State *env) env->regs[2] =3D abs(ret); /* Return value is 0..4096 */ env->regs[7] =3D ret > 0xfffff000u; - env->regs[R_PC] +=3D 4; + env->pc +=3D 4; break; =20 case 1: qemu_log_mask(CPU_LOG_INT, "\nTrap 1\n"); - force_sig_fault(TARGET_SIGUSR1, 0, env->regs[R_PC]); + force_sig_fault(TARGET_SIGUSR1, 0, env->pc); break; case 2: qemu_log_mask(CPU_LOG_INT, "\nTrap 2\n"); - force_sig_fault(TARGET_SIGUSR2, 0, env->regs[R_PC]); + force_sig_fault(TARGET_SIGUSR2, 0, env->pc); break; case 31: qemu_log_mask(CPU_LOG_INT, "\nTrap 31\n"); - force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->re= gs[R_PC]); + force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc= ); break; default: qemu_log_mask(CPU_LOG_INT, "\nTrap %d\n", env->error_code); - force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLTRP, - env->regs[R_PC]); + force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLTRP, env->pc); break; =20 case 16: /* QEMU specific, for __kuser_cmpxchg */ @@ -99,7 +98,7 @@ void cpu_loop(CPUNios2State *env) o =3D env->regs[5]; n =3D env->regs[6]; env->regs[2] =3D qatomic_cmpxchg(h, o, n) - o; - env->regs[R_PC] +=3D 4; + env->pc +=3D 4; } break; } @@ -117,7 +116,7 @@ void cpu_loop(CPUNios2State *env) info.si_errno =3D 0; /* TODO: check env->error_code */ info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->regs[R_PC]; + info._sifields._sigfault._addr =3D env->pc; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); } break; @@ -155,6 +154,6 @@ void target_cpu_copy_regs(CPUArchState *env, struct tar= get_pt_regs *regs) env->regs[R_SP] =3D regs->sp; env->regs[R_GP] =3D regs->gp; env->regs[CR_ESTATUS] =3D regs->estatus; - env->regs[R_PC] =3D regs->ea; + env->pc =3D regs->ea; /* TODO: unsigned long orig_r7; */ } diff --git a/linux-user/nios2/signal.c b/linux-user/nios2/signal.c index 517cd39270..ccfaa75d3b 100644 --- a/linux-user/nios2/signal.c +++ b/linux-user/nios2/signal.c @@ -73,7 +73,7 @@ static void rt_setup_ucontext(struct target_ucontext *uc,= CPUNios2State *env) __put_user(env->regs[R_RA], &gregs[23]); __put_user(env->regs[R_FP], &gregs[24]); __put_user(env->regs[R_GP], &gregs[25]); - __put_user(env->regs[R_PC], &gregs[27]); + __put_user(env->pc, &gregs[27]); __put_user(env->regs[R_SP], &gregs[28]); } =20 @@ -122,7 +122,7 @@ static int rt_restore_ucontext(CPUNios2State *env, stru= ct target_ucontext *uc, __get_user(env->regs[R_GP], &gregs[25]); /* Not really necessary no user settable bits */ __get_user(temp, &gregs[26]); - __get_user(env->regs[R_PC], &gregs[27]); + __get_user(env->pc, &gregs[27]); =20 __get_user(env->regs[R_RA], &gregs[23]); __get_user(env->regs[R_SP], &gregs[28]); @@ -180,7 +180,7 @@ void setup_rt_frame(int sig, struct target_sigaction *k= a, env->regs[4] =3D sig; env->regs[5] =3D frame_addr + offsetof(struct target_rt_sigframe, info= ); env->regs[6] =3D frame_addr + offsetof(struct target_rt_sigframe, uc); - env->regs[R_PC] =3D ka->_sa_handler; + env->pc =3D ka->_sa_handler; =20 unlock_user_struct(frame, frame_addr, 1); } diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 6975ae4bdb..40031c9f20 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -31,7 +31,7 @@ static void nios2_cpu_set_pc(CPUState *cs, vaddr value) Nios2CPU *cpu =3D NIOS2_CPU(cs); CPUNios2State *env =3D &cpu->env; =20 - env->regs[R_PC] =3D value; + env->pc =3D value; } =20 static bool nios2_cpu_has_work(CPUState *cs) @@ -54,7 +54,7 @@ static void nios2_cpu_reset(DeviceState *dev) ncc->parent_reset(dev); =20 memset(env->regs, 0, sizeof(uint32_t) * NUM_CORE_REGS); - env->regs[R_PC] =3D cpu->reset_addr; + env->pc =3D cpu->reset_addr; =20 #if defined(CONFIG_USER_ONLY) /* Start in user mode with interrupts enabled. */ @@ -161,7 +161,7 @@ static int nios2_cpu_gdb_read_register(CPUState *cs, GB= yteArray *mem_buf, int n) if (n < 32) { /* GP regs */ return gdb_get_reg32(mem_buf, env->regs[n]); } else if (n =3D=3D 32) { /* PC */ - return gdb_get_reg32(mem_buf, env->regs[R_PC]); + return gdb_get_reg32(mem_buf, env->pc); } else if (n < 49) { /* Status regs */ return gdb_get_reg32(mem_buf, env->regs[n - 1]); } @@ -183,7 +183,7 @@ static int nios2_cpu_gdb_write_register(CPUState *cs, u= int8_t *mem_buf, int n) if (n < 32) { /* GP regs */ env->regs[n] =3D ldl_p(mem_buf); } else if (n =3D=3D 32) { /* PC */ - env->regs[R_PC] =3D ldl_p(mem_buf); + env->pc =3D ldl_p(mem_buf); } else if (n < 49) { /* Status regs */ env->regs[n - 1] =3D ldl_p(mem_buf); } diff --git a/target/nios2/helper.c b/target/nios2/helper.c index e5c98650e1..31cec29e89 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -35,7 +35,7 @@ void nios2_cpu_do_interrupt(CPUState *cs) Nios2CPU *cpu =3D NIOS2_CPU(cs); CPUNios2State *env =3D &cpu->env; cs->exception_index =3D -1; - env->regs[R_EA] =3D env->regs[R_PC] + 4; + env->regs[R_EA] =3D env->pc + 4; } =20 void nios2_cpu_record_sigsegv(CPUState *cs, vaddr addr, @@ -58,7 +58,7 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_IRQ: assert(env->regs[CR_STATUS] & CR_STATUS_PIE); =20 - qemu_log_mask(CPU_LOG_INT, "interrupt at pc=3D%x\n", env->regs[R_P= C]); + qemu_log_mask(CPU_LOG_INT, "interrupt at pc=3D%x\n", env->pc); =20 env->regs[CR_ESTATUS] =3D env->regs[CR_STATUS]; env->regs[CR_STATUS] |=3D CR_STATUS_IH; @@ -67,14 +67,13 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[CR_EXCEPTION] &=3D ~(0x1F << 2); env->regs[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; =20 - env->regs[R_EA] =3D env->regs[R_PC] + 4; - env->regs[R_PC] =3D cpu->exception_addr; + env->regs[R_EA] =3D env->pc + 4; + env->pc =3D cpu->exception_addr; break; =20 case EXCP_TLBD: if ((env->regs[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { - qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=3D%x\n", - env->regs[R_PC]); + qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=3D%x\n", env= ->pc); =20 /* Fast TLB miss */ /* Variation from the spec. Table 3-35 of the cpu reference sh= ows @@ -90,11 +89,10 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[CR_TLBMISC] &=3D ~CR_TLBMISC_DBL; env->regs[CR_TLBMISC] |=3D CR_TLBMISC_WR; =20 - env->regs[R_EA] =3D env->regs[R_PC] + 4; - env->regs[R_PC] =3D cpu->fast_tlb_miss_addr; + env->regs[R_EA] =3D env->pc + 4; + env->pc =3D cpu->fast_tlb_miss_addr; } else { - qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=3D%x\n", - env->regs[R_PC]); + qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=3D%x\n", e= nv->pc); =20 /* Double TLB miss */ env->regs[CR_STATUS] |=3D CR_STATUS_EH; @@ -105,14 +103,14 @@ void nios2_cpu_do_interrupt(CPUState *cs) =20 env->regs[CR_TLBMISC] |=3D CR_TLBMISC_DBL; =20 - env->regs[R_PC] =3D cpu->exception_addr; + env->pc =3D cpu->exception_addr; } break; =20 case EXCP_TLBR: case EXCP_TLBW: case EXCP_TLBX: - qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=3D%x\n", env->regs[R_PC= ]); + qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=3D%x\n", env->pc); =20 env->regs[CR_ESTATUS] =3D env->regs[CR_STATUS]; env->regs[CR_STATUS] |=3D CR_STATUS_EH; @@ -125,19 +123,18 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[CR_TLBMISC] |=3D CR_TLBMISC_WR; } =20 - env->regs[R_EA] =3D env->regs[R_PC] + 4; - env->regs[R_PC] =3D cpu->exception_addr; + env->regs[R_EA] =3D env->pc + 4; + env->pc =3D cpu->exception_addr; break; =20 case EXCP_SUPERA: case EXCP_SUPERI: case EXCP_SUPERD: - qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=3D%x\n", - env->regs[R_PC]); + qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=3D%x\n", en= v->pc); =20 if ((env->regs[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { env->regs[CR_ESTATUS] =3D env->regs[CR_STATUS]; - env->regs[R_EA] =3D env->regs[R_PC] + 4; + env->regs[R_EA] =3D env->pc + 4; } =20 env->regs[CR_STATUS] |=3D CR_STATUS_EH; @@ -146,17 +143,16 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[CR_EXCEPTION] &=3D ~(0x1F << 2); env->regs[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; =20 - env->regs[R_PC] =3D cpu->exception_addr; + env->pc =3D cpu->exception_addr; break; =20 case EXCP_ILLEGAL: case EXCP_TRAP: - qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=3D%x\n", - env->regs[R_PC]); + qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=3D%x\n", env->pc); =20 if ((env->regs[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { env->regs[CR_ESTATUS] =3D env->regs[CR_STATUS]; - env->regs[R_EA] =3D env->regs[R_PC] + 4; + env->regs[R_EA] =3D env->pc + 4; } =20 env->regs[CR_STATUS] |=3D CR_STATUS_EH; @@ -165,24 +161,23 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[CR_EXCEPTION] &=3D ~(0x1F << 2); env->regs[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; =20 - env->regs[R_PC] =3D cpu->exception_addr; + env->pc =3D cpu->exception_addr; break; =20 case EXCP_BREAK: - qemu_log_mask(CPU_LOG_INT, "BREAK exception at pc=3D%x\n", - env->regs[R_PC]); + qemu_log_mask(CPU_LOG_INT, "BREAK exception at pc=3D%x\n", env->pc= ); /* The semihosting instruction is "break 1". */ if (semihosting_enabled() && - cpu_ldl_code(env, env->regs[R_PC]) =3D=3D 0x003da07a) { + cpu_ldl_code(env, env->pc) =3D=3D 0x003da07a) { qemu_log_mask(CPU_LOG_INT, "Entering semihosting\n"); - env->regs[R_PC] +=3D 4; + env->pc +=3D 4; do_nios2_semihosting(env); break; } =20 if ((env->regs[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { env->regs[CR_BSTATUS] =3D env->regs[CR_STATUS]; - env->regs[R_BA] =3D env->regs[R_PC] + 4; + env->regs[R_BA] =3D env->pc + 4; } =20 env->regs[CR_STATUS] |=3D CR_STATUS_EH; @@ -191,7 +186,7 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[CR_EXCEPTION] &=3D ~(0x1F << 2); env->regs[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; =20 - env->regs[R_PC] =3D cpu->exception_addr; + env->pc =3D cpu->exception_addr; break; =20 default: diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 1e0ab686dc..154ffacbea 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -104,6 +104,7 @@ typedef struct DisasContext { } DisasContext; =20 static TCGv cpu_R[NUM_CORE_REGS]; +static TCGv cpu_pc; =20 typedef struct Nios2Instruction { void (*handler)(DisasContext *dc, uint32_t code, uint32_t flags); @@ -144,7 +145,7 @@ static void t_gen_helper_raise_exception(DisasContext *= dc, { TCGv_i32 tmp =3D tcg_const_i32(index); =20 - tcg_gen_movi_tl(cpu_R[R_PC], dc->pc); + tcg_gen_movi_tl(cpu_pc, dc->pc); gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); dc->base.is_jmp =3D DISAS_NORETURN; @@ -156,10 +157,10 @@ static void gen_goto_tb(DisasContext *dc, int n, uint= 32_t dest) =20 if (translator_use_goto_tb(&dc->base, dest)) { tcg_gen_goto_tb(n); - tcg_gen_movi_tl(cpu_R[R_PC], dest); + tcg_gen_movi_tl(cpu_pc, dest); tcg_gen_exit_tb(tb, n); } else { - tcg_gen_movi_tl(cpu_R[R_PC], dest); + tcg_gen_movi_tl(cpu_pc, dest); tcg_gen_exit_tb(NULL, 0); } } @@ -391,7 +392,7 @@ static void eret(DisasContext *dc, uint32_t code, uint3= 2_t flags) } =20 tcg_gen_mov_tl(cpu_R[CR_STATUS], cpu_R[CR_ESTATUS]); - tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_EA]); + tcg_gen_mov_tl(cpu_pc, cpu_R[R_EA]); =20 dc->base.is_jmp =3D DISAS_JUMP; } @@ -399,7 +400,7 @@ static void eret(DisasContext *dc, uint32_t code, uint3= 2_t flags) /* PC <- ra */ static void ret(DisasContext *dc, uint32_t code, uint32_t flags) { - tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_RA]); + tcg_gen_mov_tl(cpu_pc, cpu_R[R_RA]); =20 dc->base.is_jmp =3D DISAS_JUMP; } @@ -407,7 +408,7 @@ static void ret(DisasContext *dc, uint32_t code, uint32= _t flags) /* PC <- ba */ static void bret(DisasContext *dc, uint32_t code, uint32_t flags) { - tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_BA]); + tcg_gen_mov_tl(cpu_pc, cpu_R[R_BA]); =20 dc->base.is_jmp =3D DISAS_JUMP; } @@ -417,7 +418,7 @@ static void jmp(DisasContext *dc, uint32_t code, uint32= _t flags) { R_TYPE(instr, code); =20 - tcg_gen_mov_tl(cpu_R[R_PC], load_gpr(dc, instr.a)); + tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a)); =20 dc->base.is_jmp =3D DISAS_JUMP; } @@ -440,7 +441,7 @@ static void callr(DisasContext *dc, uint32_t code, uint= 32_t flags) { R_TYPE(instr, code); =20 - tcg_gen_mov_tl(cpu_R[R_PC], load_gpr(dc, instr.a)); + tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a)); tcg_gen_movi_tl(cpu_R[R_RA], dc->base.pc_next); =20 dc->base.is_jmp =3D DISAS_JUMP; @@ -742,7 +743,7 @@ illegal_op: t_gen_helper_raise_exception(dc, EXCP_ILLEGAL); } =20 -static const char * const regnames[] =3D { +static const char * const regnames[NUM_CORE_REGS] =3D { "zero", "at", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", @@ -759,7 +760,6 @@ static const char * const regnames[] =3D { "reserved6", "reserved7", "reserved8", "reserved9", "reserved10", "reserved11", "reserved12", "reserved13", "reserved14", "reserved15", "reserved16", "reserved17", - "rpc" }; =20 #include "exec/gen-icount.h" @@ -827,7 +827,7 @@ static void nios2_tr_tb_stop(DisasContextBase *dcbase, = CPUState *cs) case DISAS_TOO_MANY: case DISAS_UPDATE: /* Save the current PC back into the CPU register */ - tcg_gen_movi_tl(cpu_R[R_PC], dc->base.pc_next); + tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); tcg_gen_exit_tb(NULL, 0); break; =20 @@ -876,8 +876,7 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int fl= ags) return; } =20 - qemu_fprintf(f, "IN: PC=3D%x %s\n", - env->regs[R_PC], lookup_symbol(env->regs[R_PC])); + qemu_fprintf(f, "IN: PC=3D%x %s\n", env->pc, lookup_symbol(env->pc)); =20 for (i =3D 0; i < NUM_CORE_REGS; i++) { qemu_fprintf(f, "%9s=3D%8.8x ", regnames[i], env->regs[i]); @@ -903,10 +902,12 @@ void nios2_tcg_init(void) offsetof(CPUNios2State, regs[i]), regnames[i]); } + cpu_pc =3D tcg_global_mem_new(cpu_env, + offsetof(CPUNios2State, pc), "pc"); } =20 void restore_state_to_opc(CPUNios2State *env, TranslationBlock *tb, target_ulong *data) { - env->regs[R_PC] =3D data[0]; + env->pc =3D data[0]; } --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646911817997141.53672510124943; Thu, 10 Mar 2022 03:30:17 -0800 (PST) Received: from localhost ([::1]:33472 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSGzo-0007yT-W1 for importer@patchew.org; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.27.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:27:32 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JwvNUZim2yApAOIks/gNVf1oLVx5CVGA+91qmxfeNYY=; b=Ny/2s4jhqYmWx7BbT/XrJ3Nk6R4IBdravzVIYmVegrzcB1U6Bc9KKid3D5RCidAput UQUnoAHW+RxUN5087+3trXlIqgFgRQunH/hkw/1bto58uwNdK7pr86Aj6QYj/+9RfJDf U5x+mXvoS9Ruppx9ehGjtYAMOaEcBy3y+w9vi/dBNUdmL8nGzBDzM623027YJ6BqI330 omHcv35ay0fuXd9Cx5Rxo2TQd25oV1vE8q+DQjvzW9EGl4VGQsiQpyNaPUyDmlDehfk7 tFl7KxsnfUQAPQRkSzLDRvkQ7PSS0Nv4LaYNglGppcaUk52NsYXA+dshhZJC0LtT/XhC mTQw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JwvNUZim2yApAOIks/gNVf1oLVx5CVGA+91qmxfeNYY=; b=KXPg/YmMgQUvxhjRoSO7QSgKBjSaRB+ydb6Uuoa/0XSssZWtWkxnLEMxgcbKmospIR H3qz3ZTbDjlhER+LQWXdUckUO2yHEbAZi1UlmSypWFvf+1dArj50V3y/a2WCH3f/SshC a9xnbQ4noSvUiMJNvAtTb8kdmk7wBrRxE3KX4gtJ4jKuJOastBExjJSc/AEZSB8+8BuS zd2ezfBS6Xs0M3Qz0bcIau1NswkYqp7pKJOvnbKVEfEmWTWocW2gzD4EUsF0TKwvSmSV OEWVfwoHaEDl5h/k/v1Bz1jhwCK+pCqfyKGsxFYiumcuyRubaIrKESilfbPDLgIeovwq is1g== X-Gm-Message-State: AOAM533M8j4Ma4tiYjpS45KNhJr+njFKDHdX40R2hHV3FlnJAp8nxGCB ZiICUr6vNrM3ZTSap8eWRiB1jqKELzzyKg== X-Google-Smtp-Source: ABdhPJz0FJwKglVJ8eUw+l1fGg0+NFWUC6oMjdfjnwH+rwj8zwkO0nnf7Q/TjbWpWwKIU5rO7RoqCQ== X-Received: by 2002:a62:7c58:0:b0:4f6:ebf1:e78d with SMTP id x85-20020a627c58000000b004f6ebf1e78dmr4625994pfc.18.1646911652862; Thu, 10 Mar 2022 03:27:32 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 05/48] target/nios2: Split out helper for eret instruction Date: Thu, 10 Mar 2022 03:26:42 -0800 Message-Id: <20220310112725.570053-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::433 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646911819689100001 Content-Type: text/plain; charset="utf-8" From: Amir Gonnen The implementation of eret will become much more complex with the introduction of shadow registers. Reviewed-by: Peter Maydell Signed-off-by: Amir Gonnen Message-Id: <20220303153906.2024748-3-amir.gonnen@neuroblade.ai> [rth: Split out of a larger patch for shadow register sets. Directly exit to the cpu loop from the helper.] Signed-off-by: Richard Henderson --- target/nios2/helper.h | 1 + target/nios2/op_helper.c | 9 +++++++++ target/nios2/translate.c | 10 ++++++---- 3 files changed, 16 insertions(+), 4 deletions(-) diff --git a/target/nios2/helper.h b/target/nios2/helper.h index a44ecfdf7a..525b6b685b 100644 --- a/target/nios2/helper.h +++ b/target/nios2/helper.h @@ -21,6 +21,7 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) =20 #if !defined(CONFIG_USER_ONLY) +DEF_HELPER_3(eret, noreturn, env, i32, i32) DEF_HELPER_2(mmu_write_tlbacc, void, env, i32) DEF_HELPER_2(mmu_write_tlbmisc, void, env, i32) DEF_HELPER_2(mmu_write_pteaddr, void, env, i32) diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index caa885f7b4..ee5ad8b23f 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -30,3 +30,12 @@ void helper_raise_exception(CPUNios2State *env, uint32_t= index) cs->exception_index =3D index; cpu_loop_exit(cs); } + +#ifndef CONFIG_USER_ONLY +void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc) +{ + env->regs[CR_STATUS] =3D new_status; + env->pc =3D new_pc; + cpu_loop_exit(env_cpu(env)); +} +#endif /* !CONFIG_USER_ONLY */ diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 154ffacbea..7c2c430e99 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -391,10 +391,12 @@ static void eret(DisasContext *dc, uint32_t code, uin= t32_t flags) return; } =20 - tcg_gen_mov_tl(cpu_R[CR_STATUS], cpu_R[CR_ESTATUS]); - tcg_gen_mov_tl(cpu_pc, cpu_R[R_EA]); - - dc->base.is_jmp =3D DISAS_JUMP; +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + gen_helper_eret(cpu_env, cpu_R[CR_ESTATUS], cpu_R[R_EA]); + dc->base.is_jmp =3D DISAS_NORETURN; +#endif } =20 /* PC <- ra */ --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16469120935312.793994595758136; Thu, 10 Mar 2022 03:34:53 -0800 (PST) Received: from localhost ([::1]:41748 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSH4G-0005Ep-A9 for importer@patchew.org; Thu, 10 Mar 2022 06:34:52 -0500 Received: from eggs.gnu.org ([209.51.188.92]:50598) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGxE-00050l-RQ for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:37 -0500 Received: from [2607:f8b0:4864:20::42e] (port=46757 helo=mail-pf1-x42e.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGxD-0007vY-9e for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:36 -0500 Received: by mail-pf1-x42e.google.com with SMTP id s11so4812792pfu.13 for ; Thu, 10 Mar 2022 03:27:34 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.27.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:27:33 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sLj6JkBIZs+pNXo0KcbHngyos4ugjFtFayVOvZJfdpk=; b=LdGuY8oX8KCnL3VZ0f5HoKPlY+taKpgKAemBRuz+nuarsPBkwzGRYtMslizFfwc4ja +QVqUVmc/VhETytNP9gxvJCkNg3YkR/Cibd+R7teLbYIUAaEDyJa0gURCAtoQW5HNqI8 CzS1ev6A392a7MNm6VVY0lanXFQcBMXInRw0C3ISgD9hfttydPizy3UXATA4AgC+Tbgi tqxLMPSfKr2vPOqPINmucUVNtIpgn2wg0ASoBIlmMItViOA28jRrh1GdFA31gUScwkMU znb/oZqT4ywuwDpNKV9bseuC38pyd6TPTzW0KvwXvnO5W2nR4By69E6D71UEOdQNJnHD wb0Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sLj6JkBIZs+pNXo0KcbHngyos4ugjFtFayVOvZJfdpk=; b=5bj2uPSE8UZ8V2vrUgsda+2YyXUtjTa9UF0T1H20nYs5AcF9f7gQ/H7i6l+7OtyIbJ GVFJPW3gny3VEWzyt7linlZnugtyyynGdT4o0y2ZGnlq341w21vqEDYudXILNp7IQTcu iaveK0p8ZAGWq/mLS/LezR8PB+UDwa06bcsyb1yNkwNKVQrfsmVESEnJDpRzGu2O1Fqh EoLDprJrJYtXORThOvtWbxXongiKz7Cg+S2EGLjEALWgHZTfQ3rrItbVWRJDrW9uQCx/ je+u9wRVf1IdQgFau2AxPoWIAqDnaSLq21FatMEjf+BYqkL4NtBaDg8MSzlIyJFaBHc6 r9mg== X-Gm-Message-State: AOAM530q9xrY3R57L1OizTBOBQ7CMkJg+9c5FJGn+I8P5vrf+hi3Djof dgQJx80m6DNBydKLYkM5LD31jVS0XBsTdA== X-Google-Smtp-Source: ABdhPJw/ek5rryPEPlMUACEthVvhM7f9LVKhYFc9NNTsEEdrNbI5lc1XHuUaNk6ECS0yHUe/OdlC/w== X-Received: by 2002:a63:1c8:0:b0:380:189b:1e66 with SMTP id 191-20020a6301c8000000b00380189b1e66mr3599120pgb.71.1646911653938; Thu, 10 Mar 2022 03:27:33 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 06/48] target/nios2: Fix BRET instruction Date: Thu, 10 Mar 2022 03:26:43 -0800 Message-Id: <20220310112725.570053-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42e (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646912094690100001 Content-Type: text/plain; charset="utf-8" We had failed to copy BSTATUS back to STATUS, and diagnose supervisor-only. The spec is light on the specifics of the implementation of bret, but it is an easy assumption that the restore into STATUS should work the same as eret. Therefore, reuse the existing helper_eret. Reported-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/translate.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 7c2c430e99..3f7bbd6d7b 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -407,12 +407,22 @@ static void ret(DisasContext *dc, uint32_t code, uint= 32_t flags) dc->base.is_jmp =3D DISAS_JUMP; } =20 -/* PC <- ba */ +/* + * status <- bstatus + * PC <- ba + */ static void bret(DisasContext *dc, uint32_t code, uint32_t flags) { - tcg_gen_mov_tl(cpu_pc, cpu_R[R_BA]); + if (!gen_check_supervisor(dc)) { + return; + } =20 - dc->base.is_jmp =3D DISAS_JUMP; +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + gen_helper_eret(cpu_env, cpu_R[CR_BSTATUS], cpu_R[R_BA]); + dc->base.is_jmp =3D DISAS_NORETURN; +#endif } =20 /* PC <- rA */ --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646912129600588.0959725237019; Thu, 10 Mar 2022 03:35:29 -0800 (PST) Received: from localhost ([::1]:41912 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSH4p-0005LS-Uh for importer@patchew.org; Thu, 10 Mar 2022 06:35:27 -0500 Received: from eggs.gnu.org ([209.51.188.92]:50620) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGxG-00053Y-00 for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:38 -0500 Received: from [2607:f8b0:4864:20::536] (port=39935 helo=mail-pg1-x536.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGxE-0007vj-Al for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:37 -0500 Received: by mail-pg1-x536.google.com with SMTP id q19so4486294pgm.6 for ; Thu, 10 Mar 2022 03:27:35 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.27.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:27:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PuQXs01EVc8/4vklrwlVd1dwEAykk2bEYyKpnLalt08=; b=TkAxNSGWlcC4O+XeqHAAQORvajDnfsn9h9ABW/3rbu19TooNxCvdFk7XP6LxydKBaz Gv774xRENsWsoOdg+uOXWLy8cuOcO0EsDOpLNl/qlR+r74JmgYZzcNvjtPSg9YerfZ1R GgvkKn3cR64ElkMnQpj0qcqm5qj4pIB0I2uwwyJHdYpP5ChZ0q3uU9Zimx17KGYFwb7K /vAPt6wbJGDoayfvrUsMAZJHyXX/YCBUX+LWtv5vrP8GQ9dHzajwC82fDv0i5dvhdhvY fu4Zgd+Nmh3PaeXg34U/tqnPi2oQIe+GGmpyzXocmbI4UzJTqlHNl1EmFvTyRKGDPiPC xtWA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PuQXs01EVc8/4vklrwlVd1dwEAykk2bEYyKpnLalt08=; b=HtDtCED3gXFfhR/7f4juCMlotiv6Gcu3Y3Z34Vehz7VLYzffvM2CfqhqiC+8rTpRTn DE48PM0kwIgIc5GSc75/Ao2hOEofYi+Xg2ApwTYGEufZDI3tvjGgUCVWWE4ENFoJzPjE AhsMLJu/vwSisxKWTMegPKtApL2cF60vqXJIQ38sT+W1iC5N2hrtWeTaPP5nzsCy/GtT pGjrZpyhEeTehliBEmDy9LTCzKX36SVw+oNC2LXz6b4POOSCqSrtM6RFG7cvDIHjCTJa 9SJd4Tzl5hmaLcOlWWz7WJSnvN6OSDAjL4K8wnnN8yT//Z/F7e1wHjUoxAK6UpM0JZhf UYyQ== X-Gm-Message-State: AOAM5334XmxDTINMDGKbfRFiM0RlTo6Py3X86p0gpeSv+DVfKJSheVUv n+3HKMNJkbMZNrIF1U6GuXWbvhOeOGo/Tg== X-Google-Smtp-Source: ABdhPJwIUL4aytlA3/+Srn2+o88SnHwHco+wDmsi3yBlnoV6MwlZKNwCTFYLTTrUt9a/9366gxjNfQ== X-Received: by 2002:a63:515:0:b0:379:460f:7bda with SMTP id 21-20020a630515000000b00379460f7bdamr3713022pgf.534.1646911655070; Thu, 10 Mar 2022 03:27:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 07/48] target/nios2: Do not create TCGv for control registers Date: Thu, 10 Mar 2022 03:26:44 -0800 Message-Id: <20220310112725.570053-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::536 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646912130914100003 Content-Type: text/plain; charset="utf-8" We don't need to reference them often, and when we do it is just as easy to load/store from cpu_env directly. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/translate.c | 33 ++++++++++++++++++++++++++------- 1 file changed, 26 insertions(+), 7 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 3f7bbd6d7b..e6e9a5ac6f 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -103,7 +103,7 @@ typedef struct DisasContext { int mem_idx; } DisasContext; =20 -static TCGv cpu_R[NUM_CORE_REGS]; +static TCGv cpu_R[NUM_GP_REGS]; static TCGv cpu_pc; =20 typedef struct Nios2Instruction { @@ -394,7 +394,11 @@ static void eret(DisasContext *dc, uint32_t code, uint= 32_t flags) #ifdef CONFIG_USER_ONLY g_assert_not_reached(); #else - gen_helper_eret(cpu_env, cpu_R[CR_ESTATUS], cpu_R[R_EA]); + TCGv tmp =3D tcg_temp_new(); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, regs[CR_ESTATUS])); + gen_helper_eret(cpu_env, tmp, cpu_R[R_EA]); + tcg_temp_free(tmp); + dc->base.is_jmp =3D DISAS_NORETURN; #endif } @@ -420,7 +424,11 @@ static void bret(DisasContext *dc, uint32_t code, uint= 32_t flags) #ifdef CONFIG_USER_ONLY g_assert_not_reached(); #else - gen_helper_eret(cpu_env, cpu_R[CR_BSTATUS], cpu_R[R_BA]); + TCGv tmp =3D tcg_temp_new(); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, regs[CR_BSTATUS])); + gen_helper_eret(cpu_env, tmp, cpu_R[R_BA]); + tcg_temp_free(tmp); + dc->base.is_jmp =3D DISAS_NORETURN; #endif } @@ -463,6 +471,7 @@ static void callr(DisasContext *dc, uint32_t code, uint= 32_t flags) static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, code); + TCGv t1, t2; =20 if (!gen_check_supervisor(dc)) { return; @@ -482,10 +491,19 @@ static void rdctl(DisasContext *dc, uint32_t code, ui= nt32_t flags) * must perform the AND here, and anywhere else we need the * guest value of ipending. */ - tcg_gen_and_tl(cpu_R[instr.c], cpu_R[CR_IPENDING], cpu_R[CR_IENABL= E]); + t1 =3D tcg_temp_new(); + t2 =3D tcg_temp_new(); + tcg_gen_ld_tl(t1, cpu_env, + offsetof(CPUNios2State, regs[CR_IPENDING])); + tcg_gen_ld_tl(t2, cpu_env, + offsetof(CPUNios2State, regs[CR_IENABLE])); + tcg_gen_and_tl(cpu_R[instr.c], t1, t2); + tcg_temp_free(t1); + tcg_temp_free(t2); break; default: - tcg_gen_mov_tl(cpu_R[instr.c], cpu_R[instr.imm5 + CR_BASE]); + tcg_gen_ld_tl(cpu_R[instr.c], cpu_env, + offsetof(CPUNios2State, regs[instr.imm5 + CR_BASE])); break; } } @@ -522,7 +540,8 @@ static void wrctl(DisasContext *dc, uint32_t code, uint= 32_t flags) dc->base.is_jmp =3D DISAS_UPDATE; /* fall through */ default: - tcg_gen_mov_tl(cpu_R[instr.imm5 + CR_BASE], v); + tcg_gen_st_tl(v, cpu_env, + offsetof(CPUNios2State, regs[instr.imm5 + CR_BASE])); break; } #endif @@ -909,7 +928,7 @@ void nios2_tcg_init(void) { int i; =20 - for (i =3D 0; i < NUM_CORE_REGS; i++) { + for (i =3D 0; i < NUM_GP_REGS; i++) { cpu_R[i] =3D tcg_global_mem_new(cpu_env, offsetof(CPUNios2State, regs[i]), regnames[i]); --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646912400214351.80923916497613; Thu, 10 Mar 2022 03:40:00 -0800 (PST) Received: from localhost ([::1]:50228 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSH9C-0002gn-Mx for importer@patchew.org; Thu, 10 Mar 2022 06:39:58 -0500 Received: from eggs.gnu.org ([209.51.188.92]:50636) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGxG-00055C-PQ for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:38 -0500 Received: from [2607:f8b0:4864:20::42f] (port=33513 helo=mail-pf1-x42f.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGxF-0007w0-6R for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:38 -0500 Received: by mail-pf1-x42f.google.com with SMTP id s42so4889778pfg.0 for ; Thu, 10 Mar 2022 03:27:36 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.27.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:27:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hT9+kz2FAkTBjPGP7wP7XlOIGomdVd803xe/PZq0Q4s=; b=bWeHWB3vjwbcZuJKqb7uF2HS60ggyIyHzls7IPzcRjRK9xxeKLRxRdWHhMuy+NNt6U vK8sjn1QWLsjA8sII0yg0LSIXaYoFFaRkmoXKJaaPeOcNYzv4KT80BX+a/xvcoR5dyDl zwrLeOG5mjRGasLC0MWsfjkc0XebbhCumbunuONl2IO6t2u8HufxYZitGon1WWlMXrFD IVDZPbDBWhBqM3ncR8h85YMFCkBuw5Onkjfk6VXXyDckB19MZIGUGAunfY64CXQPJsek DiMuMYzDcXzs1cW3ufOlz5fZ1Z48jxR+Ja8elMJq5T2uXQZPmDSlNRafNfd/t9wXSjgD jBkw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hT9+kz2FAkTBjPGP7wP7XlOIGomdVd803xe/PZq0Q4s=; b=4MdOQFJBShuiiPQDK2R25BN9ZCjOb47jXvp8dyYW046cn8Avd6qMlg5uumb29sNnb+ hy4KHUu0xjN5OiXsP/XKHZIEziOiX/bMU3WPvNv4QxE8Qr2R3kKx/WO1X/BYzgoQQDu9 jGPDRVUka4aHVyRStSJJ6h0k9Q61iGPwPVF3mumnt4b4Rmbb9Wzh89+JGoHZIsJEraEl +6n2vvkk+kGAjY4S7EbklDKrz2f7VY6/Vec2rGDgmyqGrQ8bBcdgEfOVEOPRxCUKmMEW RexbdM9Qjuj9duJ6Io1hkavSuZCR53fhp+N69IO61WUSmfZwlrdOHL51lWAyb2eOjgbT fGOg== X-Gm-Message-State: AOAM533pihM4NgPoEQvxW6ynGwgCEQPmWqpsqMwSGfJXIAoR1uqL6Xs4 I5yR1ZiKNTwm3wCp617vhzW/kMj+qUXv1Q== X-Google-Smtp-Source: ABdhPJzY5Yc/zzyNnpafew8AsGJYvj8cOMwzzAmmrEePRi2MzrDvzKlHWAu1/A/q/EeesTrnvX3JQw== X-Received: by 2002:a63:824a:0:b0:37c:94e3:e7de with SMTP id w71-20020a63824a000000b0037c94e3e7demr3723745pgd.496.1646911655857; Thu, 10 Mar 2022 03:27:35 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 08/48] linux-user/nios2: Only initialize SP and PC in target_cpu_copy_regs Date: Thu, 10 Mar 2022 03:26:45 -0800 Message-Id: <20220310112725.570053-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42f (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646912401216100001 Content-Type: text/plain; charset="utf-8" Drop the set of estatus in init_thread; it was clearly intended to be setting the value of CR_STATUS for the application, but we never actually performed that copy. However, the proper value is set in nios2_cpu_reset so we don't need to do anything here. We only initialize SP and EA in init_thread, there's no value in copying other uninitialized data into ENV. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- linux-user/elfload.c | 1 - linux-user/nios2/cpu_loop.c | 22 ---------------------- 2 files changed, 23 deletions(-) diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 23ff9659a5..8c85c933b7 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1096,7 +1096,6 @@ static void init_thread(struct target_pt_regs *regs, = struct image_info *infop) { regs->ea =3D infop->entry; regs->sp =3D infop->start_stack; - regs->estatus =3D 0x3; } =20 #define LO_COMMPAGE TARGET_PAGE_SIZE diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index 7b20c024db..fa234cb2af 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -132,28 +132,6 @@ void cpu_loop(CPUNios2State *env) =20 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { - env->regs[0] =3D 0; - env->regs[1] =3D regs->r1; - env->regs[2] =3D regs->r2; - env->regs[3] =3D regs->r3; - env->regs[4] =3D regs->r4; - env->regs[5] =3D regs->r5; - env->regs[6] =3D regs->r6; - env->regs[7] =3D regs->r7; - env->regs[8] =3D regs->r8; - env->regs[9] =3D regs->r9; - env->regs[10] =3D regs->r10; - env->regs[11] =3D regs->r11; - env->regs[12] =3D regs->r12; - env->regs[13] =3D regs->r13; - env->regs[14] =3D regs->r14; - env->regs[15] =3D regs->r15; - /* TODO: unsigned long orig_r2; */ - env->regs[R_RA] =3D regs->ra; - env->regs[R_FP] =3D regs->fp; env->regs[R_SP] =3D regs->sp; - env->regs[R_GP] =3D regs->gp; - env->regs[CR_ESTATUS] =3D regs->estatus; env->pc =3D regs->ea; - /* TODO: unsigned long orig_r7; */ } --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646913690152691.3257372409208; Thu, 10 Mar 2022 04:01:30 -0800 (PST) Received: from localhost ([::1]:51550 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHU0-0000QG-RU for importer@patchew.org; Thu, 10 Mar 2022 07:01:28 -0500 Received: from eggs.gnu.org ([209.51.188.92]:50648) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGxH-00057e-MG for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:39 -0500 Received: from [2607:f8b0:4864:20::435] (port=38551 helo=mail-pf1-x435.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGxG-0007w9-0h for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:39 -0500 Received: by mail-pf1-x435.google.com with SMTP id f8so4847757pfj.5 for ; Thu, 10 Mar 2022 03:27:37 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.27.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:27:36 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Cj1Mv1TK+d1R4GNVLpYWtLlcIcx/OqQSWvfjy4IfC40=; b=TyNW+pRTW0n2lRdUpmRyrzv2a63QvMUHFkGeDvKbCpKE3RLEBRmaE6MMfJYeAryjxu V+J5+44WMIL7FWT7BVfvG4VcWGtrhNZa+i+yoX1pDNw8swhoULgwCGvlhNiV+BZtWdNI PjqdkJossw9DmX4fA6/PiR8/sVweL610j3czGq2gXzYOVMaKv/ZLYNmGy2l+DQEMCQlF sIjShuN+H6/SsWNFPugCPvxJQXbdx2+yoY/NdUfmSIAOx0w1PvZWc5Duq4Mew9GFoPfD W953yDjgssbrlzTtdt9M66FjCo+DYXsnPd0SQCwXI2EMSDTh1fwCQ4MHyKKFiJLp+iXj y33w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Cj1Mv1TK+d1R4GNVLpYWtLlcIcx/OqQSWvfjy4IfC40=; b=BLwhnrQ8zxJnmZ44fGFs2pL6tW/+WD76oONDjIlZPNsOu/P11KXOiZ6yu3/7KmlExD LUFE8dMRfvziX5vfv4s0DkgdPUbfq10GeybW1RVwfI+kifpuWU9d+VxAJtCWvMNY1ers Me7bLMoFJdw9W/8OUGPLMqJ3z8EGsSJumP6bRo+x8llSGInktA2Z9fwvTrTbFHsYI79t KkAJKroPXkGLtQZyUUCZjXLhyUQ8QO9YeeduTXT1raX/IXPa6AHtadXiLJYp+9wcvzu8 zSk4P4oMaALAqEnMggXVKQFcc/+9lxlVovvjLXqJpne9ll7q600O5ckerU2JAm9iWLOW ED4A== X-Gm-Message-State: AOAM533DtOJVD/nzrQ9nJXg2T/c1DRqN79q8zkdqYI19GNF2BiaH1wiB c1B85PzccfsEJY5TRjputPlR/kDcgUyZKw== X-Google-Smtp-Source: ABdhPJyDjxkQToW8JUQdOHJgZBlraLjpOzpAHqn7zU3Pluxp+CoPpYYeUrRqWRknmxpDd3XmlaP7xg== X-Received: by 2002:a63:4403:0:b0:375:6d5b:5aa7 with SMTP id r3-20020a634403000000b003756d5b5aa7mr3578406pga.269.1646911656721; Thu, 10 Mar 2022 03:27:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 09/48] target/nios2: Remove cpu_interrupts_enabled Date: Thu, 10 Mar 2022 03:26:46 -0800 Message-Id: <20220310112725.570053-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::435 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646913690789100001 Content-Type: text/plain; charset="utf-8" This function is unused. The real computation of this value is located in nios2_cpu_exec_interrupt. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 5 ----- 1 file changed, 5 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 9be128d63a..59e950dae6 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -226,11 +226,6 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, bool probe, uintptr_t retaddr); #endif =20 -static inline int cpu_interrupts_enabled(CPUNios2State *env) -{ - return env->regs[CR_STATUS] & CR_STATUS_PIE; -} - typedef CPUNios2State CPUArchState; typedef Nios2CPU ArchCPU; =20 --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646913842051498.7422344529027; Thu, 10 Mar 2022 04:04:02 -0800 (PST) Received: from localhost ([::1]:58058 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHWS-0004ux-Mx for importer@patchew.org; Thu, 10 Mar 2022 07:04:00 -0500 Received: from eggs.gnu.org ([209.51.188.92]:50684) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGxJ-0005EV-Uf for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:41 -0500 Received: from [2607:f8b0:4864:20::1031] (port=52820 helo=mail-pj1-x1031.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGxH-0007wT-9a for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:41 -0500 Received: by mail-pj1-x1031.google.com with SMTP id v4so4972215pjh.2 for ; Thu, 10 Mar 2022 03:27:38 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.27.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:27:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ODzUuO9Bo/dCZ/z6T/TQX0tDH/2DhM3+AVV8gLtx3XM=; b=eVWoLQwyg/RcC3ZBEEuEfTKXmo47wvJ3WOpnTwuKSOYvIJ6UiM/F16enk8wFrvyrB8 VoKb6KmgNgbeWIKdFNobV9hNvFb4QJUNniTWHsLvLfKKCeQJRG3ED77hmoyCGxOlQQv6 cNtwCWDIi0OwIBHfVyfpr4vh5GXrQlNBmYcjmWgJlX7g1MTjDSuzVOCKvWLLa3ATfxXG Fuz9G6fEUBamXbdYpK8OW3B++SFjgWuff0Vk5PN05tjtqcKWs7k9iVyulAxnk2/tls7t PtCCG3oKUQV4ATPxFbmpHS/jMxbgynKrDClhzcPJxKaCWS1K4WL0/jc2oqBzIHH2oKv/ lPyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ODzUuO9Bo/dCZ/z6T/TQX0tDH/2DhM3+AVV8gLtx3XM=; b=YfQkoFd8MLEAu8NCgjM2uR6tEhzxjin04reWe5+xjXFYkLqyOXSfU3AslFrj4AlS7g YL7WkCKdXJu6FoZGtsgEyfSMVYMKcN8tpGVhpWUB6D0VpQMeG8YJLQ3A0Hn6zlj7PCO1 HHu+pSfnypzAuze7SO4gvcgoI4kXgu2T9AbmRm8IBSIIzRMz7Yj6xF+3v7GIdfR6v9su md2slqj+2vA+efYGpPjU+5rBz3mRukDl+Jn0MFRb4zIoQ5H1b3lM1zcu/qyRXEEtrdDb BVXKNIMMLOJAraK3RxGcwFVjSCiYYggV3SXxwClhgpGx15JB/qUxV9kuqDef87WcLGeD Z6DQ== X-Gm-Message-State: AOAM530cCbsoKK9YxkoE2qjrbSc4rPaWxz879q5NoPQ04tPYPO5wfRah bXtHA9be0ZyshZCvVGi8TSetYE+rBOuoNQ== X-Google-Smtp-Source: ABdhPJzwqBNQ7GReTH9wBQTtYEHaM81sxuwMDKUXFYYE6S94SHO5oBT5GQL1nWdrdea0uBpetEsFJg== X-Received: by 2002:a17:90b:38c9:b0:1bf:8668:9399 with SMTP id nn9-20020a17090b38c900b001bf86689399mr15145597pjb.87.1646911657897; Thu, 10 Mar 2022 03:27:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 10/48] target/nios2: Split control registers away from general registers Date: Thu, 10 Mar 2022 03:26:47 -0800 Message-Id: <20220310112725.570053-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1031 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646913842823100001 Content-Type: text/plain; charset="utf-8" Place the control registers into their own array, env->ctrl[]. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 43 ++++++++-------- target/nios2/cpu.c | 19 +++---- target/nios2/helper.c | 106 +++++++++++++++++++-------------------- target/nios2/mmu.c | 26 +++++----- target/nios2/op_helper.c | 2 +- target/nios2/translate.c | 35 +++++++------ 6 files changed, 118 insertions(+), 113 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 59e950dae6..1bcbc9ed63 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -59,9 +59,6 @@ struct Nios2CPUClass { #define NUM_GP_REGS 32 #define NUM_CR_REGS 32 =20 -/* GP regs + CR regs */ -#define NUM_CORE_REGS (NUM_GP_REGS + NUM_CR_REGS) - /* General purpose register aliases */ #define R_ZERO 0 #define R_AT 1 @@ -81,8 +78,7 @@ struct Nios2CPUClass { #define R_RA 31 =20 /* Control register aliases */ -#define CR_BASE NUM_GP_REGS -#define CR_STATUS (CR_BASE + 0) +#define CR_STATUS 0 #define CR_STATUS_PIE (1 << 0) #define CR_STATUS_U (1 << 1) #define CR_STATUS_EH (1 << 2) @@ -92,19 +88,19 @@ struct Nios2CPUClass { #define CR_STATUS_PRS (63 << 16) #define CR_STATUS_NMI (1 << 22) #define CR_STATUS_RSIE (1 << 23) -#define CR_ESTATUS (CR_BASE + 1) -#define CR_BSTATUS (CR_BASE + 2) -#define CR_IENABLE (CR_BASE + 3) -#define CR_IPENDING (CR_BASE + 4) -#define CR_CPUID (CR_BASE + 5) -#define CR_CTL6 (CR_BASE + 6) -#define CR_EXCEPTION (CR_BASE + 7) -#define CR_PTEADDR (CR_BASE + 8) +#define CR_ESTATUS 1 +#define CR_BSTATUS 2 +#define CR_IENABLE 3 +#define CR_IPENDING 4 +#define CR_CPUID 5 +#define CR_CTL6 6 +#define CR_EXCEPTION 7 +#define CR_PTEADDR 8 #define CR_PTEADDR_PTBASE_SHIFT 22 #define CR_PTEADDR_PTBASE_MASK (0x3FF << CR_PTEADDR_PTBASE_SHIFT) #define CR_PTEADDR_VPN_SHIFT 2 #define CR_PTEADDR_VPN_MASK (0xFFFFF << CR_PTEADDR_VPN_SHIFT) -#define CR_TLBACC (CR_BASE + 9) +#define CR_TLBACC 9 #define CR_TLBACC_IGN_SHIFT 25 #define CR_TLBACC_IGN_MASK (0x7F << CR_TLBACC_IGN_SHIFT) #define CR_TLBACC_C (1 << 24) @@ -113,7 +109,7 @@ struct Nios2CPUClass { #define CR_TLBACC_X (1 << 21) #define CR_TLBACC_G (1 << 20) #define CR_TLBACC_PFN_MASK 0x000FFFFF -#define CR_TLBMISC (CR_BASE + 10) +#define CR_TLBMISC 10 #define CR_TLBMISC_WAY_SHIFT 20 #define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT) #define CR_TLBMISC_RD (1 << 19) @@ -124,11 +120,11 @@ struct Nios2CPUClass { #define CR_TLBMISC_BAD (1 << 2) #define CR_TLBMISC_PERM (1 << 1) #define CR_TLBMISC_D (1 << 0) -#define CR_ENCINJ (CR_BASE + 11) -#define CR_BADADDR (CR_BASE + 12) -#define CR_CONFIG (CR_BASE + 13) -#define CR_MPUBASE (CR_BASE + 14) -#define CR_MPUACC (CR_BASE + 15) +#define CR_ENCINJ 11 +#define CR_BADADDR 12 +#define CR_CONFIG 13 +#define CR_MPUBASE 14 +#define CR_MPUACC 15 =20 /* Exceptions */ #define EXCP_BREAK 0x1000 @@ -154,7 +150,8 @@ struct Nios2CPUClass { #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 =20 struct CPUArchState { - uint32_t regs[NUM_CORE_REGS]; + uint32_t regs[NUM_GP_REGS]; + uint32_t ctrl[NUM_CR_REGS]; uint32_t pc; =20 #if !defined(CONFIG_USER_ONLY) @@ -212,7 +209,7 @@ void do_nios2_semihosting(CPUNios2State *env); =20 static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch) { - return (env->regs[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX : + return (env->ctrl[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX : MMU_SUPERVISOR_IDX; } =20 @@ -236,7 +233,7 @@ static inline void cpu_get_tb_cpu_state(CPUNios2State *= env, target_ulong *pc, { *pc =3D env->pc; *cs_base =3D 0; - *flags =3D (env->regs[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U)); + *flags =3D env->ctrl[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U); } =20 #endif /* NIOS2_CPU_H */ diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 40031c9f20..182ddcc18f 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -53,14 +53,15 @@ static void nios2_cpu_reset(DeviceState *dev) =20 ncc->parent_reset(dev); =20 - memset(env->regs, 0, sizeof(uint32_t) * NUM_CORE_REGS); + memset(env->regs, 0, sizeof(env->regs)); + memset(env->ctrl, 0, sizeof(env->ctrl)); env->pc =3D cpu->reset_addr; =20 #if defined(CONFIG_USER_ONLY) /* Start in user mode with interrupts enabled. */ - env->regs[CR_STATUS] =3D CR_STATUS_U | CR_STATUS_PIE; + env->ctrl[CR_STATUS] =3D CR_STATUS_U | CR_STATUS_PIE; #else - env->regs[CR_STATUS] =3D 0; + env->ctrl[CR_STATUS] =3D 0; #endif } =20 @@ -71,9 +72,9 @@ static void nios2_cpu_set_irq(void *opaque, int irq, int = level) CPUNios2State *env =3D &cpu->env; CPUState *cs =3D CPU(cpu); =20 - env->regs[CR_IPENDING] =3D deposit32(env->regs[CR_IPENDING], irq, 1, != !level); + env->ctrl[CR_IPENDING] =3D deposit32(env->ctrl[CR_IPENDING], irq, 1, != !level); =20 - if (env->regs[CR_IPENDING]) { + if (env->ctrl[CR_IPENDING]) { cpu_interrupt(cs, CPU_INTERRUPT_HARD); } else { cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); @@ -131,8 +132,8 @@ static bool nios2_cpu_exec_interrupt(CPUState *cs, int = interrupt_request) CPUNios2State *env =3D &cpu->env; =20 if ((interrupt_request & CPU_INTERRUPT_HARD) && - (env->regs[CR_STATUS] & CR_STATUS_PIE) && - (env->regs[CR_IPENDING] & env->regs[CR_IENABLE])) { + (env->ctrl[CR_STATUS] & CR_STATUS_PIE) && + (env->ctrl[CR_IPENDING] & env->ctrl[CR_IENABLE])) { cs->exception_index =3D EXCP_IRQ; nios2_cpu_do_interrupt(cs); return true; @@ -163,7 +164,7 @@ static int nios2_cpu_gdb_read_register(CPUState *cs, GB= yteArray *mem_buf, int n) } else if (n =3D=3D 32) { /* PC */ return gdb_get_reg32(mem_buf, env->pc); } else if (n < 49) { /* Status regs */ - return gdb_get_reg32(mem_buf, env->regs[n - 1]); + return gdb_get_reg32(mem_buf, env->ctrl[n - 33]); } =20 /* Invalid regs */ @@ -185,7 +186,7 @@ static int nios2_cpu_gdb_write_register(CPUState *cs, u= int8_t *mem_buf, int n) } else if (n =3D=3D 32) { /* PC */ env->pc =3D ldl_p(mem_buf); } else if (n < 49) { /* Status regs */ - env->regs[n - 1] =3D ldl_p(mem_buf); + env->ctrl[n - 33] =3D ldl_p(mem_buf); } =20 return 4; diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 31cec29e89..90f918524e 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -56,38 +56,38 @@ void nios2_cpu_do_interrupt(CPUState *cs) =20 switch (cs->exception_index) { case EXCP_IRQ: - assert(env->regs[CR_STATUS] & CR_STATUS_PIE); + assert(env->ctrl[CR_STATUS] & CR_STATUS_PIE); =20 qemu_log_mask(CPU_LOG_INT, "interrupt at pc=3D%x\n", env->pc); =20 - env->regs[CR_ESTATUS] =3D env->regs[CR_STATUS]; - env->regs[CR_STATUS] |=3D CR_STATUS_IH; - env->regs[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); + env->ctrl[CR_ESTATUS] =3D env->ctrl[CR_STATUS]; + env->ctrl[CR_STATUS] |=3D CR_STATUS_IH; + env->ctrl[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); =20 - env->regs[CR_EXCEPTION] &=3D ~(0x1F << 2); - env->regs[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] &=3D ~(0x1F << 2); + env->ctrl[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; =20 env->regs[R_EA] =3D env->pc + 4; env->pc =3D cpu->exception_addr; break; =20 case EXCP_TLBD: - if ((env->regs[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { + if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=3D%x\n", env= ->pc); =20 /* Fast TLB miss */ /* Variation from the spec. Table 3-35 of the cpu reference sh= ows * estatus not being changed for TLB miss but this appears to * be incorrect. */ - env->regs[CR_ESTATUS] =3D env->regs[CR_STATUS]; - env->regs[CR_STATUS] |=3D CR_STATUS_EH; - env->regs[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); + env->ctrl[CR_ESTATUS] =3D env->ctrl[CR_STATUS]; + env->ctrl[CR_STATUS] |=3D CR_STATUS_EH; + env->ctrl[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); =20 - env->regs[CR_EXCEPTION] &=3D ~(0x1F << 2); - env->regs[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] &=3D ~(0x1F << 2); + env->ctrl[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; =20 - env->regs[CR_TLBMISC] &=3D ~CR_TLBMISC_DBL; - env->regs[CR_TLBMISC] |=3D CR_TLBMISC_WR; + env->ctrl[CR_TLBMISC] &=3D ~CR_TLBMISC_DBL; + env->ctrl[CR_TLBMISC] |=3D CR_TLBMISC_WR; =20 env->regs[R_EA] =3D env->pc + 4; env->pc =3D cpu->fast_tlb_miss_addr; @@ -95,13 +95,13 @@ void nios2_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=3D%x\n", e= nv->pc); =20 /* Double TLB miss */ - env->regs[CR_STATUS] |=3D CR_STATUS_EH; - env->regs[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); + env->ctrl[CR_STATUS] |=3D CR_STATUS_EH; + env->ctrl[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); =20 - env->regs[CR_EXCEPTION] &=3D ~(0x1F << 2); - env->regs[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] &=3D ~(0x1F << 2); + env->ctrl[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; =20 - env->regs[CR_TLBMISC] |=3D CR_TLBMISC_DBL; + env->ctrl[CR_TLBMISC] |=3D CR_TLBMISC_DBL; =20 env->pc =3D cpu->exception_addr; } @@ -112,15 +112,15 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_TLBX: qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=3D%x\n", env->pc); =20 - env->regs[CR_ESTATUS] =3D env->regs[CR_STATUS]; - env->regs[CR_STATUS] |=3D CR_STATUS_EH; - env->regs[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); + env->ctrl[CR_ESTATUS] =3D env->ctrl[CR_STATUS]; + env->ctrl[CR_STATUS] |=3D CR_STATUS_EH; + env->ctrl[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); =20 - env->regs[CR_EXCEPTION] &=3D ~(0x1F << 2); - env->regs[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] &=3D ~(0x1F << 2); + env->ctrl[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; =20 - if ((env->regs[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { - env->regs[CR_TLBMISC] |=3D CR_TLBMISC_WR; + if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { + env->ctrl[CR_TLBMISC] |=3D CR_TLBMISC_WR; } =20 env->regs[R_EA] =3D env->pc + 4; @@ -132,16 +132,16 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_SUPERD: qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=3D%x\n", en= v->pc); =20 - if ((env->regs[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { - env->regs[CR_ESTATUS] =3D env->regs[CR_STATUS]; + if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { + env->ctrl[CR_ESTATUS] =3D env->ctrl[CR_STATUS]; env->regs[R_EA] =3D env->pc + 4; } =20 - env->regs[CR_STATUS] |=3D CR_STATUS_EH; - env->regs[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); + env->ctrl[CR_STATUS] |=3D CR_STATUS_EH; + env->ctrl[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); =20 - env->regs[CR_EXCEPTION] &=3D ~(0x1F << 2); - env->regs[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] &=3D ~(0x1F << 2); + env->ctrl[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; =20 env->pc =3D cpu->exception_addr; break; @@ -150,16 +150,16 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_TRAP: qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=3D%x\n", env->pc); =20 - if ((env->regs[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { - env->regs[CR_ESTATUS] =3D env->regs[CR_STATUS]; + if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { + env->ctrl[CR_ESTATUS] =3D env->ctrl[CR_STATUS]; env->regs[R_EA] =3D env->pc + 4; } =20 - env->regs[CR_STATUS] |=3D CR_STATUS_EH; - env->regs[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); + env->ctrl[CR_STATUS] |=3D CR_STATUS_EH; + env->ctrl[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); =20 - env->regs[CR_EXCEPTION] &=3D ~(0x1F << 2); - env->regs[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] &=3D ~(0x1F << 2); + env->ctrl[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; =20 env->pc =3D cpu->exception_addr; break; @@ -175,16 +175,16 @@ void nios2_cpu_do_interrupt(CPUState *cs) break; } =20 - if ((env->regs[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { - env->regs[CR_BSTATUS] =3D env->regs[CR_STATUS]; + if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { + env->ctrl[CR_BSTATUS] =3D env->ctrl[CR_STATUS]; env->regs[R_BA] =3D env->pc + 4; } =20 - env->regs[CR_STATUS] |=3D CR_STATUS_EH; - env->regs[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); + env->ctrl[CR_STATUS] |=3D CR_STATUS_EH; + env->ctrl[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); =20 - env->regs[CR_EXCEPTION] &=3D ~(0x1F << 2); - env->regs[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] &=3D ~(0x1F << 2); + env->ctrl[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; =20 env->pc =3D cpu->exception_addr; break; @@ -227,8 +227,8 @@ void nios2_cpu_do_unaligned_access(CPUState *cs, vaddr = addr, Nios2CPU *cpu =3D NIOS2_CPU(cs); CPUNios2State *env =3D &cpu->env; =20 - env->regs[CR_BADADDR] =3D addr; - env->regs[CR_EXCEPTION] =3D EXCP_UNALIGN << 2; + env->ctrl[CR_BADADDR] =3D addr; + env->ctrl[CR_EXCEPTION] =3D EXCP_UNALIGN << 2; helper_raise_exception(env, EXCP_UNALIGN); } =20 @@ -266,7 +266,7 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, return false; } cs->exception_index =3D EXCP_SUPERA; - env->regs[CR_BADADDR] =3D address; + env->ctrl[CR_BADADDR] =3D address; cpu_loop_exit_restore(cs, retaddr); } } @@ -295,16 +295,16 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, } =20 if (access_type =3D=3D MMU_INST_FETCH) { - env->regs[CR_TLBMISC] &=3D ~CR_TLBMISC_D; + env->ctrl[CR_TLBMISC] &=3D ~CR_TLBMISC_D; } else { - env->regs[CR_TLBMISC] |=3D CR_TLBMISC_D; + env->ctrl[CR_TLBMISC] |=3D CR_TLBMISC_D; } - env->regs[CR_PTEADDR] &=3D CR_PTEADDR_PTBASE_MASK; - env->regs[CR_PTEADDR] |=3D (address >> 10) & CR_PTEADDR_VPN_MASK; - env->mmu.pteaddr_wr =3D env->regs[CR_PTEADDR]; + env->ctrl[CR_PTEADDR] &=3D CR_PTEADDR_PTBASE_MASK; + env->ctrl[CR_PTEADDR] |=3D (address >> 10) & CR_PTEADDR_VPN_MASK; + env->mmu.pteaddr_wr =3D env->ctrl[CR_PTEADDR]; =20 cs->exception_index =3D excp; - env->regs[CR_BADADDR] =3D address; + env->ctrl[CR_BADADDR] =3D address; cpu_loop_exit_restore(cs, retaddr); } #endif /* !CONFIG_USER_ONLY */ diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 4daab2a7ab..95900724e8 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -95,8 +95,8 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t= v) v & CR_TLBACC_PFN_MASK); =20 /* if tlbmisc.WE =3D=3D 1 then trigger a TLB write on writes to TLBACC= */ - if (env->regs[CR_TLBMISC] & CR_TLBMISC_WR) { - int way =3D (env->regs[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT); + if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WR) { + int way =3D (env->ctrl[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT); int vpn =3D (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2; int pid =3D (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; int g =3D (v & CR_TLBACC_G) ? 1 : 0; @@ -117,8 +117,8 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32= _t v) entry->data =3D newData; } /* Auto-increment tlbmisc.WAY */ - env->regs[CR_TLBMISC] =3D - (env->regs[CR_TLBMISC] & ~CR_TLBMISC_WAY_MASK) | + env->ctrl[CR_TLBMISC] =3D + (env->ctrl[CR_TLBMISC] & ~CR_TLBMISC_WAY_MASK) | (((way + 1) & (cpu->tlb_num_ways - 1)) << CR_TLBMISC_WAY_SHIFT); } @@ -153,17 +153,17 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uin= t32_t v) &env->mmu.tlb[(way * cpu->tlb_num_ways) + (vpn & env->mmu.tlb_entry_mask)]; =20 - env->regs[CR_TLBACC] &=3D CR_TLBACC_IGN_MASK; - env->regs[CR_TLBACC] |=3D entry->data; - env->regs[CR_TLBACC] |=3D (entry->tag & (1 << 11)) ? CR_TLBACC_G := 0; - env->regs[CR_TLBMISC] =3D + env->ctrl[CR_TLBACC] &=3D CR_TLBACC_IGN_MASK; + env->ctrl[CR_TLBACC] |=3D entry->data; + env->ctrl[CR_TLBACC] |=3D (entry->tag & (1 << 11)) ? CR_TLBACC_G := 0; + env->ctrl[CR_TLBMISC] =3D (v & ~CR_TLBMISC_PID_MASK) | ((entry->tag & ((1 << cpu->pid_num_bits) - 1)) << CR_TLBMISC_PID_SHIFT); - env->regs[CR_PTEADDR] &=3D ~CR_PTEADDR_VPN_MASK; - env->regs[CR_PTEADDR] |=3D (entry->tag >> 12) << CR_PTEADDR_VPN_SH= IFT; + env->ctrl[CR_PTEADDR] &=3D ~CR_PTEADDR_VPN_MASK; + env->ctrl[CR_PTEADDR] |=3D (entry->tag >> 12) << CR_PTEADDR_VPN_SH= IFT; } else { - env->regs[CR_TLBMISC] =3D v; + env->ctrl[CR_TLBMISC] =3D v; } =20 env->mmu.tlbmisc_wr =3D v; @@ -175,8 +175,8 @@ void helper_mmu_write_pteaddr(CPUNios2State *env, uint3= 2_t v) (v & CR_PTEADDR_VPN_MASK) >> CR_PTEADDR_= VPN_SHIFT); =20 /* Writes to PTEADDR don't change the read-back VPN value */ - env->regs[CR_PTEADDR] =3D (v & ~CR_PTEADDR_VPN_MASK) | - (env->regs[CR_PTEADDR] & CR_PTEADDR_VPN_MASK); + env->ctrl[CR_PTEADDR] =3D ((v & ~CR_PTEADDR_VPN_MASK) | + (env->ctrl[CR_PTEADDR] & CR_PTEADDR_VPN_MASK)= ); env->mmu.pteaddr_wr =3D v; } =20 diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index ee5ad8b23f..08ed3b4598 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -34,7 +34,7 @@ void helper_raise_exception(CPUNios2State *env, uint32_t = index) #ifndef CONFIG_USER_ONLY void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc) { - env->regs[CR_STATUS] =3D new_status; + env->ctrl[CR_STATUS] =3D new_status; env->pc =3D new_pc; cpu_loop_exit(env_cpu(env)); } diff --git a/target/nios2/translate.c b/target/nios2/translate.c index e6e9a5ac6f..2e486651f5 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -395,7 +395,7 @@ static void eret(DisasContext *dc, uint32_t code, uint3= 2_t flags) g_assert_not_reached(); #else TCGv tmp =3D tcg_temp_new(); - tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, regs[CR_ESTATUS])); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_ESTATUS])); gen_helper_eret(cpu_env, tmp, cpu_R[R_EA]); tcg_temp_free(tmp); =20 @@ -425,7 +425,7 @@ static void bret(DisasContext *dc, uint32_t code, uint3= 2_t flags) g_assert_not_reached(); #else TCGv tmp =3D tcg_temp_new(); - tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, regs[CR_BSTATUS])); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_BSTATUS])); gen_helper_eret(cpu_env, tmp, cpu_R[R_BA]); tcg_temp_free(tmp); =20 @@ -481,7 +481,7 @@ static void rdctl(DisasContext *dc, uint32_t code, uint= 32_t flags) return; } =20 - switch (instr.imm5 + CR_BASE) { + switch (instr.imm5) { case CR_IPENDING: /* * The value of the ipending register is synthetic. @@ -493,17 +493,15 @@ static void rdctl(DisasContext *dc, uint32_t code, ui= nt32_t flags) */ t1 =3D tcg_temp_new(); t2 =3D tcg_temp_new(); - tcg_gen_ld_tl(t1, cpu_env, - offsetof(CPUNios2State, regs[CR_IPENDING])); - tcg_gen_ld_tl(t2, cpu_env, - offsetof(CPUNios2State, regs[CR_IENABLE])); + tcg_gen_ld_tl(t1, cpu_env, offsetof(CPUNios2State, ctrl[CR_IPENDIN= G])); + tcg_gen_ld_tl(t2, cpu_env, offsetof(CPUNios2State, ctrl[CR_IENABLE= ])); tcg_gen_and_tl(cpu_R[instr.c], t1, t2); tcg_temp_free(t1); tcg_temp_free(t2); break; default: tcg_gen_ld_tl(cpu_R[instr.c], cpu_env, - offsetof(CPUNios2State, regs[instr.imm5 + CR_BASE])); + offsetof(CPUNios2State, ctrl[instr.imm5])); break; } } @@ -521,7 +519,7 @@ static void wrctl(DisasContext *dc, uint32_t code, uint= 32_t flags) R_TYPE(instr, code); TCGv v =3D load_gpr(dc, instr.a); =20 - switch (instr.imm5 + CR_BASE) { + switch (instr.imm5) { case CR_PTEADDR: gen_helper_mmu_write_pteaddr(cpu_env, v); break; @@ -541,7 +539,7 @@ static void wrctl(DisasContext *dc, uint32_t code, uint= 32_t flags) /* fall through */ default: tcg_gen_st_tl(v, cpu_env, - offsetof(CPUNios2State, regs[instr.imm5 + CR_BASE])); + offsetof(CPUNios2State, ctrl[instr.imm5])); break; } #endif @@ -774,7 +772,7 @@ illegal_op: t_gen_helper_raise_exception(dc, EXCP_ILLEGAL); } =20 -static const char * const regnames[NUM_CORE_REGS] =3D { +static const char * const gr_regnames[NUM_GP_REGS] =3D { "zero", "at", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", @@ -783,6 +781,9 @@ static const char * const regnames[NUM_CORE_REGS] =3D { "r20", "r21", "r22", "r23", "et", "bt", "gp", "sp", "fp", "ea", "ba", "ra", +}; + +static const char * const cr_regnames[NUM_CR_REGS] =3D { "status", "estatus", "bstatus", "ienable", "ipending", "cpuid", "reserved0", "exception", "pteaddr", "tlbacc", "tlbmisc", "reserved1", @@ -909,8 +910,14 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int f= lags) =20 qemu_fprintf(f, "IN: PC=3D%x %s\n", env->pc, lookup_symbol(env->pc)); =20 - for (i =3D 0; i < NUM_CORE_REGS; i++) { - qemu_fprintf(f, "%9s=3D%8.8x ", regnames[i], env->regs[i]); + for (i =3D 0; i < NUM_GP_REGS; i++) { + qemu_fprintf(f, "%9s=3D%8.8x ", gr_regnames[i], env->regs[i]); + if ((i + 1) % 4 =3D=3D 0) { + qemu_fprintf(f, "\n"); + } + } + for (i =3D 0; i < NUM_CR_REGS; i++) { + qemu_fprintf(f, "%9s=3D%8.8x ", cr_regnames[i], env->ctrl[i]); if ((i + 1) % 4 =3D=3D 0) { qemu_fprintf(f, "\n"); } @@ -931,7 +938,7 @@ void nios2_tcg_init(void) for (i =3D 0; i < NUM_GP_REGS; i++) { cpu_R[i] =3D tcg_global_mem_new(cpu_env, offsetof(CPUNios2State, regs[i]), - regnames[i]); + gr_regnames[i]); } cpu_pc =3D tcg_global_mem_new(cpu_env, offsetof(CPUNios2State, pc), "pc"); --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646912572512916.9591965128021; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.27.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:27:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FucOuRxzk9AY38GO4hr3Q5xePPb7ussh8W5FYQ6tFWc=; b=zxPuKA7Hj06xHJ9eBovLJbCbsSSPPteW3CWWNEGxJ1MFPYRQ15Up0u0mCBdHZHGvtO DciqIydZWgrmWTGcihDoJchF1tcbSqvo1dIivGv0lUIWOgRVYMdKnRVlNdAerCi34J9G tsak0K0J7G4FWSONXN2c0NwGsINxFyoOVK1MOk2EFYWWyOmVCBcEMBfxAENo6K/lB/to GlWI0YQUT/YDAO9oOiPvAvC+6ok+9z0xXUQxdUK2spQB1lJa2fAf8cMBA3QinF4rpkAr g1ZKhW0UtEYJNxzOIXvVg0YPe+5iAbkOWnsdBb1KByLHTqDDH607YwabpdbGEdXCfcT0 MO+Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FucOuRxzk9AY38GO4hr3Q5xePPb7ussh8W5FYQ6tFWc=; b=gTWKYaUS4cRWwRrPCtSQvNr+Cq9jg3FV8wQxmGnoDXe4rcRlY7I+akKzo3cQPp6VnI NRnbiMGJb48B4tXLd5JeKU2FhshueyOMTk/kbYqRuAoj7yAseuDmzfF0vPS5vVArDebW d2AeMxObrwH26gQggsvBXE6kcWsQx2wANebkL41oprfhNDaG+yKdpvL68LLgn43TNr0/ ye5p6jph9cj6l4GTX/i58J0gkUbyku2V57uMk/DI7OrJONIOpqaIpuY19FQLeXNW/M76 +ldz4yz0FFYyJPO2IVcymo6RPl+tS7ogiez9MVZMNO6jH5MU7snp9kKjezT3xKafbSfd 4+lQ== X-Gm-Message-State: AOAM5318OI6SF9bjnv105NzXsphI8e6EqG+D02aFORobqC/RODzXMBFe X6D6nf/8GZePg1BZCC8x53zxlwVPMQPZ6g== X-Google-Smtp-Source: ABdhPJyETTV7aVSa2EbYGC6xipv2hloYVX89KXpLx/UgzGgpwB15XTVjJ54A/uEic7qxTlpEgHAgNQ== X-Received: by 2002:a63:34c1:0:b0:380:c330:64c6 with SMTP id b184-20020a6334c1000000b00380c33064c6mr3700460pga.442.1646911659089; Thu, 10 Mar 2022 03:27:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 11/48] target/nios2: Do not zero the general registers on reset Date: Thu, 10 Mar 2022 03:26:48 -0800 Message-Id: <20220310112725.570053-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::434 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646912572937100001 Content-Type: text/plain; charset="utf-8" The bulk of the general register set is undefined on reset. The zero register is for the most part special-cased in translate, but the slot is still exposed to gdbstub and nios2_cpu_dump_state, so continue to make sure that's zeroed. Signed-off-by: Richard Henderson --- target/nios2/cpu.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 182ddcc18f..97bdc0a61b 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -53,16 +53,16 @@ static void nios2_cpu_reset(DeviceState *dev) =20 ncc->parent_reset(dev); =20 - memset(env->regs, 0, sizeof(env->regs)); memset(env->ctrl, 0, sizeof(env->ctrl)); - env->pc =3D cpu->reset_addr; - #if defined(CONFIG_USER_ONLY) /* Start in user mode with interrupts enabled. */ env->ctrl[CR_STATUS] =3D CR_STATUS_U | CR_STATUS_PIE; #else env->ctrl[CR_STATUS] =3D 0; #endif + + env->regs[R_ZERO] =3D 0; + env->pc =3D cpu->reset_addr; } =20 #ifndef CONFIG_USER_ONLY --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646912783712332.28710685870965; Thu, 10 Mar 2022 03:46:23 -0800 (PST) Received: from localhost ([::1]:39086 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHFO-0005nM-ET for importer@patchew.org; Thu, 10 Mar 2022 06:46:22 -0500 Received: from eggs.gnu.org ([209.51.188.92]:50696) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGxK-0005Ge-Q5 for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:42 -0500 Received: from [2607:f8b0:4864:20::102b] (port=35645 helo=mail-pj1-x102b.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGxJ-0007wr-7t for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:42 -0500 Received: by mail-pj1-x102b.google.com with SMTP id mg21-20020a17090b371500b001bef9e4657cso8015301pjb.0 for ; Thu, 10 Mar 2022 03:27:40 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.27.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:27:39 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NO5qDCidg6tXT/kBs+ctrp9mOI+zlSE5VUcpn5RQSbI=; b=Mq0oxVi4HUaSZ9l0SxP5Z2LoFJrv2mz+s/HxKiAVEp/qeJo93dDTlWsohwcdFsZe4W rzybK2xVNehIfg3GyhEjNQBhmY3vUrvV8NskGfvI8EznR0iFSB7CeEonGkrI+8W2+sZa Sy2WskG3gl44gi9fXvsolAieLNWPAZaHSH+W2stOZkIZPhQuDrFajUXgXFR94348kbZN 5OnTOqhH236pASucXt12FNnq7hAkE34S8p8PqdYYbOE6TY88o/wjqSQfoh7acQRBo7tF /awe3sb9g1oIeMBXsI+lf5/9eJ5x01ai7Bi3mb2zWC0z3Fn2Ur2FR2OOhhP++Y/v1JIw l5Uw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NO5qDCidg6tXT/kBs+ctrp9mOI+zlSE5VUcpn5RQSbI=; b=zyib/qOz2JwjhzWos8WwMTa/Uk1f1VTrCKVFj91EYBsWio9767iTmtMpb85mBZxNJ/ rQovL6Yjg+B5zUCwPLKyczyrSnMYcCjrIL3xZkAsVVbknut7itWQxTds+ZyhyA+86agL umRUdisw+lZmUKCudGY3Tsz0A53Rd0v/ASvDqyV0xSsGVk/rWCZ/n+6ToJZ2I4U6R7jp pf4jExfRamh5wOPpwRON49WzObxbdmUb+NcfrS6XS+QLR4Dt2zTybsDpV88pYwYbXhA+ mm1PXMIP2lO64N4eFaQbQyapYX8wuHYGtMC07lsK5+iqpC9JZYRmQoCVDkKvk1L6FMde 1qrg== X-Gm-Message-State: AOAM530SKVIA8PjyoDmhSzW3pJxwzBpni6ffF1rUlkFKU0ywczAx7/hT gIqqjntawZH4HvIPrqFpKnvjzwhBIkpgMQ== X-Google-Smtp-Source: ABdhPJwtyk+vsd4pg58WWkjiEbkElhj+pmR2skMX0Wf2aKt/7TDWdc0oEcDiICzRqhNkMtD0AI4qRw== X-Received: by 2002:a17:902:ab4c:b0:151:eb86:dcb5 with SMTP id ij12-20020a170902ab4c00b00151eb86dcb5mr4470962plb.126.1646911659982; Thu, 10 Mar 2022 03:27:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 12/48] target/nios2: Clean up nios2_cpu_dump_state Date: Thu, 10 Mar 2022 03:26:49 -0800 Message-Id: <20220310112725.570053-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102b (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646912784175100001 Content-Type: text/plain; charset="utf-8" Do not print control registers for user-only mode. Rename reserved control registers to "resN", where N is the control register index. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/translate.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 2e486651f5..45fe2f9a05 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -783,16 +783,18 @@ static const char * const gr_regnames[NUM_GP_REGS] = =3D { "fp", "ea", "ba", "ra", }; =20 +#ifndef CONFIG_USER_ONLY static const char * const cr_regnames[NUM_CR_REGS] =3D { "status", "estatus", "bstatus", "ienable", - "ipending", "cpuid", "reserved0", "exception", + "ipending", "cpuid", "res6", "exception", "pteaddr", "tlbacc", "tlbmisc", "reserved1", "badaddr", "config", "mpubase", "mpuacc", - "reserved2", "reserved3", "reserved4", "reserved5", - "reserved6", "reserved7", "reserved8", "reserved9", - "reserved10", "reserved11", "reserved12", "reserved13", - "reserved14", "reserved15", "reserved16", "reserved17", + "res16", "res17", "res18", "res19", + "res20", "res21", "res22", "res23", + "res24", "res25", "res26", "res27", + "res28", "res29", "res30", "res31", }; +#endif =20 #include "exec/gen-icount.h" =20 @@ -904,10 +906,6 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int f= lags) CPUNios2State *env =3D &cpu->env; int i; =20 - if (!env) { - return; - } - qemu_fprintf(f, "IN: PC=3D%x %s\n", env->pc, lookup_symbol(env->pc)); =20 for (i =3D 0; i < NUM_GP_REGS; i++) { @@ -916,13 +914,14 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int = flags) qemu_fprintf(f, "\n"); } } + +#if !defined(CONFIG_USER_ONLY) for (i =3D 0; i < NUM_CR_REGS; i++) { qemu_fprintf(f, "%9s=3D%8.8x ", cr_regnames[i], env->ctrl[i]); if ((i + 1) % 4 =3D=3D 0) { qemu_fprintf(f, "\n"); } } -#if !defined(CONFIG_USER_ONLY) qemu_fprintf(f, " mmu write: VPN=3D%05X PID %02X TLBACC %08X\n", env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK, (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4, --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646912982628883.9729407959402; Thu, 10 Mar 2022 03:49:42 -0800 (PST) Received: from localhost ([::1]:46814 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHIc-0002iq-Hi for importer@patchew.org; Thu, 10 Mar 2022 06:49:42 -0500 Received: from eggs.gnu.org ([209.51.188.92]:50712) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGxL-0005K0-T2 for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:43 -0500 Received: from [2607:f8b0:4864:20::1034] (port=50878 helo=mail-pj1-x1034.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGxK-0007x0-Cw for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:43 -0500 Received: by mail-pj1-x1034.google.com with SMTP id m22so5002437pja.0 for ; Thu, 10 Mar 2022 03:27:41 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.27.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:27:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Gt6Df7YFZj3yIOaHOAXNxeneFRB5t2HH9HYYGKeZPd8=; b=AQQXji4rnhgAAQr38u97QZIOMNlTdasBbQ7aHHiB8yScDZKedi6AtTrbId/+2BcOCO dN5wqSTiaIBg8UMqHOCHu5CKdm0JDCd1R4IC4v6mGaJdc77XQP2JLJ4yTBbRfHUwvNYt C/Fwc9cY9atZVRMlq7DgpRsJZmn78YUbSI/p5uQ6AG7InqVG3/6kZm78TjCYR7O/tF6Z 87ZqLw9rwQ18H2vRNSJ8K52hrsTiuL+J/c6gnnsgX6frGiTodXbLZLMwzpAeBYxvNNNc p7HjteW6o52zyO1dJB2mxkktP2yen9yAfjtF4zI7kvQVU52agMo+441sWsj3nfeFyTvt UlFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Gt6Df7YFZj3yIOaHOAXNxeneFRB5t2HH9HYYGKeZPd8=; b=pgug3/BGsuh63Wn6NI/HUF5axexjTQ6mz0IRwB84pSK0p1XDtvM6CA6fhP9Y/nMrxq HegeFRbgxu2BbP9gcE2oNkEscPJ/gLcXJzeqbfmLiFm8HZqKoOQtA+tEKd+x9/ox6PC7 EOh8b05LBp+Gx6P9vwoQBCZCHI81Nl4Aztdv4gq85LJaLd3Jk3RZf5CkHTCGDabPlz52 FVJfMhXBXOWrr7oBDE8nltuFrAFdyQDSW3zS/C0ete7sT4zRZ1aMhUKa3AnjdzXMGEQT vQha4ENLBLeTJKkVptaEqDmkK7E6P7GOQfMgYW1UWWPrsoVYKrSuwn3PweeeYOTs9koB 5bwQ== X-Gm-Message-State: AOAM532zdCBnLr2eYTxEwnNFZU8qkWGs+0hJlDlHhcNnEynQBAbGlswl l9p5IJhei/+dkPJoUlv9QYvKt4sQ1zXfZA== X-Google-Smtp-Source: ABdhPJzzidDnMH1OjFqeqiqCPxZODCoyy4Jon5fx97HrswQl1vfNcs7tPH3PF0fBVuOn3hM3/yFXig== X-Received: by 2002:a17:90b:4a07:b0:1bf:b159:185 with SMTP id kk7-20020a17090b4a0700b001bfb1590185mr4537730pjb.65.1646911661058; Thu, 10 Mar 2022 03:27:41 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 13/48] target/nios2: Use hw/registerfields.h for CR_STATUS fields Date: Thu, 10 Mar 2022 03:26:50 -0800 Message-Id: <20220310112725.570053-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1034 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646912984785100001 Content-Type: text/plain; charset="utf-8" Add all fields; retain the helper macros for single bit fields. So far there are no uses of the multi-bit status fields. Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 28 +++++++++++++++++++--------- 1 file changed, 19 insertions(+), 9 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 1bcbc9ed63..ecf8cc929f 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -23,6 +23,7 @@ =20 #include "exec/cpu-defs.h" #include "hw/core/cpu.h" +#include "hw/registerfields.h" #include "qom/object.h" =20 typedef struct CPUArchState CPUNios2State; @@ -79,15 +80,24 @@ struct Nios2CPUClass { =20 /* Control register aliases */ #define CR_STATUS 0 -#define CR_STATUS_PIE (1 << 0) -#define CR_STATUS_U (1 << 1) -#define CR_STATUS_EH (1 << 2) -#define CR_STATUS_IH (1 << 3) -#define CR_STATUS_IL (63 << 4) -#define CR_STATUS_CRS (63 << 10) -#define CR_STATUS_PRS (63 << 16) -#define CR_STATUS_NMI (1 << 22) -#define CR_STATUS_RSIE (1 << 23) + +FIELD(CR_STATUS, PIE, 0, 1) +FIELD(CR_STATUS, U, 1, 1) +FIELD(CR_STATUS, EH, 2, 1) +FIELD(CR_STATUS, IH, 3, 1) +FIELD(CR_STATUS, IL, 4, 6) +FIELD(CR_STATUS, CRS, 10, 6) +FIELD(CR_STATUS, PRS, 16, 6) +FIELD(CR_STATUS, NMI, 22, 1) +FIELD(CR_STATUS, RSIE, 23, 1) + +#define CR_STATUS_PIE R_CR_STATUS_PIE_MASK +#define CR_STATUS_U R_CR_STATUS_U_MASK +#define CR_STATUS_EH R_CR_STATUS_EH_MASK +#define CR_STATUS_IH R_CR_STATUS_IH_MASK +#define CR_STATUS_NMI R_CR_STATUS_NMI_MASK +#define CR_STATUS_RSIE R_CR_STATUS_RSIE_MASK + #define CR_ESTATUS 1 #define CR_BSTATUS 2 #define CR_IENABLE 3 --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646912989834734.1526905115702; Thu, 10 Mar 2022 03:49:49 -0800 (PST) Received: from localhost ([::1]:47326 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHIi-000343-QJ for importer@patchew.org; Thu, 10 Mar 2022 06:49:48 -0500 Received: from eggs.gnu.org ([209.51.188.92]:50734) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGxN-0005Mt-9u for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:45 -0500 Received: from [2607:f8b0:4864:20::102a] (port=37402 helo=mail-pj1-x102a.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGxL-0007xG-DO for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:44 -0500 Received: by mail-pj1-x102a.google.com with SMTP id lj8-20020a17090b344800b001bfaa46bca3so4845809pjb.2 for ; Thu, 10 Mar 2022 03:27:43 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.27.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:27:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8buwJrjtMj1NFA6rdKhvKicQJO4j8m6F/Eaj8v2A0XQ=; b=rpeX2oFdmtOBiqvjxZnpGTTd+MUcOTawUQr2eSvq47qEy3yJlu5klzqVEO4eMSd5e1 uLw8Vb7chgDYw720chxwBgBM9r12CqT6a8EHnqx8xpe5YjFdqpQrosM53mpbErKC3V6I /Ol/zZb4dytC4ap7ssx8jRIX9PpFjNHZtWt6LfrChRh+W2KSLuI9zKRPq4gv4xRTqAws DGLhlts9pfB/FrRxJ78aqcI6MqAjceyiV8iVJJRZ+b9Y/PvrkBZUce7Lqs4l6NVOL981 3kwOs4exPQffmvgC1YYpzTWVafTjxcX0G43GrrUhA27rnzWhvmvrV6Batw/l7/kkBP57 24tg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8buwJrjtMj1NFA6rdKhvKicQJO4j8m6F/Eaj8v2A0XQ=; b=guXNtGAmMUg6qI50sEkLx1ewsb9EjRYAN6C2MVR8I8v/aYpPPXZI2PN+iC9tb+Xs5z c3Q6rKIXe9Ba7zoQK+l0EWhZEUZ9JbHzsIEuJbYKY8f9nrg6+ZViJ1orP3jB1Dtg2Qut WIkCKSkuf/onF9g9dl4VJsBZThzq+lAPOsQyz/usJTEDHh9G/x1437CbLCaTSkfDzvw8 PoYsZL4qtloRQp0xBhGdWPo2DDt6q4BgtN4URy4QYz0aIv6sJP/ZmTBKUZDiaguUSkWW BmG0WT0I10aLl/Zgf5b10l0+c5vD/HemB7EHO/ZARtaJDebFUNaNItfVvLYkxHvRo8Z0 VsDA== X-Gm-Message-State: AOAM531ThWEdOsUoFRnyvpYjg6p9oOntWnHVJ0ix5IIxjL4j6z8Sadth E/yyZOWv+p2Vk1mrNW/E3k2ZB9DViuN01Q== X-Google-Smtp-Source: ABdhPJyXOsfZ/81c5ZZOy3lF3MTSmTZgd9E7wrNApjIgAyZqClly7JN6vQHid+quyZS0EUo+GjFfvw== X-Received: by 2002:a17:902:cec7:b0:151:bb1b:5c9d with SMTP id d7-20020a170902cec700b00151bb1b5c9dmr4535242plg.41.1646911662081; Thu, 10 Mar 2022 03:27:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 14/48] target/nios2: Use hw/registerfields.h for CR_EXCEPTION fields Date: Thu, 10 Mar 2022 03:26:51 -0800 Message-Id: <20220310112725.570053-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102a (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646912991510100001 Content-Type: text/plain; charset="utf-8" Use FIELD_DP32 instead of manual shifting and masking. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/cpu.h | 4 ++++ target/nios2/helper.c | 37 ++++++++++++++++++++++--------------- 2 files changed, 26 insertions(+), 15 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index ecf8cc929f..963cdec161 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -105,6 +105,10 @@ FIELD(CR_STATUS, RSIE, 23, 1) #define CR_CPUID 5 #define CR_CTL6 6 #define CR_EXCEPTION 7 + +FIELD(CR_EXCEPTION, CAUSE, 2, 5) +FIELD(CR_EXCEPTION, ECCFTL, 31, 1) + #define CR_PTEADDR 8 #define CR_PTEADDR_PTBASE_SHIFT 22 #define CR_PTEADDR_PTBASE_MASK (0x3FF << CR_PTEADDR_PTBASE_SHIFT) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 90f918524e..54458a5447 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -64,8 +64,9 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->ctrl[CR_STATUS] |=3D CR_STATUS_IH; env->ctrl[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); =20 - env->ctrl[CR_EXCEPTION] &=3D ~(0x1F << 2); - env->ctrl[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] =3D FIELD_DP32(env->ctrl[CR_EXCEPTION], + CR_EXCEPTION, CAUSE, + cs->exception_index); =20 env->regs[R_EA] =3D env->pc + 4; env->pc =3D cpu->exception_addr; @@ -83,8 +84,9 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->ctrl[CR_STATUS] |=3D CR_STATUS_EH; env->ctrl[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); =20 - env->ctrl[CR_EXCEPTION] &=3D ~(0x1F << 2); - env->ctrl[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] =3D FIELD_DP32(env->ctrl[CR_EXCEPTION], + CR_EXCEPTION, CAUSE, + cs->exception_index); =20 env->ctrl[CR_TLBMISC] &=3D ~CR_TLBMISC_DBL; env->ctrl[CR_TLBMISC] |=3D CR_TLBMISC_WR; @@ -98,8 +100,9 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->ctrl[CR_STATUS] |=3D CR_STATUS_EH; env->ctrl[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); =20 - env->ctrl[CR_EXCEPTION] &=3D ~(0x1F << 2); - env->ctrl[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] =3D FIELD_DP32(env->ctrl[CR_EXCEPTION], + CR_EXCEPTION, CAUSE, + cs->exception_index); =20 env->ctrl[CR_TLBMISC] |=3D CR_TLBMISC_DBL; =20 @@ -116,8 +119,9 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->ctrl[CR_STATUS] |=3D CR_STATUS_EH; env->ctrl[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); =20 - env->ctrl[CR_EXCEPTION] &=3D ~(0x1F << 2); - env->ctrl[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] =3D FIELD_DP32(env->ctrl[CR_EXCEPTION], + CR_EXCEPTION, CAUSE, + cs->exception_index); =20 if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { env->ctrl[CR_TLBMISC] |=3D CR_TLBMISC_WR; @@ -140,8 +144,9 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->ctrl[CR_STATUS] |=3D CR_STATUS_EH; env->ctrl[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); =20 - env->ctrl[CR_EXCEPTION] &=3D ~(0x1F << 2); - env->ctrl[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] =3D FIELD_DP32(env->ctrl[CR_EXCEPTION], + CR_EXCEPTION, CAUSE, + cs->exception_index); =20 env->pc =3D cpu->exception_addr; break; @@ -158,8 +163,9 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->ctrl[CR_STATUS] |=3D CR_STATUS_EH; env->ctrl[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); =20 - env->ctrl[CR_EXCEPTION] &=3D ~(0x1F << 2); - env->ctrl[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] =3D FIELD_DP32(env->ctrl[CR_EXCEPTION], + CR_EXCEPTION, CAUSE, + cs->exception_index); =20 env->pc =3D cpu->exception_addr; break; @@ -183,8 +189,9 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->ctrl[CR_STATUS] |=3D CR_STATUS_EH; env->ctrl[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); =20 - env->ctrl[CR_EXCEPTION] &=3D ~(0x1F << 2); - env->ctrl[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; + env->ctrl[CR_EXCEPTION] =3D FIELD_DP32(env->ctrl[CR_EXCEPTION], + CR_EXCEPTION, CAUSE, + cs->exception_index); =20 env->pc =3D cpu->exception_addr; break; @@ -228,7 +235,7 @@ void nios2_cpu_do_unaligned_access(CPUState *cs, vaddr = addr, CPUNios2State *env =3D &cpu->env; =20 env->ctrl[CR_BADADDR] =3D addr; - env->ctrl[CR_EXCEPTION] =3D EXCP_UNALIGN << 2; + env->ctrl[CR_EXCEPTION] =3D FIELD_DP32(0, CR_EXCEPTION, CAUSE, EXCP_UN= ALIGN); helper_raise_exception(env, EXCP_UNALIGN); } =20 --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646913154795806.6786940396682; Thu, 10 Mar 2022 03:52:34 -0800 (PST) Received: from localhost ([::1]:55700 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHLN-0000Y0-Fd for importer@patchew.org; Thu, 10 Mar 2022 06:52:33 -0500 Received: from eggs.gnu.org ([209.51.188.92]:50742) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGxN-0005PD-VD for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:46 -0500 Received: from [2607:f8b0:4864:20::635] (port=33544 helo=mail-pl1-x635.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGxM-0007xW-AO for qemu-devel@nongnu.org; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.27.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:27:42 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=f9kEO6gPHdFHbcVjWJEx3cRnSvZ1MpAPY6GCaaYYMWU=; b=v8U0sjgFWHyqvmqJGP/YPh3JcCGOqJHBjXqaxDD6pnBcgtV0GI5adzXGXDgnqmJSos NXjmn/UN8cobecQslh9/+UgzBr9ev+OuCaYMKfb3ua2KFXCSj2SanDatw0YS6DAPiH/f l2/KOejZBXxxUdJ75zqPaD00uiz8oSOQyq/v6SRpfulaluqsFJFhOndIwXqpgLEOQCov O7oT827s9Y0wQ/SHOzFLN0ruoVYFC1zYluU8y4mNtJlzlpLXDnVen88xIXarTfPOzzBY 3aMP5Q6kM5fUvGRa7z7RqB/uSdLb0JGREvSBl/zCyYh1Xib86ucA26pfaYJWWp/8nhWu AfQA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=f9kEO6gPHdFHbcVjWJEx3cRnSvZ1MpAPY6GCaaYYMWU=; b=ZFmk315DH9dYSoh6jFXvWtyWZIusmnp9vUa1ZX6VfTVHa+HQ2bb5PMFejJBq8Nc6o7 flNmxqmy9+c/kRK4p84fheTPPpqIhbW8d+7wW2fMxRHviE2zWTymc1jTFxTR0WdFCqRE 5lWjscI+hsJB32vh8mAP836hUKYeqRuqWnS4tmdcg2Zq9lt1mJe0tOq4vpZ/xZo8AEpg 1u9ttNXZXp+DusWZ+PEHWhE2Xa02t9QkrSFLK3kJu06IHTsQ1h3dDTZmeRD2t1fRpaGj pzVgOVa0Gc3SOnxMteFgyC5B22e/ee1XXFwSbMzSCP8wkqCM6kx48RPtXjjNzlln7mrL 7PjA== X-Gm-Message-State: AOAM531bznT8OZrs8paDK/K0zNnhoASHRZJLMMUqs3BX2bKbORPEBfzS mXh0WCnGLgCmmKHQNI84ZKmq0aU57yekDA== X-Google-Smtp-Source: ABdhPJwoupIaLyZ0shfGkGDKFZSJTe/gDbDxJcJKVM+VE9A+bYB1PNUPf5hVnVlpqqlP3j7ItnRyZg== X-Received: by 2002:a17:902:6b8b:b0:14d:66c4:f704 with SMTP id p11-20020a1709026b8b00b0014d66c4f704mr4617398plk.53.1646911663043; Thu, 10 Mar 2022 03:27:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 15/48] target/nios2: Use hw/registerfields.h for CR_TLBADDR fields Date: Thu, 10 Mar 2022 03:26:52 -0800 Message-Id: <20220310112725.570053-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::635 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646913156247100001 Content-Type: text/plain; charset="utf-8" Use FIELD_EX32 and FIELD_DP32 instead of manual manipulation of the fields. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 8 ++++---- target/nios2/helper.c | 4 ++-- target/nios2/mmu.c | 17 +++++++++-------- target/nios2/translate.c | 2 +- 4 files changed, 16 insertions(+), 15 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 963cdec161..e1c2bf8c31 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -110,10 +110,10 @@ FIELD(CR_EXCEPTION, CAUSE, 2, 5) FIELD(CR_EXCEPTION, ECCFTL, 31, 1) =20 #define CR_PTEADDR 8 -#define CR_PTEADDR_PTBASE_SHIFT 22 -#define CR_PTEADDR_PTBASE_MASK (0x3FF << CR_PTEADDR_PTBASE_SHIFT) -#define CR_PTEADDR_VPN_SHIFT 2 -#define CR_PTEADDR_VPN_MASK (0xFFFFF << CR_PTEADDR_VPN_SHIFT) + +FIELD(CR_PTEADDR, VPN, 2, 20) +FIELD(CR_PTEADDR, PTBASE, 22, 10) + #define CR_TLBACC 9 #define CR_TLBACC_IGN_SHIFT 25 #define CR_TLBACC_IGN_MASK (0x7F << CR_TLBACC_IGN_SHIFT) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 54458a5447..da3a289fc7 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -306,8 +306,8 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, } else { env->ctrl[CR_TLBMISC] |=3D CR_TLBMISC_D; } - env->ctrl[CR_PTEADDR] &=3D CR_PTEADDR_PTBASE_MASK; - env->ctrl[CR_PTEADDR] |=3D (address >> 10) & CR_PTEADDR_VPN_MASK; + env->ctrl[CR_PTEADDR] =3D FIELD_DP32(env->ctrl[CR_PTEADDR], CR_PTEADDR= , VPN, + address >> TARGET_PAGE_BITS); env->mmu.pteaddr_wr =3D env->ctrl[CR_PTEADDR]; =20 cs->exception_index =3D excp; diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 95900724e8..75afc56daf 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -97,7 +97,7 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t= v) /* if tlbmisc.WE =3D=3D 1 then trigger a TLB write on writes to TLBACC= */ if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WR) { int way =3D (env->ctrl[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT); - int vpn =3D (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2; + int vpn =3D FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN); int pid =3D (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; int g =3D (v & CR_TLBACC_G) ? 1 : 0; int valid =3D ((vpn & CR_TLBACC_PFN_MASK) < 0xC0000) ? 1 : 0; @@ -148,7 +148,7 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint3= 2_t v) /* if tlbmisc.RD =3D=3D 1 then trigger a TLB read on writes to TLBMISC= */ if (v & CR_TLBMISC_RD) { int way =3D (v >> CR_TLBMISC_WAY_SHIFT); - int vpn =3D (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2; + int vpn =3D FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN); Nios2TLBEntry *entry =3D &env->mmu.tlb[(way * cpu->tlb_num_ways) + (vpn & env->mmu.tlb_entry_mask)]; @@ -160,8 +160,9 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint3= 2_t v) (v & ~CR_TLBMISC_PID_MASK) | ((entry->tag & ((1 << cpu->pid_num_bits) - 1)) << CR_TLBMISC_PID_SHIFT); - env->ctrl[CR_PTEADDR] &=3D ~CR_PTEADDR_VPN_MASK; - env->ctrl[CR_PTEADDR] |=3D (entry->tag >> 12) << CR_PTEADDR_VPN_SH= IFT; + env->ctrl[CR_PTEADDR] =3D FIELD_DP32(env->ctrl[CR_PTEADDR], + CR_PTEADDR, VPN, + entry->tag >> TARGET_PAGE_BITS); } else { env->ctrl[CR_TLBMISC] =3D v; } @@ -171,12 +172,12 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uin= t32_t v) =20 void helper_mmu_write_pteaddr(CPUNios2State *env, uint32_t v) { - trace_nios2_mmu_write_pteaddr(v >> CR_PTEADDR_PTBASE_SHIFT, - (v & CR_PTEADDR_VPN_MASK) >> CR_PTEADDR_= VPN_SHIFT); + trace_nios2_mmu_write_pteaddr(FIELD_EX32(v, CR_PTEADDR, PTBASE), + FIELD_EX32(v, CR_PTEADDR, VPN)); =20 /* Writes to PTEADDR don't change the read-back VPN value */ - env->ctrl[CR_PTEADDR] =3D ((v & ~CR_PTEADDR_VPN_MASK) | - (env->ctrl[CR_PTEADDR] & CR_PTEADDR_VPN_MASK)= ); + env->ctrl[CR_PTEADDR] =3D ((v & ~R_CR_PTEADDR_VPN_MASK) | + (env->ctrl[CR_PTEADDR] & R_CR_PTEADDR_VPN_MAS= K)); env->mmu.pteaddr_wr =3D v; } =20 diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 45fe2f9a05..9b81a2b29e 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -923,7 +923,7 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int fl= ags) } } qemu_fprintf(f, " mmu write: VPN=3D%05X PID %02X TLBACC %08X\n", - env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK, + env->mmu.pteaddr_wr & R_CR_PTEADDR_VPN_MASK, (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4, env->mmu.tlbacc_wr); #endif --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646913145030729.1515813525689; Thu, 10 Mar 2022 03:52:25 -0800 (PST) Received: from localhost ([::1]:55154 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHLE-00009w-Ur for importer@patchew.org; Thu, 10 Mar 2022 06:52:24 -0500 Received: from eggs.gnu.org ([209.51.188.92]:50782) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGxQ-0005WW-Bv for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:48 -0500 Received: from [2607:f8b0:4864:20::1032] (port=46629 helo=mail-pj1-x1032.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGxO-0007xy-F4 for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:48 -0500 Received: by mail-pj1-x1032.google.com with SMTP id 15-20020a17090a098f00b001bef0376d5cso4935041pjo.5 for ; Thu, 10 Mar 2022 03:27:46 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.27.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:27:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GKFLxmbTYTFJV6/p4TM5MrilKQbtlOw6w8FSPR9X89E=; b=tZ4DQVvoX5L7A3EfnKywYn5U04oPGL4UjZiVynQh/Banf+iRUlCBJx+o5qyna2Vnt7 i2G/p9qSGSib7PwifHawl2QNmftQSsWu0vSz1lhBf8WjuD1rU40EXd41SCrDABZAPOx3 8Qj8f7ODd/gADspqmzdq861CTeMRjrWCfdPSNyxR6EXW0nH4NknbRl+ZgAYe8LMnAdOO G6vJ6NXwDxOp+joiJfWAGLxyjEf6wgQKombPLt3aaW87ENgwZ65HSIGTozjjeCR8wAwU 3W7R+sD4pHUJiJRAPWTNYuRnQjLlo8uCWJrpPEv93DQuzF583N0f1G95SqTFTZxQ655J sjCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GKFLxmbTYTFJV6/p4TM5MrilKQbtlOw6w8FSPR9X89E=; b=CiTvjvc7IBg2eRszh2LLFY0DBfrS7tPvNDfQo8f0etFokPK25uWD+vDARxAhY/Cb3v 8Kcxj8VTYJJSnfom/Qkc5oRNU8kegGi2kEsT7CrXpUoU0+XGFEHpphrDvjdDhGlhcweL bzTZy+LM0QkEoEjqVMN42C9D6DDyidCDK8Pz7BHI7l/rCzdLSQ24oEIqazyR8Hamgje0 aSMQvcRMUakAym8OA53QOjRD01RvOXkj4yET7/EI4CiJnAU9SeQ3AZBQyr7SgOSJXFQ/ szEuUF8bKCNdts8jEV9thpw21VlsCaGH5dqAZSNUKgwOyZJUPIqcLN8L/mWmqOl9Au3D 8qYw== X-Gm-Message-State: AOAM531TFxWgvN5Z+B4dfuaAOPMjJ/LZ1ufg54NV7O3yp8KarWFh697N mskPevhhK7OrFmcvXwC/JZ3c1dMRpNXyaw== X-Google-Smtp-Source: ABdhPJyTLmZvD0L2sjR6VWTr+THKQlAvjL92VgCNBe7NUFoLHEZjFFNpdl7yszW5pK5q3nCS4U0SIg== X-Received: by 2002:a17:902:d492:b0:151:86ac:bc7b with SMTP id c18-20020a170902d49200b0015186acbc7bmr4477089plg.52.1646911664109; Thu, 10 Mar 2022 03:27:44 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 16/48] target/nios2: Use hw/registerfields.h for CR_TLBACC fields Date: Thu, 10 Mar 2022 03:26:53 -0800 Message-Id: <20220310112725.570053-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1032 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646913146806100001 Content-Type: text/plain; charset="utf-8" Retain the helper macros for single bit fields as aliases to the longer R_*_MASK names. Use FIELD_EX32 and FIELD_DP32 instead of manually manipulating the fields. Since we're rewriting the references to CR_TLBACC_IGN_* anyway, we correct the name of this field to IG, which is its name in the official CPU documentation. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 23 +++++++++++++++-------- target/nios2/mmu.c | 16 ++++++++-------- 2 files changed, 23 insertions(+), 16 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index e1c2bf8c31..25b77916ca 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -115,14 +115,21 @@ FIELD(CR_PTEADDR, VPN, 2, 20) FIELD(CR_PTEADDR, PTBASE, 22, 10) =20 #define CR_TLBACC 9 -#define CR_TLBACC_IGN_SHIFT 25 -#define CR_TLBACC_IGN_MASK (0x7F << CR_TLBACC_IGN_SHIFT) -#define CR_TLBACC_C (1 << 24) -#define CR_TLBACC_R (1 << 23) -#define CR_TLBACC_W (1 << 22) -#define CR_TLBACC_X (1 << 21) -#define CR_TLBACC_G (1 << 20) -#define CR_TLBACC_PFN_MASK 0x000FFFFF + +FIELD(CR_TLBACC, PFN, 0, 20) +FIELD(CR_TLBACC, G, 20, 1) +FIELD(CR_TLBACC, X, 21, 1) +FIELD(CR_TLBACC, W, 22, 1) +FIELD(CR_TLBACC, R, 23, 1) +FIELD(CR_TLBACC, C, 24, 1) +FIELD(CR_TLBACC, IG, 25, 7) + +#define CR_TLBACC_C R_CR_TLBACC_C_MASK +#define CR_TLBACC_R R_CR_TLBACC_R_MASK +#define CR_TLBACC_W R_CR_TLBACC_W_MASK +#define CR_TLBACC_X R_CR_TLBACC_X_MASK +#define CR_TLBACC_G R_CR_TLBACC_G_MASK + #define CR_TLBMISC 10 #define CR_TLBMISC_WAY_SHIFT 20 #define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT) diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 75afc56daf..826cd2afb4 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -49,7 +49,7 @@ unsigned int mmu_translate(CPUNios2State *env, } =20 lu->vaddr =3D vaddr & TARGET_PAGE_MASK; - lu->paddr =3D (entry->data & CR_TLBACC_PFN_MASK) << TARGET_PAGE_BI= TS; + lu->paddr =3D FIELD_EX32(entry->data, CR_TLBACC, PFN) << TARGET_PA= GE_BITS; lu->prot =3D ((entry->data & CR_TLBACC_R) ? PAGE_READ : 0) | ((entry->data & CR_TLBACC_W) ? PAGE_WRITE : 0) | ((entry->data & CR_TLBACC_X) ? PAGE_EXEC : 0); @@ -86,27 +86,27 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32= _t v) CPUState *cs =3D env_cpu(env); Nios2CPU *cpu =3D env_archcpu(env); =20 - trace_nios2_mmu_write_tlbacc(v >> CR_TLBACC_IGN_SHIFT, + trace_nios2_mmu_write_tlbacc(FIELD_EX32(v, CR_TLBACC, IG), (v & CR_TLBACC_C) ? 'C' : '.', (v & CR_TLBACC_R) ? 'R' : '.', (v & CR_TLBACC_W) ? 'W' : '.', (v & CR_TLBACC_X) ? 'X' : '.', (v & CR_TLBACC_G) ? 'G' : '.', - v & CR_TLBACC_PFN_MASK); + FIELD_EX32(v, CR_TLBACC, PFN)); =20 /* if tlbmisc.WE =3D=3D 1 then trigger a TLB write on writes to TLBACC= */ if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WR) { int way =3D (env->ctrl[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT); int vpn =3D FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN); int pid =3D (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; - int g =3D (v & CR_TLBACC_G) ? 1 : 0; - int valid =3D ((vpn & CR_TLBACC_PFN_MASK) < 0xC0000) ? 1 : 0; + int g =3D FIELD_EX32(v, CR_TLBACC, G); + int valid =3D FIELD_EX32(vpn, CR_TLBACC, PFN) < 0xC0000; Nios2TLBEntry *entry =3D &env->mmu.tlb[(way * cpu->tlb_num_ways) + (vpn & env->mmu.tlb_entry_mask)]; uint32_t newTag =3D (vpn << 12) | (g << 11) | (valid << 10) | pid; uint32_t newData =3D v & (CR_TLBACC_C | CR_TLBACC_R | CR_TLBACC_W | - CR_TLBACC_X | CR_TLBACC_PFN_MASK); + CR_TLBACC_X | R_CR_TLBACC_PFN_MASK); =20 if ((entry->tag !=3D newTag) || (entry->data !=3D newData)) { if (entry->tag & (1 << 10)) { @@ -153,7 +153,7 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint3= 2_t v) &env->mmu.tlb[(way * cpu->tlb_num_ways) + (vpn & env->mmu.tlb_entry_mask)]; =20 - env->ctrl[CR_TLBACC] &=3D CR_TLBACC_IGN_MASK; + env->ctrl[CR_TLBACC] &=3D R_CR_TLBACC_IG_MASK; env->ctrl[CR_TLBACC] |=3D entry->data; env->ctrl[CR_TLBACC] |=3D (entry->tag & (1 << 11)) ? CR_TLBACC_G := 0; env->ctrl[CR_TLBMISC] =3D @@ -208,7 +208,7 @@ void dump_mmu(CPUNios2State *env) entry->tag >> 12, entry->tag & ((1 << cpu->pid_num_bits) - 1), (entry->tag & (1 << 11)) ? 'G' : '-', - entry->data & CR_TLBACC_PFN_MASK, + FIELD_EX32(entry->data, CR_TLBACC, PFN), (entry->data & CR_TLBACC_C) ? 'C' : '-', (entry->data & CR_TLBACC_R) ? 'R' : '-', (entry->data & CR_TLBACC_W) ? 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.27.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:27:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jwiItv/W7hsxOLFZ9QGpLLDQ+Ql5lsRDNyYEtGuJ3Fw=; b=FkDhEB3IcWan3V3kWqpwhPQvXxZ2qI4GcEYWup1wW6KvBTnnpKiyMMP1gwsTn0hcZY HGfgSmo7T72CF37rbgV2Zvy41GktfbxgbvChpx9AEpVxFBpqzpuJ52zZ9QYRSidOVppS oEARLXXysz5zEPECV89fiZDAEmXH6Hg6zK8PO9HojQOh1u/FwzUjmJhGIkkvypkQIf6w nxoKpWbb9jVE2AqC4mllnQgheqey7kazC6VYnNOvAJ2tRA5PJ6BQAIX+ndH3AX1lDbGp GjbUtnowcnhlmBQubbb15+78mqYhu4KoUuXqXjKEUhEqYIgOd4gGVyaNdI5kaF0M/Ld3 amkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jwiItv/W7hsxOLFZ9QGpLLDQ+Ql5lsRDNyYEtGuJ3Fw=; b=1iO+j9n8kspwO4Jq53q3zWEjQHOA3Nr33mRM+D4R8qg9GaiNxf9rwvtmL/D0T0b67R lCbBRta9pRO8NERTLW+YMhZkOkkd7cgWDAnkhVsc1+mViuAWsz93WOLjewjbw4BtBAlo XDfarDNmuxbzWj7XHV1kNAPjEPqzCTrZPqTDe3Zk7PFmx85WYDNa7r98KwO4WFon5Emv kdBq4HDDUOdk0P4KdHWx4kSOt/jieUns0Wiv1N7cb+OueORM2d7WYB0t35jBmdBvHjno aizyjen3dQKyrxHpr3MGIXo9Zot9VCOfEXrWrbXno0VaTfZirpXern4QMdnEIG0/dgak eQ5A== X-Gm-Message-State: AOAM531VUKibk5MUgkONr8VjWXPufeuDcjebL8DcUR2PulV/rbRUxKon sPkMnnipcRKy5FV7GQBNt3fB2ARD9+IszA== X-Google-Smtp-Source: ABdhPJyHDpDpO8ZP6c0xlMir0Gu9G7YY40mnnrnUpnxcge79m2Q+Pp38VMDgGvLxl/kpYBM7gOHW9g== X-Received: by 2002:a17:903:4a:b0:151:be09:3de9 with SMTP id l10-20020a170903004a00b00151be093de9mr4464030pla.138.1646911665149; Thu, 10 Mar 2022 03:27:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 17/48] target/nios2: Rename CR_TLBMISC_WR to CR_TLBMISC_WE Date: Thu, 10 Mar 2022 03:26:54 -0800 Message-Id: <20220310112725.570053-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102f (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646913315662100001 Content-Type: text/plain; charset="utf-8" WE is the architectural name of the field, not WR. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/cpu.h | 2 +- target/nios2/helper.c | 4 ++-- target/nios2/mmu.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 25b77916ca..81472be686 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -134,7 +134,7 @@ FIELD(CR_TLBACC, IG, 25, 7) #define CR_TLBMISC_WAY_SHIFT 20 #define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT) #define CR_TLBMISC_RD (1 << 19) -#define CR_TLBMISC_WR (1 << 18) +#define CR_TLBMISC_WE (1 << 18) #define CR_TLBMISC_PID_SHIFT 4 #define CR_TLBMISC_PID_MASK (0x3FFF << CR_TLBMISC_PID_SHIFT) #define CR_TLBMISC_DBL (1 << 3) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index da3a289fc7..308d66ad93 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -89,7 +89,7 @@ void nios2_cpu_do_interrupt(CPUState *cs) cs->exception_index); =20 env->ctrl[CR_TLBMISC] &=3D ~CR_TLBMISC_DBL; - env->ctrl[CR_TLBMISC] |=3D CR_TLBMISC_WR; + env->ctrl[CR_TLBMISC] |=3D CR_TLBMISC_WE; =20 env->regs[R_EA] =3D env->pc + 4; env->pc =3D cpu->fast_tlb_miss_addr; @@ -124,7 +124,7 @@ void nios2_cpu_do_interrupt(CPUState *cs) cs->exception_index); =20 if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { - env->ctrl[CR_TLBMISC] |=3D CR_TLBMISC_WR; + env->ctrl[CR_TLBMISC] |=3D CR_TLBMISC_WE; } =20 env->regs[R_EA] =3D env->pc + 4; diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 826cd2afb4..0f33ea5e04 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -95,7 +95,7 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t= v) FIELD_EX32(v, CR_TLBACC, PFN)); =20 /* if tlbmisc.WE =3D=3D 1 then trigger a TLB write on writes to TLBACC= */ - if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WR) { + if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WE) { int way =3D (env->ctrl[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT); int vpn =3D FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN); int pid =3D (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; @@ -133,7 +133,7 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint3= 2_t v) =20 trace_nios2_mmu_write_tlbmisc(v >> CR_TLBMISC_WAY_SHIFT, (v & CR_TLBMISC_RD) ? 'R' : '.', - (v & CR_TLBMISC_WR) ? 'W' : '.', + (v & CR_TLBMISC_WE) ? 'W' : '.', (v & CR_TLBMISC_DBL) ? '2' : '.', (v & CR_TLBMISC_BAD) ? 'B' : '.', (v & CR_TLBMISC_PERM) ? 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.27.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:27:45 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GADV/jExPWz+mF0nwm5rQZ+l5e8TEkrJvePYWSdN3A0=; b=RE03IV6b/3dyMzGnR7wG72Vp3/nmdtJZcyuEzlSI82IEs73wUWWmSTNgbwMHzQpDOP ryUM1/Fbj3KbuFfXDm/1N0TPUBP3kW/SyuPrRPyXph/DAaWNQGmk/CbLr5CecRzZlb+8 szr4N2FXhTz7fFegQBo/SP8K/ahvgjzSvAAeMkwQZYqpgAlBWYZdUIDjD51KO0HnvYCI Bwc92zX1c+lj8mErM3CKFDv3+svmiEuxVSQCjOY0WCpyNtufQah+Y/cQP9F6ASBnEIT9 4lxhuyH38B6LiDnCt/nnFAtAfj1Ao9KnfRRyu4JzjTCO3283caHTauIrUurGnEoEoG2Q B2Xw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GADV/jExPWz+mF0nwm5rQZ+l5e8TEkrJvePYWSdN3A0=; b=eVBIPOe25JNT6fL20fPAVD1KW5xHX8sD9v4lMYznnCNmxvGXiZ20yYj5VYe9XtUgyk q9p7Pdp9mlRszyIVqvRIkcmkjYS4GTBNJo6dAPE7rEOmTMXcX1+5c/1HzuqSxjSS3zWq R5M08DpkksHtj4BGQ/p87BVSgARmQwxeNgcKGnyZl1QNnWwgoQgxXDi8W0/D+KV6Ruov l/kTBMz95qrlwQ911Bxz7JoxpsDfQsJWVT3wgYORDDkAOv6Vmsnlu7yoJyo697Vjun9W VT44E7WqmUeoX7/XPC4r0APtgXSBjBagMyTybpPbFiROCBs2ltY6i5pTxwWiE2WIAqBd HnOA== X-Gm-Message-State: AOAM531bFRVjFWV6U0DwSyXj8MoscvT9T57gECDCVE4nPom6XctpN8EH Nc7mCQk2FRxiRpT9cCfMh9Lc6GVmkRNlhA== X-Google-Smtp-Source: ABdhPJzXDflfc+ML5LCbYZ6AvJIcV+GlP35brHPretWzTkfDnBUpQgrP+cIzgxItE2LatMEqXZWGfg== X-Received: by 2002:a17:902:9a0a:b0:14a:199:bc5c with SMTP id v10-20020a1709029a0a00b0014a0199bc5cmr4424586plp.10.1646911666313; Thu, 10 Mar 2022 03:27:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 18/48] target/nios2: Use hw/registerfields.h for CR_TLBMISC fields Date: Thu, 10 Mar 2022 03:26:55 -0800 Message-Id: <20220310112725.570053-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1036 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646914065915100005 Content-Type: text/plain; charset="utf-8" Use FIELD_EX32 and FIELD_DP32 instead of managing the masking by hand. Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 29 +++++++++++++++++++---------- target/nios2/helper.c | 7 ++----- target/nios2/mmu.c | 35 +++++++++++++++++------------------ target/nios2/translate.c | 2 +- 4 files changed, 39 insertions(+), 34 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 81472be686..7f805a933e 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -131,16 +131,25 @@ FIELD(CR_TLBACC, IG, 25, 7) #define CR_TLBACC_G R_CR_TLBACC_G_MASK =20 #define CR_TLBMISC 10 -#define CR_TLBMISC_WAY_SHIFT 20 -#define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT) -#define CR_TLBMISC_RD (1 << 19) -#define CR_TLBMISC_WE (1 << 18) -#define CR_TLBMISC_PID_SHIFT 4 -#define CR_TLBMISC_PID_MASK (0x3FFF << CR_TLBMISC_PID_SHIFT) -#define CR_TLBMISC_DBL (1 << 3) -#define CR_TLBMISC_BAD (1 << 2) -#define CR_TLBMISC_PERM (1 << 1) -#define CR_TLBMISC_D (1 << 0) + +FIELD(CR_TLBMISC, D, 0, 1) +FIELD(CR_TLBMISC, PERM, 1, 1) +FIELD(CR_TLBMISC, BAD, 2, 1) +FIELD(CR_TLBMISC, DBL, 3, 1) +FIELD(CR_TLBMISC, PID, 4, 14) +FIELD(CR_TLBMISC, WE, 18, 1) +FIELD(CR_TLBMISC, RD, 19, 1) +FIELD(CR_TLBMISC, WAY, 20, 4) +FIELD(CR_TLBMISC, EE, 24, 1) + +#define CR_TLBMISC_EE R_CR_TLBMISC_EE_MASK +#define CR_TLBMISC_RD R_CR_TLBMISC_RD_MASK +#define CR_TLBMISC_WE R_CR_TLBMISC_WE_MASK +#define CR_TLBMISC_DBL R_CR_TLBMISC_DBL_MASK +#define CR_TLBMISC_BAD R_CR_TLBMISC_BAD_MASK +#define CR_TLBMISC_PERM R_CR_TLBMISC_PERM_MASK +#define CR_TLBMISC_D R_CR_TLBMISC_D_MASK + #define CR_ENCINJ 11 #define CR_BADADDR 12 #define CR_CONFIG 13 diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 308d66ad93..52a49f7ead 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -301,11 +301,8 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, return false; } =20 - if (access_type =3D=3D MMU_INST_FETCH) { - env->ctrl[CR_TLBMISC] &=3D ~CR_TLBMISC_D; - } else { - env->ctrl[CR_TLBMISC] |=3D CR_TLBMISC_D; - } + env->ctrl[CR_TLBMISC] =3D FIELD_DP32(env->ctrl[CR_TLBMISC], CR_TLBMISC= , D, + access_type !=3D MMU_INST_FETCH); env->ctrl[CR_PTEADDR] =3D FIELD_DP32(env->ctrl[CR_PTEADDR], CR_PTEADDR= , VPN, address >> TARGET_PAGE_BITS); env->mmu.pteaddr_wr =3D env->ctrl[CR_PTEADDR]; diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 0f33ea5e04..d9b690b78e 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -33,7 +33,7 @@ unsigned int mmu_translate(CPUNios2State *env, target_ulong vaddr, int rw, int mmu_idx) { Nios2CPU *cpu =3D env_archcpu(env); - int pid =3D (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; + int pid =3D FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID); int vpn =3D vaddr >> 12; int way, n_ways =3D cpu->tlb_num_ways; =20 @@ -96,9 +96,9 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t= v) =20 /* if tlbmisc.WE =3D=3D 1 then trigger a TLB write on writes to TLBACC= */ if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WE) { - int way =3D (env->ctrl[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT); + int way =3D FIELD_EX32(env->ctrl[CR_TLBMISC], CR_TLBMISC, WAY); int vpn =3D FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN); - int pid =3D (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; + int pid =3D FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID); int g =3D FIELD_EX32(v, CR_TLBACC, G); int valid =3D FIELD_EX32(vpn, CR_TLBACC, PFN) < 0xC0000; Nios2TLBEntry *entry =3D @@ -117,10 +117,9 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint3= 2_t v) entry->data =3D newData; } /* Auto-increment tlbmisc.WAY */ - env->ctrl[CR_TLBMISC] =3D - (env->ctrl[CR_TLBMISC] & ~CR_TLBMISC_WAY_MASK) | - (((way + 1) & (cpu->tlb_num_ways - 1)) << - CR_TLBMISC_WAY_SHIFT); + env->ctrl[CR_TLBMISC] =3D FIELD_DP32(env->ctrl[CR_TLBMISC], + CR_TLBMISC, WAY, + (way + 1) & (cpu->tlb_num_ways = - 1)); } =20 /* Writes to TLBACC don't change the read-back value */ @@ -130,24 +129,25 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint= 32_t v) void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v) { Nios2CPU *cpu =3D env_archcpu(env); + uint32_t new_pid =3D FIELD_EX32(v, CR_TLBMISC, PID); + uint32_t old_pid =3D FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID); + uint32_t way =3D FIELD_EX32(v, CR_TLBMISC, WAY); =20 - trace_nios2_mmu_write_tlbmisc(v >> CR_TLBMISC_WAY_SHIFT, + trace_nios2_mmu_write_tlbmisc(way, (v & CR_TLBMISC_RD) ? 'R' : '.', (v & CR_TLBMISC_WE) ? 'W' : '.', (v & CR_TLBMISC_DBL) ? '2' : '.', (v & CR_TLBMISC_BAD) ? 'B' : '.', (v & CR_TLBMISC_PERM) ? 'P' : '.', (v & CR_TLBMISC_D) ? 'D' : '.', - (v & CR_TLBMISC_PID_MASK) >> 4); + new_pid); =20 - if ((v & CR_TLBMISC_PID_MASK) !=3D - (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK)) { - mmu_flush_pid(env, (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> - CR_TLBMISC_PID_SHIFT); + if (new_pid !=3D old_pid) { + mmu_flush_pid(env, old_pid); } + /* if tlbmisc.RD =3D=3D 1 then trigger a TLB read on writes to TLBMISC= */ if (v & CR_TLBMISC_RD) { - int way =3D (v >> CR_TLBMISC_WAY_SHIFT); int vpn =3D FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN); Nios2TLBEntry *entry =3D &env->mmu.tlb[(way * cpu->tlb_num_ways) + @@ -156,10 +156,9 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint= 32_t v) env->ctrl[CR_TLBACC] &=3D R_CR_TLBACC_IG_MASK; env->ctrl[CR_TLBACC] |=3D entry->data; env->ctrl[CR_TLBACC] |=3D (entry->tag & (1 << 11)) ? CR_TLBACC_G := 0; - env->ctrl[CR_TLBMISC] =3D - (v & ~CR_TLBMISC_PID_MASK) | - ((entry->tag & ((1 << cpu->pid_num_bits) - 1)) << - CR_TLBMISC_PID_SHIFT); + env->ctrl[CR_TLBMISC] =3D FIELD_DP32(v, CR_TLBMISC, PID, + entry->tag & + ((1 << cpu->pid_num_bits) - 1)); env->ctrl[CR_PTEADDR] =3D FIELD_DP32(env->ctrl[CR_PTEADDR], CR_PTEADDR, VPN, entry->tag >> TARGET_PAGE_BITS); diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 9b81a2b29e..459e30b338 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -924,7 +924,7 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int fl= ags) } qemu_fprintf(f, " mmu write: VPN=3D%05X PID %02X TLBACC %08X\n", env->mmu.pteaddr_wr & R_CR_PTEADDR_VPN_MASK, - (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4, + FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID), env->mmu.tlbacc_wr); #endif qemu_fprintf(f, "\n\n"); --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646913305978918.3588860940097; Thu, 10 Mar 2022 03:55:05 -0800 (PST) Received: from localhost ([::1]:35084 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHNo-0005so-SN for importer@patchew.org; Thu, 10 Mar 2022 06:55:04 -0500 Received: from eggs.gnu.org ([209.51.188.92]:50818) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGxS-0005cR-IM for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:50 -0500 Received: from [2607:f8b0:4864:20::1031] (port=46034 helo=mail-pj1-x1031.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGxQ-0007yV-VT for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:50 -0500 Received: by mail-pj1-x1031.google.com with SMTP id m11-20020a17090a7f8b00b001beef6143a8so4944991pjl.4 for ; Thu, 10 Mar 2022 03:27:48 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.27.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:27:47 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=e6sq5+VxzJ+iyeBdvkBx4ESzy/gdXULWUf0uyVhwts4=; b=ckV13nbAONqcjv7XIU0kL0eomQJTYp8RKRCHlrhu6he+2yvYE3j93z33QptmbrQpoe IezDqRCDeABj0npYedzBT877LqywYC7/kE/+CC0JXCCwESg4lqyXXEFLaMsPvL5GYX5j gkiBSmcserLjGcMSYUur+JEvOcv4VKDLqpTOOoA0+5p4xs/YN9IlQR2UeSyZjPBlQWRZ bnLyENDq7Is1kfC8Kuud/4SHWFDuoQIj94AfsNbao/fFoc8cGTpVtSxKWUqi+VCPhc+V YbUJJv449CMjG/BSnZEoB7sf0vD9fczIuUaQBiMekxuJdgOpKDps2UDwTGn0IE8a/1HU MTrg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=e6sq5+VxzJ+iyeBdvkBx4ESzy/gdXULWUf0uyVhwts4=; b=rxmIOAftXctnoiDvxbo8Jra6F6UWJSr1OW0ZCuBEmHcJmN4Nni8ZcI3mMRsgJpWE0T xHt1MR2KYrhPq2btIW88Wn2B1FOwymyA450RPOoDWdRl+dIm8sqcBI9j/urMaNhRFw9e e3ZfGHICCzSLiWu6bFxdWq77AJjLtTwROoPin/JYr6mbVjbOi0vUqR+rdAT5pyDw4T14 ISyCOEz3WCVAqFBam7pYgmPnTl50rGZRnkkK28vDiXtmOTDYCRgf/d/TZEoUl/pgKFHH dTkrqfm6bUCYgHvbr7OYB6Sr0R2OqUUk0WR2f+ofF62AdA8O9ip5On0VEm0Za9uFqcG5 IJ2g== X-Gm-Message-State: AOAM531Zn5tfSuDpPp1zTvN4R5VAvJrRgSFxg0xjQSFrDQU8QkgeW273 nkXxmBq2mpWseTvBEDFpxtPao5YCLRbxbQ== X-Google-Smtp-Source: ABdhPJzD1wjJk9oHn2yWpmU63kNSPcRccQsvISaTNL9jX+2eMTUZ7MqeGtPBmGyDQ7Vhy/uVsFTZnQ== X-Received: by 2002:a17:902:d482:b0:151:ef7f:f5aa with SMTP id c2-20020a170902d48200b00151ef7ff5aamr4456489plg.58.1646911667698; Thu, 10 Mar 2022 03:27:47 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 19/48] target/nios2: Move R_FOO and CR_BAR into enumerations Date: Thu, 10 Mar 2022 03:26:56 -0800 Message-Id: <20220310112725.570053-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1031 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646913307718100001 Content-Type: text/plain; charset="utf-8" These symbols become available to the debugger. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 72 ++++++++++++++++++++++------------------------ 1 file changed, 35 insertions(+), 37 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 7f805a933e..555972fe6b 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -61,25 +61,43 @@ struct Nios2CPUClass { #define NUM_CR_REGS 32 =20 /* General purpose register aliases */ -#define R_ZERO 0 -#define R_AT 1 -#define R_RET0 2 -#define R_RET1 3 -#define R_ARG0 4 -#define R_ARG1 5 -#define R_ARG2 6 -#define R_ARG3 7 -#define R_ET 24 -#define R_BT 25 -#define R_GP 26 -#define R_SP 27 -#define R_FP 28 -#define R_EA 29 -#define R_BA 30 -#define R_RA 31 +enum { + R_ZERO =3D 0, + R_AT =3D 1, + R_RET0 =3D 2, + R_RET1 =3D 3, + R_ARG0 =3D 4, + R_ARG1 =3D 5, + R_ARG2 =3D 6, + R_ARG3 =3D 7, + R_ET =3D 24, + R_BT =3D 25, + R_GP =3D 26, + R_SP =3D 27, + R_FP =3D 28, + R_EA =3D 29, + R_BA =3D 30, + R_RA =3D 31, +}; =20 /* Control register aliases */ -#define CR_STATUS 0 +enum { + CR_STATUS =3D 0, + CR_ESTATUS =3D 1, + CR_BSTATUS =3D 2, + CR_IENABLE =3D 3, + CR_IPENDING =3D 4, + CR_CPUID =3D 5, + CR_EXCEPTION =3D 7, + CR_PTEADDR =3D 8, + CR_TLBACC =3D 9, + CR_TLBMISC =3D 10, + CR_ENCINJ =3D 11, + CR_BADADDR =3D 12, + CR_CONFIG =3D 13, + CR_MPUBASE =3D 14, + CR_MPUACC =3D 15, +}; =20 FIELD(CR_STATUS, PIE, 0, 1) FIELD(CR_STATUS, U, 1, 1) @@ -98,24 +116,12 @@ FIELD(CR_STATUS, RSIE, 23, 1) #define CR_STATUS_NMI R_CR_STATUS_NMI_MASK #define CR_STATUS_RSIE R_CR_STATUS_RSIE_MASK =20 -#define CR_ESTATUS 1 -#define CR_BSTATUS 2 -#define CR_IENABLE 3 -#define CR_IPENDING 4 -#define CR_CPUID 5 -#define CR_CTL6 6 -#define CR_EXCEPTION 7 - FIELD(CR_EXCEPTION, CAUSE, 2, 5) FIELD(CR_EXCEPTION, ECCFTL, 31, 1) =20 -#define CR_PTEADDR 8 - FIELD(CR_PTEADDR, VPN, 2, 20) FIELD(CR_PTEADDR, PTBASE, 22, 10) =20 -#define CR_TLBACC 9 - FIELD(CR_TLBACC, PFN, 0, 20) FIELD(CR_TLBACC, G, 20, 1) FIELD(CR_TLBACC, X, 21, 1) @@ -130,8 +136,6 @@ FIELD(CR_TLBACC, IG, 25, 7) #define CR_TLBACC_X R_CR_TLBACC_X_MASK #define CR_TLBACC_G R_CR_TLBACC_G_MASK =20 -#define CR_TLBMISC 10 - FIELD(CR_TLBMISC, D, 0, 1) FIELD(CR_TLBMISC, PERM, 1, 1) FIELD(CR_TLBMISC, BAD, 2, 1) @@ -150,12 +154,6 @@ FIELD(CR_TLBMISC, EE, 24, 1) #define CR_TLBMISC_PERM R_CR_TLBMISC_PERM_MASK #define CR_TLBMISC_D R_CR_TLBMISC_D_MASK =20 -#define CR_ENCINJ 11 -#define CR_BADADDR 12 -#define CR_CONFIG 13 -#define CR_MPUBASE 14 -#define CR_MPUACC 15 - /* Exceptions */ #define EXCP_BREAK 0x1000 #define EXCP_RESET 0 --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164691349280486.81711767986576; Thu, 10 Mar 2022 03:58:12 -0800 (PST) Received: from localhost ([::1]:43338 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHQq-0003FX-Ek for importer@patchew.org; Thu, 10 Mar 2022 06:58:12 -0500 Received: from eggs.gnu.org ([209.51.188.92]:50832) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGxT-0005fI-Jb for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:51 -0500 Received: from [2607:f8b0:4864:20::102f] (port=34508 helo=mail-pj1-x102f.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGxR-0007yn-UL for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:51 -0500 Received: by mail-pj1-x102f.google.com with SMTP id k5-20020a17090a3cc500b001befa0d3102so6092114pjd.1 for ; Thu, 10 Mar 2022 03:27:49 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.27.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:27:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=62d8othJIfgAKm86Avncs/clZTnNTHcuD30Oj5z4NnM=; b=Js6I3+tl4MgfPZk/1FQAe90hI3aIBtY49Q94ebm322DRaLmAJ9Ksyvtr7dURWTgy1P ARrvEyba6AnWjQYuBuvyUzJISjkldJE+69zTgZxCX7bbmlGTwo+XVGhEtL89OJ2stAU2 7fp6u5vcAzDSBG0Uv6aBjSlamlT0BqBxWJGH2vImsMfbqKzVOp6s/2Js7u5OBzk4wlBO tf9Nqqs3wkCK75/xHbfK9sr8ec7+ZJBUwVXfBVmMDM9ZQS2/Kcb7UJIZaQ4+an0j1DYD wTjPl3pUeyBS8bWTalptZPBFtF2Attf2deUY28E8Wrp9g5zId1C0TcEaerCnd9R9hrVj +z0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=62d8othJIfgAKm86Avncs/clZTnNTHcuD30Oj5z4NnM=; b=0t5SB9rqR+9n8DeFJc8ODFm11ZcPeekge2UXgPcLeV4kMLfcvwuWEVShRmtrodQRen mUzfepf1fWUNY0msKxaO/Hjk185E0UslC7vPODt/PhHrkCA/DMhjNdh53bxZyLNjXacE sQ7W6QY66fspZHohqFx/d4+ATFoPcK5nh+9Zr5hNRDIu8NmbEGz91GZbzmSCaISPiJS5 BQU3q8FFueNUtBEbAK63TBtGIXAHzEcE+VHobFyJTSwit3entJOflC+mvXLJE0dR/kcL nYWHw9BOzwdcTg6p9FN98XhzlgG0Dje1lmc64A8mlNj4hUnUvBmTYvscu8j0gzTpZ6sb DDpw== X-Gm-Message-State: AOAM531uuOBK4KNelF9A6EZsBcRFVFIk8ZaUU6aZeD6awhIvDcd6XWA6 9kW/WlStRI+DifkAl4rihadz2hYq/37o7g== X-Google-Smtp-Source: ABdhPJxfyUGewrisVsG08Wua8yFmDrqGeaGDBtenTYIPePJZmMC4pJraq7UWX3/tiz3Tthn2Wzza9w== X-Received: by 2002:a17:902:c40a:b0:151:a792:71f2 with SMTP id k10-20020a170902c40a00b00151a79271f2mr4631360plk.36.1646911668699; Thu, 10 Mar 2022 03:27:48 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 20/48] target/nios2: Create EXCP_SEMIHOST for semi-hosting Date: Thu, 10 Mar 2022 03:26:57 -0800 Message-Id: <20220310112725.570053-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102f (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646913494741100001 Content-Type: text/plain; charset="utf-8" Decode 'break 1' during translation, rather than doing it again during exception processing. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 1 + target/nios2/helper.c | 14 ++++++-------- target/nios2/translate.c | 17 ++++++++++++++++- 3 files changed, 23 insertions(+), 9 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 555972fe6b..d003af5afc 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -156,6 +156,7 @@ FIELD(CR_TLBMISC, EE, 24, 1) =20 /* Exceptions */ #define EXCP_BREAK 0x1000 +#define EXCP_SEMIHOST 0x1001 #define EXCP_RESET 0 #define EXCP_PRESET 1 #define EXCP_IRQ 2 diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 52a49f7ead..eeff032379 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -172,14 +172,6 @@ void nios2_cpu_do_interrupt(CPUState *cs) =20 case EXCP_BREAK: qemu_log_mask(CPU_LOG_INT, "BREAK exception at pc=3D%x\n", env->pc= ); - /* The semihosting instruction is "break 1". */ - if (semihosting_enabled() && - cpu_ldl_code(env, env->pc) =3D=3D 0x003da07a) { - qemu_log_mask(CPU_LOG_INT, "Entering semihosting\n"); - env->pc +=3D 4; - do_nios2_semihosting(env); - break; - } =20 if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { env->ctrl[CR_BSTATUS] =3D env->ctrl[CR_STATUS]; @@ -196,6 +188,12 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->pc =3D cpu->exception_addr; break; =20 + case EXCP_SEMIHOST: + qemu_log_mask(CPU_LOG_INT, "BREAK semihosting at pc=3D%x\n", env->= pc); + env->pc +=3D 4; + do_nios2_semihosting(env); + break; + default: cpu_abort(cs, "unhandled exception type=3D%d\n", cs->exception_index); diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 459e30b338..cfad110186 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -33,6 +33,7 @@ #include "exec/translator.h" #include "qemu/qemu-print.h" #include "exec/gen-icount.h" +#include "semihosting/semihost.h" =20 /* is_jmp field values */ #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ @@ -686,6 +687,20 @@ static void trap(DisasContext *dc, uint32_t code, uint= 32_t flags) t_gen_helper_raise_exception(dc, EXCP_TRAP); } =20 +static void gen_break(DisasContext *dc, uint32_t code, uint32_t flags) +{ +#ifndef CONFIG_USER_ONLY + /* The semihosting instruction is "break 1". */ + R_TYPE(instr, code); + if (semihosting_enabled() && instr.imm5 =3D=3D 1) { + t_gen_helper_raise_exception(dc, EXCP_SEMIHOST); + return; + } +#endif + + t_gen_helper_raise_exception(dc, EXCP_BREAK); +} + static const Nios2Instruction r_type_instructions[] =3D { INSTRUCTION_ILLEGAL(), INSTRUCTION(eret), /* eret */ @@ -739,7 +754,7 @@ static const Nios2Instruction r_type_instructions[] =3D= { INSTRUCTION(add), /* add */ INSTRUCTION_ILLEGAL(), INSTRUCTION_ILLEGAL(), - INSTRUCTION_FLG(gen_excp, EXCP_BREAK), /* break */ + INSTRUCTION(gen_break), /* break */ INSTRUCTION_ILLEGAL(), INSTRUCTION(nop), /* nop */ INSTRUCTION_ILLEGAL(), --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646913502659844.4128576150739; Thu, 10 Mar 2022 03:58:22 -0800 (PST) Received: from localhost ([::1]:43990 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHQz-0003gT-IR for importer@patchew.org; Thu, 10 Mar 2022 06:58:21 -0500 Received: from eggs.gnu.org ([209.51.188.92]:50852) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGxV-0005iw-2f for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:53 -0500 Received: from [2607:f8b0:4864:20::630] (port=33540 helo=mail-pl1-x630.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGxT-0007z0-71 for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:52 -0500 Received: by mail-pl1-x630.google.com with SMTP id m2so4642307pll.0 for ; Thu, 10 Mar 2022 03:27:50 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.27.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:27:49 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rza+S9dP6OxTxmW7BN1PpFg5SK23R8f/DSGJ4keNmyI=; b=CNrSCPn850CBlkthbD1oNj9qQdzV15JoyNkOrxknFIqBWArr+h9n+JEe+fTQsrh8ty JhaBUKiMEwGR50NYBgvXViqhh4aUjFIdStI6CO63d2Pzrp0qK2Ph4Jm3LeKG+WpXxSn3 0vXYOHcCmC8Bwtp3wQTf9AdvTsfgYb+6If861AFwn1JQTXuMT3M+dsSg8k0ZCA77yWHO FO/AAqJ/AcLxqDnMnaGdHSVL/qoni56b7w+Az41T4GKRhe7QYQgl9+8nQBZo1ynonwn9 kPBBPSmR6rqdQUV8cAG3kBpI0Kq9a0TAFMEgt4vY2lWVL23paHw9kOrH7c+YfvWQ9PeL 2Z9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rza+S9dP6OxTxmW7BN1PpFg5SK23R8f/DSGJ4keNmyI=; b=uTHqZ/uIcjh2TLhrAbz9/q2n7u8fwjSi/sRlr50cO7gk/xGkhwtnHewZjNNjPCM0Bu LvxD+f/T7G1lCxmRr733V58mYBRjy7TA92/gRaXqhM1jjCbD7orjm/mbJOHHIzl5Zyiw AZ9Lrvtq7IEp+gzynIn5HvlzooqoJy/vWWa/JCKpkM9N+FxZIUawdjCcwaEYrlj/SGaT 21MG0ZdQiiKNH5ojjhIDNXwevjTc6vdLxbZ8iPzLQC2EfQfjcU//cgZlX3LODzXQ1xw3 t4jt73aZHZED/yRiX0yfFENLnn7THdCXaMrexm/AGR6Z0095Ao4Cmqif7nzJrfTviv9m +ygw== X-Gm-Message-State: AOAM531w8tYqWKa2BlZlcpOqAEsZfHWcfPnxiu83m2raxTvXAoRX1BzO /bLOiPh1xQHTtBZHEGbzrCIErPWTE7TxOw== X-Google-Smtp-Source: ABdhPJzD+WlAPZ0QGfCvcMLfqHKLrwtpyv6VqUsfZw3L9vtv1X2S8iVJRXfc6erSK/uzuBllYnYlMQ== X-Received: by 2002:a17:902:9308:b0:14e:def5:e6b5 with SMTP id bc8-20020a170902930800b0014edef5e6b5mr4490447plb.73.1646911669835; Thu, 10 Mar 2022 03:27:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 21/48] target/nios2: Clean up nios2_cpu_do_interrupt Date: Thu, 10 Mar 2022 03:26:58 -0800 Message-Id: <20220310112725.570053-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::630 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646913503967100001 Content-Type: text/plain; charset="utf-8" Split out do_exception and do_iic_irq to handle bulk of the interrupt and exception processing. Parameterize the changes required to cpu state. The status.EH bit, which protects some data against double-faults, is only present with the MMU. Several exception cases did not check for status.EH being set, as required. The status.IH bit, which had been set by EXCP_IRQ, is exclusive to the external interrupt controller, which we do not yet implement. The internal interrupt controller, when the MMU is also present, sets the status.EH bit. Signed-off-by: Richard Henderson --- target/nios2/helper.c | 141 +++++++++++++----------------------------- 1 file changed, 44 insertions(+), 97 deletions(-) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index eeff032379..6019e2443b 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -49,6 +49,42 @@ void nios2_cpu_record_sigsegv(CPUState *cs, vaddr addr, =20 #else /* !CONFIG_USER_ONLY */ =20 +static void do_exception(Nios2CPU *cpu, uint32_t exception_addr, bool is_b= reak) +{ + CPUNios2State *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); + uint32_t old_status =3D env->ctrl[CR_STATUS]; + uint32_t new_status =3D old_status; + + if ((old_status & CR_STATUS_EH) =3D=3D 0) { + int r_ea =3D R_EA, cr_es =3D CR_ESTATUS; + + if (is_break) { + r_ea =3D R_BA; + cr_es =3D CR_BSTATUS; + } + env->ctrl[cr_es] =3D old_status; + env->regs[r_ea] =3D env->pc + 4; + + if (cpu->mmu_present) { + new_status |=3D CR_STATUS_EH; + } + } + + new_status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); + + env->ctrl[CR_STATUS] =3D new_status; + env->ctrl[CR_EXCEPTION] =3D FIELD_DP32(env->ctrl[CR_EXCEPTION], + CR_EXCEPTION, CAUSE, + cs->exception_index); + env->pc =3D exception_addr; +} + +static void do_iic_irq(Nios2CPU *cpu) +{ + do_exception(cpu, cpu->exception_addr, false); +} + void nios2_cpu_do_interrupt(CPUState *cs) { Nios2CPU *cpu =3D NIOS2_CPU(cs); @@ -56,57 +92,20 @@ void nios2_cpu_do_interrupt(CPUState *cs) =20 switch (cs->exception_index) { case EXCP_IRQ: - assert(env->ctrl[CR_STATUS] & CR_STATUS_PIE); - qemu_log_mask(CPU_LOG_INT, "interrupt at pc=3D%x\n", env->pc); - - env->ctrl[CR_ESTATUS] =3D env->ctrl[CR_STATUS]; - env->ctrl[CR_STATUS] |=3D CR_STATUS_IH; - env->ctrl[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); - - env->ctrl[CR_EXCEPTION] =3D FIELD_DP32(env->ctrl[CR_EXCEPTION], - CR_EXCEPTION, CAUSE, - cs->exception_index); - - env->regs[R_EA] =3D env->pc + 4; - env->pc =3D cpu->exception_addr; + do_iic_irq(cpu); break; =20 case EXCP_TLBD: if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=3D%x\n", env= ->pc); - - /* Fast TLB miss */ - /* Variation from the spec. Table 3-35 of the cpu reference sh= ows - * estatus not being changed for TLB miss but this appears to - * be incorrect. */ - env->ctrl[CR_ESTATUS] =3D env->ctrl[CR_STATUS]; - env->ctrl[CR_STATUS] |=3D CR_STATUS_EH; - env->ctrl[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); - - env->ctrl[CR_EXCEPTION] =3D FIELD_DP32(env->ctrl[CR_EXCEPTION], - CR_EXCEPTION, CAUSE, - cs->exception_index); - env->ctrl[CR_TLBMISC] &=3D ~CR_TLBMISC_DBL; env->ctrl[CR_TLBMISC] |=3D CR_TLBMISC_WE; - - env->regs[R_EA] =3D env->pc + 4; - env->pc =3D cpu->fast_tlb_miss_addr; + do_exception(cpu, cpu->fast_tlb_miss_addr, false); } else { qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=3D%x\n", e= nv->pc); - - /* Double TLB miss */ - env->ctrl[CR_STATUS] |=3D CR_STATUS_EH; - env->ctrl[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); - - env->ctrl[CR_EXCEPTION] =3D FIELD_DP32(env->ctrl[CR_EXCEPTION], - CR_EXCEPTION, CAUSE, - cs->exception_index); - env->ctrl[CR_TLBMISC] |=3D CR_TLBMISC_DBL; - - env->pc =3D cpu->exception_addr; + do_exception(cpu, cpu->exception_addr, false); } break; =20 @@ -114,78 +113,28 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_TLBW: case EXCP_TLBX: qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=3D%x\n", env->pc); - - env->ctrl[CR_ESTATUS] =3D env->ctrl[CR_STATUS]; - env->ctrl[CR_STATUS] |=3D CR_STATUS_EH; - env->ctrl[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); - - env->ctrl[CR_EXCEPTION] =3D FIELD_DP32(env->ctrl[CR_EXCEPTION], - CR_EXCEPTION, CAUSE, - cs->exception_index); - if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { env->ctrl[CR_TLBMISC] |=3D CR_TLBMISC_WE; } - - env->regs[R_EA] =3D env->pc + 4; - env->pc =3D cpu->exception_addr; + do_exception(cpu, cpu->exception_addr, false); break; =20 case EXCP_SUPERA: case EXCP_SUPERI: case EXCP_SUPERD: qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=3D%x\n", en= v->pc); - - if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { - env->ctrl[CR_ESTATUS] =3D env->ctrl[CR_STATUS]; - env->regs[R_EA] =3D env->pc + 4; - } - - env->ctrl[CR_STATUS] |=3D CR_STATUS_EH; - env->ctrl[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); - - env->ctrl[CR_EXCEPTION] =3D FIELD_DP32(env->ctrl[CR_EXCEPTION], - CR_EXCEPTION, CAUSE, - cs->exception_index); - - env->pc =3D cpu->exception_addr; + do_exception(cpu, cpu->exception_addr, false); break; =20 case EXCP_ILLEGAL: case EXCP_TRAP: qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=3D%x\n", env->pc); - - if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { - env->ctrl[CR_ESTATUS] =3D env->ctrl[CR_STATUS]; - env->regs[R_EA] =3D env->pc + 4; - } - - env->ctrl[CR_STATUS] |=3D CR_STATUS_EH; - env->ctrl[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); - - env->ctrl[CR_EXCEPTION] =3D FIELD_DP32(env->ctrl[CR_EXCEPTION], - CR_EXCEPTION, CAUSE, - cs->exception_index); - - env->pc =3D cpu->exception_addr; + do_exception(cpu, cpu->exception_addr, false); break; =20 case EXCP_BREAK: qemu_log_mask(CPU_LOG_INT, "BREAK exception at pc=3D%x\n", env->pc= ); - - if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { - env->ctrl[CR_BSTATUS] =3D env->ctrl[CR_STATUS]; - env->regs[R_BA] =3D env->pc + 4; - } - - env->ctrl[CR_STATUS] |=3D CR_STATUS_EH; - env->ctrl[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); - - env->ctrl[CR_EXCEPTION] =3D FIELD_DP32(env->ctrl[CR_EXCEPTION], - CR_EXCEPTION, CAUSE, - cs->exception_index); - - env->pc =3D cpu->exception_addr; + do_exception(cpu, cpu->exception_addr, true); break; =20 case EXCP_SEMIHOST: @@ -195,9 +144,7 @@ void nios2_cpu_do_interrupt(CPUState *cs) break; =20 default: - cpu_abort(cs, "unhandled exception type=3D%d\n", - cs->exception_index); - break; + cpu_abort(cs, "unhandled exception type=3D%d\n", cs->exception_ind= ex); } } =20 --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646913686429548.2984579775699; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.27.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:27:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CrZNI1SxmaS+Q1Ja/qtDT6B5V9ddvf4cp0nG/uUGkSI=; b=vYrEtOkZvnsHvUObs23VxdT1EAqQKFFhCaHLdLJn540Cz4BByKl70igKU5xKjPk9AE VMBIzgJcTSEwOOIi6Wy6DyU8wVt96Hxye3Q70uaOnnAFMtISzwaustld1rpfAUhKwNKD 0JAr2xIM/SaofA2XXLR1JWepPRjyW6bpQQafKPfdUFVInQ7HrwS16Xb+2I/zLtKh640Z vlcbsc200a4DnoIpL+c11XcSew5x+QEUiTNAp7DFhsvmVqA2PAepziQTKk5yUullIkFs meZdpaBFfI6OIbd2oDtsencypQlXYhw89rBbfaebXM0QIYpyaC6yawKPel6dvJ00amkX rJuA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CrZNI1SxmaS+Q1Ja/qtDT6B5V9ddvf4cp0nG/uUGkSI=; b=C1pNl7ri2W9k6SX9RLXhm2G0hR7HDEec+2KyI6GJNHA6SVMJ5uDNqRUfoDduH2ZoDL 2oCPiVJf6qdxdV6fSCAOxumZy3HR+iZzuew/7LrWN8YlvsZO6zLcycD4BhNysdotHcwu zkIq2YV4182qX8Vju0uyr9wkqXfL8/Tdp3olBuyChtQTKmrmCurasmYis78Eqzrt8XH5 DleOKnNIMEGmGEBaWNgc/+ZTBDr1NARuHiTEpuKOclxLvci2ADR1S1DDsf0txadZIbTr vaAUcqiNK+R9crwcgDrdO25JZQcWxKPU+W1tQ1QfnfUMlRmtg+JcYV5F5zJZvemJo7ic j9yA== X-Gm-Message-State: AOAM530kqcv7+Ue0L4qUikg9D97Zopr/3bIJ3FoCtO6Ftzo7oj1/kqZ4 xb/qbt64TgayTzyff9pHNseLa0hNzvYSLw== X-Google-Smtp-Source: ABdhPJzlvK36l4oDJLTHcpFP6o7pXUf+mv01N6mypCsjV8x1WkKtRj8A/YDeUs5YC4DckK8SzEyISg== X-Received: by 2002:a17:902:e74e:b0:151:c46f:6e18 with SMTP id p14-20020a170902e74e00b00151c46f6e18mr4491481plf.32.1646911670987; Thu, 10 Mar 2022 03:27:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 22/48] target/nios2: Hoist CPU_LOG_INT logging Date: Thu, 10 Mar 2022 03:26:59 -0800 Message-Id: <20220310112725.570053-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102f (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646913716989100001 Content-Type: text/plain; charset="utf-8" Performing this early means that we can merge more cases within the non-logging switch statement. Signed-off-by: Richard Henderson --- target/nios2/helper.c | 58 +++++++++++++++++++++++++++++++++++-------- 1 file changed, 47 insertions(+), 11 deletions(-) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 6019e2443b..285f3aae1d 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -90,20 +90,64 @@ void nios2_cpu_do_interrupt(CPUState *cs) Nios2CPU *cpu =3D NIOS2_CPU(cs); CPUNios2State *env =3D &cpu->env; =20 + if (qemu_loglevel_mask(CPU_LOG_INT)) { + const char *name =3D NULL; + + switch (cs->exception_index) { + case EXCP_IRQ: + name =3D "interrupt"; + break; + case EXCP_TLBD: + if (env->ctrl[CR_STATUS] & CR_STATUS_EH) { + name =3D "TLB MISS (double)"; + } else { + name =3D "TLB MISS (fast)"; + } + break; + case EXCP_TLBR: + case EXCP_TLBW: + case EXCP_TLBX: + name =3D "TLB PERM"; + break; + case EXCP_SUPERA: + case EXCP_SUPERD: + name =3D "SUPERVISOR (address)"; + break; + case EXCP_SUPERI: + name =3D "SUPERVISOR (insn)"; + break; + case EXCP_ILLEGAL: + name =3D "ILLEGAL insn"; + break; + case EXCP_TRAP: + name =3D "TRAP insn"; + break; + case EXCP_BREAK: + name =3D "TRAP insn"; + break; + case EXCP_SEMIHOST: + name =3D "SEMIHOST insn"; + break; + } + if (name) { + qemu_log("%s at pc=3D0x%08x\n", name, env->pc); + } else { + qemu_log("Unknown exception %d at pc=3D0x%08x\n", + cs->exception_index, env->pc); + } + } + switch (cs->exception_index) { case EXCP_IRQ: - qemu_log_mask(CPU_LOG_INT, "interrupt at pc=3D%x\n", env->pc); do_iic_irq(cpu); break; =20 case EXCP_TLBD: if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { - qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=3D%x\n", env= ->pc); env->ctrl[CR_TLBMISC] &=3D ~CR_TLBMISC_DBL; env->ctrl[CR_TLBMISC] |=3D CR_TLBMISC_WE; do_exception(cpu, cpu->fast_tlb_miss_addr, false); } else { - qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=3D%x\n", e= nv->pc); env->ctrl[CR_TLBMISC] |=3D CR_TLBMISC_DBL; do_exception(cpu, cpu->exception_addr, false); } @@ -112,7 +156,6 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_TLBR: case EXCP_TLBW: case EXCP_TLBX: - qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=3D%x\n", env->pc); if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { env->ctrl[CR_TLBMISC] |=3D CR_TLBMISC_WE; } @@ -122,23 +165,16 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_SUPERA: case EXCP_SUPERI: case EXCP_SUPERD: - qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=3D%x\n", en= v->pc); - do_exception(cpu, cpu->exception_addr, false); - break; - case EXCP_ILLEGAL: case EXCP_TRAP: - qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=3D%x\n", env->pc); do_exception(cpu, cpu->exception_addr, false); break; =20 case EXCP_BREAK: - qemu_log_mask(CPU_LOG_INT, "BREAK exception at pc=3D%x\n", env->pc= ); do_exception(cpu, cpu->exception_addr, true); break; =20 case EXCP_SEMIHOST: - qemu_log_mask(CPU_LOG_INT, "BREAK semihosting at pc=3D%x\n", env->= pc); env->pc +=3D 4; do_nios2_semihosting(env); break; --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646914361204994.3161521262299; Thu, 10 Mar 2022 04:12:41 -0800 (PST) Received: from localhost ([::1]:43038 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHeq-0006Rg-1H for importer@patchew.org; Thu, 10 Mar 2022 07:12:40 -0500 Received: from eggs.gnu.org ([209.51.188.92]:50874) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGxX-0005nW-6e for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:55 -0500 Received: from [2607:f8b0:4864:20::1036] (port=42533 helo=mail-pj1-x1036.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGxV-0007zS-PS for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:54 -0500 Received: by mail-pj1-x1036.google.com with SMTP id c16-20020a17090aa61000b001befad2bfaaso4970182pjq.1 for ; Thu, 10 Mar 2022 03:27:53 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.27.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:27:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GQKtq5EmgHv2pf8acDMhuJ8SB17+NoN37aNM30IhfvE=; b=jtOiGy3FYwQP3MCPQKueM36CjJDClkhfzP7GS1+H6iFjFbaIXyJp1fZpmcMN5vi1JW qhuify425kryo/WWX5g5MFg9FAHMSm6N0SVWagC2XWw25AFjw89Xqa/NnVXZneZpCGgH N15S6EBfr/5VKd9Q9GcD8taM7E3w+wpHQ+FKxE9W2ePy3jht47IGi95b4dz3kE44Ii6z tdzNlpZRh7DUWpWPqUWW9WGK3iB4FgFfaGtW7Qi1ehVWHxwtHUYISBM3yvxWQLAFLJLr O0QRVJrWth9FgbsTf+A9sg4N5TBt/MMoYuK3aaKKsBCKxXzRUIKQcBfS8PF9W9OcWu1M HwyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GQKtq5EmgHv2pf8acDMhuJ8SB17+NoN37aNM30IhfvE=; b=hjHS8HWjYQr5vKPiMRlfE/QSTH6EDkGr92jpIaUKZteMvxuUUGGXrMcUZdpfMCNr4n PRgXoPd5PMw3OPWVZATo7HorTLBOOkCOcQnQtejB1+50NHwTp4b8A+nJ70cJx63FkBeH Gs216/ZSarLT+dgdPEodCRF2KIfSxYSW8l2i+A/PKSYkMtldsQSUXy4BfXZA2ALiY7sT QhsMT7wZww7JxeIv4HgQMn1kmrhHnjchCrEsiUtB5PH8arynwBGXXBWPlnIQluB3tRE7 7C4XQuJEAbuSUbCHG8+VwjOpnJP2QyvJuQGNr5r/nn4tfy7tunsGKBW5PTfyBW4Lnv+h 1bvA== X-Gm-Message-State: AOAM530jmoGLqLDR0tIeCXUyIqeXvVkljgEC39AWGkjUKqpxMZ4ezWn/ HG4XSqnrA1jl8SLLlEYUfgg6mSBruA6MHw== X-Google-Smtp-Source: ABdhPJzXVUyvhHQDiY4OLa1tBTIAQSusDweAX2LhG57unBu3gnXq7sN4oG25YPSOzuAwct4qTvXbCw== X-Received: by 2002:a17:90b:788:b0:1bf:41d:a9ff with SMTP id l8-20020a17090b078800b001bf041da9ffmr4456639pjz.116.1646911672487; Thu, 10 Mar 2022 03:27:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 23/48] target/nios2: Handle EXCP_UNALIGN and EXCP_UALIGND Date: Thu, 10 Mar 2022 03:27:00 -0800 Message-Id: <20220310112725.570053-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1036 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646914362903100001 Content-Type: text/plain; charset="utf-8" These misaligned data and misaligned destination exceptions are defined, but not currently raised. Signed-off-by: Richard Henderson --- target/nios2/helper.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 285f3aae1d..0392c0ea84 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -119,6 +119,12 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_ILLEGAL: name =3D "ILLEGAL insn"; break; + case EXCP_UNALIGN: + name =3D "Misaligned (data)"; + break; + case EXCP_UNALIGND: + name =3D "Misaligned (destination)"; + break; case EXCP_TRAP: name =3D "TRAP insn"; break; @@ -167,6 +173,8 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_SUPERD: case EXCP_ILLEGAL: case EXCP_TRAP: + case EXCP_UNALIGN: + case EXCP_UNALIGND: do_exception(cpu, cpu->exception_addr, false); break; =20 --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646914566124635.6075550891177; Thu, 10 Mar 2022 04:16:06 -0800 (PST) Received: from localhost ([::1]:49584 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHi9-0002NP-47 for importer@patchew.org; Thu, 10 Mar 2022 07:16:05 -0500 Received: from eggs.gnu.org ([209.51.188.92]:50890) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGxY-0005sT-Tu for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:56 -0500 Received: from [2607:f8b0:4864:20::62d] (port=35569 helo=mail-pl1-x62d.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGxX-0007ze-8v for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:56 -0500 Received: by mail-pl1-x62d.google.com with SMTP id n15so4609254plh.2 for ; Thu, 10 Mar 2022 03:27:54 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.27.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:27:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=kC6IYNjsGbxQ1O1vqjxYEFxpw4YN+TjfQjKfECaeneY=; b=E+FqzeMLYkMsGZA46EH5rxCmD2SIxJ64cuBJoFwAqf5xmz6H73ANYIFCxyKAJ7SgH0 DDYkf6nzX/ODRTrt2MbcnmWSoMTtgKi9zcjIxqvH4zbblq9mhdG3ew7f9e8jk+QpQzqN H7bW7ls/UK3ZSUmH/lwEUkNawNe6G9rig9yc8xgx9Lb2M7sKxwg4xgv+hhA3IR1p1S6o GiF/YFqrBtJGqJZPUQl5N8pNBy+9ZZAkecj7TtSA597c19Q/anPdRTq96RZvk48D4/+u aUe5iu2lFzs8OyPW7QIuHurt/TEYeyRJxA3a13k8MmouQnSYFLJOjYV15d/nREFN0SW5 M6lw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=kC6IYNjsGbxQ1O1vqjxYEFxpw4YN+TjfQjKfECaeneY=; b=JGK3t2DPuqXNyGGdI7d1CKVMs+MCZalaq+Qdg+wbMI5BWI8Nl/WMCGvJb/u2+kT9Er vrVrfm1q0P3RdBBmkrfSnFHPQp82Dg/6sucULgDo5Fxg2vIQSIfRq/AIoii4qJS/tmnD 8XbdesU4KCUnzFR7rO/zxBoR8z6CQBfMB1/BshBw1H178RKs/1ggo9+7BhuMbVb6SVy+ kCURpOjfSA2bB9anc3hPYv7qFNArc9uFU3uhvxcBrWh6MNOhqUV2RerM4HOYaIovRSm1 9NLL/C2h7LhY5294CjNTbPELnZ4zzaGsX4xC5yBg9deffxLOtly+jTdU923I+eJcq8wu a62A== X-Gm-Message-State: AOAM532UlDsFq+fsyA5SCH6nOdgfNDs7axFngbOMe8guX69WEatMLDLe qYsLrygxOoP4vScobSO2kqlD4k6dZBXkQA== X-Google-Smtp-Source: ABdhPJxfjs54To/dsxqoPwUcez210IR7RKzYrtvdry31OcnQ9zY4h/Zzg3hD/pniFVqXOknDODrF4g== X-Received: by 2002:a17:902:720a:b0:151:d7d7:6ac0 with SMTP id ba10-20020a170902720a00b00151d7d76ac0mr4410040plb.128.1646911673955; Thu, 10 Mar 2022 03:27:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 24/48] target/nios2: Cleanup set of CR_EXCEPTION for do_interrupt Date: Thu, 10 Mar 2022 03:27:01 -0800 Message-Id: <20220310112725.570053-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62d (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646914568435100001 Content-Type: text/plain; charset="utf-8" The register is entirely read-only for software, and we do not implement ECC, so we need not deposit the cause into an existing value; just create a new value from scratch. Furthermore, exception.CAUSE is not written for break exceptions. Signed-off-by: Richard Henderson --- target/nios2/helper.c | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 0392c0ea84..afbafd1fdc 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -74,9 +74,10 @@ static void do_exception(Nios2CPU *cpu, uint32_t excepti= on_addr, bool is_break) new_status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); =20 env->ctrl[CR_STATUS] =3D new_status; - env->ctrl[CR_EXCEPTION] =3D FIELD_DP32(env->ctrl[CR_EXCEPTION], - CR_EXCEPTION, CAUSE, - cs->exception_index); + if (!is_break) { + env->ctrl[CR_EXCEPTION] =3D FIELD_DP32(0, CR_EXCEPTION, CAUSE, + cs->exception_index); + } env->pc =3D exception_addr; } =20 --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646914870837745.5841062536257; Thu, 10 Mar 2022 04:21:10 -0800 (PST) Received: from localhost ([::1]:58226 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHn3-0008Jz-Me for importer@patchew.org; Thu, 10 Mar 2022 07:21:09 -0500 Received: from eggs.gnu.org ([209.51.188.92]:50924) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGxb-0005xO-92 for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:59 -0500 Received: from [2607:f8b0:4864:20::630] (port=42704 helo=mail-pl1-x630.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGxZ-0007zt-CU for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:27:58 -0500 Received: by mail-pl1-x630.google.com with SMTP id p17so4584086plo.9 for ; Thu, 10 Mar 2022 03:27:56 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.27.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:27:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=EnAEYpcIY00+k1hPlmrXoRht11ltOEwUcRv8uGR7V3g=; b=HZRH8/99MaZQociLL7QMujn/GJYzHrvrrxLteENWlYL5pJb5vO3nGvXr1zjmifN+W+ 4NBuOWqrVe4IGYhUr+yPikV0MyNanVWM/qU46tfV2LqmnMngU4bB9HTIUcafG2Bt5FKO MIHzYaQInSDHM9yFepi+1McJkSCyU+TobnV49K1o/93ruaeo54WOcAHBo53yAn+0Pd1r LMLFCrrxsY+prSftKYhSfDR/D6gGk4fz2xuXT+2bd6jqHJhJkkBkay/gSIR8O1pbBwcl ZdrbOWctCqgTp4pXSmeV8RUv1M5WxoUZI6+jRVgD6JSth3uEbCA9bIx47ifTilkNkRGq oZzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EnAEYpcIY00+k1hPlmrXoRht11ltOEwUcRv8uGR7V3g=; b=1pb1q+z8JNHBbvHqxs6zmdWX4XJn4YRqvej/NsbpayW8Zhm23k/s6DtPs148YS+vTU 98KkFLqzohllWnc6ENF3rskl79tRii2ABZ89Nc/3yt+Tmld1MVM3gK0L+YFimIun4EzN o0VVnI44zhFqrADmE3d14PiPiCb0wJY6YymksDuF0Lgjqbhn1vaAhRcoXQPujHKjq8Wh +A3TCnL1MCRPue1mPzFfYcU97+3JOQy//AxUBFgp8O2Cy6x8dmhQrkoP67saYHvYVTyC 9BsNws6g7httQ4KhQVHiug3Wtsm23pur16AO5l3gpvTfj1qQSQvmrRE18ucDwhqLX0nr sIfA== X-Gm-Message-State: AOAM533iRb0yfWh1NHVAAdI1hxKwY47leUaaLTR2Ver2A/eD07OX+sm5 OTS4wydVEDgW48B0v3boVQyRWe1b1Ma5Yg== X-Google-Smtp-Source: ABdhPJzAU4WDrmyWuNerCKZ69QQALSFsvQsr7U9ndxrFM+Ja8ghTk4kpqNS0RxLOZ1fwtzSCe0DTtQ== X-Received: by 2002:a17:90b:1d04:b0:1bf:cd14:d3ff with SMTP id on4-20020a17090b1d0400b001bfcd14d3ffmr3628606pjb.67.1646911675257; Thu, 10 Mar 2022 03:27:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 25/48] target/nios2: Clean up handling of tlbmisc in do_exception Date: Thu, 10 Mar 2022 03:27:02 -0800 Message-Id: <20220310112725.570053-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::630 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646914872937100001 Content-Type: text/plain; charset="utf-8" The 4 lower bits, D, PERM, BAD, DBL, are unconditionally set on any exception with EH=3D0, or so says Table 42 (Processor Status After Taking Exception). We currently do not set PERM or BAD at all, and only set/clear DBL for tlb miss, and do not clear DBL for any other exception. It is a bit confusing to set D in tlb_fill and the rest during do_interrupt, so move the setting of D to do_interrupt as well. To do this, split EXP_TLBD into two cases, EXCP_TLB_X and EXCP_TLB_D, which allows us to distinguish them during do_interrupt. Choose a value for EXCP_TLB_D such that when truncated it produces the correct value for exception.CAUSE. Rename EXCP_TLB[RWX] to EXCP_PERM_[RWX], to emphasize that the exception is permissions related. Rename EXCP_SUPER[AD] to EXCP_SUPERA_[DX] to emphasize that they are both "supervisor address" exceptions, data and execute. Retain the setting of tlbmisc.WE for the fast-tlb-miss path, as it is being relied upon, but remove it from the permission path. Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 13 +++--- target/nios2/helper.c | 102 +++++++++++++++++++++++++++++------------- 2 files changed, 77 insertions(+), 38 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index d003af5afc..c925cdd8e3 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -166,13 +166,14 @@ FIELD(CR_TLBMISC, EE, 24, 1) #define EXCP_UNALIGN 6 #define EXCP_UNALIGND 7 #define EXCP_DIV 8 -#define EXCP_SUPERA 9 +#define EXCP_SUPERA_X 9 #define EXCP_SUPERI 10 -#define EXCP_SUPERD 11 -#define EXCP_TLBD 12 -#define EXCP_TLBX 13 -#define EXCP_TLBR 14 -#define EXCP_TLBW 15 +#define EXCP_SUPERA_D 11 +#define EXCP_TLB_X 12 +#define EXCP_TLB_D (0x1000 | EXCP_TLB_X) +#define EXCP_PERM_X 13 +#define EXCP_PERM_R 14 +#define EXCP_PERM_W 15 #define EXCP_MPUI 16 #define EXCP_MPUD 17 =20 diff --git a/target/nios2/helper.c b/target/nios2/helper.c index afbafd1fdc..8b69918ba3 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -49,7 +49,8 @@ void nios2_cpu_record_sigsegv(CPUState *cs, vaddr addr, =20 #else /* !CONFIG_USER_ONLY */ =20 -static void do_exception(Nios2CPU *cpu, uint32_t exception_addr, bool is_b= reak) +static void do_exception(Nios2CPU *cpu, uint32_t exception_addr, + uint32_t tlbmisc_set, bool is_break) { CPUNios2State *env =3D &cpu->env; CPUState *cs =3D CPU(cpu); @@ -68,6 +69,16 @@ static void do_exception(Nios2CPU *cpu, uint32_t excepti= on_addr, bool is_break) =20 if (cpu->mmu_present) { new_status |=3D CR_STATUS_EH; + + /* + * There are 4 bits that are always written. + * Explicitly clear them, to be set via the argument. + */ + env->ctrl[CR_TLBMISC] &=3D ~(CR_TLBMISC_D | + CR_TLBMISC_PERM | + CR_TLBMISC_BAD | + CR_TLBMISC_DBL); + env->ctrl[CR_TLBMISC] |=3D tlbmisc_set; } } =20 @@ -83,13 +94,14 @@ static void do_exception(Nios2CPU *cpu, uint32_t except= ion_addr, bool is_break) =20 static void do_iic_irq(Nios2CPU *cpu) { - do_exception(cpu, cpu->exception_addr, false); + do_exception(cpu, cpu->exception_addr, 0, false); } =20 void nios2_cpu_do_interrupt(CPUState *cs) { Nios2CPU *cpu =3D NIOS2_CPU(cs); CPUNios2State *env =3D &cpu->env; + uint32_t tlbmisc_set =3D 0; =20 if (qemu_loglevel_mask(CPU_LOG_INT)) { const char *name =3D NULL; @@ -98,20 +110,21 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_IRQ: name =3D "interrupt"; break; - case EXCP_TLBD: + case EXCP_TLB_X: + case EXCP_TLB_D: if (env->ctrl[CR_STATUS] & CR_STATUS_EH) { name =3D "TLB MISS (double)"; } else { name =3D "TLB MISS (fast)"; } break; - case EXCP_TLBR: - case EXCP_TLBW: - case EXCP_TLBX: + case EXCP_PERM_R: + case EXCP_PERM_W: + case EXCP_PERM_X: name =3D "TLB PERM"; break; - case EXCP_SUPERA: - case EXCP_SUPERD: + case EXCP_SUPERA_X: + case EXCP_SUPERA_D: name =3D "SUPERVISOR (address)"; break; case EXCP_SUPERI: @@ -149,38 +162,60 @@ void nios2_cpu_do_interrupt(CPUState *cs) do_iic_irq(cpu); break; =20 - case EXCP_TLBD: - if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { - env->ctrl[CR_TLBMISC] &=3D ~CR_TLBMISC_DBL; - env->ctrl[CR_TLBMISC] |=3D CR_TLBMISC_WE; - do_exception(cpu, cpu->fast_tlb_miss_addr, false); + case EXCP_TLB_D: + tlbmisc_set =3D CR_TLBMISC_D; + /* fall through */ + case EXCP_TLB_X: + if (env->ctrl[CR_STATUS] & CR_STATUS_EH) { + tlbmisc_set |=3D CR_TLBMISC_DBL; + /* + * Normally, we don't write to tlbmisc unless !EH, + * so do it manually for the double-tlb miss exception. + */ + env->ctrl[CR_TLBMISC] &=3D ~(CR_TLBMISC_D | + CR_TLBMISC_PERM | + CR_TLBMISC_BAD); + env->ctrl[CR_TLBMISC] |=3D tlbmisc_set; + do_exception(cpu, cpu->exception_addr, 0, false); } else { - env->ctrl[CR_TLBMISC] |=3D CR_TLBMISC_DBL; - do_exception(cpu, cpu->exception_addr, false); + /* + * ??? Implicitly setting tlbmisc.WE for the fast-tlb-miss + * handler appears to be out of spec. But, the linux kernel + * handler relies on it, writing to tlbacc without first + * setting tlbmisc.WE. + */ + tlbmisc_set |=3D CR_TLBMISC_WE; + do_exception(cpu, cpu->fast_tlb_miss_addr, tlbmisc_set, false); } break; =20 - case EXCP_TLBR: - case EXCP_TLBW: - case EXCP_TLBX: - if ((env->ctrl[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { - env->ctrl[CR_TLBMISC] |=3D CR_TLBMISC_WE; - } - do_exception(cpu, cpu->exception_addr, false); + case EXCP_PERM_R: + case EXCP_PERM_W: + tlbmisc_set =3D CR_TLBMISC_D; + /* fall through */ + case EXCP_PERM_X: + tlbmisc_set |=3D CR_TLBMISC_PERM; + do_exception(cpu, cpu->exception_addr, tlbmisc_set, false); + break; + + case EXCP_SUPERA_D: + case EXCP_UNALIGN: + tlbmisc_set =3D CR_TLBMISC_D; + /* fall through */ + case EXCP_SUPERA_X: + case EXCP_UNALIGND: + tlbmisc_set |=3D CR_TLBMISC_BAD; + do_exception(cpu, cpu->exception_addr, tlbmisc_set, false); break; =20 - case EXCP_SUPERA: case EXCP_SUPERI: - case EXCP_SUPERD: case EXCP_ILLEGAL: case EXCP_TRAP: - case EXCP_UNALIGN: - case EXCP_UNALIGND: - do_exception(cpu, cpu->exception_addr, false); + do_exception(cpu, cpu->exception_addr, 0, false); break; =20 case EXCP_BREAK: - do_exception(cpu, cpu->exception_addr, true); + do_exception(cpu, cpu->exception_addr, 0, true); break; =20 case EXCP_SEMIHOST: @@ -235,7 +270,7 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, { Nios2CPU *cpu =3D NIOS2_CPU(cs); CPUNios2State *env =3D &cpu->env; - unsigned int excp =3D EXCP_TLBD; + unsigned int excp; target_ulong vaddr, paddr; Nios2MMULookup lu; unsigned int hit; @@ -262,7 +297,8 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, if (probe) { return false; } - cs->exception_index =3D EXCP_SUPERA; + cs->exception_index =3D (access_type =3D=3D MMU_INST_FETCH + ? EXCP_SUPERA_X : EXCP_SUPERA_D); env->ctrl[CR_BADADDR] =3D address; cpu_loop_exit_restore(cs, retaddr); } @@ -283,8 +319,10 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, } =20 /* Permission violation */ - excp =3D (access_type =3D=3D MMU_DATA_LOAD ? EXCP_TLBR : - access_type =3D=3D MMU_DATA_STORE ? EXCP_TLBW : EXCP_TLBX); + excp =3D (access_type =3D=3D MMU_DATA_LOAD ? EXCP_PERM_R : + access_type =3D=3D MMU_DATA_STORE ? EXCP_PERM_W : EXCP_PER= M_X); + } else { + excp =3D (access_type =3D=3D MMU_INST_FETCH ? EXCP_TLB_X: EXCP_TLB= _D); } =20 if (probe) { --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164691405817010.781121137778882; Thu, 10 Mar 2022 04:07:38 -0800 (PST) Received: from localhost ([::1]:36148 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHZw-00015A-Qo for importer@patchew.org; Thu, 10 Mar 2022 07:07:36 -0500 Received: from eggs.gnu.org ([209.51.188.92]:50968) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGxd-00064X-Q4 for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:28:01 -0500 Received: from [2607:f8b0:4864:20::62b] (port=36634 helo=mail-pl1-x62b.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGxb-00080G-OE for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:28:01 -0500 Received: by mail-pl1-x62b.google.com with SMTP id e13so4606203plh.3 for ; Thu, 10 Mar 2022 03:27:59 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.27.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:27:55 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=t6Arg14tlq3SbtAOWylBKjkAobqm1S/G3HUBx+owul4=; b=u4d07xsxDZllfiLr6CNgW1eikocieJMlubrrLduuaUQtmWWhFyGFao/R48KBo8DUlK TLne3Z67I/hEctA1Ra/BW6l6DkftdC5GGZgNj5GB41uIT7UaTChs8C3IGIqxvSudCsbm Jxr0Alm7BX2J43VqXUkvM+8Z9coYGGQK5ZDnhzYPBEUhp9KVJd5UPUaKrNIaUhTBpST2 xSwslrOiQI50dSxe+WE4uet3Xy6M08JqUFV+NXv8KSWWB9PHOBr6IGqIQPfpiOAlxrSF uKljG+szVZnwBsfZALeLTTh2nlbOdPyZhaQDk/r0bFdz2a5viXpHZpvEDymG1qLv3ww+ 0j8A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=t6Arg14tlq3SbtAOWylBKjkAobqm1S/G3HUBx+owul4=; b=Wp/dpT4ZVhqJ6zrA3/8FBEGsxb0/OguQEBNfNm5A35Is8YEl+euupnQTohDH61r8hN E2XqUaCpM3qjk2queZCajvBdORevmOttSdW4XVfW/E+0j5GP6GBCWueb7qSsOx69QBob M5Q24RvngY1utVc8+FXFRSK/gUs7CtGjS56Y3pnZMmW6xl6giB4qoJpCNHid1TWhiuMF 1fJjczZ285nDtiK+G6UlXqpdGWN+rzNz1Q7+1zBIQ/CXtL4JZBH5ZctLCXNzVVBsIQFE u8ulb97PCVID95cF96+tzt0MIqOApnX7jkLYLJzF4rMRzzs6WIGrCkAaFUwgBGKMQpHT A0hA== X-Gm-Message-State: AOAM532IVBSjs9TR2U23EAEwZkQA2tGIIpe1ljBvasOmhsW2pYI7gN5o cJ/BN2DTnz3nyK16I1c0z+sH4EFXHaM2JA== X-Google-Smtp-Source: ABdhPJzfLgoHsHCLC/z1T7PQt0Ahm27DsuOIromhDrzWQYOdOZm+bPdqT+lG2OvUeVFmwoVad1OL1w== X-Received: by 2002:a17:90a:4d07:b0:1bf:6ac4:b94a with SMTP id c7-20020a17090a4d0700b001bf6ac4b94amr15292489pjg.89.1646911676546; Thu, 10 Mar 2022 03:27:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 26/48] target/nios2: Prevent writes to read-only or reserved control fields Date: Thu, 10 Mar 2022 03:27:03 -0800 Message-Id: <20220310112725.570053-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62b (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646914058731100001 Content-Type: text/plain; charset="utf-8" Create an array of masks which detail the writable and readonly bits for each control register. Apply them when writing to control registers, including the write to status during eret. Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 13 ++++++ target/nios2/cpu.c | 94 +++++++++++++++++++++++++++++++++------- target/nios2/op_helper.c | 9 ++++ target/nios2/translate.c | 80 +++++++++++++++++++++++++++------- 4 files changed, 165 insertions(+), 31 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index c925cdd8e3..410e76ccbb 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -190,6 +190,11 @@ struct CPUArchState { int error_code; }; =20 +typedef struct { + uint32_t writable; + uint32_t readonly; +} ControlRegState; + /** * Nios2CPU: * @env: #CPUNios2State @@ -213,9 +218,17 @@ struct ArchCPU { uint32_t reset_addr; uint32_t exception_addr; uint32_t fast_tlb_miss_addr; + + /* Bits within each control register which are reserved or readonly. */ + ControlRegState cr_state[NUM_CR_REGS]; }; =20 =20 +static inline bool nios2_cr_reserved(const ControlRegState *s) +{ + return (s->writable | s->readonly) =3D=3D 0; +} + void nios2_tcg_init(void); void nios2_cpu_do_interrupt(CPUState *cs); void dump_mmu(CPUNios2State *env); diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 97bdc0a61b..ce2b0c6493 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -88,6 +88,59 @@ static void nios2_cpu_initfn(Object *obj) =20 cpu_set_cpustate_pointers(cpu); =20 + /* Begin with all fields of all registers are reserved. */ + memset(cpu->cr_state, 0, sizeof(cpu->cr_state)); + + /* + * The combination of writable and readonly is the set of all + * non-reserved fields. We apply writable as a mask to bits, + * and merge in existing readonly bits, before storing. + */ +#define WR_REG(C) cpu->cr_state[C].writable =3D -1 +#define RO_REG(C) cpu->cr_state[C].readonly =3D -1 +#define WR_FIELD(C, F) cpu->cr_state[C].writable |=3D R_##C##_##F##_MASK +#define RO_FIELD(C, F) cpu->cr_state[C].readonly |=3D R_##C##_##F##_MASK + + WR_FIELD(CR_STATUS, PIE); + WR_REG(CR_ESTATUS); + WR_REG(CR_BSTATUS); + RO_REG(CR_CPUID); + RO_REG(CR_EXCEPTION); + WR_REG(CR_BADADDR); + + /* TODO: These control registers are not present with the EIC. */ + WR_REG(CR_IENABLE); + RO_REG(CR_IPENDING); + + if (cpu->mmu_present) { + WR_FIELD(CR_STATUS, U); + WR_FIELD(CR_STATUS, EH); + + WR_FIELD(CR_PTEADDR, VPN); + WR_FIELD(CR_PTEADDR, PTBASE); + + RO_FIELD(CR_TLBMISC, D); + RO_FIELD(CR_TLBMISC, PERM); + RO_FIELD(CR_TLBMISC, BAD); + RO_FIELD(CR_TLBMISC, DBL); + WR_FIELD(CR_TLBMISC, PID); + WR_FIELD(CR_TLBMISC, WE); + WR_FIELD(CR_TLBMISC, RD); + WR_FIELD(CR_TLBMISC, WAY); + + WR_REG(CR_TLBACC); + } + + /* + * TODO: ECC (config, eccinj) and MPU (config, mpubase, mpuacc) are + * unimplemented, so their corresponding control regs remain reserved. + */ + +#undef WR_REG +#undef RO_REG +#undef WR_FIELD +#undef RO_FIELD + #if !defined(CONFIG_USER_ONLY) mmu_init(&cpu->env); =20 @@ -152,23 +205,26 @@ static void nios2_cpu_disas_set_info(CPUState *cpu, d= isassemble_info *info) static int nios2_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, = int n) { Nios2CPU *cpu =3D NIOS2_CPU(cs); - CPUClass *cc =3D CPU_GET_CLASS(cs); CPUNios2State *env =3D &cpu->env; + uint32_t val; =20 - if (n > cc->gdb_num_core_regs) { + if (n < 32) { /* GP regs */ + val =3D env->regs[n]; + } else if (n =3D=3D 32) { /* PC */ + val =3D env->pc; + } else if (n < 49) { /* Status regs */ + unsigned cr =3D n - 33; + if (nios2_cr_reserved(&cpu->cr_state[cr])) { + val =3D 0; + } else { + val =3D env->ctrl[n - 33]; + } + } else { + /* Invalid regs */ return 0; } =20 - if (n < 32) { /* GP regs */ - return gdb_get_reg32(mem_buf, env->regs[n]); - } else if (n =3D=3D 32) { /* PC */ - return gdb_get_reg32(mem_buf, env->pc); - } else if (n < 49) { /* Status regs */ - return gdb_get_reg32(mem_buf, env->ctrl[n - 33]); - } - - /* Invalid regs */ - return 0; + return gdb_get_reg32(mem_buf, val); } =20 static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, in= t n) @@ -176,17 +232,25 @@ static int nios2_cpu_gdb_write_register(CPUState *cs,= uint8_t *mem_buf, int n) Nios2CPU *cpu =3D NIOS2_CPU(cs); CPUClass *cc =3D CPU_GET_CLASS(cs); CPUNios2State *env =3D &cpu->env; + uint32_t val; =20 if (n > cc->gdb_num_core_regs) { return 0; } + val =3D ldl_p(mem_buf); =20 if (n < 32) { /* GP regs */ - env->regs[n] =3D ldl_p(mem_buf); + env->regs[n] =3D val; } else if (n =3D=3D 32) { /* PC */ - env->pc =3D ldl_p(mem_buf); + env->pc =3D val; } else if (n < 49) { /* Status regs */ - env->ctrl[n - 33] =3D ldl_p(mem_buf); + unsigned cr =3D n - 33; + /* ??? Maybe allow the debugger to write to readonly fields. */ + val &=3D cpu->cr_state[cr].writable; + val |=3D cpu->cr_state[cr].readonly & env->ctrl[cr]; + env->ctrl[cr] =3D val; + } else { + g_assert_not_reached(); } =20 return 4; diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index 08ed3b4598..c56fc15283 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -34,6 +34,15 @@ void helper_raise_exception(CPUNios2State *env, uint32_t= index) #ifndef CONFIG_USER_ONLY void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc) { + Nios2CPU *cpu =3D env_archcpu(env); + + /* + * Both estatus and bstatus have no constraints on write; + * do not allow reserved fields in status to be set. + */ + new_status &=3D (cpu->cr_state[CR_STATUS].writable | + cpu->cr_state[CR_STATUS].readonly); + env->ctrl[CR_STATUS] =3D new_status; env->pc =3D new_pc; cpu_loop_exit(env_cpu(env)); diff --git a/target/nios2/translate.c b/target/nios2/translate.c index cfad110186..21dc6947cf 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -102,6 +102,7 @@ typedef struct DisasContext { TCGv_i32 zero; target_ulong pc; int mem_idx; + const ControlRegState *cr_state; } DisasContext; =20 static TCGv cpu_R[NUM_GP_REGS]; @@ -471,17 +472,26 @@ static void callr(DisasContext *dc, uint32_t code, ui= nt32_t flags) /* rC <- ctlN */ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) { - R_TYPE(instr, code); - TCGv t1, t2; - if (!gen_check_supervisor(dc)) { return; } =20 +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + R_TYPE(instr, code); + TCGv t1, t2; + if (unlikely(instr.c =3D=3D R_ZERO)) { return; } =20 + /* Reserved registers read as zero. */ + if (nios2_cr_reserved(&dc->cr_state[instr.imm5])) { + tcg_gen_movi_tl(cpu_R[instr.c], 0); + return; + } + switch (instr.imm5) { case CR_IPENDING: /* @@ -505,6 +515,7 @@ static void rdctl(DisasContext *dc, uint32_t code, uint= 32_t flags) offsetof(CPUNios2State, ctrl[instr.imm5])); break; } +#endif } =20 /* ctlN <- rA */ @@ -519,6 +530,14 @@ static void wrctl(DisasContext *dc, uint32_t code, uin= t32_t flags) #else R_TYPE(instr, code); TCGv v =3D load_gpr(dc, instr.a); + uint32_t ofs =3D offsetof(CPUNios2State, ctrl[instr.imm5]); + uint32_t wr =3D dc->cr_state[instr.imm5].writable; + uint32_t ro =3D dc->cr_state[instr.imm5].readonly; + + /* Skip reserved or readonly registers. */ + if (wr =3D=3D 0) { + return; + } =20 switch (instr.imm5) { case CR_PTEADDR: @@ -530,17 +549,35 @@ static void wrctl(DisasContext *dc, uint32_t code, ui= nt32_t flags) case CR_TLBMISC: gen_helper_mmu_write_tlbmisc(cpu_env, v); break; - case CR_IPENDING: - /* ipending is read only, writes ignored. */ - break; case CR_STATUS: case CR_IENABLE: /* If interrupts were enabled using WRCTL, trigger them. */ dc->base.is_jmp =3D DISAS_UPDATE; /* fall through */ default: - tcg_gen_st_tl(v, cpu_env, - offsetof(CPUNios2State, ctrl[instr.imm5])); + if (wr =3D=3D -1) { + /* The register is entirely writable. */ + tcg_gen_st_tl(v, cpu_env, ofs); + } else { + /* + * The register is partially read-only or reserved: + * merge the value. + */ + TCGv n =3D tcg_temp_new(); + + tcg_gen_andi_tl(n, v, wr); + + if (ro !=3D 0) { + TCGv o =3D tcg_temp_new(); + tcg_gen_ld_tl(o, cpu_env, ofs); + tcg_gen_andi_tl(o, o, ro); + tcg_gen_or_tl(n, n, o); + tcg_temp_free(o); + } + + tcg_gen_st_tl(n, cpu_env, ofs); + tcg_temp_free(n); + } break; } #endif @@ -818,9 +855,11 @@ static void nios2_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUNios2State *env =3D cs->env_ptr; + Nios2CPU *cpu =3D env_archcpu(env); int page_insns; =20 dc->mem_idx =3D cpu_mmu_index(env, false); + dc->cr_state =3D cpu->cr_state; =20 /* Bound the number of insns to execute to those left on the page. */ page_insns =3D -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; @@ -931,16 +970,25 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int = flags) } =20 #if !defined(CONFIG_USER_ONLY) - for (i =3D 0; i < NUM_CR_REGS; i++) { - qemu_fprintf(f, "%9s=3D%8.8x ", cr_regnames[i], env->ctrl[i]); - if ((i + 1) % 4 =3D=3D 0) { - qemu_fprintf(f, "\n"); + int j; + + for (i =3D j =3D 0; i < NUM_CR_REGS; i++) { + if (!nios2_cr_reserved(&cpu->cr_state[i])) { + qemu_fprintf(f, "%9s=3D%8.8x ", cr_regnames[i], env->ctrl[i]); + if (++j % 4 =3D=3D 0) { + qemu_fprintf(f, "\n"); + } } } - qemu_fprintf(f, " mmu write: VPN=3D%05X PID %02X TLBACC %08X\n", - env->mmu.pteaddr_wr & R_CR_PTEADDR_VPN_MASK, - FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID), - env->mmu.tlbacc_wr); + if (j % 4 !=3D 0) { + qemu_fprintf(f, "\n"); + } + if (cpu->mmu_present) { + qemu_fprintf(f, " mmu write: VPN=3D%05X PID %02X TLBACC %08X\n", + env->mmu.pteaddr_wr & R_CR_PTEADDR_VPN_MASK, + FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID), + env->mmu.tlbacc_wr); + } #endif qemu_fprintf(f, "\n\n"); } --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.27.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:27:57 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=O8yV5sFKZ931fgVLOgWvtxvBKBH4NQ4GdxvxJ8ycVLk=; b=Uusg49HLaN7UQ4M88l8vhFOywqJSuEhV9EX6T87hxr0jthadi0Dobf2qSbTqwz/aAu EdjUc1/518Pxa1NkOh6bayAEUlaTKEIfdaxfHU4MFrirZI42nhkLD4dxTrjY4++Zlzr1 PgwGV1R0CBK9/nyICcxRbuOTytfyuAKMv1j8VShbhcYVFzVrQ/bVdS5xzdBbBbMz2Sbz nk0MGTCbA4YCd3kHPQLQ3rJMYcuy9zxAFYhdGJvTAagLRbNl8PQfKZXHciAmpsSMNkq3 DAmMCInKS6NAmOwQmZEMsOasH/tEgY/zJK3CxgN7PBdSebSJNwIacY6gjs58ur3Wwd4A tt5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=O8yV5sFKZ931fgVLOgWvtxvBKBH4NQ4GdxvxJ8ycVLk=; b=YFSjpD2m81tjnqaoIayRNH5S5jyuHgCCwf0Vio4Xxs51CgDutRdKYYlmG/O6e5qVlQ ZtZqQNYtKdtJjvAQ6uVjlHYbphRL+cl7xkotQ/eZq4SqfDpVW5DHvH0VpDYqcEue8B6U I4Ad9BuWY2I4x9Mce7YYIYonYxpS00KcDsqihh/y8tRV6dciZU+zJiYGMPvAN+FMHT6r GI0hNeMm70Uh+e59mGGjH45pwbAVfUp7No76EBAM4YRbdY+8sKnTZ5dqmRZw4S49agW2 OMIEAwS++DvBa56vhzUkt+flnIB6kUOsHfRNslmTGJDwtfTuikI4AftdiZXm7JvvWLTu WVcA== X-Gm-Message-State: AOAM530aTepBTQLzxuLJdGQlyCT8NIQhQA8fHR8f78r+9R6x+2YuY9hG TUHIETSTYCYjWFnSwdIZh8Mct8eTvhjuFw== X-Google-Smtp-Source: ABdhPJwJtAo+93UmfurvFx01FaJbhKtiiQ1IpPP4dZ5dMqMsFJYOJpUfBiS8MBKYcdfx1tcjJ2gTxw== X-Received: by 2002:a63:7c5c:0:b0:380:7412:341b with SMTP id l28-20020a637c5c000000b003807412341bmr3701409pgn.38.1646911677833; Thu, 10 Mar 2022 03:27:57 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 27/48] target/nios2: Implement cpuid Date: Thu, 10 Mar 2022 03:27:04 -0800 Message-Id: <20220310112725.570053-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::52e (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646913840134100001 Content-Type: text/plain; charset="utf-8" Copy the existing cpu_index into the space reserved for CR_CPUID. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index ce2b0c6493..d491360973 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -163,6 +163,7 @@ static ObjectClass *nios2_cpu_class_by_name(const char = *cpu_model) static void nios2_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); + Nios2CPU *cpu =3D NIOS2_CPU(cs); Nios2CPUClass *ncc =3D NIOS2_CPU_GET_CLASS(dev); Error *local_err =3D NULL; =20 @@ -175,6 +176,9 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error= **errp) qemu_init_vcpu(cs); cpu_reset(cs); =20 + /* We have reserved storage for cpuid; might as well use it. */ + cpu->env.ctrl[CR_CPUID] =3D cs->cpu_index; + ncc->parent_realize(dev, errp); } =20 --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646914352388320.94559107025964; Thu, 10 Mar 2022 04:12:32 -0800 (PST) Received: from localhost ([::1]:42636 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHeh-00067C-11 for importer@patchew.org; Thu, 10 Mar 2022 07:12:31 -0500 Received: from eggs.gnu.org ([209.51.188.92]:50980) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGxe-00065D-6Z for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:28:02 -0500 Received: from [2607:f8b0:4864:20::52f] (port=42544 helo=mail-pg1-x52f.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGxc-00080R-HR for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:28:01 -0500 Received: by mail-pg1-x52f.google.com with SMTP id o8so4480933pgf.9 for ; Thu, 10 Mar 2022 03:28:00 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.27.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:27:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/Bkn+M8H5Sg7KsSEJjzM7NcRnu8uA0epSOYEx1aHzNA=; b=XmJyrFeH3FCnsweb9OB80hyfGlrS4hcMEAeHrT7uRfkYCpYS/hwQr16W7mnPOPtW4q tcAU+Gsek5hKjxBDXp2XoRlXX5BbiRiaZxfF94ESM+9zV+Oyzatk5HOOwTYkiNk181wZ s4guo0dUAXXjzNR0mspMRB9R1+36pTVG3mVsRbM8MUi76d3CNbKCheRYgbANttvdXJ6e CerWfr9TmJ1J/VYy3xD9vuiHLptz7LgY+H9F5ycwDyP6UadsxsMWwyJasr6V1/a81RJg YCcQQWgmDycQHMEY3i7C+QNtQwe/7+QR/LVuX0BxtrzCOOytXptHU5K3J5vMaDRrxz9E HSjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/Bkn+M8H5Sg7KsSEJjzM7NcRnu8uA0epSOYEx1aHzNA=; b=6ZFyHYzzxV9NMq0H637iKLDVlmxIKRb1mwW0Zeehpi1q5ADJVbWrksZAwwREy3+7ij MKKW965UkDY7l+Rqdf0rE0jjIET6KBHWeqrmYBCveb9uAGiW8/gndEa9ZyCPQHXiIf9+ XvGy4S3G4zf6MVtHTySndXOS3J3L4nksv7aSmGok/PxFcIrZjGvhTd/J08EvqKnd5Hr0 bZbJFNMA7OVIlrWPD5srQDDq6pYcLx+zddcRrs9NWIqzOcnXCf+6KkvximhJSZOWH8Nf H0dCLOztSqJb2Pzm11eWo3POyfQNHRGHpFVLGoD3cmAvU+ZAv5sDj6E6CXi09WKHHFLj iFsg== X-Gm-Message-State: AOAM533xT7dMNcUoQxBmncssMQ0+40bnEHH19cSM1QScSK+y2pQ6ejJU LZ7JbRB3XNl/TNwjf5Yd31oZUTJZNoecUg== X-Google-Smtp-Source: ABdhPJx5aF8+UO+veZ8Rrqk9ZD1tFuiCCvsg9pNSVfpMupQs0+KvQdyljvZKH05zA9lUouAqHCunWA== X-Received: by 2002:a63:1665:0:b0:378:ba21:ddb9 with SMTP id 37-20020a631665000000b00378ba21ddb9mr3659626pgw.268.1646911679120; Thu, 10 Mar 2022 03:27:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 28/48] target/nios2: Implement CR_STATUS.RSIE Date: Thu, 10 Mar 2022 03:27:05 -0800 Message-Id: <20220310112725.570053-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::52f (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646914353231100001 Content-Type: text/plain; charset="utf-8" Without EIC, this bit is RES1. So set the bit at reset, and add it to the readonly fields of CR_STATUS. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/cpu.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index d491360973..64dc916ed2 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -56,9 +56,9 @@ static void nios2_cpu_reset(DeviceState *dev) memset(env->ctrl, 0, sizeof(env->ctrl)); #if defined(CONFIG_USER_ONLY) /* Start in user mode with interrupts enabled. */ - env->ctrl[CR_STATUS] =3D CR_STATUS_U | CR_STATUS_PIE; + env->ctrl[CR_STATUS] =3D CR_STATUS_RSIE | CR_STATUS_U | CR_STATUS_PIE; #else - env->ctrl[CR_STATUS] =3D 0; + env->ctrl[CR_STATUS] =3D CR_STATUS_RSIE; #endif =20 env->regs[R_ZERO] =3D 0; @@ -109,6 +109,7 @@ static void nios2_cpu_initfn(Object *obj) WR_REG(CR_BADADDR); =20 /* TODO: These control registers are not present with the EIC. */ + RO_FIELD(CR_STATUS, RSIE); WR_REG(CR_IENABLE); RO_REG(CR_IPENDING); =20 --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646915097627887.3598670378077; Thu, 10 Mar 2022 04:24:57 -0800 (PST) Received: from localhost ([::1]:38914 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHqi-0006Pu-Dv for importer@patchew.org; Thu, 10 Mar 2022 07:24:56 -0500 Received: from eggs.gnu.org ([209.51.188.92]:50998) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGxf-000689-7N for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:28:03 -0500 Received: from [2607:f8b0:4864:20::62b] (port=43855 helo=mail-pl1-x62b.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGxd-00080c-Mv for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:28:02 -0500 Received: by mail-pl1-x62b.google.com with SMTP id e2so4579794pls.10 for ; Thu, 10 Mar 2022 03:28:01 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.27.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:27:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=X9NHWUxVFbhUbKp9xmQLehwV/i5chUkMUmRvZ87Nmy4=; b=bz9XmRB8VQu6dOEwqenN5EROsQoUuMV9GjtKCMFTATg2HEfFfOG0HrYrVO133bBDu4 +JG/Xeg6SnDerwDp1ZUQa7RhmCHT5fV5Sbq+QlSQy6efBuVC1OFEo97FQ9Csnp4ya2hP g+RWC5uhYBoGVcJgGqXa0+BW/fA8/iM3UTWyfDX/BIq1N5AaoDpkm56oKCRoLzsDVfzB s+/2cEf6s9I6KQ6FEb4s8+iimH/DY8SUyqubVGQ/4mdL8YLk9buK5xgDuigCSZ4GuZRw 3ixjAFQZIkfWajTTudDKcUjAlgy0zjl3OCFKLFms0q0X3UCHmNPy0Y9b1smz1hLl3hlY Lx2Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=X9NHWUxVFbhUbKp9xmQLehwV/i5chUkMUmRvZ87Nmy4=; b=iLgnqI3EexicANQicFtdssV48bCpgSvWQNh4/EqEbAYhv9ubxqDI4J93zn440zuT3O wfhrRktgv2EYLccSa+0FFnFa/RRItdqTlLZNsLkQjmKrL3vG8+tgRcjuwf7TCjzQkFRp opyemJddyQEIRIdR8Lt/JW38G4qdmSaCCbL1TXB1tJWGESsnYKVgrTUOEHTR+y7x3mKE CIEb5jLZcGzFG2ffpu93OKe15oyZwsAIvvo5qxxqArFXUtC2R5zzVxs0V73SDwOh2jqE leq5n+tRPsSsQd4HLgNpIIWUV4q9xB0kK4shBbXwFUf+CwvDVKadW4BVeIS/HWAxvprD 8rXQ== X-Gm-Message-State: AOAM530WCsdcSNhlr5rh/pFFwJgmjDk0DOAVzyjVa3wgGGyDs30ydivB RhDsfNhDKOElgzKKe1YEqc4gXzDC3sHUZA== X-Google-Smtp-Source: ABdhPJyz8IlHDl4HQ/wDXund9y9lVObazAwe6fqkpFZaIW0IFbDIzpZraCxIwOYBjwQin/Og+a+s5Q== X-Received: by 2002:a17:903:40c3:b0:151:c8a2:1c46 with SMTP id t3-20020a17090340c300b00151c8a21c46mr4605705pld.141.1646911680374; Thu, 10 Mar 2022 03:28:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 29/48] target/nios2: Remove CPU_INTERRUPT_NMI Date: Thu, 10 Mar 2022 03:27:06 -0800 Message-Id: <20220310112725.570053-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62b (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646915099491100001 Content-Type: text/plain; charset="utf-8" This interrupt bit is never set, so testing it in nios2_cpu_has_work is pointless. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 2 -- target/nios2/cpu.c | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 410e76ccbb..161f8efe82 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -177,8 +177,6 @@ FIELD(CR_TLBMISC, EE, 24, 1) #define EXCP_MPUI 16 #define EXCP_MPUD 17 =20 -#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 - struct CPUArchState { uint32_t regs[NUM_GP_REGS]; uint32_t ctrl[NUM_CR_REGS]; diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 64dc916ed2..745a583f9d 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -36,7 +36,7 @@ static void nios2_cpu_set_pc(CPUState *cs, vaddr value) =20 static bool nios2_cpu_has_work(CPUState *cs) { - return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI= ); + return cs->interrupt_request & CPU_INTERRUPT_HARD; } =20 static void nios2_cpu_reset(DeviceState *dev) --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646914541841820.2338049779476; Thu, 10 Mar 2022 04:15:41 -0800 (PST) Received: from localhost ([::1]:49124 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHhk-00024l-PZ for importer@patchew.org; Thu, 10 Mar 2022 07:15:40 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51026) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGxg-0006BY-Ty for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:28:04 -0500 Received: from [2607:f8b0:4864:20::529] (port=35714 helo=mail-pg1-x529.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGxe-00080w-T8 for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:28:04 -0500 Received: by mail-pg1-x529.google.com with SMTP id e6so4501193pgn.2 for ; Thu, 10 Mar 2022 03:28:02 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.28.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:28:00 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PvVjJW4JNMk/C3CxxpvaZU1mv/KFzjzrkRcyiH8whDc=; b=tjkEhfJxD4TAgJh8t7FY6PDRv9n2hM0/UjnEDfWrUaX9HktSyYl07qdFmIr1JW1jPi mQNZpIcRlppC4vDQ7jr8i8gW2/LBo2cOsgqZ5lwZ3whiyFwoe1OL9jTgKyLctraTb+BR zhzG40TGgsWOuhBkq9dPiKzibehI4vmUf2Rld+aHg9d8GoP/sIEhCDVIsSrwpbfZnuuU MX898mTztam9Oz49zJyaQTaibz2+I9y6eUwfZIbthidYJvKEEpBnfMXsSINm+oi3j4pT vNJKXEwUmKZNxLBuNskTJh8wXgnNPeQ3AepRosR7ulfUQ2YXT0pK2PdRMUHCopuzo/lI RqNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PvVjJW4JNMk/C3CxxpvaZU1mv/KFzjzrkRcyiH8whDc=; b=qXkY3sEC3VKwBVVbmwwvDFHHzS3FK/GBSLCWQM8JhglgO4cf0ubTXtL75Lij0kYTy9 xD4wWHpFBdv7GjrI6Pbm7vYS2ClxIXpcb8wEwsYLllIei4l2k7OtdIH7Kh2yvRK5g8Gv 1gOFjODiqj56RciDr470P+c2T9buim00nt/vyj+TbQEGxRycHiEXdGmSIVkamYIAspql x7oWBcZDl+foP+8udk5uJS3rOPgEBH9W87+VkTqCeRdbkrdrQDgNzfQxru9BY9l3JCzn y3NYLbxucDu283NoP9WMOxqHU7kA+90cIROXrmFfPXboojZQX6ap+zkK10NmVePrMiZm AaQA== X-Gm-Message-State: AOAM533mse0IVHHAM/WeIgGarMQfjKMfUxHB1TKxeXdrbCck4CM3BjoX P//aQ3uZ0KaCOkF4CwuXvfAC4pciVjSMEQ== X-Google-Smtp-Source: ABdhPJwFcFH3OOE9eB6fzax9PAD211erhXXRYVWe12jT5g+NVRBlwqv95umYSw3z6FRdVA1adxQIew== X-Received: by 2002:a63:1321:0:b0:376:333b:3ed with SMTP id i33-20020a631321000000b00376333b03edmr3577341pgl.283.1646911681397; Thu, 10 Mar 2022 03:28:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 30/48] target/nios2: Support division error exception Date: Thu, 10 Mar 2022 03:27:07 -0800 Message-Id: <20220310112725.570053-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::529 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646914543853100003 Content-Type: text/plain; charset="utf-8" Division may (optionally) raise a division exception. Since the linux kernel has been prepared for this for some time, enable it by default. Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 2 ++ target/nios2/helper.h | 2 ++ linux-user/nios2/cpu_loop.c | 4 +++ target/nios2/cpu.c | 1 + target/nios2/helper.c | 4 +++ target/nios2/op_helper.c | 29 ++++++++++++++++++ target/nios2/translate.c | 60 +++++++++++++------------------------ 7 files changed, 62 insertions(+), 40 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 161f8efe82..95079c186c 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -207,7 +207,9 @@ struct ArchCPU { CPUNegativeOffsetState neg; CPUNios2State env; =20 + bool diverr_present; bool mmu_present; + uint32_t pid_num_bits; uint32_t tlb_num_ways; uint32_t tlb_num_entries; diff --git a/target/nios2/helper.h b/target/nios2/helper.h index 525b6b685b..6f5ec60b0d 100644 --- a/target/nios2/helper.h +++ b/target/nios2/helper.h @@ -19,6 +19,8 @@ */ =20 DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) +DEF_HELPER_FLAGS_3(divs, TCG_CALL_NO_WG, s32, env, s32, s32) +DEF_HELPER_FLAGS_3(divu, TCG_CALL_NO_WG, i32, env, i32, i32) =20 #if !defined(CONFIG_USER_ONLY) DEF_HELPER_3(eret, noreturn, env, i32, i32) diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index fa234cb2af..ea364b7d1f 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -39,6 +39,10 @@ void cpu_loop(CPUNios2State *env) /* just indicate that signals should be handled asap */ break; =20 + case EXCP_DIV: + force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->pc); + break; + case EXCP_TRAP: switch (env->error_code) { case 0: diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 745a583f9d..b8410d8447 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -262,6 +262,7 @@ static int nios2_cpu_gdb_write_register(CPUState *cs, u= int8_t *mem_buf, int n) } =20 static Property nios2_properties[] =3D { + DEFINE_PROP_BOOL("diverr_present", Nios2CPU, diverr_present, true), DEFINE_PROP_BOOL("mmu_present", Nios2CPU, mmu_present, true), /* ALTR,pid-num-bits */ DEFINE_PROP_UINT32("mmu_pid_num_bits", Nios2CPU, pid_num_bits, 8), diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 8b69918ba3..460032adc0 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -139,6 +139,9 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_UNALIGND: name =3D "Misaligned (destination)"; break; + case EXCP_DIV: + name =3D "DIV error"; + break; case EXCP_TRAP: name =3D "TRAP insn"; break; @@ -210,6 +213,7 @@ void nios2_cpu_do_interrupt(CPUState *cs) =20 case EXCP_SUPERI: case EXCP_ILLEGAL: + case EXCP_DIV: case EXCP_TRAP: do_exception(cpu, cpu->exception_addr, 0, false); break; diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index c56fc15283..c93b66c9aa 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -31,6 +31,35 @@ void helper_raise_exception(CPUNios2State *env, uint32_t= index) cpu_loop_exit(cs); } =20 +static void maybe_raise_div(CPUNios2State *env, uintptr_t ra) +{ + Nios2CPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); + + if (cpu->diverr_present) { + cs->exception_index =3D EXCP_DIV; + cpu_loop_exit_restore(cs, ra); + } +} + +int32_t helper_divs(CPUNios2State *env, int32_t num, int32_t den) +{ + if (unlikely(den =3D=3D 0) || unlikely(den =3D=3D -1 && num =3D=3D INT= 32_MIN)) { + maybe_raise_div(env, GETPC()); + return num; /* undefined */ + } + return num / den; +} + +uint32_t helper_divu(CPUNios2State *env, uint32_t num, uint32_t den) +{ + if (unlikely(den =3D=3D 0)) { + maybe_raise_div(env, GETPC()); + return num; /* undefined */ + } + return num / den; +} + #ifndef CONFIG_USER_ONLY void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc) { diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 21dc6947cf..c8fb05a9cb 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -654,59 +654,39 @@ gen_r_shift_s(ror, rotr_tl) static void divs(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, (code)); + TCGv dest; =20 - /* Stores into R_ZERO are ignored */ - if (unlikely(instr.c =3D=3D R_ZERO)) { - return; + if (instr.c =3D=3D R_ZERO) { + dest =3D tcg_temp_new(); + } else { + dest =3D cpu_R[instr.c]; } =20 - TCGv t0 =3D tcg_temp_new(); - TCGv t1 =3D tcg_temp_new(); - TCGv t2 =3D tcg_temp_new(); - TCGv t3 =3D tcg_temp_new(); + gen_helper_divs(dest, cpu_env, + load_gpr(dc, instr.a), load_gpr(dc, instr.b)); =20 - tcg_gen_ext32s_tl(t0, load_gpr(dc, instr.a)); - tcg_gen_ext32s_tl(t1, load_gpr(dc, instr.b)); - tcg_gen_setcondi_tl(TCG_COND_EQ, t2, t0, INT_MIN); - tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, -1); - tcg_gen_and_tl(t2, t2, t3); - tcg_gen_setcondi_tl(TCG_COND_EQ, t3, t1, 0); - tcg_gen_or_tl(t2, t2, t3); - tcg_gen_movi_tl(t3, 0); - tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); - tcg_gen_div_tl(cpu_R[instr.c], t0, t1); - tcg_gen_ext32s_tl(cpu_R[instr.c], cpu_R[instr.c]); - - tcg_temp_free(t3); - tcg_temp_free(t2); - tcg_temp_free(t1); - tcg_temp_free(t0); + if (instr.c =3D=3D R_ZERO) { + tcg_temp_free(dest); + } } =20 static void divu(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, (code)); + TCGv dest; =20 - /* Stores into R_ZERO are ignored */ - if (unlikely(instr.c =3D=3D R_ZERO)) { - return; + if (instr.c =3D=3D R_ZERO) { + dest =3D tcg_temp_new(); + } else { + dest =3D cpu_R[instr.c]; } =20 - TCGv t0 =3D tcg_temp_new(); - TCGv t1 =3D tcg_temp_new(); - TCGv t2 =3D tcg_const_tl(0); - TCGv t3 =3D tcg_const_tl(1); + gen_helper_divu(dest, cpu_env, + load_gpr(dc, instr.a), load_gpr(dc, instr.b)); =20 - tcg_gen_ext32u_tl(t0, load_gpr(dc, instr.a)); - tcg_gen_ext32u_tl(t1, load_gpr(dc, instr.b)); - tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); - tcg_gen_divu_tl(cpu_R[instr.c], t0, t1); - tcg_gen_ext32s_tl(cpu_R[instr.c], cpu_R[instr.c]); - - tcg_temp_free(t3); - tcg_temp_free(t2); - tcg_temp_free(t1); - tcg_temp_free(t0); + if (instr.c =3D=3D R_ZERO) { + tcg_temp_free(dest); + } } =20 static void trap(DisasContext *dc, uint32_t code, uint32_t flags) --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646912471196290.5568027587948; Thu, 10 Mar 2022 03:41:11 -0800 (PST) Received: from localhost ([::1]:53322 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHAN-0004m7-42 for importer@patchew.org; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.28.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:28:02 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ryxSDJJrKjueVH0OEsU0bn5y9v3EMgUpEWxAYhSIfi0=; b=ZZviliMdA7iS9Uc5FMCSioqYhTyyTd8R7dbXt3Q3LXy7YzbF8GWjTw8hrFX1dTPDcG qPPY6evnzpt0tnZIQ2ABrnmCERRGora9dtIvXCD+4RZtvGdfAH9VFTqCGIo9MyikxW4f ufarYiBKyYCCcgZM/sd0sOmMCnh7BUfucYrHsJHhvOppxRvSMEo4GBZs9XbVlMBrAbWR f9Zie1av6XRQ3Rzlun1UKKlfnZrzUde5aRXjHGt6IZ9JvqyJwV7hNtu09u1681ixpZtl 39Nlr/dlVoIefqlPaIcplMM160M1HSqzSk9i72HsejtqKeMxTvEKQerr6iVAHhVJgOGU 26CQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ryxSDJJrKjueVH0OEsU0bn5y9v3EMgUpEWxAYhSIfi0=; b=z41Tg099BVuii6URjjDRm7mdp6CtFQ2E5UpXo0lPTZ4MN1or0P09W10NFdPSNIYXa2 E2FvfTHBD9DLsUUDesaekq2/EOx3IlfIrpI54lqgqrHOM+tx7F02vGCL5HMO3eOn/bX8 l9AqyRb/kDkM0rUm2xtBwHyohAFeoVhfij49h6+jiDFibHzOx+k6Xq/oVlTfb00WV4zU 0BBn3LSQ14ccsjMb+RH0hM2nS6E87E+0ADnMKqgfTPhpCK8em5vlg1v5Q9967kXcQ5M8 OZyxivGvg0f78PJeepzYGvQPIYzZLn0jqQsJM7PY8VsLUGxkBXX2DwMHV5JGfbFaBwfd LPjA== X-Gm-Message-State: AOAM533VqfH/ahiEIoEoY38nnzL3QmuAXLj50WZJC64S9D4z1HaHKCQT u0YqVEyFPPzfN4hLSyCnEpGceQ0ggW27Pw== X-Google-Smtp-Source: ABdhPJwlq3SslQZBg6+i2f7cxAPlpVX4fD7xEe8Iu3ENrGo3A4NjnAMo/DDn2Wn7EazDp2tbnTxiaQ== X-Received: by 2002:a17:90a:6543:b0:1b9:1dce:a23d with SMTP id f3-20020a17090a654300b001b91dcea23dmr4416244pjs.243.1646911682793; Thu, 10 Mar 2022 03:28:02 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 31/48] target/nios2: Use tcg_constant_tl Date: Thu, 10 Mar 2022 03:27:08 -0800 Message-Id: <20220310112725.570053-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102b (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646912480756100001 Content-Type: text/plain; charset="utf-8" Replace current uses of tcg_const_tl, and remove the frees. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/translate.c | 30 ++++++------------------------ 1 file changed, 6 insertions(+), 24 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index c8fb05a9cb..4ad47bb966 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -99,7 +99,6 @@ =20 typedef struct DisasContext { DisasContextBase base; - TCGv_i32 zero; target_ulong pc; int mem_idx; const ControlRegState *cr_state; @@ -125,31 +124,20 @@ static uint8_t get_opxcode(uint32_t code) return instr.opx; } =20 -static TCGv load_zero(DisasContext *dc) +static TCGv load_gpr(DisasContext *dc, unsigned reg) { - if (!dc->zero) { - dc->zero =3D tcg_const_i32(0); - } - return dc->zero; -} - -static TCGv load_gpr(DisasContext *dc, uint8_t reg) -{ - if (likely(reg !=3D R_ZERO)) { - return cpu_R[reg]; - } else { - return load_zero(dc); + assert(reg < NUM_GP_REGS); + if (unlikely(reg =3D=3D R_ZERO)) { + return tcg_constant_tl(0); } + return cpu_R[reg]; } =20 static void t_gen_helper_raise_exception(DisasContext *dc, uint32_t index) { - TCGv_i32 tmp =3D tcg_const_i32(index); - tcg_gen_movi_tl(cpu_pc, dc->pc); - gen_helper_raise_exception(cpu_env, tmp); - tcg_temp_free_i32(tmp); + gen_helper_raise_exception(cpu_env, tcg_constant_i32(index)); dc->base.is_jmp =3D DISAS_NORETURN; } =20 @@ -876,14 +864,8 @@ static void nios2_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) return; } =20 - dc->zero =3D NULL; - instr =3D &i_type_instructions[op]; instr->handler(dc, code, instr->flags); - - if (dc->zero) { - tcg_temp_free(dc->zero); - } } =20 static void nios2_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164691366248661.11568624209713; Thu, 10 Mar 2022 04:01:02 -0800 (PST) Received: from localhost ([::1]:51100 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHTY-0008WT-7x for importer@patchew.org; Thu, 10 Mar 2022 07:01:00 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51076) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGxj-0006Et-6W for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:28:08 -0500 Received: from [2607:f8b0:4864:20::62f] (port=44793 helo=mail-pl1-x62f.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGxh-00081I-70 for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:28:06 -0500 Received: by mail-pl1-x62f.google.com with SMTP id q11so4571389pln.11 for ; Thu, 10 Mar 2022 03:28:04 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.28.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:28:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rjl4pB0UOR++7sXmU/aZUMTVos+sgfIbyM2Yn1YOAwo=; b=PdzvJM+aG+amviE2rU06oocexqlR5KZxMmh442vNxzmNq1J1YAaGgKfwLekAol9NtE yoSnSQKlLJQolHyCSWTWMQJp0dwa0BzHhNI0JRZ/Nq2K/1rsR+GCyu34jii2FYYT+f5Z zcsISBlgegNOlqNqSXVRDI4PaSogr3tsD5aqd7S94V5hFsKoaMECcj1HjyTRhP0hZhj5 yceBWV/fEQWqzlgL/PyxjJ+T+bZNtg07cbBvRyQ6izcTa7mWP8eqOjDPJUi7j/LJ/Vg1 Suz4QEZM3cCZOtMHH34CjpPUoKXF99S0vMWoHFeKTcDn7zeJ9eHnDiDY2jckAqKUGnr6 qRKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rjl4pB0UOR++7sXmU/aZUMTVos+sgfIbyM2Yn1YOAwo=; b=va5/YWunOMyudK+oqdkFQhH+d3wJJheQMk0bRxVvrJb/U29qLtgync6YMTb41IIXXX g4UzyrMyLzxCrx+zyJaA5UGV/L6eubGljNOx4z3+jlEEm4vVMiGhk/SADMG2RvlXt2eP 2DhAbK5Xwg07HFWjy8v4z2o+aDPOBffqeo/ypt1d2u+2O5fSzkrqKdBHi+FBFUpv4zwx aWftoxyCEpv8+ntSKAf8A7kVZT0av8NeGbxs01S3Zj7vxi7qpI8/8QdYlWkSeV/v5cbV EHeZZYeyK1AniU7Z1smNVYaC3Z2RXTSIx7sXOeK4Ab2hYm3krvh7k0Z8vN+J4Tg+dJzn MChQ== X-Gm-Message-State: AOAM531gqscREzUMVzV5zDctKcoXxS5RkYgnVUw9RAE73yO2CWS3ZVa4 gPkvI4yCpDUby6UC/bWzOgmWAuKWTJqpMA== X-Google-Smtp-Source: ABdhPJwzRsoF2G/1lSriOATzPfZmtF6WQb536rm1O89eHDsGZtucHfvJU3W8YoOE/jAOrVGCqZqkKw== X-Received: by 2002:a17:902:ab4c:b0:151:eb86:dcb5 with SMTP id ij12-20020a170902ab4c00b00151eb86dcb5mr4472762plb.126.1646911683796; Thu, 10 Mar 2022 03:28:03 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 32/48] target/nios2: Introduce dest_gpr Date: Thu, 10 Mar 2022 03:27:09 -0800 Message-Id: <20220310112725.570053-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62f (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646913664646100001 Content-Type: text/plain; charset="utf-8" Constrain all references to cpu_R[] to load_gpr and dest_gpr. This will be required for supporting shadow register sets. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/translate.c | 153 ++++++++++++++------------------------- 1 file changed, 55 insertions(+), 98 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 4ad47bb966..d5f2e98de9 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -101,6 +101,7 @@ typedef struct DisasContext { DisasContextBase base; target_ulong pc; int mem_idx; + TCGv sink; const ControlRegState *cr_state; } DisasContext; =20 @@ -133,6 +134,18 @@ static TCGv load_gpr(DisasContext *dc, unsigned reg) return cpu_R[reg]; } =20 +static TCGv dest_gpr(DisasContext *dc, unsigned reg) +{ + assert(reg < NUM_GP_REGS); + if (unlikely(reg =3D=3D R_ZERO)) { + if (dc->sink =3D=3D NULL) { + dc->sink =3D tcg_temp_new(); + } + return dc->sink; + } + return cpu_R[reg]; +} + static void t_gen_helper_raise_exception(DisasContext *dc, uint32_t index) { @@ -191,7 +204,7 @@ static void jmpi(DisasContext *dc, uint32_t code, uint3= 2_t flags) =20 static void call(DisasContext *dc, uint32_t code, uint32_t flags) { - tcg_gen_movi_tl(cpu_R[R_RA], dc->base.pc_next); + tcg_gen_movi_tl(dest_gpr(dc, R_RA), dc->base.pc_next); jmpi(dc, code, flags); } =20 @@ -204,27 +217,10 @@ static void gen_ldx(DisasContext *dc, uint32_t code, = uint32_t flags) I_TYPE(instr, code); =20 TCGv addr =3D tcg_temp_new(); - TCGv data; - - /* - * WARNING: Loads into R_ZERO are ignored, but we must generate the - * memory access itself to emulate the CPU precisely. Load - * from a protected page to R_ZERO will cause SIGSEGV on - * the Nios2 CPU. - */ - if (likely(instr.b !=3D R_ZERO)) { - data =3D cpu_R[instr.b]; - } else { - data =3D tcg_temp_new(); - } + TCGv data =3D dest_gpr(dc, instr.b); =20 tcg_gen_addi_tl(addr, load_gpr(dc, instr.a), instr.imm16.s); tcg_gen_qemu_ld_tl(data, addr, dc->mem_idx, flags); - - if (unlikely(instr.b =3D=3D R_ZERO)) { - tcg_temp_free(data); - } - tcg_temp_free(addr); } =20 @@ -254,7 +250,7 @@ static void gen_bxx(DisasContext *dc, uint32_t code, ui= nt32_t flags) I_TYPE(instr, code); =20 TCGLabel *l1 =3D gen_new_label(); - tcg_gen_brcond_tl(flags, cpu_R[instr.a], cpu_R[instr.b], l1); + tcg_gen_brcond_tl(flags, load_gpr(dc, instr.a), load_gpr(dc, instr.b),= l1); gen_goto_tb(dc, 0, dc->base.pc_next); gen_set_label(l1); gen_goto_tb(dc, 1, dc->base.pc_next + (instr.imm16.s & -4)); @@ -262,11 +258,12 @@ static void gen_bxx(DisasContext *dc, uint32_t code, = uint32_t flags) } =20 /* Comparison instructions */ -#define gen_i_cmpxx(fname, op3) = \ -static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) = \ -{ = \ - I_TYPE(instr, (code)); = \ - tcg_gen_setcondi_tl(flags, cpu_R[instr.b], cpu_R[instr.a], (op3)); = \ +#define gen_i_cmpxx(fname, op3) \ +static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \ +{ \ + I_TYPE(instr, (code)); \ + tcg_gen_setcondi_tl(flags, dest_gpr(dc, instr.b), \ + load_gpr(dc, instr.a), (op3)); \ } =20 gen_i_cmpxx(gen_cmpxxsi, instr.imm16.s) @@ -277,13 +274,7 @@ gen_i_cmpxx(gen_cmpxxui, instr.imm16.u) static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) = \ { = \ I_TYPE(instr, (code)); = \ - if (unlikely(instr.b =3D=3D R_ZERO)) { /* Store to R_ZERO is ignored *= / \ - return; = \ - } else if (instr.a =3D=3D R_ZERO) { /* MOVxI optimizations */ = \ - tcg_gen_movi_tl(cpu_R[instr.b], (resimm) ? (op3) : 0); = \ - } else { = \ - tcg_gen_##insn##_tl(cpu_R[instr.b], cpu_R[instr.a], (op3)); = \ - } = \ + tcg_gen_##insn##_tl(dest_gpr(dc, instr.b), load_gpr(dc, instr.a), (op3= )); \ } =20 gen_i_math_logic(addi, addi, 1, instr.imm16.s) @@ -386,7 +377,7 @@ static void eret(DisasContext *dc, uint32_t code, uint3= 2_t flags) #else TCGv tmp =3D tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_ESTATUS])); - gen_helper_eret(cpu_env, tmp, cpu_R[R_EA]); + gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_EA)); tcg_temp_free(tmp); =20 dc->base.is_jmp =3D DISAS_NORETURN; @@ -396,8 +387,7 @@ static void eret(DisasContext *dc, uint32_t code, uint3= 2_t flags) /* PC <- ra */ static void ret(DisasContext *dc, uint32_t code, uint32_t flags) { - tcg_gen_mov_tl(cpu_pc, cpu_R[R_RA]); - + tcg_gen_mov_tl(cpu_pc, load_gpr(dc, R_RA)); dc->base.is_jmp =3D DISAS_JUMP; } =20 @@ -416,7 +406,7 @@ static void bret(DisasContext *dc, uint32_t code, uint3= 2_t flags) #else TCGv tmp =3D tcg_temp_new(); tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_BSTATUS])); - gen_helper_eret(cpu_env, tmp, cpu_R[R_BA]); + gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_BA)); tcg_temp_free(tmp); =20 dc->base.is_jmp =3D DISAS_NORETURN; @@ -429,7 +419,6 @@ static void jmp(DisasContext *dc, uint32_t code, uint32= _t flags) R_TYPE(instr, code); =20 tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a)); - dc->base.is_jmp =3D DISAS_JUMP; } =20 @@ -438,9 +427,7 @@ static void nextpc(DisasContext *dc, uint32_t code, uin= t32_t flags) { R_TYPE(instr, code); =20 - if (likely(instr.c !=3D R_ZERO)) { - tcg_gen_movi_tl(cpu_R[instr.c], dc->base.pc_next); - } + tcg_gen_movi_tl(dest_gpr(dc, instr.c), dc->base.pc_next); } =20 /* @@ -452,7 +439,7 @@ static void callr(DisasContext *dc, uint32_t code, uint= 32_t flags) R_TYPE(instr, code); =20 tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a)); - tcg_gen_movi_tl(cpu_R[R_RA], dc->base.pc_next); + tcg_gen_movi_tl(dest_gpr(dc, R_RA), dc->base.pc_next); =20 dc->base.is_jmp =3D DISAS_JUMP; } @@ -468,15 +455,11 @@ static void rdctl(DisasContext *dc, uint32_t code, ui= nt32_t flags) g_assert_not_reached(); #else R_TYPE(instr, code); - TCGv t1, t2; - - if (unlikely(instr.c =3D=3D R_ZERO)) { - return; - } + TCGv t1, t2, dest =3D dest_gpr(dc, instr.c); =20 /* Reserved registers read as zero. */ if (nios2_cr_reserved(&dc->cr_state[instr.imm5])) { - tcg_gen_movi_tl(cpu_R[instr.c], 0); + tcg_gen_movi_tl(dest, 0); return; } =20 @@ -494,12 +477,12 @@ static void rdctl(DisasContext *dc, uint32_t code, ui= nt32_t flags) t2 =3D tcg_temp_new(); tcg_gen_ld_tl(t1, cpu_env, offsetof(CPUNios2State, ctrl[CR_IPENDIN= G])); tcg_gen_ld_tl(t2, cpu_env, offsetof(CPUNios2State, ctrl[CR_IENABLE= ])); - tcg_gen_and_tl(cpu_R[instr.c], t1, t2); + tcg_gen_and_tl(dest, t1, t2); tcg_temp_free(t1); tcg_temp_free(t2); break; default: - tcg_gen_ld_tl(cpu_R[instr.c], cpu_env, + tcg_gen_ld_tl(dest, cpu_env, offsetof(CPUNios2State, ctrl[instr.imm5])); break; } @@ -575,10 +558,8 @@ static void wrctl(DisasContext *dc, uint32_t code, uin= t32_t flags) static void gen_cmpxx(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, code); - if (likely(instr.c !=3D R_ZERO)) { - tcg_gen_setcond_tl(flags, cpu_R[instr.c], cpu_R[instr.a], - cpu_R[instr.b]); - } + tcg_gen_setcond_tl(flags, dest_gpr(dc, instr.c), + load_gpr(dc, instr.a), load_gpr(dc, instr.b)); } =20 /* Math/logic instructions */ @@ -586,9 +567,7 @@ static void gen_cmpxx(DisasContext *dc, uint32_t code, = uint32_t flags) static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) = \ { = \ R_TYPE(instr, (code)); = \ - if (likely(instr.c !=3D R_ZERO)) { = \ - tcg_gen_##insn(cpu_R[instr.c], load_gpr((dc), instr.a), (op3)); = \ - } = \ + tcg_gen_##insn(dest_gpr(dc, instr.c), load_gpr(dc, instr.a), (op3)); = \ } =20 gen_r_math_logic(add, add_tl, load_gpr(dc, instr.b)) @@ -609,28 +588,24 @@ gen_r_math_logic(roli, rotli_tl, instr.imm5) static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \ { \ R_TYPE(instr, (code)); \ - if (likely(instr.c !=3D R_ZERO)) { \ - TCGv t0 =3D tcg_temp_new(); \ - tcg_gen_##insn(t0, cpu_R[instr.c], \ - load_gpr(dc, instr.a), load_gpr(dc, instr.b)); \ - tcg_temp_free(t0); \ - } \ + TCGv t0 =3D tcg_temp_new(); \ + tcg_gen_##insn(t0, dest_gpr(dc, instr.c), \ + load_gpr(dc, instr.a), load_gpr(dc, instr.b)); \ + tcg_temp_free(t0); \ } =20 gen_r_mul(mulxss, muls2_tl) gen_r_mul(mulxuu, mulu2_tl) gen_r_mul(mulxsu, mulsu2_tl) =20 -#define gen_r_shift_s(fname, insn) = \ -static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) = \ -{ = \ - R_TYPE(instr, (code)); = \ - if (likely(instr.c !=3D R_ZERO)) { = \ - TCGv t0 =3D tcg_temp_new(); = \ - tcg_gen_andi_tl(t0, load_gpr((dc), instr.b), 31); = \ - tcg_gen_##insn(cpu_R[instr.c], load_gpr((dc), instr.a), t0); = \ - tcg_temp_free(t0); = \ - } = \ +#define gen_r_shift_s(fname, insn) \ +static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \ +{ \ + R_TYPE(instr, (code)); \ + TCGv t0 =3D tcg_temp_new(); \ + tcg_gen_andi_tl(t0, load_gpr(dc, instr.b), 31); \ + tcg_gen_##insn(dest_gpr(dc, instr.c), load_gpr(dc, instr.a), t0); \ + tcg_temp_free(t0); \ } =20 gen_r_shift_s(sra, sar_tl) @@ -642,39 +617,15 @@ gen_r_shift_s(ror, rotr_tl) static void divs(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, (code)); - TCGv dest; - - if (instr.c =3D=3D R_ZERO) { - dest =3D tcg_temp_new(); - } else { - dest =3D cpu_R[instr.c]; - } - - gen_helper_divs(dest, cpu_env, + gen_helper_divs(dest_gpr(dc, instr.c), cpu_env, load_gpr(dc, instr.a), load_gpr(dc, instr.b)); - - if (instr.c =3D=3D R_ZERO) { - tcg_temp_free(dest); - } } =20 static void divu(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, (code)); - TCGv dest; - - if (instr.c =3D=3D R_ZERO) { - dest =3D tcg_temp_new(); - } else { - dest =3D cpu_R[instr.c]; - } - - gen_helper_divu(dest, cpu_env, + gen_helper_divu(dest_gpr(dc, instr.c), cpu_env, load_gpr(dc, instr.a), load_gpr(dc, instr.b)); - - if (instr.c =3D=3D R_ZERO) { - tcg_temp_free(dest); - } } =20 static void trap(DisasContext *dc, uint32_t code, uint32_t flags) @@ -864,8 +815,14 @@ static void nios2_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) return; } =20 + dc->sink =3D NULL; + instr =3D &i_type_instructions[op]; instr->handler(dc, code, instr->flags); + + if (dc->sink) { + tcg_temp_free(dc->sink); + } } =20 static void nios2_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646912621037705.4158307805737; Thu, 10 Mar 2022 03:43:41 -0800 (PST) Received: from localhost ([::1]:33700 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHCl-000270-Vf for importer@patchew.org; Thu, 10 Mar 2022 06:43:39 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51078) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGxj-0006Ev-HN for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:28:08 -0500 Received: from [2607:f8b0:4864:20::42f] (port=42634 helo=mail-pf1-x42f.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGxi-00081X-7p for qemu-devel@nongnu.org; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.28.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:28:04 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lGnYRwLa1Sdp2FVEXMpjEqak7lSPIuu/eJVT8HDcZLI=; b=t8ugzzGh13hhzZytrFxNNz1j5VkeLVl5fucfXPS6xKlXoQKx6LizIzxJXmG5yqmIPH +WGbtryS4gevTA8bfsJEVgE1TC6Y5Cjg284JNaiOdlNG5z9ZwSR4DnKCYGniuFGePXuG JA6iZnbUOS7RrEb67tG5HaumwwP62AvZi6o2jCXqc9peNobDCZ5bnxiU1YZhEDFCGhKJ o3PcVfyvH9GD+OySY3GKKSkKffwuKiGw8qFVsLAmEhAug30fhtMPfnn5Iox5xnKpghbd 1TPeWqxIYYykJ7cD7vmeJcdYDy9+CI5QlnFMcNIVUC0hebNy1adpBz+V2g6joyz7j1eV LqBA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lGnYRwLa1Sdp2FVEXMpjEqak7lSPIuu/eJVT8HDcZLI=; b=ZCH329eCaebLFAyIJwhemeu3o1FI7xsQ1hHbxUfgq9YbAtNwNESlsequ45r08kgj7+ /TpYRL3fyu3XIY9LTxA0SQPUIZ91z/O1L94y/qNrHGBG6XJsrPQuQ8u7QfAxdk0C+3id Cbfj0giRTSdRcZ/6MfJFYT3klJ/uOWud1QL+GnRhqhgRq5nmETIS3E5MLgxaSE32BNgD Ma0DvefBq64gK6Qg6qk7swIrgfbsvMWtPabluCMwqGNE5UElvxIC34po9CnMP8rUzndb Ykip+89CZxBA1xSkRODX+IQ4GtcZuW7z0caLvNAyqnNbyPBu7NBM4GB6zcq8msEyJFUO zDJA== X-Gm-Message-State: AOAM533FH4WIGWeQl6FaIEHA8kHTUKBbfEbZGMY+CkxLKRkivDzr0fLu KUJCPgLmu1EUF2x2AoyNSgiX8fpZ1sq73g== X-Google-Smtp-Source: ABdhPJzfkBNJpDfKciZFLszPP/Zi5YayxrRyG8BdqCZsg6qyVKV+JRZEvlw2K55Y4uyhDbpH19FpoA== X-Received: by 2002:a05:6a00:acf:b0:4e1:9222:1ef3 with SMTP id c15-20020a056a000acf00b004e192221ef3mr4355358pfl.18.1646911685015; Thu, 10 Mar 2022 03:28:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 33/48] target/nios2: Drop CR_STATUS_EH from tb->flags Date: Thu, 10 Mar 2022 03:27:10 -0800 Message-Id: <20220310112725.570053-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42f (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646912623262100001 Content-Type: text/plain; charset="utf-8" There's nothing about EH that affects translation, so there's no need to include it in tb->flags. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 95079c186c..d5255e9e76 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -276,7 +276,7 @@ static inline void cpu_get_tb_cpu_state(CPUNios2State *= env, target_ulong *pc, { *pc =3D env->pc; *cs_base =3D 0; - *flags =3D env->ctrl[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U); + *flags =3D env->ctrl[CR_STATUS] & CR_STATUS_U; } =20 #endif /* NIOS2_CPU_H */ --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646913833968967.0221522217117; Thu, 10 Mar 2022 04:03:53 -0800 (PST) Received: from localhost ([::1]:57530 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHWL-0004XS-EQ for importer@patchew.org; Thu, 10 Mar 2022 07:03:53 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51108) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGxl-0006Gy-B6 for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:28:10 -0500 Received: from [2607:f8b0:4864:20::435] (port=36601 helo=mail-pf1-x435.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGxj-00081p-Rx for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:28:09 -0500 Received: by mail-pf1-x435.google.com with SMTP id z16so4860814pfh.3 for ; Thu, 10 Mar 2022 03:28:07 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.28.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:28:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Q//3kePGgY2lzpncF0BtSDXigvkTy7INMFgUKN7BKXk=; b=TJ6zZ/qsnRY/oDfupoqzP27kParNBnJekeH6TmOs+t2BijfY5Yy/U+cN8QjXbTIOSN tzo0lI1nO8GiwpdYGJIRIbEQ1h/LqRTFXui4QVjgD6hAXfxpzqX1BA1GWjomYmFgf9UN g9KK6KnNpbGBu6hTzhz+uzfMU28CqrFnMmKcMngVWYQIzabZAt3w2/nx3PIrJ7vM054Z vfBew+O4c63rDg/9YS7ScLfdqL54mgD0VBQBvwFl5V6gUDdij1mMlPNVApzsDLpIayeO tsQat+gcn2LKJ7ijgvLk1BokcIHVA92NAmoEhlfvSGccyXSc31ExDthNUQMnGG4+LvV5 lLDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Q//3kePGgY2lzpncF0BtSDXigvkTy7INMFgUKN7BKXk=; b=KA3pS8/oWTYQdbuQ2GpOpnkc7NJywV7zPeZxgOjBehUUIIOBLf9JreqkveKZ1Rrrja g01CpL9Yq+Z9Zux+KZTENczpWTnykK+e2mon6hd+cJXn3V23Fb2XOGq7fOnprqMS8dCN gwQ3oGgTUAQMezUBo5/5UvVdJlW5HfekbGf8cV/0eLPIdYJSpsyIRbTHtuj9+dMGHLzF AmjBUdqC4U1q1Q7GjP8skvftBo9kGXCcurbquGJCUtxXU+rvmpfwD6GgSFWhMjRJybUy T8X5AYgp5TpC2sxCXen5Pn9EC7RcDi8w604yTVkrXW98zedYmsPaQ0utoQrFGPAItXbJ HdPw== X-Gm-Message-State: AOAM531QQEhPOBeyZo8J257qLPkVOnlV+UumiZaWa1eJ8HTFeCCMe7BJ LyS3wzxJfukSDIcNHhUEYZx2qkjrnKUSEw== X-Google-Smtp-Source: ABdhPJwmrRFQNO+TZRhszHG+k+9EKwqhUIAbI6dSW65ZV/176tj+CiIc/4njQptmQEU1nT9evK8rBw== X-Received: by 2002:a05:6a00:2166:b0:4f6:67fe:a336 with SMTP id r6-20020a056a00216600b004f667fea336mr4533678pff.17.1646911686072; Thu, 10 Mar 2022 03:28:06 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 34/48] target/nios2: Enable unaligned traps for system mode Date: Thu, 10 Mar 2022 03:27:11 -0800 Message-Id: <20220310112725.570053-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::435 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::435; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x435.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646913836884100001 Content-Type: text/plain; charset="utf-8" Unaligned traps are optional, but required with an mmu. Turn them on always, because the fallback behaviour is not documented (though presumably it discards low bits). Enable alignment checks in the config file. Unwind the guest pc properly from do_unaligned_access. Signed-off-by: Richard Henderson --- configs/targets/nios2-softmmu.mak | 1 + target/nios2/helper.c | 4 ++-- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/configs/targets/nios2-softmmu.mak b/configs/targets/nios2-soft= mmu.mak index 9a372f0717..1e93b54cd1 100644 --- a/configs/targets/nios2-softmmu.mak +++ b/configs/targets/nios2-softmmu.mak @@ -1 +1,2 @@ TARGET_ARCH=3Dnios2 +TARGET_ALIGNED_ONLY=3Dy diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 460032adc0..bf40cff779 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -264,8 +264,8 @@ void nios2_cpu_do_unaligned_access(CPUState *cs, vaddr = addr, CPUNios2State *env =3D &cpu->env; =20 env->ctrl[CR_BADADDR] =3D addr; - env->ctrl[CR_EXCEPTION] =3D FIELD_DP32(0, CR_EXCEPTION, CAUSE, EXCP_UN= ALIGN); - helper_raise_exception(env, EXCP_UNALIGN); + cs->exception_index =3D EXCP_UNALIGN; + cpu_loop_exit_restore(cs, retaddr); } =20 bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, int size, --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646914927700533.801725422499; Thu, 10 Mar 2022 04:22:07 -0800 (PST) Received: from localhost ([::1]:60638 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHny-0001j4-Ht for importer@patchew.org; Thu, 10 Mar 2022 07:22:06 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51116) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGxm-0006HQ-AU for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:28:10 -0500 Received: from [2607:f8b0:4864:20::531] (port=41818 helo=mail-pg1-x531.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGxk-00081x-CC for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:28:09 -0500 Received: by mail-pg1-x531.google.com with SMTP id o26so4484750pgb.8 for ; Thu, 10 Mar 2022 03:28:07 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.28.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:28:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=a0Y1+UOzMYE465JAg/1XZp8FHRvlzNh9RDhixInPs2c=; b=UxensK2TuV6aJUw6wTkkqlJOX4X1PpGUrf6kigLv44qOCxM2YeMsKdl4RG6dcmsFle 7lpRu9muFb1Qdh4bxAmsWJD45LlgSn1lRCckHuYXfbrBBlbNDfFLHwVGfcDADMuXn4vJ j1RDFZMXSk+9162990JnbnR6+FTqCh9Hv/YRmqYq3O0jZHJJULbqaoiOMHZJ53nXat5k F6UF5LrkOcxAK1FZBFpx5dS27XMBl/rBxgFTkZl3ZREhf5ocI5ved3veinggAn9UEnQA b0OyAHskLQsD2r7MgCxoNASr9WNK6nBty3344Xo4q/24RVryzdpvBBBR0Y43cVJhrsZp eRXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=a0Y1+UOzMYE465JAg/1XZp8FHRvlzNh9RDhixInPs2c=; b=eW38fODZRL+gX1GU7wFTcCultpWuS/tmsz2RMEjdphjvBPF1Ki4Yv+pPD1o39y5qgQ ZuO2KaAzwEcaMwSWrXu/76WPSdKuVuvfTQ291cjywAc3qlftfEhJyQ7crFo+8n1pXZRr 2dwSRHNE4xmytdDVFZt05wqftrKfoCQHIYKxPpxfdNN3dzl8zOeJiQcvHE2bR9GHl2o4 nsng3FoU5W2R+OEure3QUUmCe+Vn/k8RCvNzDARswsE9s5ebyGMy+ttvvhkJC094gz8K gUepMZqicYlGG+V53QgCU8ULv3EGiUsz4TDGP1UicgRIn6c29/xGoV56xo2D5N8CLAGn FYcA== X-Gm-Message-State: AOAM532c9FZvXC7Iv8M4j8B1WSNoxwUPXztjeE2XE343hh4eond47xEA 2wJdYIVHNXYyDRS4yWT5qMokh/2rRlZ0og== X-Google-Smtp-Source: ABdhPJzrtPa2H1UOM26kM5rPAQNvZruo2mY2Xyt7ERzocan5ovgocfyegRHmckeRxrt364otj52xRQ== X-Received: by 2002:a65:4845:0:b0:325:c147:146d with SMTP id i5-20020a654845000000b00325c147146dmr3769599pgs.140.1646911687159; Thu, 10 Mar 2022 03:28:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 35/48] target/nios2: Create gen_jumpr Date: Thu, 10 Mar 2022 03:27:12 -0800 Message-Id: <20220310112725.570053-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::531 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646914929912100001 Content-Type: text/plain; charset="utf-8" Split out a function to perform an indirect branch. Signed-off-by: Richard Henderson --- target/nios2/translate.c | 27 +++++++++++++-------------- 1 file changed, 13 insertions(+), 14 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index d5f2e98de9..f61ba92052 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -36,7 +36,6 @@ #include "semihosting/semihost.h" =20 /* is_jmp field values */ -#define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ #define DISAS_UPDATE DISAS_TARGET_1 /* cpu state was modified dynamically= */ =20 #define INSTRUCTION_FLG(func, flags) { (func), (flags) } @@ -168,6 +167,16 @@ static void gen_goto_tb(DisasContext *dc, int n, uint3= 2_t dest) } } =20 +static void gen_jumpr(DisasContext *dc, int regno, bool is_call) +{ + tcg_gen_mov_tl(cpu_pc, load_gpr(dc, regno)); + if (is_call) { + tcg_gen_movi_tl(dest_gpr(dc, R_RA), dc->base.pc_next); + } + tcg_gen_exit_tb(NULL, 0); + dc->base.is_jmp =3D DISAS_NORETURN; +} + static void gen_excp(DisasContext *dc, uint32_t code, uint32_t flags) { t_gen_helper_raise_exception(dc, flags); @@ -387,8 +396,7 @@ static void eret(DisasContext *dc, uint32_t code, uint3= 2_t flags) /* PC <- ra */ static void ret(DisasContext *dc, uint32_t code, uint32_t flags) { - tcg_gen_mov_tl(cpu_pc, load_gpr(dc, R_RA)); - dc->base.is_jmp =3D DISAS_JUMP; + gen_jumpr(dc, R_RA, false); } =20 /* @@ -418,8 +426,7 @@ static void jmp(DisasContext *dc, uint32_t code, uint32= _t flags) { R_TYPE(instr, code); =20 - tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a)); - dc->base.is_jmp =3D DISAS_JUMP; + gen_jumpr(dc, instr.a, false); } =20 /* rC <- PC + 4 */ @@ -438,10 +445,7 @@ static void callr(DisasContext *dc, uint32_t code, uin= t32_t flags) { R_TYPE(instr, code); =20 - tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a)); - tcg_gen_movi_tl(dest_gpr(dc, R_RA), dc->base.pc_next); - - dc->base.is_jmp =3D DISAS_JUMP; + gen_jumpr(dc, instr.a, true); } =20 /* rC <- ctlN */ @@ -838,11 +842,6 @@ static void nios2_tr_tb_stop(DisasContextBase *dcbase,= CPUState *cs) tcg_gen_exit_tb(NULL, 0); break; =20 - case DISAS_JUMP: - /* The jump will already have updated the PC register */ - tcg_gen_exit_tb(NULL, 0); - break; - case DISAS_NORETURN: /* nothing more to generate */ break; --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164691524682482.09815459076515; Thu, 10 Mar 2022 04:27:26 -0800 (PST) Received: from localhost ([::1]:44362 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHt7-0001y3-QB for importer@patchew.org; Thu, 10 Mar 2022 07:27:25 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51154) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGxo-0006K4-Ih for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:28:14 -0500 Received: from [2607:f8b0:4864:20::532] (port=41819 helo=mail-pg1-x532.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGxl-00082B-CO for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:28:11 -0500 Received: by mail-pg1-x532.google.com with SMTP id o26so4484785pgb.8 for ; Thu, 10 Mar 2022 03:28:09 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.28.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:28:07 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PHMXz9q73HVjYaAorTgnEhJkrDs42cYUdRyVosZEm/k=; b=UO36UmZntZvgjIPv5B0+rQ27YUeBJ/Iwa7/nvsUwT9IeiWn6KzBiy45kZl5URtgXjT JXKE60W8g3Ug8Tp0ec9wcUFp/s1cfrLQk6cm9pA0DRTFIkHGi28UWMI6sttspZR55nUw J4PeriBNbi5prGQaBGec8oSyAd3SD7Np5lWhwHFL9lgxEGs43IVnLND85mPjfVoMPcrH Khsl/s05OF+X+ldvqz9PkCsCkSpWaFb236PQECBc/72vS/e9dIQkMRb1cO1sVgGMUXal zTp9ltfQuJyIxt8RFnMjFQEPsyoYyVOG9mMIzZ1UTs0Ea8s+RRt17io5KjFjCZdW/70Z GDcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PHMXz9q73HVjYaAorTgnEhJkrDs42cYUdRyVosZEm/k=; b=Omf1Rxb1Sv3npqywiKF8q6Q/ZrdQr9/jWDXvoKk97fwXLbOVhLEH94Ghhs3Z2KCmdV ONeS+7fHIj45xjdZnGd1IlhwspBt4MC9ssJFVvdEMlO2AKdStASm42HR7DMo2GLUt3xT 7JNRqqrF1uzlLJT04cWgUKDqawYj/qTFF99XfAqlxPYgXdPZHLhRy+oux+SqIfra8q9O EArXkD9+khCHfc4QudlPPHv8lL/51zYAM8kKgaz4m2HxgvNfBu98IFctMP3uz1AwjMWl bh9nx5/QSRHlLBSZQVIYi/hC5ZNjvqVfnKe889uaaKkrAvKgE9upxTJEdoulKhRT1Uiv VKpA== X-Gm-Message-State: AOAM531Y/eWppf8BqAkwQ1oA1aIQVs+nu56Fb+wrqOsru8R4jSa4St1T JzMtZsjqp7Gk1xKSxSwOA2/Bhc9MR/jsCw== X-Google-Smtp-Source: ABdhPJzGwPtmJkx6BLf0S3I+9FEmNOEv0jzaLhZ7fCnm0yiFjQFUQUtp0vXDc9TcUTc3vVTaBwkATA== X-Received: by 2002:a05:6a00:a8f:b0:4e1:2619:11a2 with SMTP id b15-20020a056a000a8f00b004e1261911a2mr4483830pfl.53.1646911688184; Thu, 10 Mar 2022 03:28:08 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 36/48] target/nios2: Hoist set of is_jmp into gen_goto_tb Date: Thu, 10 Mar 2022 03:27:13 -0800 Message-Id: <20220310112725.570053-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::532 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646915248395100001 Content-Type: text/plain; charset="utf-8" Rather than force all callers to set this, do it within the subroutine. Signed-off-by: Richard Henderson --- target/nios2/translate.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index f61ba92052..51907586ab 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -165,6 +165,7 @@ static void gen_goto_tb(DisasContext *dc, int n, uint32= _t dest) tcg_gen_movi_tl(cpu_pc, dest); tcg_gen_exit_tb(NULL, 0); } + dc->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_jumpr(DisasContext *dc, int regno, bool is_call) @@ -208,7 +209,6 @@ static void jmpi(DisasContext *dc, uint32_t code, uint3= 2_t flags) { J_TYPE(instr, code); gen_goto_tb(dc, 0, (dc->pc & 0xF0000000) | (instr.imm26 << 2)); - dc->base.is_jmp =3D DISAS_NORETURN; } =20 static void call(DisasContext *dc, uint32_t code, uint32_t flags) @@ -251,7 +251,6 @@ static void br(DisasContext *dc, uint32_t code, uint32_= t flags) I_TYPE(instr, code); =20 gen_goto_tb(dc, 0, dc->base.pc_next + (instr.imm16.s & -4)); - dc->base.is_jmp =3D DISAS_NORETURN; } =20 static void gen_bxx(DisasContext *dc, uint32_t code, uint32_t flags) @@ -263,7 +262,6 @@ static void gen_bxx(DisasContext *dc, uint32_t code, ui= nt32_t flags) gen_goto_tb(dc, 0, dc->base.pc_next); gen_set_label(l1); gen_goto_tb(dc, 1, dc->base.pc_next + (instr.imm16.s & -4)); - dc->base.is_jmp =3D DISAS_NORETURN; } =20 /* Comparison instructions */ --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646914023832525.0985845046913; Thu, 10 Mar 2022 04:07:03 -0800 (PST) Received: from localhost ([::1]:35666 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHZP-0000fd-FK for importer@patchew.org; Thu, 10 Mar 2022 07:07:03 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51158) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGxo-0006K8-Kq for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:28:14 -0500 Received: from [2607:f8b0:4864:20::52d] (port=45863 helo=mail-pg1-x52d.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGxm-00083U-GB for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:28:11 -0500 Received: by mail-pg1-x52d.google.com with SMTP id z4so4467905pgh.12 for ; Thu, 10 Mar 2022 03:28:10 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.28.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:28:08 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3YCeMoFSIPOtuFxyHW9qCFQJFQUeLRVbZvCIxi8q4XE=; b=FINuLbuz155DTpUngqqhLnixH2INKODooSjzfWh2RnsW6z4Mk4N6E7OlDKQ7hMKbPI pAozDFYy2B2meSoYAEyn2mzN03pae7B85xy7eG7dgKzoYULFQfAVOYBZ/AQvV6E4Cy06 xyO+BNTG0iFhB+GaUlC1FZgsrbr7II/av3RKgAzKWVdC4MIflnrSBbYqkv5SSRt46esY sqXPDbCaGfVbQAQqBvCoMAOy9Nydjixzh9xagjVXuiUpA0Q7g/YUElBZlndEh08o14Tp vYkxSj0f0gHHcv+ZVy8OmW3rHmrlARUDw3lh8f5HdgPg45e/7fW0drPa5HBCkYobJbgA JIjg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3YCeMoFSIPOtuFxyHW9qCFQJFQUeLRVbZvCIxi8q4XE=; b=tR2eEXmBQlqY6CFqqoF3LX/3qutHsCeCJaKuRQeUXMbnkqIVp170oX/kQdqK4b4wun MDpri7/ZwtVbDrwS5zEEUT91GqXO/6mt7i4CVDfwzgZzSQ4JambKnsBdA71MLCqFoXKR KzsBvFAMgQXaIeolsJFl0Hn0eoClXPQuWc3kcFSK0Jd+ApOkO5qpzPCz6Ua65INpY0Dn xy4CN2LtWQGBUX6hL4JGvs1V/iGlii1lEYcxcPIzsSIqZau+jWJU/TTlYHn3XWCFctMr TqRneSyi5FddEMs6ZspspF5VzoyuQHZUd23bNLiCdL378IV0ut9FBSCMhKK1T3fDfPqi t6bA== X-Gm-Message-State: AOAM531OD0cEF+GK+4UQg2Q2id3V6Cdwv3g1qMcHCNUieqsVpHkXPmWP aSWHJDqel3W13LvzRryAArAqluD3WYZm+w== X-Google-Smtp-Source: ABdhPJw0sr2HXlqhbUthr43+X2Vyl7gnuxqLoQ81t7tdxEGt4Zzi84u0bqdtfXj4vGIvCJ/rMxaVgQ== X-Received: by 2002:a05:6a00:24c4:b0:4f7:2fc6:50e8 with SMTP id d4-20020a056a0024c400b004f72fc650e8mr4176073pfv.63.1646911689247; Thu, 10 Mar 2022 03:28:09 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 37/48] target/nios2: Use gen_goto_tb for DISAS_TOO_MANY Date: Thu, 10 Mar 2022 03:27:14 -0800 Message-Id: <20220310112725.570053-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::52d (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646914033305100001 Content-Type: text/plain; charset="utf-8" Depending on the reason for ending the TB, we can chain to the next TB because the PC is constant. Signed-off-by: Richard Henderson --- target/nios2/translate.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 51907586ab..6f31b6cc50 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -834,8 +834,11 @@ static void nios2_tr_tb_stop(DisasContextBase *dcbase,= CPUState *cs) /* Indicate where the next block should start */ switch (dc->base.is_jmp) { case DISAS_TOO_MANY: + gen_goto_tb(dc, 0, dc->base.pc_next); + break; + case DISAS_UPDATE: - /* Save the current PC back into the CPU register */ + /* Save the current PC, and return to the main loop. */ tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); tcg_gen_exit_tb(NULL, 0); break; --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646915264849248.96146497638097; Thu, 10 Mar 2022 04:27:44 -0800 (PST) Received: from localhost ([::1]:45476 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHtP-0002lF-QU for importer@patchew.org; Thu, 10 Mar 2022 07:27:43 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51180) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGxq-0006Ka-Ie for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:28:14 -0500 Received: from [2607:f8b0:4864:20::42c] (port=33513 helo=mail-pf1-x42c.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGxo-00083n-A6 for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:28:13 -0500 Received: by mail-pf1-x42c.google.com with SMTP id s42so4890849pfg.0 for ; Thu, 10 Mar 2022 03:28:11 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.28.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:28:09 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QMOimEYkivNn0EOtJQFRq+oOiueoNqaCGaU7AEWQQss=; b=Byn5Go+LYQ2Av8Mi3qz+Sgft9F2TIfzHppda4474BXPpc/YF00oQaTNplQ4nLg4s6s hN81MvLAtXwaxAlB6QDXkjukpR+jTQapcQ9odadgwkv+NqRsFO4+Nkd00467hFQoWul/ jMBoc/GT05z3+LkGF8nPbG1XxJiJ14V7chtG5Xgd6RL8p1F5MpMSb1f/Tjn9z/yCY0Pq 7fJRkqxSs/5PjzgiMgyobduEgknCUDyEjPNx8AEk7y4TSQqqbDfj6aOuE9rdHBgTsdYt 9LpMdbhMsF10nKZKYTfjV0V1FhA6LKneMcfJwuTOC4zfycXwC/3wVZAPKwY0JxPH4dQ8 poCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QMOimEYkivNn0EOtJQFRq+oOiueoNqaCGaU7AEWQQss=; b=wYzhODRRP2Qhn6GbxVK7yQ8zQE5Z6gxNnYoqkdfUwki0HC+48ZL1uwbNhnq5AbXZ8Y oYFWyKzWlsUV4XZgNHsAtGnflg4uGMRJr8x28Tj3keICCifFcrlT+1ArSWpqEVH3Xq1W vkkYJ27XgRQuO0a9ciZfQT4+VB+GO1HkirISUwLg03l7yzcJZ+IcxuxZKoHqrHtLlmHd RyEaG/EMGp+rcD7kfe/D/fya45f0j7HEToLAK3KQKwX/28qINLgr8X7CE1nqBjzc4kWg aV4NTI+AlRAHYZVdJ7TV1oXxKwQer3As9xO8JA7z+9OQbGwVHsI7RFO0SPRWCPYXbuun m43A== X-Gm-Message-State: AOAM532I3JuLY6nv53K9Ik2cxp5OUS4xMN/NaWixo2zT+10BVpsKcQWr Cua7PltO/sRtMP1FDfzYEnvtXW7Y5P2LyA== X-Google-Smtp-Source: ABdhPJx278faL2dcaWDpAEzYZRQocjV5AnwdEshwSqeJAbRv/WM3Nq6ADJqkmHzpvAryPF06ssqnEg== X-Received: by 2002:a63:724b:0:b0:378:7967:e45c with SMTP id c11-20020a63724b000000b003787967e45cmr3753719pgn.602.1646911690234; Thu, 10 Mar 2022 03:28:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 38/48] target/nios2: Use tcg_gen_lookup_and_goto_ptr Date: Thu, 10 Mar 2022 03:27:15 -0800 Message-Id: <20220310112725.570053-39-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42c (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646915267093100001 Content-Type: text/plain; charset="utf-8" Use lookup_and_goto_ptr for indirect chaining between TBs. Signed-off-by: Richard Henderson --- target/nios2/translate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 6f31b6cc50..f7bab0908b 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -163,7 +163,7 @@ static void gen_goto_tb(DisasContext *dc, int n, uint32= _t dest) tcg_gen_exit_tb(tb, n); } else { tcg_gen_movi_tl(cpu_pc, dest); - tcg_gen_exit_tb(NULL, 0); + tcg_gen_lookup_and_goto_ptr(); } dc->base.is_jmp =3D DISAS_NORETURN; } @@ -174,7 +174,7 @@ static void gen_jumpr(DisasContext *dc, int regno, bool= is_call) if (is_call) { tcg_gen_movi_tl(dest_gpr(dc, R_RA), dc->base.pc_next); } - tcg_gen_exit_tb(NULL, 0); + tcg_gen_lookup_and_goto_ptr(); dc->base.is_jmp =3D DISAS_NORETURN; } =20 --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646915169893155.40357498784738; Thu, 10 Mar 2022 04:26:09 -0800 (PST) Received: from localhost ([::1]:40582 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHrs-0007X7-Kr for importer@patchew.org; Thu, 10 Mar 2022 07:26:08 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51178) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSGxq-0006KZ-Ht for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:28:14 -0500 Received: from [2607:f8b0:4864:20::62f] (port=47055 helo=mail-pl1-x62f.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSGxo-00083z-Ds for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:28:13 -0500 Received: by mail-pl1-x62f.google.com with SMTP id w4so4560095ply.13 for ; Thu, 10 Mar 2022 03:28:12 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id js15-20020a17090b148f00b001bfc8614b93sm3114977pjb.1.2022.03.10.03.28.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:28:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LTuw5YwD7AAqbGDKsXNMlzx47tIusaHPWNHDAjQuUEg=; b=Hl+PbNhubeLhz963N5yNtLp0Vln4ixO4efwemAj7Q7Gfv5gN177fqK+69jmfFI55SQ ieFrAht5Kv08VZmz2peZdGT6MGYYqkTo5oDH0lbBUpgWPldawIlUn0PTBoBaOe+SZQYU n1GAZHgu1lK6hdviOSEUKs0mh4QWja7II6YCyEGdQuEdaITdz4HCDxkGZHPrcHm+7mVM 3kKISdZoeO3XNNA3ysw1mSchUzSNIBXenqPXSHrXLAhhuvmdh4PfoXyYW9nW6KUkjhgs eGLhrOmWIylI1PrMuRbwYDD3dDShnjpXF1IOq7d5MULttSVdFFoFfa7l2gsyKqHagI46 9IWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LTuw5YwD7AAqbGDKsXNMlzx47tIusaHPWNHDAjQuUEg=; b=i8NCPTjjk2HumkBvA3fCha93+XrUYLpVppGEl6ukXCSNlzr/PcP4fktpfqmG10ermv tOB2rzWhYyGICsCY1NVShL9vxeVLW2vWQc2hucJ97ZnKU1SkQPN+pn7AgILh9xzYX6U3 sDzLSTS3oorq0VorEVJo/d88sIlhN0Ze18PS0AqeUapMvgl5e2TUVuQ8bilCcJ1u08kD SW+zBuON2Gu4vZUl9+WdU7ad/RDjI4VKJJD3kIP+tl+t8sREEPAA5puN4P18jNQ8I89Q QQfSZqME9fBlkYDIbmsB3KCM9HPLDrDhcqaec0mmPn/WhI676QmFdlPSUMVbDDPVlLqA N6MQ== X-Gm-Message-State: AOAM530ajzWcZVRrmoCa9favmcwPkorIst9nvR8u0XNyF2WbgkXDS/Fp FrRqA0ZgASZ6WTWQghx9elnhM9R2I/mntg== X-Google-Smtp-Source: ABdhPJzFmv3JXKD+4rYYQAWKoREO5BA9yUUZRPyqYE70wfWT2iH+IBcsj06h5WGiYkLSHw985SgXZg== X-Received: by 2002:a17:90b:1e0a:b0:1bf:4d46:741c with SMTP id pg10-20020a17090b1e0a00b001bf4d46741cmr15430919pjb.116.1646911691197; Thu, 10 Mar 2022 03:28:11 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 39/48] target/nios2: Implement Misaligned destination exception Date: Thu, 10 Mar 2022 03:27:16 -0800 Message-Id: <20220310112725.570053-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62f (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62f; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62f.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646915171522100001 Content-Type: text/plain; charset="utf-8" Indirect branches, plus eret and bret optionally raise an exception when branching to a misaligned address. The exception is required when an mmu is enabled, but enable it always because the fallback behaviour is not documented (though presumably it discards low bits). For the purposes of the linux-user cpu loop, if EXCP_UNALIGN (misaligned data) were to arrive, it would be treated the same as EXCP_UNALIGND (misaligned destination). See the !defined(CONFIG_NIOS2_ALIGNMENT_TRAP) block in kernel/traps.c. Signed-off-by: Richard Henderson --- linux-user/nios2/cpu_loop.c | 6 ++++++ target/nios2/op_helper.c | 9 ++++++++- target/nios2/translate.c | 15 ++++++++++++++- 3 files changed, 28 insertions(+), 2 deletions(-) diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index ea364b7d1f..67220128aa 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -43,6 +43,12 @@ void cpu_loop(CPUNios2State *env) force_sig_fault(TARGET_SIGFPE, TARGET_FPE_INTDIV, env->pc); break; =20 + case EXCP_UNALIGN: + case EXCP_UNALIGND: + force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN, + env->ctrl[CR_BADADDR]); + break; + case EXCP_TRAP: switch (env->error_code) { case 0: diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index c93b66c9aa..849867becd 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -64,6 +64,13 @@ uint32_t helper_divu(CPUNios2State *env, uint32_t num, u= int32_t den) void helper_eret(CPUNios2State *env, uint32_t new_status, uint32_t new_pc) { Nios2CPU *cpu =3D env_archcpu(env); + CPUState *cs =3D env_cpu(env); + + if (unlikely(new_pc & 3)) { + env->ctrl[CR_BADADDR] =3D new_pc; + cs->exception_index =3D EXCP_UNALIGND; + cpu_loop_exit_restore(cs, GETPC()); + } =20 /* * Both estatus and bstatus have no constraints on write; @@ -74,6 +81,6 @@ void helper_eret(CPUNios2State *env, uint32_t new_status,= uint32_t new_pc) =20 env->ctrl[CR_STATUS] =3D new_status; env->pc =3D new_pc; - cpu_loop_exit(env_cpu(env)); + cpu_loop_exit(cs); } #endif /* !CONFIG_USER_ONLY */ diff --git a/target/nios2/translate.c b/target/nios2/translate.c index f7bab0908b..1e784c8a37 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -170,11 +170,24 @@ static void gen_goto_tb(DisasContext *dc, int n, uint= 32_t dest) =20 static void gen_jumpr(DisasContext *dc, int regno, bool is_call) { - tcg_gen_mov_tl(cpu_pc, load_gpr(dc, regno)); + TCGLabel *l =3D gen_new_label(); + TCGv test =3D tcg_temp_new(); + TCGv dest =3D load_gpr(dc, regno); + + tcg_gen_andi_tl(test, dest, 3); + tcg_gen_brcondi_tl(TCG_COND_NE, test, 0, l); + tcg_temp_free(test); + + tcg_gen_mov_tl(cpu_pc, dest); if (is_call) { tcg_gen_movi_tl(dest_gpr(dc, R_RA), dc->base.pc_next); } tcg_gen_lookup_and_goto_ptr(); + + gen_set_label(l); + tcg_gen_st_tl(dest, cpu_env, offsetof(CPUNios2State, ctrl[CR_BADADDR])= ); + t_gen_helper_raise_exception(dc, EXCP_UNALIGND); + dc->base.is_jmp =3D DISAS_NORETURN; } =20 --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16469154738041016.4138576968675; Thu, 10 Mar 2022 04:31:13 -0800 (PST) Received: from localhost ([::1]:49748 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHwm-0005zF-6A for importer@patchew.org; Thu, 10 Mar 2022 07:31:12 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51740) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSH0m-0002Vt-OI for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:31:17 -0500 Received: from [2607:f8b0:4864:20::1029] (port=34518 helo=mail-pj1-x1029.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSH0l-0008Sq-8Y for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:31:16 -0500 Received: by mail-pj1-x1029.google.com with SMTP id k5-20020a17090a3cc500b001befa0d3102so6097687pjd.1 for ; Thu, 10 Mar 2022 03:31:13 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id e14-20020a056a001a8e00b004f75cf1ab6csm6011246pfv.206.2022.03.10.03.31.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:31:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aUIv8mPilapal9RFUm8fJDHj8xhqXeKP3105ESvQPFk=; b=rJQWPPJXwXzp9TRp24MRTjirq45N7llzkfCJ+J7PrKc0wAgDdUm7iJ36QOEAz91ed5 qy9CySuBpZJKUVt0T5ho7SdjC/7o5cdka+t/ZAzGP29Q1OxVvAORXGVe1mZ5RKvP8s2k F7+A7m0Sri8sCUWRoNlK7/+j8y+dlZzykRZA/EnPa47Lr73L/5N1XyKhE0MzKGpPj41B z6nwkYeDiRwdgROUOOuCHPd+GTu5SZAkfBkOyI/k8vDNl62UVaN14TGPuZO2QEJOEvdI FdTLYyPKcGLYTsyM4ByASPZQTW/4ZRORHKZL6v9E8VxhAbR6swi2VCq7ntiTqEZ4l54f YOEA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aUIv8mPilapal9RFUm8fJDHj8xhqXeKP3105ESvQPFk=; b=eZ49sl2iTPp6bQZtJRQWvYyUc8f0FlEKpCw0LsqrG+SZ5+NCIGYympcDs/YlSWRAu/ YdXHAj5xLZectueDAHlzX3EjqNMtM6AtjuUWrkniJM0IRKcHxGDrGqPaoEktZbQdzQfi SvRB9GLkOdN388NALnBJ8p/gUQDTLXEmijHJXvvxqIIqzjR7blp/8mlJmNNtT3mQj/Rh rGVhCItq98JYHI/4R3BEM/YpKtOUn8EZMBgQrZhjYFm/479q8vdyIR5XDCJJieaDNmbJ 4PnDneJcyu9n1dW5OGLiMymr3Sj7Gvwl0kpjw6o0tWQ1J4Sdbm+83CiOrEn6uNxHpb0g wgcw== X-Gm-Message-State: AOAM530FfE6WvjJnIS8ZRmgi6iOMmWXjxTX29PJZuQVgl74jJ7aq7UkM KpJaIk+fpmj5Nz8KF/gqgGunmfSzQRcwzQ== X-Google-Smtp-Source: ABdhPJxJcA/W6qSp82qiQIuUQFf+lrlAGAMBCva/Z+u1AS2sLmaSCqs4/9DOwzrh9mavO/g2mbqYMA== X-Received: by 2002:a17:90a:9ac:b0:1bf:a3e2:3f5c with SMTP id 41-20020a17090a09ac00b001bfa3e23f5cmr4506913pjo.105.1646911872818; Thu, 10 Mar 2022 03:31:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 40/48] linux-user/nios2: Handle various SIGILL exceptions Date: Thu, 10 Mar 2022 03:27:17 -0800 Message-Id: <20220310112725.570053-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1029 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646915475772100001 Content-Type: text/plain; charset="utf-8" We missed out on a couple of exception types that may legitimately be raised by a userland program. Signed-off-by: Richard Henderson --- linux-user/nios2/cpu_loop.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index 67220128aa..f223238275 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -49,6 +49,14 @@ void cpu_loop(CPUNios2State *env) env->ctrl[CR_BADADDR]); break; =20 + case EXCP_ILLEGAL: + case EXCP_UNIMPL: + force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLOPC, env->pc); + break; + case EXCP_SUPERI: + force_sig_fault(TARGET_SIGILL, TARGET_ILL_PRVOPC, env->pc); + break; + case EXCP_TRAP: switch (env->error_code) { case 0: --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646915625952369.8885251822437; Thu, 10 Mar 2022 04:33:45 -0800 (PST) Received: from localhost ([::1]:56416 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHzE-0002N9-Bc for importer@patchew.org; Thu, 10 Mar 2022 07:33:44 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51748) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSH0n-0002Vw-A2 for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:31:17 -0500 Received: from [2607:f8b0:4864:20::52a] (port=46778 helo=mail-pg1-x52a.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSH0l-0008Sv-Dt for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:31:16 -0500 Received: by mail-pg1-x52a.google.com with SMTP id o23so4464899pgk.13 for ; Thu, 10 Mar 2022 03:31:15 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id e14-20020a056a001a8e00b004f75cf1ab6csm6011246pfv.206.2022.03.10.03.31.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:31:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ItyhHSiGdc58HAGraU/SXIWa8zv4816zOwkBCWpNHUs=; b=uXnYCF/cLCJx51+LWAIwgtC7Pt9tyU+PxtALMfCYqGei4QUx48rKku9+IwUQAEQhWV gcdi4APUpaiJArwEbJkMcHVS/VyUZs53ss87AMISA/BJTwyP7abHroFjc9Xzmt+3snYS oc14U3psHKdasi/7MaJDNSSKdlsLvCEaL2vyKeiCFiP+eqaTWQUe/GGlg+96GKgycx9X k23/5XJxUZAKeeRRb4po1ZAp2fwjfErNr+sjc0P31VUpwGreEOqYhDh0dKXo03FNgcmr qjNl5XY9BnGNvansItTF++5t2SHGTfV1oia0KzrjBOtafsQttQaM4C0aUQg+OMUpkuBz OnYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ItyhHSiGdc58HAGraU/SXIWa8zv4816zOwkBCWpNHUs=; b=3xvlBi4dXET6wYu91CUSra/t5zrrpof94ZhXkEmVFQbmE0WCqKh3PtaEvunA785cLe vZCPCaIAjlxwuMsZFzBS9Zr+So46NngYhJVW4LAi7cQpxCi3bl+6CaOzRw59yBKLSD3F cCF5L6A0JcvXzW88NW76T6VmisZXvBmDG0pNBRgtiNzAVBUTqQUkVR3a/0UnjXrlp0zB j4ztkpZl0QXBMjIjEt91QgioKTAXimkwqBa4MDg4H9ZpXUIblPFyxnd0dRsdr8J3ZjAA qjTydQP4hD6N+6HMjk8/Pfj/vv/Na9usxnoty5Ac072p9RPQ3J+gv1MM840NEHqmWn2a UfmQ== X-Gm-Message-State: AOAM5315aEagMo3TN9G/wN3jc6GPzo1xz6QdD2hLXjjxpE7hTbgjBMhg hMZONEQWAm93aKJB2fr3ZyECg1I3aZl45Q== X-Google-Smtp-Source: ABdhPJwlixa4izaPel3ESRG2jNdvcBietvXgJtqFyYJy3liTp5ktXHLk57B5fRpybcRuIfIEEjGNew== X-Received: by 2002:a62:402:0:b0:4f7:81a3:7c47 with SMTP id 2-20020a620402000000b004f781a37c47mr617181pfe.9.1646911873933; Thu, 10 Mar 2022 03:31:13 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 41/48] target/nios2: Introduce shadow register sets Date: Thu, 10 Mar 2022 03:27:18 -0800 Message-Id: <20220310112725.570053-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::52a (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646915627377100001 Content-Type: text/plain; charset="utf-8" Do not actually enable them so far, but add all of the plumbing to address them. Do not enable them for user-only. Add an env->regs pointer that handles the indirection to the current register set. The naming of the pointer hides the difference between old and new, user-only and sysemu. From the notes on wrprs, which states that r0 must be initialized before use in shadow register sets, infer that R_ZERO is *not* hardwired to zero in shadow register sets. Adjust load_gpr and dest_gpr to reflect this. At the same time we might as well special case crs =3D=3D 0 to avoid the indirection through env->regs during translation as well. Given that this is intended to be the most common case for non-interrupt handlers. Init env->regs at reset. Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 24 +++++++++++++++++ target/nios2/cpu.c | 1 + target/nios2/translate.c | 58 +++++++++++++++++++++++++++++++--------- 3 files changed, 70 insertions(+), 13 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index d5255e9e76..e32bebe9b7 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -60,6 +60,11 @@ struct Nios2CPUClass { #define NUM_GP_REGS 32 #define NUM_CR_REGS 32 =20 +#ifndef CONFIG_USER_ONLY +/* 63 shadow register sets; index 0 is the primary register set. */ +#define NUM_REG_SETS 64 +#endif + /* General purpose register aliases */ enum { R_ZERO =3D 0, @@ -178,7 +183,13 @@ FIELD(CR_TLBMISC, EE, 24, 1) #define EXCP_MPUD 17 =20 struct CPUArchState { +#ifdef CONFIG_USER_ONLY uint32_t regs[NUM_GP_REGS]; +#else + uint32_t shadow_regs[NUM_REG_SETS][NUM_GP_REGS]; + /* Pointer into shadow_regs for the current register set. */ + uint32_t *regs; +#endif uint32_t ctrl[NUM_CR_REGS]; uint32_t pc; =20 @@ -229,6 +240,14 @@ static inline bool nios2_cr_reserved(const ControlRegS= tate *s) return (s->writable | s->readonly) =3D=3D 0; } =20 +static inline void nios2_update_crs(CPUNios2State *env) +{ +#ifndef CONFIG_USER_ONLY + unsigned crs =3D FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, CRS); + env->regs =3D env->shadow_regs[crs]; +#endif +} + void nios2_tcg_init(void); void nios2_cpu_do_interrupt(CPUState *cs); void dump_mmu(CPUNios2State *env); @@ -271,12 +290,17 @@ typedef Nios2CPU ArchCPU; =20 #include "exec/cpu-all.h" =20 +FIELD(TBFLAGS, CRS0, 0, 1) /* Set if CRS =3D=3D 0. */ +FIELD(TBFLAGS, U, 1, 1) /* Overlaps CR_STATUS_U */ + static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *= pc, target_ulong *cs_base, uint32_t *f= lags) { *pc =3D env->pc; *cs_base =3D 0; *flags =3D env->ctrl[CR_STATUS] & CR_STATUS_U; + *flags |=3D (env->ctrl[CR_STATUS] & R_CR_STATUS_CRS_MASK + ? 0 : R_TBFLAGS_CRS0_MASK); } =20 #endif /* NIOS2_CPU_H */ diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index b8410d8447..efd6a21a8e 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -59,6 +59,7 @@ static void nios2_cpu_reset(DeviceState *dev) env->ctrl[CR_STATUS] =3D CR_STATUS_RSIE | CR_STATUS_U | CR_STATUS_PIE; #else env->ctrl[CR_STATUS] =3D CR_STATUS_RSIE; + nios2_update_crs(env); #endif =20 env->regs[R_ZERO] =3D 0; diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 1e784c8a37..525df7b023 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -100,12 +100,16 @@ typedef struct DisasContext { DisasContextBase base; target_ulong pc; int mem_idx; + bool crs0; TCGv sink; const ControlRegState *cr_state; } DisasContext; =20 static TCGv cpu_R[NUM_GP_REGS]; static TCGv cpu_pc; +#ifndef CONFIG_USER_ONLY +static TCGv cpu_crs_R[NUM_GP_REGS]; +#endif =20 typedef struct Nios2Instruction { void (*handler)(DisasContext *dc, uint32_t code, uint32_t flags); @@ -127,22 +131,36 @@ static uint8_t get_opxcode(uint32_t code) static TCGv load_gpr(DisasContext *dc, unsigned reg) { assert(reg < NUM_GP_REGS); - if (unlikely(reg =3D=3D R_ZERO)) { - return tcg_constant_tl(0); + if (dc->crs0) { + if (unlikely(reg =3D=3D R_ZERO)) { + return tcg_constant_tl(0); + } + return cpu_R[reg]; } - return cpu_R[reg]; +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + return cpu_crs_R[reg]; +#endif } =20 static TCGv dest_gpr(DisasContext *dc, unsigned reg) { assert(reg < NUM_GP_REGS); - if (unlikely(reg =3D=3D R_ZERO)) { - if (dc->sink =3D=3D NULL) { - dc->sink =3D tcg_temp_new(); + if (dc->crs0) { + if (unlikely(reg =3D=3D R_ZERO)) { + if (dc->sink =3D=3D NULL) { + dc->sink =3D tcg_temp_new(); + } + return dc->sink; } - return dc->sink; + return cpu_R[reg]; } - return cpu_R[reg]; +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + return cpu_crs_R[reg]; +#endif } =20 static void t_gen_helper_raise_exception(DisasContext *dc, @@ -198,7 +216,7 @@ static void gen_excp(DisasContext *dc, uint32_t code, u= int32_t flags) =20 static bool gen_check_supervisor(DisasContext *dc) { - if (dc->base.tb->flags & CR_STATUS_U) { + if (dc->base.tb->flags & R_TBFLAGS_U_MASK) { /* CPU in user mode, privileged instruction called, stop. */ t_gen_helper_raise_exception(dc, EXCP_SUPERI); return false; @@ -794,6 +812,7 @@ static void nios2_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) =20 dc->mem_idx =3D cpu_mmu_index(env, false); dc->cr_state =3D cpu->cr_state; + dc->crs0 =3D FIELD_EX32(dc->base.tb->flags, TBFLAGS, CRS0); =20 /* Bound the number of insns to execute to those left on the page. */ page_insns =3D -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; @@ -927,13 +946,26 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int = flags) =20 void nios2_tcg_init(void) { - int i; +#ifndef CONFIG_USER_ONLY + TCGv_ptr crs =3D tcg_global_mem_new_ptr(cpu_env, + offsetof(CPUNios2State, regs), "= crs"); =20 - for (i =3D 0; i < NUM_GP_REGS; i++) { - cpu_R[i] =3D tcg_global_mem_new(cpu_env, - offsetof(CPUNios2State, regs[i]), + for (int i =3D 0; i < NUM_GP_REGS; i++) { + cpu_crs_R[i] =3D tcg_global_mem_new(crs, 4 * i, gr_regnames[i]); + } + +#define offsetof_regs0(N) offsetof(CPUNios2State, shadow_regs[0][N]) +#else +#define offsetof_regs0(N) offsetof(CPUNios2State, regs[N]) +#endif + + for (int i =3D 0; i < NUM_GP_REGS; i++) { + cpu_R[i] =3D tcg_global_mem_new(cpu_env, offsetof_regs0(i), gr_regnames[i]); } + +#undef offsetof_regs0 + cpu_pc =3D tcg_global_mem_new(cpu_env, offsetof(CPUNios2State, pc), "pc"); } --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646915506334191.93414033893202; Thu, 10 Mar 2022 04:31:46 -0800 (PST) Received: from localhost ([::1]:51360 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHxJ-0007OP-B8 for importer@patchew.org; Thu, 10 Mar 2022 07:31:45 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51772) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSH0o-0002Wl-I1 for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:31:21 -0500 Received: from [2607:f8b0:4864:20::632] (port=41562 helo=mail-pl1-x632.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSH0m-0008T3-OI for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:31:18 -0500 Received: by mail-pl1-x632.google.com with SMTP id z3so4599401plg.8 for ; Thu, 10 Mar 2022 03:31:16 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id e14-20020a056a001a8e00b004f75cf1ab6csm6011246pfv.206.2022.03.10.03.31.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:31:14 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zL4ULUAZFLG4NiZ2Xxof4c8+aeBvBkKbH83Le8PjFIE=; b=NQbcez9BQoOX6fuFu7cB1PvBsES3In949mJVL6L4weQ7seculiM5aQH1YKxx5dBSKf pn6v8hJPRcb0NTeddGJLtf6Ik098cHS9QLinWBcnTCC8i5iv8rQ2ulK8janGVDXjUrHZ +L+RX/p72nfZpgo/i9d5D3M9dpKrJFPnjKoSJ8uT2PxqyM1J/59vFuKmygBq33rCGr2l 4a25RORcANPrFF20XzqMNMgk4p8YdZQALnVB2SNBsKCTonDxG68r37Yz/7RScWkjcR/4 h6GmU46qkNUXt52z9TENl3xPXNAuMmvppOLqusLwQHWgaXn6Qp6XVzhDqKqmLnm9uV4E RRCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zL4ULUAZFLG4NiZ2Xxof4c8+aeBvBkKbH83Le8PjFIE=; b=ZYjofjYfOe1eEyzcZJkWQbvgpgzxIMFtKdKyZCXhLGnB7OHi84OqX7OOIjPn8mdIq0 cSGHaJcVv6poycsCTHPw+sS9+KDmV7brutqrMLhzy+/eYog233xR9wnC7eZfnon95eR4 k1TUKyAh+aY8FF8QC+kYzFOv2bAak38ywBKG+iQ5q7/45GtBAySXCNddPjuf9Hd4DSnh afkOGwFvgsUO+OmwvvvPcyr3ae0ZP2fHr4IzJTEc7R6TbfBlEVI6ffrWrQOdN5izELAW Sv3BaEccn1CSktUZdaslmUaeEynl4uKYRqReTWOJm+AFBz80xI/qhCR2PAhcoGhHOXp0 gJdA== X-Gm-Message-State: AOAM532S8Wj6bn/YZB2gZrR2UoC3LvcXFgpvVkZuTT4gA3YW+tbcg+2K 8WUWccLR00fYy4t4kifmAm+rCd5cilew+w== X-Google-Smtp-Source: ABdhPJwZb1swk6q8oQnO7XB6ws9TncgprLDJGrq9bxbyG7l/JowMsYIctlruQgWBnveIq+khAayj5A== X-Received: by 2002:a17:90b:4c87:b0:1bf:7ff7:4f39 with SMTP id my7-20020a17090b4c8700b001bf7ff74f39mr15460413pjb.163.1646911875374; Thu, 10 Mar 2022 03:31:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 42/48] target/nios2: Implement rdprs, wrprs Date: Thu, 10 Mar 2022 03:27:19 -0800 Message-Id: <20220310112725.570053-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::632 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::632; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x632.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646915509799100003 Content-Type: text/plain; charset="utf-8" Implement these out of line, so that tcg global temps (aka the architectural registers) are synced back to tcg storage as required. This makes sure that we get the proper results when status.PRS =3D=3D status.CRS. Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 1 + target/nios2/helper.h | 2 ++ target/nios2/op_helper.c | 12 ++++++++++ target/nios2/translate.c | 47 ++++++++++++++++++++++++++++++++++++++-- 4 files changed, 60 insertions(+), 2 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index e32bebe9b7..26d4dcfe12 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -220,6 +220,7 @@ struct ArchCPU { =20 bool diverr_present; bool mmu_present; + bool eic_present; =20 uint32_t pid_num_bits; uint32_t tlb_num_ways; diff --git a/target/nios2/helper.h b/target/nios2/helper.h index 6f5ec60b0d..1648d76ade 100644 --- a/target/nios2/helper.h +++ b/target/nios2/helper.h @@ -24,6 +24,8 @@ DEF_HELPER_FLAGS_3(divu, TCG_CALL_NO_WG, i32, env, i32, i= 32) =20 #if !defined(CONFIG_USER_ONLY) DEF_HELPER_3(eret, noreturn, env, i32, i32) +DEF_HELPER_FLAGS_2(rdprs, TCG_CALL_NO_WG, i32, env, i32) +DEF_HELPER_3(wrprs, void, env, i32, i32) DEF_HELPER_2(mmu_write_tlbacc, void, env, i32) DEF_HELPER_2(mmu_write_tlbmisc, void, env, i32) DEF_HELPER_2(mmu_write_pteaddr, void, env, i32) diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index 849867becd..e5e70268da 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -83,4 +83,16 @@ void helper_eret(CPUNios2State *env, uint32_t new_status= , uint32_t new_pc) env->pc =3D new_pc; cpu_loop_exit(cs); } + +uint32_t helper_rdprs(CPUNios2State *env, uint32_t regno) +{ + unsigned prs =3D FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, PRS); + return env->shadow_regs[prs][regno]; +} + +void helper_wrprs(CPUNios2State *env, uint32_t regno, uint32_t val) +{ + unsigned prs =3D FIELD_EX32(env->ctrl[CR_STATUS], CR_STATUS, PRS); + env->shadow_regs[prs][regno] =3D val; +} #endif /* !CONFIG_USER_ONLY */ diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 525df7b023..2b2f528e00 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -103,6 +103,7 @@ typedef struct DisasContext { bool crs0; TCGv sink; const ControlRegState *cr_state; + bool eic_present; } DisasContext; =20 static TCGv cpu_R[NUM_GP_REGS]; @@ -326,6 +327,27 @@ gen_i_math_logic(andhi, andi, 0, instr.imm16.u << 16) gen_i_math_logic(orhi , ori, 1, instr.imm16.u << 16) gen_i_math_logic(xorhi, xori, 1, instr.imm16.u << 16) =20 +/* rB <- prs.rA + sigma(IMM16) */ +static void rdprs(DisasContext *dc, uint32_t code, uint32_t flags) +{ + if (!dc->eic_present) { + t_gen_helper_raise_exception(dc, EXCP_ILLEGAL); + return; + } + if (!gen_check_supervisor(dc)) { + return; + } + +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + I_TYPE(instr, code); + TCGv dest =3D dest_gpr(dc, instr.b); + gen_helper_rdprs(dest, cpu_env, tcg_constant_i32(instr.a)); + tcg_gen_addi_tl(dest, dest, instr.imm16.s); +#endif +} + /* Prototype only, defined below */ static void handle_r_type_instr(DisasContext *dc, uint32_t code, uint32_t flags); @@ -387,7 +409,7 @@ static const Nios2Instruction i_type_instructions[] =3D= { INSTRUCTION_FLG(gen_stx, MO_SL), /* stwio */ INSTRUCTION_FLG(gen_bxx, TCG_COND_LTU), /* bltu */ INSTRUCTION_FLG(gen_ldx, MO_UL), /* ldwio */ - INSTRUCTION_UNIMPLEMENTED(), /* rdprs */ + INSTRUCTION(rdprs), /* rdprs */ INSTRUCTION_ILLEGAL(), INSTRUCTION_FLG(handle_r_type_instr, 0), /* R-Type */ INSTRUCTION_NOP(), /* flushd */ @@ -587,6 +609,26 @@ static void wrctl(DisasContext *dc, uint32_t code, uin= t32_t flags) #endif } =20 +/* prs.rC <- rA */ +static void wrprs(DisasContext *dc, uint32_t code, uint32_t flags) +{ + if (!dc->eic_present) { + t_gen_helper_raise_exception(dc, EXCP_ILLEGAL); + return; + } + if (!gen_check_supervisor(dc)) { + return; + } + +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + R_TYPE(instr, code); + gen_helper_wrprs(cpu_env, tcg_constant_i32(instr.c), + load_gpr(dc, instr.a)); +#endif +} + /* Comparison instructions */ static void gen_cmpxx(DisasContext *dc, uint32_t code, uint32_t flags) { @@ -711,7 +753,7 @@ static const Nios2Instruction r_type_instructions[] =3D= { INSTRUCTION_ILLEGAL(), INSTRUCTION(slli), /* slli */ INSTRUCTION(sll), /* sll */ - INSTRUCTION_UNIMPLEMENTED(), /* wrprs */ + INSTRUCTION(wrprs), /* wrprs */ INSTRUCTION_ILLEGAL(), INSTRUCTION(or), /* or */ INSTRUCTION(mulxsu), /* mulxsu */ @@ -812,6 +854,7 @@ static void nios2_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) =20 dc->mem_idx =3D cpu_mmu_index(env, false); dc->cr_state =3D cpu->cr_state; + dc->eic_present =3D cpu->eic_present; dc->crs0 =3D FIELD_EX32(dc->base.tb->flags, TBFLAGS, CRS0); =20 /* Bound the number of insns to execute to those left on the page. */ --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[174.21.142.130]) by smtp.gmail.com with ESMTPSA id e14-20020a056a001a8e00b004f75cf1ab6csm6011246pfv.206.2022.03.10.03.31.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:31:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MVyC4ASoKbDoWqWtQ6it33/tXOmFXiabY9tyAWzkgHg=; b=G8JdJh/mnLXGyv0MmsQUXsBl2mSG8XRFkAfJkovZ7cMY5SO2XK1KepvXOvx/qw6xaV H/i1LoUqECvKwAomO8Sq7L5nDRmPYL6AoUeYwwxqAbR4a944LtZZNEA5HCqMJrhVV7TY g7l1V22dox1xdc9hgRZYmlwj8ZtlYTc7VFeMrdGV9hKdZOT57yrI4jaCTOV/hk3+WO88 bFYnBAAFpYvNez9Cb00nUyzjEsArwyOFgEh6cJXfVJRkpZAhBcsQh8sQgvvuuGSJ4mHb 99vkcEKCNETxJwaNxytiuW1SKTTIkt5rrcMuaymXLYVzw1t22LUGOKBzgQVdi68GAowU c4VA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MVyC4ASoKbDoWqWtQ6it33/tXOmFXiabY9tyAWzkgHg=; b=mi2Oat6Q7j8o1058hVA5hN5TGcTvkgLnW8dG5zPYyoibB6kgiV2MFE9CItkG9zqPtk DYYDHUojEqZhAqjdh8Pett9WM1tLNwJWuN8De+dqPPHEQM9Use8xN7V+9o6VGRBLEjbK wCJdtgzpl/gPVklHHFpiPbojJ3y7rrI+7SPcf5yiTEjwaOstmqnhuj5byUZp4hwydSCu 0oBYHSkVx5OTG73YEv2At1OC2uUKs1SKikyzbraDC1wqMChvNkRsaQUT166BIPn9mrpF 4oy1hvpDHihUJ7OIyaXg4q/qeaAYjGB2fRbqW071ajQjPmDyXVhka8xL4tgE00M9x6XZ cj3g== X-Gm-Message-State: AOAM53198l37cePNd8L/8s4aFlGdCToBREXV5C48Q8099zaET4Vbl3WB d+tidbS1kc+qfCB59eNxOxuEsgSKwJwFHA== X-Google-Smtp-Source: ABdhPJxe2zcTHqR0bKax9nosSGaydRuKATmH9dyXwsKCVJmkwjP1zDv66n2o/mJyuj7Sy7ZBD0Nf9g== X-Received: by 2002:a17:90a:a78f:b0:1bc:8042:9330 with SMTP id f15-20020a17090aa78f00b001bc80429330mr15339983pjq.229.1646911876397; Thu, 10 Mar 2022 03:31:16 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 43/48] target/nios2: Update helper_eret for shadow registers Date: Thu, 10 Mar 2022 03:27:20 -0800 Message-Id: <20220310112725.570053-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1033 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646915756650100001 Content-Type: text/plain; charset="utf-8" When CRS =3D 0, we restore from estatus; otherwise from sstatus. Update for the new CRS. Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 1 + target/nios2/op_helper.c | 3 ++- target/nios2/translate.c | 13 ++++++++----- 3 files changed, 11 insertions(+), 6 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 26d4dcfe12..62a73c7b32 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -82,6 +82,7 @@ enum { R_FP =3D 28, R_EA =3D 29, R_BA =3D 30, + R_SSTATUS =3D 30, R_RA =3D 31, }; =20 diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index e5e70268da..2eac957f68 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -73,7 +73,7 @@ void helper_eret(CPUNios2State *env, uint32_t new_status,= uint32_t new_pc) } =20 /* - * Both estatus and bstatus have no constraints on write; + * None of estatus, bstatus, or sstatus have constraints on write; * do not allow reserved fields in status to be set. */ new_status &=3D (cpu->cr_state[CR_STATUS].writable | @@ -81,6 +81,7 @@ void helper_eret(CPUNios2State *env, uint32_t new_status,= uint32_t new_pc) =20 env->ctrl[CR_STATUS] =3D new_status; env->pc =3D new_pc; + nios2_update_crs(env); cpu_loop_exit(cs); } =20 diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 2b2f528e00..7a25c864e2 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -435,11 +435,14 @@ static void eret(DisasContext *dc, uint32_t code, uin= t32_t flags) #ifdef CONFIG_USER_ONLY g_assert_not_reached(); #else - TCGv tmp =3D tcg_temp_new(); - tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_ESTATUS])); - gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_EA)); - tcg_temp_free(tmp); - + if (dc->crs0) { + TCGv tmp =3D tcg_temp_new(); + tcg_gen_ld_tl(tmp, cpu_env, offsetof(CPUNios2State, ctrl[CR_ESTATU= S])); + gen_helper_eret(cpu_env, tmp, load_gpr(dc, R_EA)); + tcg_temp_free(tmp); + } else { + gen_helper_eret(cpu_env, load_gpr(dc, R_SSTATUS), load_gpr(dc, R_E= A)); + } dc->base.is_jmp =3D DISAS_NORETURN; #endif } --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646912888749282.0198283732502; Thu, 10 Mar 2022 03:48:08 -0800 (PST) Received: from localhost ([::1]:42362 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHH5-00089F-FL for importer@patchew.org; Thu, 10 Mar 2022 06:48:07 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51802) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSH0q-0002Wq-LO for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:31:23 -0500 Received: from [2607:f8b0:4864:20::42b] (port=44785 helo=mail-pf1-x42b.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSH0o-0008TU-Op for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:31:20 -0500 Received: by mail-pf1-x42b.google.com with SMTP id u17so2670152pfk.11 for ; Thu, 10 Mar 2022 03:31:18 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id e14-20020a056a001a8e00b004f75cf1ab6csm6011246pfv.206.2022.03.10.03.31.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:31:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Jku9bPh0YVOaP+OMjPsiDbVlpEa9BNiPKSyQ8r6I0fM=; b=DokEgmWacpFOEZFsBX84n8leKjhyCAeXfXd8wT/xpzawETwDokEOGB/2nxAUBaZ1sO rD1DsqJl95gA5EQrwD9mqVL16t747aFpfkHaMa1Iaksf7xt/a4lQf6VxCQk/Qb/LpN3G 9pDtyXK7qByXXe6LWm6k/YVcsWOA4SKNWh4ODM/FaQhA5l9hq/tOT3aU44Si3MLZmFmG B8Vlpkjsx19IvdyymsRD3eRFnVTNHGJUE0MrGcBK6lBZowihDOo1mjdb3blCXi+vwRr4 3hWOdHPjZkPN4KkAIZpJi5UuLoLx6Jx2S+6ezYN9OjJRiqbVPtd5UOwgVw7WyvzT/Dpk XtMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Jku9bPh0YVOaP+OMjPsiDbVlpEa9BNiPKSyQ8r6I0fM=; b=O9M5Pv74G8jXoR+roUV9e06qIf296G9YdZF+3yIajCdUGDqkwr9c/RLAniwJ9Mn/ks bSxj9Q+BesFG8yiv/BcKPcr9tmnevlB7BxSD5eNejYhAFOEwlJ/FOCw1ECZ0gN+IMVJB m0x6Sg9KStL+efTSDJt3uEnuAh2Qu2aykHFNmlwL03s85FEO0poN5dh5hX+fB0uHi2gO Q8HAclmGOE1nQY6JejODVN4mP7phlA0fvB2hK8RhdDDLP0Dl1btcCiIJmqsYhjMzmHyz w+Pu+vMwFThsjprbeMOGJMM4LSy+e7LXUIx/fZhGgSRhgnYTrt+wn+VFoeJ9iig8oIkL ceIQ== X-Gm-Message-State: AOAM531u3NT93AqCT2dDz+P7NZ2ilN0YDgQuyWH/bDz6Kpf7nFKHT3Ug ZvcMISkW4tCVKuN+tuwgtLBjPTAH4S8/kg== X-Google-Smtp-Source: ABdhPJyZwOOFEDwTcHQtHU5XzDHO8QeScKwqGlGEHYBn2ESJ3IjraMj583RmJVhgCmjNfcBRwcD0Ng== X-Received: by 2002:a62:8481:0:b0:4f7:4d4:f592 with SMTP id k123-20020a628481000000b004f704d4f592mr4484057pfd.3.1646911877472; Thu, 10 Mar 2022 03:31:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 44/48] target/nios2: Implement EIC interrupt processing Date: Thu, 10 Mar 2022 03:27:21 -0800 Message-Id: <20220310112725.570053-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42b (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646912891068100001 Content-Type: text/plain; charset="utf-8" This is the cpu side of the operation. Register one irq line, called EIC. Split out the rather different processing to a separate function. Delay initialization of gpio irqs until realize. We need to provide a window after init in which the board can set eic_present. Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 8 ++++ target/nios2/cpu.c | 92 +++++++++++++++++++++++++++++++++---------- target/nios2/helper.c | 47 ++++++++++++++++++++-- 3 files changed, 123 insertions(+), 24 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 62a73c7b32..c9356416e2 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -114,6 +114,7 @@ FIELD(CR_STATUS, CRS, 10, 6) FIELD(CR_STATUS, PRS, 16, 6) FIELD(CR_STATUS, NMI, 22, 1) FIELD(CR_STATUS, RSIE, 23, 1) +FIELD(CR_STATUS, SRS, 31, 1) /* only in sstatus */ =20 #define CR_STATUS_PIE R_CR_STATUS_PIE_MASK #define CR_STATUS_U R_CR_STATUS_U_MASK @@ -121,6 +122,7 @@ FIELD(CR_STATUS, RSIE, 23, 1) #define CR_STATUS_IH R_CR_STATUS_IH_MASK #define CR_STATUS_NMI R_CR_STATUS_NMI_MASK #define CR_STATUS_RSIE R_CR_STATUS_RSIE_MASK +#define CR_STATUS_SRS R_CR_STATUS_SRS_MASK =20 FIELD(CR_EXCEPTION, CAUSE, 2, 5) FIELD(CR_EXCEPTION, ECCFTL, 31, 1) @@ -234,6 +236,12 @@ struct ArchCPU { =20 /* Bits within each control register which are reserved or readonly. */ ControlRegState cr_state[NUM_CR_REGS]; + + /* External Interrupt Controller Interface */ + uint32_t rha; /* Requested handler address */ + uint32_t ril; /* Requested interrupt level */ + uint32_t rrs; /* Requested register set */ + bool rnmi; /* Requested nonmaskable interrupt */ }; =20 =20 diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index efd6a21a8e..c5025d32f4 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -67,7 +67,19 @@ static void nios2_cpu_reset(DeviceState *dev) } =20 #ifndef CONFIG_USER_ONLY -static void nios2_cpu_set_irq(void *opaque, int irq, int level) +static void eic_set_irq(void *opaque, int irq, int level) +{ + Nios2CPU *cpu =3D opaque; + CPUState *cs =3D CPU(cpu); + + if (level) { + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } +} + +static void iic_set_irq(void *opaque, int irq, int level) { Nios2CPU *cpu =3D opaque; CPUNios2State *env =3D &cpu->env; @@ -109,10 +121,18 @@ static void nios2_cpu_initfn(Object *obj) RO_REG(CR_EXCEPTION); WR_REG(CR_BADADDR); =20 - /* TODO: These control registers are not present with the EIC. */ - RO_FIELD(CR_STATUS, RSIE); - WR_REG(CR_IENABLE); - RO_REG(CR_IPENDING); + if (cpu->eic_present) { + WR_FIELD(CR_STATUS, RSIE); + RO_FIELD(CR_STATUS, NMI); + WR_FIELD(CR_STATUS, PRS); + RO_FIELD(CR_STATUS, CRS); + WR_FIELD(CR_STATUS, IL); + WR_FIELD(CR_STATUS, IH); + } else { + RO_FIELD(CR_STATUS, RSIE); + WR_REG(CR_IENABLE); + RO_REG(CR_IPENDING); + } =20 if (cpu->mmu_present) { WR_FIELD(CR_STATUS, U); @@ -145,15 +165,6 @@ static void nios2_cpu_initfn(Object *obj) =20 #if !defined(CONFIG_USER_ONLY) mmu_init(&cpu->env); - - /* - * These interrupt lines model the IIC (internal interrupt - * controller). QEMU does not currently support the EIC - * (external interrupt controller) -- if we did it would be - * a separate device in hw/intc with a custom interface to - * the CPU, and boards using it would not wire up these IRQ lines. - */ - qdev_init_gpio_in_named(DEVICE(cpu), nios2_cpu_set_irq, "IRQ", 32); #endif } =20 @@ -169,6 +180,14 @@ static void nios2_cpu_realizefn(DeviceState *dev, Erro= r **errp) Nios2CPUClass *ncc =3D NIOS2_CPU_GET_CLASS(dev); Error *local_err =3D NULL; =20 +#ifndef CONFIG_USER_ONLY + if (cpu->eic_present) { + qdev_init_gpio_in_named(DEVICE(cpu), eic_set_irq, "EIC", 1); + } else { + qdev_init_gpio_in_named(DEVICE(cpu), iic_set_irq, "IRQ", 32); + } +#endif + cpu_exec_realizefn(cs, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); @@ -185,17 +204,48 @@ static void nios2_cpu_realizefn(DeviceState *dev, Err= or **errp) } =20 #ifndef CONFIG_USER_ONLY +static bool eic_take_interrupt(Nios2CPU *cpu) +{ + CPUNios2State *env =3D &cpu->env; + const uint32_t status =3D env->ctrl[CR_STATUS]; + + if (cpu->rnmi) { + return !(status & CR_STATUS_NMI); + } + if (!(status & CR_STATUS_PIE)) { + return false; + } + if (cpu->ril <=3D FIELD_EX32(status, CR_STATUS, IL)) { + return false; + } + if (cpu->rrs !=3D FIELD_EX32(status, CR_STATUS, CRS)) { + return true; + } + return status & CR_STATUS_RSIE; +} + +static bool iic_take_interrupt(Nios2CPU *cpu) +{ + CPUNios2State *env =3D &cpu->env; + + if (!(env->ctrl[CR_STATUS] & CR_STATUS_PIE)) { + return false; + } + return env->ctrl[CR_IPENDING] & env->ctrl[CR_IENABLE]; +} + static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { Nios2CPU *cpu =3D NIOS2_CPU(cs); - CPUNios2State *env =3D &cpu->env; =20 - if ((interrupt_request & CPU_INTERRUPT_HARD) && - (env->ctrl[CR_STATUS] & CR_STATUS_PIE) && - (env->ctrl[CR_IPENDING] & env->ctrl[CR_IENABLE])) { - cs->exception_index =3D EXCP_IRQ; - nios2_cpu_do_interrupt(cs); - return true; + if (interrupt_request & CPU_INTERRUPT_HARD) { + if (cpu->eic_present + ? eic_take_interrupt(cpu) + : iic_take_interrupt(cpu)) { + cs->exception_index =3D EXCP_IRQ; + nios2_cpu_do_interrupt(cs); + return true; + } } return false; } diff --git a/target/nios2/helper.c b/target/nios2/helper.c index bf40cff779..00f27165d9 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -57,6 +57,9 @@ static void do_exception(Nios2CPU *cpu, uint32_t exceptio= n_addr, uint32_t old_status =3D env->ctrl[CR_STATUS]; uint32_t new_status =3D old_status; =20 + /* With shadow regs, exceptions are always taken into CRS 0. */ + new_status &=3D ~R_CR_STATUS_CRS_MASK; + if ((old_status & CR_STATUS_EH) =3D=3D 0) { int r_ea =3D R_EA, cr_es =3D CR_ESTATUS; =20 @@ -65,7 +68,7 @@ static void do_exception(Nios2CPU *cpu, uint32_t exceptio= n_addr, cr_es =3D CR_BSTATUS; } env->ctrl[cr_es] =3D old_status; - env->regs[r_ea] =3D env->pc + 4; + env->shadow_regs[0][r_ea] =3D env->pc + 4; =20 if (cpu->mmu_present) { new_status |=3D CR_STATUS_EH; @@ -83,8 +86,9 @@ static void do_exception(Nios2CPU *cpu, uint32_t exceptio= n_addr, } =20 new_status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); - env->ctrl[CR_STATUS] =3D new_status; + nios2_update_crs(env); + if (!is_break) { env->ctrl[CR_EXCEPTION] =3D FIELD_DP32(0, CR_EXCEPTION, CAUSE, cs->exception_index); @@ -97,6 +101,39 @@ static void do_iic_irq(Nios2CPU *cpu) do_exception(cpu, cpu->exception_addr, 0, false); } =20 +static void do_eic_irq(Nios2CPU *cpu) +{ + CPUNios2State *env =3D &cpu->env; + uint32_t old_status =3D env->ctrl[CR_STATUS]; + uint32_t new_status =3D old_status; + uint32_t old_rs =3D FIELD_EX32(old_status, CR_STATUS, CRS); + uint32_t new_rs =3D cpu->rrs; + + new_status =3D FIELD_DP32(new_status, CR_STATUS, CRS, new_rs); + new_status =3D FIELD_DP32(new_status, CR_STATUS, IL, cpu->ril); + new_status =3D FIELD_DP32(new_status, CR_STATUS, NMI, cpu->rnmi); + new_status &=3D ~(CR_STATUS_RSIE | CR_STATUS_U); + new_status |=3D CR_STATUS_IH; + + if (!(new_status & CR_STATUS_EH)) { + new_status =3D FIELD_DP32(new_status, CR_STATUS, PRS, old_rs); + if (new_rs =3D=3D 0) { + env->ctrl[CR_ESTATUS] =3D old_status; + } else { + if (new_rs !=3D old_rs) { + old_status |=3D CR_STATUS_SRS; + } + env->shadow_regs[new_rs][R_SSTATUS] =3D old_status; + } + env->shadow_regs[new_rs][R_EA] =3D env->pc + 4; + } + + env->ctrl[CR_STATUS] =3D new_status; + nios2_update_crs(env); + + env->pc =3D cpu->rha; +} + void nios2_cpu_do_interrupt(CPUState *cs) { Nios2CPU *cpu =3D NIOS2_CPU(cs); @@ -162,7 +199,11 @@ void nios2_cpu_do_interrupt(CPUState *cs) =20 switch (cs->exception_index) { case EXCP_IRQ: - do_iic_irq(cpu); + if (cpu->eic_present) { + do_eic_irq(cpu); + } else { + do_iic_irq(cpu); + } break; =20 case EXCP_TLB_D: --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646913090540609.8820228264775; Thu, 10 Mar 2022 03:51:30 -0800 (PST) Received: from localhost ([::1]:50852 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHKL-0005cO-BG for importer@patchew.org; Thu, 10 Mar 2022 06:51:29 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51840) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSH0s-0002X5-Pt for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:31:23 -0500 Received: from [2607:f8b0:4864:20::102f] (port=40786 helo=mail-pj1-x102f.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSH0q-0008Tg-6t for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:31:22 -0500 Received: by mail-pj1-x102f.google.com with SMTP id mv5-20020a17090b198500b001bf2a039831so7931459pjb.5 for ; Thu, 10 Mar 2022 03:31:19 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id e14-20020a056a001a8e00b004f75cf1ab6csm6011246pfv.206.2022.03.10.03.31.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:31:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Oq3+WovLC1U0SsWCHamcVpyHHoEeCG/N4mUqpqq0Etc=; b=Q+j1LZaUt5kCKClYxVzBJDlvY057auBmkhZ7pSSOGEZfb0XlhiZwg4uAxYZV9dqe9j pojytAhUgqniYs8dccZs7VRoA/a2U2+j2vJqRyi1EzOFJl6YkFLb87iDORfcZ05jEWPX U2G3nsHckRbGfQ+RwzEoNJtUWNt6oV1lkMEOthC+eRSM7mdCzRicbMK57mRJcMPnUrtc yI5INGtp8qkJrIcF3gOhR7bQi8Fow4AlWdLXqTAVY2VzV23AZxQMlg613N9peKGoTTur Ttd7vAjU5nBgpi+ljox8+ZqtIzS9esWzHehYbAJ+iRB2lEULzN3sh1g3oWP5b2PT5iB9 YJMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Oq3+WovLC1U0SsWCHamcVpyHHoEeCG/N4mUqpqq0Etc=; b=TEdjcqbk5rwSdzDIApO3zMzl+NuJTxrv75RpTE3r4HNWbu0rOmUxnB92ezdsSp0vZ1 1TkbrkOvxE6opqqT/RhdErFLIs20kywgPzlolXSf5sjyus+XPsQeorjQhU9ktHi+rpM9 17b2rB4Nr4XrCN8vBm7+YESGqqgcaT9ztdAKBJsD6yYWgcSehOY1cA0/opGEwVMu3m5H K21EyJtOYnLw9A6XfyNnsMOxGlGN+RYj8otrRHsgmgTkqfN4oKjFJxygNFDG/7yz0zDq uoKfoW483nPIwnZom56kO+00wzAp+AHo63wDFgPrQXPg1ACrXzwHC896eOTEFr2CcvNi fM9g== X-Gm-Message-State: AOAM5302LijbAoCZHLg3Ow0bqcq2Kdb6KPwwUdomaOeJ4qPQRpsCuiUd 2dhGcmuu7srPNMPy8V6nP/Um5dSvHiRW0g== X-Google-Smtp-Source: ABdhPJxN+CJiw16utCrn/aLnSD6NBWUuYQohIva+f73ExldxDLXq1my1Wn9kfQ5SXJRkJURUMeFWng== X-Received: by 2002:a17:90a:4749:b0:1be:ea64:4348 with SMTP id y9-20020a17090a474900b001beea644348mr15386292pjg.231.1646911878786; Thu, 10 Mar 2022 03:31:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 45/48] hw/intc: Vectored Interrupt Controller (VIC) Date: Thu, 10 Mar 2022 03:27:22 -0800 Message-Id: <20220310112725.570053-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102f (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646913091177100003 From: Amir Gonnen Implement nios2 Vectored Interrupt Controller (VIC). VIC is connected to EIC. It needs to update rha, ril, rrs and rnmi fields on Nios2CPU before raising an IRQ. For that purpose, VIC has a "cpu" property which should refer to the nios2 cpu and set by the board that connects VIC. Reviewed-by: Peter Maydell Signed-off-by: Amir Gonnen Message-Id: <20220303153906.2024748-5-amir.gonnen@neuroblade.ai> [rth: Split out nios2_vic.h] Signed-off-by: Richard Henderson --- include/hw/intc/nios2_vic.h | 64 ++++++++ hw/intc/nios2_vic.c | 313 ++++++++++++++++++++++++++++++++++++ hw/intc/Kconfig | 3 + hw/intc/meson.build | 1 + 4 files changed, 381 insertions(+) create mode 100644 include/hw/intc/nios2_vic.h create mode 100644 hw/intc/nios2_vic.c diff --git a/include/hw/intc/nios2_vic.h b/include/hw/intc/nios2_vic.h new file mode 100644 index 0000000000..af1517a967 --- /dev/null +++ b/include/hw/intc/nios2_vic.h @@ -0,0 +1,64 @@ +/* + * Vectored Interrupt Controller for nios2 processor + * + * Copyright (c) 2022 Neuroblade + * + * Interface: + * QOM property "cpu": link to the Nios2 CPU (must be set) + * Unnamed GPIO inputs 0..NIOS2_VIC_MAX_IRQ-1: input IRQ lines + * IRQ should be connected to nios2 IRQ0. + * + * Reference: "Embedded Peripherals IP User Guide + * for Intel=C2=AE Quartus=C2=AE Prime Design Suite: 21.4" + * Chapter 38 "Vectored Interrupt Controller Core" + * See: https://www.intel.com/content/www/us/en/docs/programmable/683130/2= 1-4/vectored-interrupt-controller-core.html + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#ifndef HW_INTC_NIOS2_VIC +#define HW_INTC_NIOS2_VIC + +#define TYPE_NIOS2_VIC "nios2-vic" +OBJECT_DECLARE_SIMPLE_TYPE(Nios2VIC, NIOS2_VIC) + +#define NIOS2_VIC_MAX_IRQ 32 + +struct Nios2VIC { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + qemu_irq output_int; + + /* properties */ + CPUState *cpu; + MemoryRegion csr; + + uint32_t int_config[NIOS2_VIC_MAX_IRQ]; + uint32_t vic_config; + uint32_t int_raw_status; + uint32_t int_enable; + uint32_t sw_int; + uint32_t vic_status; + uint32_t vec_tbl_base; + uint32_t vec_tbl_addr; +}; + +#endif /* HW_INTC_NIOS2_VIC */ diff --git a/hw/intc/nios2_vic.c b/hw/intc/nios2_vic.c new file mode 100644 index 0000000000..cf63212a88 --- /dev/null +++ b/hw/intc/nios2_vic.c @@ -0,0 +1,313 @@ +/* + * Vectored Interrupt Controller for nios2 processor + * + * Copyright (c) 2022 Neuroblade + * + * Interface: + * QOM property "cpu": link to the Nios2 CPU (must be set) + * Unnamed GPIO inputs 0..NIOS2_VIC_MAX_IRQ-1: input IRQ lines + * IRQ should be connected to nios2 IRQ0. + * + * Reference: "Embedded Peripherals IP User Guide + * for Intel=C2=AE Quartus=C2=AE Prime Design Suite: 21.4" + * Chapter 38 "Vectored Interrupt Controller Core" + * See: https://www.intel.com/content/www/us/en/docs/programmable/683130/2= 1-4/vectored-interrupt-controller-core.html + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" + +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "qapi/error.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qom/object.h" +#include "hw/intc/nios2_vic.h" +#include "cpu.h" + + +enum { + INT_CONFIG0 =3D 0, + INT_CONFIG31 =3D 31, + INT_ENABLE =3D 32, + INT_ENABLE_SET =3D 33, + INT_ENABLE_CLR =3D 34, + INT_PENDING =3D 35, + INT_RAW_STATUS =3D 36, + SW_INTERRUPT =3D 37, + SW_INTERRUPT_SET =3D 38, + SW_INTERRUPT_CLR =3D 39, + VIC_CONFIG =3D 40, + VIC_STATUS =3D 41, + VEC_TBL_BASE =3D 42, + VEC_TBL_ADDR =3D 43, + CSR_COUNT /* Last! */ +}; + +/* Requested interrupt level (INT_CONFIG[0:5]) */ +static inline uint32_t vic_int_config_ril(const Nios2VIC *vic, int irq_num) +{ + return extract32(vic->int_config[irq_num], 0, 6); +} + +/* Requested NMI (INT_CONFIG[6]) */ +static inline uint32_t vic_int_config_rnmi(const Nios2VIC *vic, int irq_nu= m) +{ + return extract32(vic->int_config[irq_num], 6, 1); +} + +/* Requested register set (INT_CONFIG[7:12]) */ +static inline uint32_t vic_int_config_rrs(const Nios2VIC *vic, int irq_num) +{ + return extract32(vic->int_config[irq_num], 7, 6); +} + +static inline uint32_t vic_config_vec_size(const Nios2VIC *vic) +{ + return 1 << (2 + extract32(vic->vic_config, 0, 3)); +} + +static inline uint32_t vic_int_pending(const Nios2VIC *vic) +{ + return (vic->int_raw_status | vic->sw_int) & vic->int_enable; +} + +static void vic_update_irq(Nios2VIC *vic) +{ + Nios2CPU *cpu =3D NIOS2_CPU(vic->cpu); + uint32_t pending =3D vic_int_pending(vic); + int irq =3D -1; + int max_ril =3D 0; + /* Note that if RIL is 0 for an interrupt it is effectively disabled */ + + vic->vec_tbl_addr =3D 0; + vic->vic_status =3D 0; + + if (pending =3D=3D 0) { + qemu_irq_lower(vic->output_int); + return; + } + + for (int i =3D 0; i < NIOS2_VIC_MAX_IRQ; i++) { + if (pending & BIT(i)) { + int ril =3D vic_int_config_ril(vic, i); + if (ril > max_ril) { + irq =3D i; + max_ril =3D ril; + } + } + } + + if (irq < 0) { + qemu_irq_lower(vic->output_int); + return; + } + + vic->vec_tbl_addr =3D irq * vic_config_vec_size(vic) + vic->vec_tbl_ba= se; + vic->vic_status =3D irq | BIT(31); + + /* + * In hardware, the interface between the VIC and the CPU is via the + * External Interrupt Controller interface, where the interrupt contro= ller + * presents the CPU with a packet of data containing: + * - Requested Handler Address (RHA): 32 bits + * - Requested Register Set (RRS) : 6 bits + * - Requested Interrupt Level (RIL) : 6 bits + * - Requested NMI flag (RNMI) : 1 bit + * In our emulation, we implement this by writing the data directly to + * fields in the CPU object and then raising the IRQ line to tell + * the CPU that we've done so. + */ + + cpu->rha =3D vic->vec_tbl_addr; + cpu->ril =3D max_ril; + cpu->rrs =3D vic_int_config_rrs(vic, irq); + cpu->rnmi =3D vic_int_config_rnmi(vic, irq); + + qemu_irq_raise(vic->output_int); +} + +static void vic_set_irq(void *opaque, int irq_num, int level) +{ + Nios2VIC *vic =3D opaque; + + vic->int_raw_status =3D deposit32(vic->int_raw_status, irq_num, 1, !!l= evel); + vic_update_irq(vic); +} + +static void nios2_vic_reset(DeviceState *dev) +{ + Nios2VIC *vic =3D NIOS2_VIC(dev); + + memset(&vic->int_config, 0, sizeof(vic->int_config)); + vic->vic_config =3D 0; + vic->int_raw_status =3D 0; + vic->int_enable =3D 0; + vic->sw_int =3D 0; + vic->vic_status =3D 0; + vic->vec_tbl_base =3D 0; + vic->vec_tbl_addr =3D 0; +} + +static uint64_t nios2_vic_csr_read(void *opaque, hwaddr offset, unsigned s= ize) +{ + Nios2VIC *vic =3D opaque; + int index =3D offset / 4; + + switch (index) { + case INT_CONFIG0 ... INT_CONFIG31: + return vic->int_config[index - INT_CONFIG0]; + case INT_ENABLE: + return vic->int_enable; + case INT_PENDING: + return vic_int_pending(vic); + case INT_RAW_STATUS: + return vic->int_raw_status; + case SW_INTERRUPT: + return vic->sw_int; + case VIC_CONFIG: + return vic->vic_config; + case VIC_STATUS: + return vic->vic_status; + case VEC_TBL_BASE: + return vic->vec_tbl_base; + case VEC_TBL_ADDR: + return vic->vec_tbl_addr; + default: + return 0; + } +} + +static void nios2_vic_csr_write(void *opaque, hwaddr offset, uint64_t valu= e, + unsigned size) +{ + Nios2VIC *vic =3D opaque; + int index =3D offset / 4; + + switch (index) { + case INT_CONFIG0 ... INT_CONFIG31: + vic->int_config[index - INT_CONFIG0] =3D value; + break; + case INT_ENABLE: + vic->int_enable =3D value; + break; + case INT_ENABLE_SET: + vic->int_enable |=3D value; + break; + case INT_ENABLE_CLR: + vic->int_enable &=3D ~value; + break; + case SW_INTERRUPT: + vic->sw_int =3D value; + break; + case SW_INTERRUPT_SET: + vic->sw_int |=3D value; + break; + case SW_INTERRUPT_CLR: + vic->sw_int &=3D ~value; + break; + case VIC_CONFIG: + vic->vic_config =3D value; + break; + case VEC_TBL_BASE: + vic->vec_tbl_base =3D value; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "nios2-vic: write to invalid CSR address %#" + HWADDR_PRIx "\n", offset); + } + + vic_update_irq(vic); +} + +static const MemoryRegionOps nios2_vic_csr_ops =3D { + .read =3D nios2_vic_csr_read, + .write =3D nios2_vic_csr_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4 } +}; + +static void nios2_vic_realize(DeviceState *dev, Error **errp) +{ + Nios2VIC *vic =3D NIOS2_VIC(dev); + + if (!vic->cpu) { + /* This is a programming error in the code using this device */ + error_setg(errp, "nios2-vic 'cpu' link property was not set"); + return; + } + + sysbus_init_irq(SYS_BUS_DEVICE(dev), &vic->output_int); + qdev_init_gpio_in(dev, vic_set_irq, NIOS2_VIC_MAX_IRQ); + + memory_region_init_io(&vic->csr, OBJECT(dev), &nios2_vic_csr_ops, vic, + "nios2.vic.csr", CSR_COUNT * sizeof(uint32_t)); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &vic->csr); +} + +static Property nios2_vic_properties[] =3D { + DEFINE_PROP_LINK("cpu", Nios2VIC, cpu, TYPE_CPU, CPUState *), + DEFINE_PROP_END_OF_LIST() +}; + +static const VMStateDescription nios2_vic_vmstate =3D { + .name =3D "nios2-vic", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]){ + VMSTATE_UINT32_ARRAY(int_config, Nios2VIC, 32), + VMSTATE_UINT32(vic_config, Nios2VIC), + VMSTATE_UINT32(int_raw_status, Nios2VIC), + VMSTATE_UINT32(int_enable, Nios2VIC), + VMSTATE_UINT32(sw_int, Nios2VIC), + VMSTATE_UINT32(vic_status, Nios2VIC), + VMSTATE_UINT32(vec_tbl_base, Nios2VIC), + VMSTATE_UINT32(vec_tbl_addr, Nios2VIC), + VMSTATE_END_OF_LIST() + }, +}; + +static void nios2_vic_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->reset =3D nios2_vic_reset; + dc->realize =3D nios2_vic_realize; + dc->vmsd =3D &nios2_vic_vmstate; + device_class_set_props(dc, nios2_vic_properties); +} + +static const TypeInfo nios2_vic_info =3D { + .name =3D TYPE_NIOS2_VIC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(Nios2VIC), + .class_init =3D nios2_vic_class_init, +}; + +static void nios2_vic_register_types(void) +{ + type_register_static(&nios2_vic_info); +} + +type_init(nios2_vic_register_types); diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index ec8d4cec29..eeb2d6f428 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -84,3 +84,6 @@ config GOLDFISH_PIC =20 config M68K_IRQC bool + +config NIOS2_VIC + bool diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 81ccdb0d78..167755ac64 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -62,3 +62,4 @@ specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'], if_true: files('spapr_xive_kvm.c')) specific_ss.add(when: 'CONFIG_GOLDFISH_PIC', if_true: files('goldfish_pic.= c')) specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c')) +specific_ss.add(when: 'CONFIG_NIOS2_VIC', if_true: files('nios2_vic.c')) --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646915867250384.1239005694813; Thu, 10 Mar 2022 04:37:47 -0800 (PST) Received: from localhost ([::1]:41250 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSI38-0002kR-5K for importer@patchew.org; Thu, 10 Mar 2022 07:37:46 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51846) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSH0t-0002X7-5n for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:31:23 -0500 Received: from [2607:f8b0:4864:20::102d] (port=55228 helo=mail-pj1-x102d.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSH0r-0008Ty-FR for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:31:22 -0500 Received: by mail-pj1-x102d.google.com with SMTP id b8so4954376pjb.4 for ; Thu, 10 Mar 2022 03:31:21 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id e14-20020a056a001a8e00b004f75cf1ab6csm6011246pfv.206.2022.03.10.03.31.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:31:19 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=v1XH3xOuF9Qfk4MizuEs6gkvLNvCljLe8Yi99oh17Cc=; b=wbkYzWORkFfhf9aL67Y6p1aACPbx+KFgYsOMUAm/Uk9oOmbXj9XxAxGLIpOlhOg4AD fn9pu65rRH+XWKqrzE9YQhSFYMC56hgR+Hc51r9GQrRTNaKk64hIva3JZ6m4UJeZTuTE h+ajaV1hnSrhBOZLCnbfRYhmJseXWv4FWL6M3vvJGBN9QJoLYxnZThTJLoYY0jQojqS1 MX3SF2MsX35xTyFO4VQX7oag5I/Q3g+sD3+3JCu0cG8nj/i6+qdE1Tfg6j7CpyGsz0ym anFkhHIdW47/GYZ91l9CwYtTV+50AcnYLVZkO+TS8izugjJKkaomNkhQHEGA7NSRCgq7 eLSQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v1XH3xOuF9Qfk4MizuEs6gkvLNvCljLe8Yi99oh17Cc=; b=olRZF9/mzCPqXuSpkSAi33u0nEaF+TDHJi4N/yJqe1h+dUOnvCcSmJI8q4wGIIWJDG bN3/kn9SOy8arIvKr0YYtkLC6vaxnckqxW6tJ+dptHqvBhjKnHNKXYTcfjJGWImlRLyP xmz7kmGKZ+QmolW0BNg+JBSMVh0TwpheWFhRrgs0cOSJ2qE+gTKd5P3L5pG8385IDoO3 kcboH0raI3irujMoBbR0vJ1XEl8BTjOJqjIkeHckSfFTBwRZ/hSJ+Q0zBCR/2GzmfXyb a7w6ZXCpcjVhDg/A84mo+cKDdbAkumwcyBmIJYmsxx4TuoJYh24kN6noXjmO793FPCuJ qVzA== X-Gm-Message-State: AOAM532Tx9OE3n5fUxQMF4NCcSIkF1/RYFXe1ZdKIMS03iJl+vwbjDMz 4NpBJIStr15/+jOPSERPBObV9njVUUupDw== X-Google-Smtp-Source: ABdhPJzNwmqdCY6sXmQ3ODhbBWB7XA0Oz6PbpMO1ZEfOyBnMAB8oAwSPiv5XR9CPJEUzQEl8d4uDkQ== X-Received: by 2002:a17:90a:2dc6:b0:1bf:654e:e17f with SMTP id q6-20020a17090a2dc600b001bf654ee17fmr4511869pjm.64.1646911880118; Thu, 10 Mar 2022 03:31:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 46/48] hw/nios2: Introduce Nios2MachineState Date: Thu, 10 Mar 2022 03:27:23 -0800 Message-Id: <20220310112725.570053-47-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102d (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646915868655100001 Content-Type: text/plain; charset="utf-8" We want to move data from the heap into Nios2MachineState, which is not possible with DEFINE_MACHINE. Signed-off-by: Richard Henderson Reviewed-by: Mark Cave-Ayland --- hw/nios2/10m50_devboard.c | 24 ++++++++++++++++++++++-- 1 file changed, 22 insertions(+), 2 deletions(-) diff --git a/hw/nios2/10m50_devboard.c b/hw/nios2/10m50_devboard.c index 3d1205b8bd..bdc3ffd50d 100644 --- a/hw/nios2/10m50_devboard.c +++ b/hw/nios2/10m50_devboard.c @@ -36,6 +36,13 @@ =20 #include "boot.h" =20 +struct Nios2MachineState { + MachineState parent_obj; +}; + +#define TYPE_NIOS2_MACHINE MACHINE_TYPE_NAME("10m50-ghrd") +OBJECT_DECLARE_TYPE(Nios2MachineState, MachineClass, NIOS2_MACHINE) + #define BINARY_DEVICE_TREE_FILE "10m50-devboard.dtb" =20 static void nios2_10m50_ghrd_init(MachineState *machine) @@ -105,11 +112,24 @@ static void nios2_10m50_ghrd_init(MachineState *machi= ne) BINARY_DEVICE_TREE_FILE, NULL); } =20 -static void nios2_10m50_ghrd_machine_init(struct MachineClass *mc) +static void nios2_10m50_ghrd_class_init(ObjectClass *oc, void *data) { + MachineClass *mc =3D MACHINE_CLASS(oc); + mc->desc =3D "Altera 10M50 GHRD Nios II design"; mc->init =3D nios2_10m50_ghrd_init; mc->is_default =3D true; } =20 -DEFINE_MACHINE("10m50-ghrd", nios2_10m50_ghrd_machine_init); +static const TypeInfo nios2_10m50_ghrd_type_info =3D { + .name =3D TYPE_NIOS2_MACHINE, + .parent =3D TYPE_MACHINE, + .instance_size =3D sizeof(Nios2MachineState), + .class_init =3D nios2_10m50_ghrd_class_init, +}; + +static void nios2_10m50_ghrd_type_init(void) +{ + type_register_static(&nios2_10m50_ghrd_type_info); +} +type_init(nios2_10m50_ghrd_type_init); --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646913192439623.1067441982807; Thu, 10 Mar 2022 03:53:12 -0800 (PST) Received: from localhost ([::1]:59168 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHLz-0002uD-6m for importer@patchew.org; Thu, 10 Mar 2022 06:53:11 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51860) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSH0u-0002Y2-9p for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:31:25 -0500 Received: from [2607:f8b0:4864:20::533] (port=42570 helo=mail-pg1-x533.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSH0s-0008U2-Hs for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:31:23 -0500 Received: by mail-pg1-x533.google.com with SMTP id o8so4487759pgf.9 for ; Thu, 10 Mar 2022 03:31:22 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id e14-20020a056a001a8e00b004f75cf1ab6csm6011246pfv.206.2022.03.10.03.31.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:31:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=k4ozRW6iziM8OJ2TKPPCOH7wy/AQ7zg7VeU+iBKaQYA=; b=j4lwk9V1TdTmTDoAFxfTNgp6AGeLFbXKuUZn5R82+4y+UIvpqL8WKEhFQIFWVF2a3v z281tf0lirswi4TUjXIuaIcRbFAGMzAFZBfIz216ffOtl9GfLFkgRWqpEupCapbWtPWZ +hWZQN95ZDYQQO0jG6/Cc7p3RaGt0G7887ylQxiKIQg9zFCrLrv0NvDh0D56/CPo/tYO jPORA0m5XmtK7a/FRLSoFssWQ0eEvJEwWlycIMbYbkbG/Bk40VloOpHjvPnVo8xYBt1n edIo4xlUxPOc8OLZs7c9506TWnFn5vEIFYAqB7uCK5j/vPrMmZ+VZjWTulBqQ0jm5LCj 1xqQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=k4ozRW6iziM8OJ2TKPPCOH7wy/AQ7zg7VeU+iBKaQYA=; b=WbW9u729+EoNojWIYx+e57D7sSR1/tWGayxr0bPEGLR2RKfKaAaVSdHtReMF4aCAKI 7NX8HHCicHV+0vhjC+uLQ4oKuPGopzUo+3bJuxgiNLGes034crPZKxOA7T0p8VaRTP+9 2dJpEDxFx26sS1fELPB9vckf0DGkureqR1PO/tRAUVDSo6K/yScVetsCWnuTzdBf/Pcs UwtV+jGEh13QM7r+STnVMQs/zubIYr63m7hyL4XHUHdjn/DRaVGjJhO+E/TGb+87hyP4 v+oc2AJ48CNSxOwropL34LL3z1nqT/edfP/IHz4OTLVlGf4jmAmHnPaGWemOo0c2Vws4 LddA== X-Gm-Message-State: AOAM530CIBGtNT+8iUbJ3H0vJg61NS/OjXAo5Ql5dTfZZeBTlN2yqM9G Hlxp7IP5vrTDf1FxesB5ocO6RAJx2sbiBw== X-Google-Smtp-Source: ABdhPJxL2RAZxl70B5/iDO4JeTn9MTW52OvI7IOl1Szq9bLJ5VC54FSzvvlrNrveWLmer9VnKSAXhA== X-Received: by 2002:a62:30c4:0:b0:4f7:2b29:984 with SMTP id w187-20020a6230c4000000b004f72b290984mr4597010pfw.11.1646911881286; Thu, 10 Mar 2022 03:31:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 47/48] hw/nios2: Move memory regions into Nios2Machine Date: Thu, 10 Mar 2022 03:27:24 -0800 Message-Id: <20220310112725.570053-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::533 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai, Mark Cave-Ayland Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646913194824100001 Content-Type: text/plain; charset="utf-8" Convert to contiguous allocation, as much as possible so far. The two timer objects are not exposed for subobject allocation. Reviewed-by: Mark Cave-Ayland Signed-off-by: Richard Henderson --- hw/nios2/10m50_devboard.c | 30 ++++++++++++++++-------------- 1 file changed, 16 insertions(+), 14 deletions(-) diff --git a/hw/nios2/10m50_devboard.c b/hw/nios2/10m50_devboard.c index bdc3ffd50d..dda4ab2bf5 100644 --- a/hw/nios2/10m50_devboard.c +++ b/hw/nios2/10m50_devboard.c @@ -38,6 +38,11 @@ =20 struct Nios2MachineState { MachineState parent_obj; + + MemoryRegion phys_tcm; + MemoryRegion phys_tcm_alias; + MemoryRegion phys_ram; + MemoryRegion phys_ram_alias; }; =20 #define TYPE_NIOS2_MACHINE MACHINE_TYPE_NAME("10m50-ghrd") @@ -47,13 +52,10 @@ OBJECT_DECLARE_TYPE(Nios2MachineState, MachineClass, NI= OS2_MACHINE) =20 static void nios2_10m50_ghrd_init(MachineState *machine) { + Nios2MachineState *nms =3D NIOS2_MACHINE(machine); Nios2CPU *cpu; DeviceState *dev; MemoryRegion *address_space_mem =3D get_system_memory(); - MemoryRegion *phys_tcm =3D g_new(MemoryRegion, 1); - MemoryRegion *phys_tcm_alias =3D g_new(MemoryRegion, 1); - MemoryRegion *phys_ram =3D g_new(MemoryRegion, 1); - MemoryRegion *phys_ram_alias =3D g_new(MemoryRegion, 1); ram_addr_t tcm_base =3D 0x0; ram_addr_t tcm_size =3D 0x1000; /* 1 kiB, but QEMU limit is 4 kiB */ ram_addr_t ram_base =3D 0x08000000; @@ -62,22 +64,22 @@ static void nios2_10m50_ghrd_init(MachineState *machine) int i; =20 /* Physical TCM (tb_ram_1k) with alias at 0xc0000000 */ - memory_region_init_ram(phys_tcm, NULL, "nios2.tcm", tcm_size, + memory_region_init_ram(&nms->phys_tcm, NULL, "nios2.tcm", tcm_size, &error_abort); - memory_region_init_alias(phys_tcm_alias, NULL, "nios2.tcm.alias", - phys_tcm, 0, tcm_size); - memory_region_add_subregion(address_space_mem, tcm_base, phys_tcm); + memory_region_init_alias(&nms->phys_tcm_alias, NULL, "nios2.tcm.alias", + &nms->phys_tcm, 0, tcm_size); + memory_region_add_subregion(address_space_mem, tcm_base, &nms->phys_tc= m); memory_region_add_subregion(address_space_mem, 0xc0000000 + tcm_base, - phys_tcm_alias); + &nms->phys_tcm_alias); =20 /* Physical DRAM with alias at 0xc0000000 */ - memory_region_init_ram(phys_ram, NULL, "nios2.ram", ram_size, + memory_region_init_ram(&nms->phys_ram, NULL, "nios2.ram", ram_size, &error_abort); - memory_region_init_alias(phys_ram_alias, NULL, "nios2.ram.alias", - phys_ram, 0, ram_size); - memory_region_add_subregion(address_space_mem, ram_base, phys_ram); + memory_region_init_alias(&nms->phys_ram_alias, NULL, "nios2.ram.alias", + &nms->phys_ram, 0, ram_size); + memory_region_add_subregion(address_space_mem, ram_base, &nms->phys_ra= m); memory_region_add_subregion(address_space_mem, 0xc0000000 + ram_base, - phys_ram_alias); + &nms->phys_ram_alias); =20 /* Create CPU -- FIXME */ cpu =3D NIOS2_CPU(cpu_create(TYPE_NIOS2_CPU)); --=20 2.25.1 From nobody Sun May 19 04:34:56 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646914348595735.02031190468; Thu, 10 Mar 2022 04:12:28 -0800 (PST) Received: from localhost ([::1]:42266 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nSHed-0005mL-6y for importer@patchew.org; Thu, 10 Mar 2022 07:12:27 -0500 Received: from eggs.gnu.org ([209.51.188.92]:51890) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nSH0v-0002Yg-HN for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:31:25 -0500 Received: from [2607:f8b0:4864:20::1033] (port=36514 helo=mail-pj1-x1033.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nSH0t-0008UG-Mf for qemu-devel@nongnu.org; Thu, 10 Mar 2022 06:31:25 -0500 Received: by mail-pj1-x1033.google.com with SMTP id kx6-20020a17090b228600b001bf859159bfso7973681pjb.1 for ; Thu, 10 Mar 2022 03:31:23 -0800 (PST) Received: from localhost.localdomain (174-21-142-130.tukw.qwest.net. [174.21.142.130]) by smtp.gmail.com with ESMTPSA id e14-20020a056a001a8e00b004f75cf1ab6csm6011246pfv.206.2022.03.10.03.31.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 10 Mar 2022 03:31:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=FgJtqezNi81L0SadvxdIqrQdrL90cWo0N9YQo1orZhs=; b=sPPRs6mT0fiwfzhP1UotP2B8QCP+1RNBxDq7vT/kSmnE/z1/wZr6aaXCYAPIVntblY dRzcQWbsOoNnQdD0VYNJi9SjHEAqh3QlokDl8+VSzoQeHPxDAl3/90TkYIRAR9HMLLlO 4rrsOv60/aBUOfCVgsc15wXKXZdDOJ3nujuWD086txbVn3fLUZer34Pe8HhCd4EQTUyA Ui76LUGAVxZh072vjneC6WTQPYqkayn131KuhpzdPnyAQgAzebsVBE1oZpwsbYAAyxDy uJkQO5qSztDT+oVQB541jGRz3hRn3i3zV2q2fBce90FCNPP7RfRJ2GzorCOiShfSJgUy wSMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=FgJtqezNi81L0SadvxdIqrQdrL90cWo0N9YQo1orZhs=; b=j0cb2Pw0LlIdI0Ov1R4gUUcbmt7pc/j8rOPgUqii4hDeffb7RVAf5eMa4MdoSOJ8cM KZ5DhLX7r+f8FBpyo+b5HoFH3YGG7cvgZLQKDj7rncphj+h4UUNtHVcQwqVmgzB+Fuf+ wQdh25kVYgo41Z16dZb4JRkN9KbvHZLvsvuPEZikCdbhsftbn3AbibmOq581OE4gFjoZ Sywv5V6bOL3MzBiU7mTXIQaIx7/boJJhyDL2BP3BmcBIlaKUoLqzqhlB6bpiGaAsm8Wm jqq0jl0gkg9RuhBlCkTuhhYYNdENOW2p0i/V852+7pVjW5kA9LKByAfgMzJvuDvA7eFJ s3Ug== X-Gm-Message-State: AOAM533gKCmMnucx7UBsIFr6/RWEfo2llX8pwrl4eMcYSaYySM1j4mGt wgw/7A9fHVZ3gipHG+lvsojKSGg5CE9kug== X-Google-Smtp-Source: ABdhPJydG6Ie5FNiaMBjQCsWAwJoOkp9Y/OX6yd/jdpsx9KJ5Nb3VXSCLomHWyVF0z/7+QHWALWAnA== X-Received: by 2002:a17:902:c1d4:b0:151:b56c:41ef with SMTP id c20-20020a170902c1d400b00151b56c41efmr4404907plc.77.1646911882431; Thu, 10 Mar 2022 03:31:22 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v5 48/48] hw/nios2: Machine with a Vectored Interrupt Controller Date: Thu, 10 Mar 2022 03:27:25 -0800 Message-Id: <20220310112725.570053-49-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220310112725.570053-1-richard.henderson@linaro.org> References: <20220310112725.570053-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1033 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646914350943100001 Content-Type: text/plain; charset="utf-8" From: Amir Gonnen Demonstrate how to use nios2 VIC on a machine. Introduce a new machine property to attach a VIC. When VIC is present, let the CPU know that it should use the External Interrupt Interface instead of the Internal Interrupt Interface. The devices on the machine are attached to the VIC and not directly to cpu. To allow VIC update EIC fields, we set the "cpu" property of the VIC with a reference to the nios2 cpu. Signed-off-by: Amir Gonnen Message-Id: <20220303153906.2024748-6-amir.gonnen@neuroblade.ai> [rth: Put a property on the 10m50-ghrd machine, rather than create a new machine class.] Signed-off-by: Richard Henderson Reviewed-by: Mark Cave-Ayland --- hw/nios2/10m50_devboard.c | 61 +++++++++++++++++++++++++++++++++------ hw/nios2/Kconfig | 1 + 2 files changed, 53 insertions(+), 9 deletions(-) diff --git a/hw/nios2/10m50_devboard.c b/hw/nios2/10m50_devboard.c index dda4ab2bf5..91383fb097 100644 --- a/hw/nios2/10m50_devboard.c +++ b/hw/nios2/10m50_devboard.c @@ -27,6 +27,7 @@ =20 #include "hw/sysbus.h" #include "hw/char/serial.h" +#include "hw/intc/nios2_vic.h" #include "hw/qdev-properties.h" #include "sysemu/sysemu.h" #include "hw/boards.h" @@ -43,6 +44,8 @@ struct Nios2MachineState { MemoryRegion phys_tcm_alias; MemoryRegion phys_ram; MemoryRegion phys_ram_alias; + + bool vic; }; =20 #define TYPE_NIOS2_MACHINE MACHINE_TYPE_NAME("10m50-ghrd") @@ -81,10 +84,39 @@ static void nios2_10m50_ghrd_init(MachineState *machine) memory_region_add_subregion(address_space_mem, 0xc0000000 + ram_base, &nms->phys_ram_alias); =20 - /* Create CPU -- FIXME */ - cpu =3D NIOS2_CPU(cpu_create(TYPE_NIOS2_CPU)); - for (i =3D 0; i < 32; i++) { - irq[i] =3D qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", i); + /* Create CPU. We need to set eic_present between init and realize. */ + cpu =3D NIOS2_CPU(object_new(TYPE_NIOS2_CPU)); + + /* Enable the External Interrupt Controller within the CPU. */ + cpu->eic_present =3D nms->vic; + + /* Configure new exception vectors. */ + cpu->reset_addr =3D 0xd4000000; + cpu->exception_addr =3D 0xc8000120; + cpu->fast_tlb_miss_addr =3D 0xc0000100; + + qdev_realize_and_unref(DEVICE(cpu), NULL, &error_fatal); + + if (nms->vic) { + DeviceState *dev =3D qdev_new(TYPE_NIOS2_VIC); + MemoryRegion *dev_mr; + qemu_irq cpu_irq; + + object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_f= atal); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + + cpu_irq =3D qdev_get_gpio_in_named(DEVICE(cpu), "EIC", 0); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq); + for (int i =3D 0; i < 32; i++) { + irq[i] =3D qdev_get_gpio_in(dev, i); + } + + dev_mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); + memory_region_add_subregion(address_space_mem, 0x18002000, dev_mr); + } else { + for (i =3D 0; i < 32; i++) { + irq[i] =3D qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", i); + } } =20 /* Register: Altera 16550 UART */ @@ -105,15 +137,22 @@ static void nios2_10m50_ghrd_init(MachineState *machi= ne) sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xe0000880); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[5]); =20 - /* Configure new exception vectors and reset CPU for it to take effect= . */ - cpu->reset_addr =3D 0xd4000000; - cpu->exception_addr =3D 0xc8000120; - cpu->fast_tlb_miss_addr =3D 0xc0000100; - nios2_load_kernel(cpu, ram_base, ram_size, machine->initrd_filename, BINARY_DEVICE_TREE_FILE, NULL); } =20 +static bool get_vic(Object *obj, Error **errp) +{ + Nios2MachineState *nms =3D NIOS2_MACHINE(obj); + return nms->vic; +} + +static void set_vic(Object *obj, bool value, Error **errp) +{ + Nios2MachineState *nms =3D NIOS2_MACHINE(obj); + nms->vic =3D value; +} + static void nios2_10m50_ghrd_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); @@ -121,6 +160,10 @@ static void nios2_10m50_ghrd_class_init(ObjectClass *o= c, void *data) mc->desc =3D "Altera 10M50 GHRD Nios II design"; mc->init =3D nios2_10m50_ghrd_init; mc->is_default =3D true; + + object_class_property_add_bool(oc, "vic", get_vic, set_vic); + object_class_property_set_description(oc, "vic", + "Set on/off to enable/disable the Vectored Interrupt Controller"); } =20 static const TypeInfo nios2_10m50_ghrd_type_info =3D { diff --git a/hw/nios2/Kconfig b/hw/nios2/Kconfig index b10ea640da..4748ae27b6 100644 --- a/hw/nios2/Kconfig +++ b/hw/nios2/Kconfig @@ -3,6 +3,7 @@ config NIOS2_10M50 select NIOS2 select SERIAL select ALTERA_TIMER + select NIOS2_VIC =20 config NIOS2_GENERIC_NOMMU bool --=20 2.25.1