From nobody Sun May 19 01:43:04 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@quicinc.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=quicinc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646766367309234.60996191753088; Tue, 8 Mar 2022 11:06:07 -0800 (PST) Received: from localhost ([::1]:49912 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nRf9p-000373-PF for importer@patchew.org; Tue, 08 Mar 2022 14:06:05 -0500 Received: from eggs.gnu.org ([209.51.188.92]:48918) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nRf8E-0002Pj-Sq for qemu-devel@nongnu.org; Tue, 08 Mar 2022 14:04:26 -0500 Received: from alexa-out.qualcomm.com ([129.46.98.28]:55057) by eggs.gnu.org with esmtps (TLS1.2:RSA_AES_256_CBC_SHA1:256) (Exim 4.90_1) (envelope-from ) id 1nRf8C-00027u-DZ for qemu-devel@nongnu.org; Tue, 08 Mar 2022 14:04:26 -0500 Received: from ironmsg-lv-alpha.qualcomm.com ([10.47.202.13]) by alexa-out.qualcomm.com with ESMTP; 08 Mar 2022 11:04:12 -0800 Received: from hu-tsimpson-lv.qualcomm.com (HELO hu-devc-lv-u18-c.qualcomm.com) ([10.47.235.220]) by ironmsg-lv-alpha.qualcomm.com with ESMTP; 08 Mar 2022 11:04:12 -0800 Received: by hu-devc-lv-u18-c.qualcomm.com (Postfix, from userid 47164) id 05214500172; Tue, 8 Mar 2022 11:04:11 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=quicinc.com; i=@quicinc.com; q=dns/txt; s=qcdkim; t=1646766264; x=1678302264; h=from:to:cc:subject:date:message-id:mime-version: content-transfer-encoding; bh=jbz3LXNXf4MvJSsbjua6vl1yhaVY13PSvzI+Bzf1wQE=; b=sduw+aw3HlzeaNr8t5e9xqXpVw9VqcBl0V1GSfNyTUi+qKkQvkRFtIJH 4R0Aq+nTDhvlvbjtDG4zmXB6meCBn6dncjt+GgLI9u9CUXZ6n2vXZdsMI UUEUg3kpdVTI9NqP725gn12u9eHmXqZ1sdqSlPNEjY4bYvlLpmuAMw6HH E=; X-QCInternal: smtphost From: Taylor Simpson To: qemu-devel@nongnu.org Subject: [PATCH v4] Hexagon (target/hexagon) properly handle NaN in dfmin/dfmax/sfmin/sfmax Date: Tue, 8 Mar 2022 11:04:10 -0800 Message-Id: <20220308190410.22355-1-tsimpson@quicinc.com> X-Mailer: git-send-email 2.17.1 MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=129.46.98.28; envelope-from=tsimpson@qualcomm.com; helo=alexa-out.qualcomm.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, HEADER_FROM_DIFFERENT_DOMAINS=0.249, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: ale@rev.ng, bcain@quicinc.com, richard.henderson@linaro.org, f4bug@amsat.org, tsimpson@quicinc.com, mlambert@quicinc.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646766369557100001 The float??_minnum implementation differs from Hexagon for SNaN, it returns NaN, but Hexagon returns the other input. So, we use float??_minimum_number. Test cases added to tests/tcg/hexagon/fpstuff.c Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson --- target/hexagon/op_helper.c | 14 ++----- tests/tcg/hexagon/fpstuff.c | 79 +++++++++++++++++++++++++++++-------- 2 files changed, 66 insertions(+), 27 deletions(-) diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 057baf9a48..33a86be7be 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -948,7 +948,7 @@ float32 HELPER(sfmax)(CPUHexagonState *env, float32 RsV= , float32 RtV) { float32 RdV; arch_fpop_start(env); - RdV =3D float32_maxnum(RsV, RtV, &env->fp_status); + RdV =3D float32_maximum_number(RsV, RtV, &env->fp_status); arch_fpop_end(env); return RdV; } @@ -957,7 +957,7 @@ float32 HELPER(sfmin)(CPUHexagonState *env, float32 RsV= , float32 RtV) { float32 RdV; arch_fpop_start(env); - RdV =3D float32_minnum(RsV, RtV, &env->fp_status); + RdV =3D float32_minimum_number(RsV, RtV, &env->fp_status); arch_fpop_end(env); return RdV; } @@ -1041,10 +1041,7 @@ float64 HELPER(dfmax)(CPUHexagonState *env, float64 = RssV, float64 RttV) { float64 RddV; arch_fpop_start(env); - RddV =3D float64_maxnum(RssV, RttV, &env->fp_status); - if (float64_is_any_nan(RssV) || float64_is_any_nan(RttV)) { - float_raise(float_flag_invalid, &env->fp_status); - } + RddV =3D float64_maximum_number(RssV, RttV, &env->fp_status); arch_fpop_end(env); return RddV; } @@ -1053,10 +1050,7 @@ float64 HELPER(dfmin)(CPUHexagonState *env, float64 = RssV, float64 RttV) { float64 RddV; arch_fpop_start(env); - RddV =3D float64_minnum(RssV, RttV, &env->fp_status); - if (float64_is_any_nan(RssV) || float64_is_any_nan(RttV)) { - float_raise(float_flag_invalid, &env->fp_status); - } + RddV =3D float64_minimum_number(RssV, RttV, &env->fp_status); arch_fpop_end(env); return RddV; } diff --git a/tests/tcg/hexagon/fpstuff.c b/tests/tcg/hexagon/fpstuff.c index 0dff429f4c..7a65ebc74d 100644 --- a/tests/tcg/hexagon/fpstuff.c +++ b/tests/tcg/hexagon/fpstuff.c @@ -39,7 +39,8 @@ const int SF_ANY =3D 0x3f800000; const int SF_HEX_NAN =3D 0xffffffff; const int SF_small_neg =3D 0xab98fba8; =20 -const long long DF_NaN =3D 0x7ff8000000000000ULL; +const long long DF_QNaN =3D 0x7ff8000000000000ULL; +const long long DF_SNaN =3D 0x7ff7000000000000ULL; const long long DF_ANY =3D 0x3f80000000000000ULL; const long long DF_HEX_NAN =3D 0xffffffffffffffffULL; const long long DF_small_neg =3D 0xbd731f7500000000ULL; @@ -126,7 +127,7 @@ static void check_compare_exception(void) "p0 =3D dfcmp.eq(%2, %3)\n\t" "%0 =3D p0\n\t" "%1 =3D usr\n\t" - : "=3Dr"(cmp), "=3Dr"(usr) : "r"(DF_NaN), "r"(DF_ANY) + : "=3Dr"(cmp), "=3Dr"(usr) : "r"(DF_QNaN), "r"(DF_ANY) : "r2", "p0", "usr"); check32(cmp, 0); check_fpstatus(usr, 0); @@ -135,7 +136,7 @@ static void check_compare_exception(void) "p0 =3D dfcmp.gt(%2, %3)\n\t" "%0 =3D p0\n\t" "%1 =3D usr\n\t" - : "=3Dr"(cmp), "=3Dr"(usr) : "r"(DF_NaN), "r"(DF_ANY) + : "=3Dr"(cmp), "=3Dr"(usr) : "r"(DF_QNaN), "r"(DF_ANY) : "r2", "p0", "usr"); check32(cmp, 0); check_fpstatus(usr, 0); @@ -144,7 +145,7 @@ static void check_compare_exception(void) "p0 =3D dfcmp.ge(%2, %3)\n\t" "%0 =3D p0\n\t" "%1 =3D usr\n\t" - : "=3Dr"(cmp), "=3Dr"(usr) : "r"(DF_NaN), "r"(DF_ANY) + : "=3Dr"(cmp), "=3Dr"(usr) : "r"(DF_QNaN), "r"(DF_ANY) : "r2", "p0", "usr"); check32(cmp, 0); check_fpstatus(usr, 0); @@ -206,7 +207,7 @@ static void check_dfminmax(void) int usr; =20 /* - * Execute dfmin/dfmax instructions with one operand as NaN + * Execute dfmin/dfmax instructions with one operand as SNaN * Check that * Result is the other operand * Invalid bit in USR is set @@ -214,7 +215,7 @@ static void check_dfminmax(void) asm (CLEAR_FPSTATUS "%0 =3D dfmin(%2, %3)\n\t" "%1 =3D usr\n\t" - : "=3Dr"(minmax), "=3Dr"(usr) : "r"(DF_NaN), "r"(DF_ANY) + : "=3Dr"(minmax), "=3Dr"(usr) : "r"(DF_SNaN), "r"(DF_ANY) : "r2", "usr"); check64(minmax, DF_ANY); check_fpstatus(usr, FPINVF); @@ -222,13 +223,35 @@ static void check_dfminmax(void) asm (CLEAR_FPSTATUS "%0 =3D dfmax(%2, %3)\n\t" "%1 =3D usr\n\t" - : "=3Dr"(minmax), "=3Dr"(usr) : "r"(DF_NaN), "r"(DF_ANY) + : "=3Dr"(minmax), "=3Dr"(usr) : "r"(DF_SNaN), "r"(DF_ANY) : "r2", "usr"); check64(minmax, DF_ANY); check_fpstatus(usr, FPINVF); =20 /* - * Execute dfmin/dfmax instructions with both operands NaN + * Execute dfmin/dfmax instructions with one operand as QNaN + * Check that + * Result is the other operand + * No bit in USR is set + */ + asm (CLEAR_FPSTATUS + "%0 =3D dfmin(%2, %3)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(minmax), "=3Dr"(usr) : "r"(DF_QNaN), "r"(DF_ANY) + : "r2", "usr"); + check64(minmax, DF_ANY); + check_fpstatus(usr, 0); + + asm (CLEAR_FPSTATUS + "%0 =3D dfmax(%2, %3)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(minmax), "=3Dr"(usr) : "r"(DF_QNaN), "r"(DF_ANY) + : "r2", "usr"); + check64(minmax, DF_ANY); + check_fpstatus(usr, 0); + + /* + * Execute dfmin/dfmax instructions with both operands SNaN * Check that * Result is DF_HEX_NAN * Invalid bit in USR is set @@ -236,7 +259,7 @@ static void check_dfminmax(void) asm (CLEAR_FPSTATUS "%0 =3D dfmin(%2, %3)\n\t" "%1 =3D usr\n\t" - : "=3Dr"(minmax), "=3Dr"(usr) : "r"(DF_NaN), "r"(DF_NaN) + : "=3Dr"(minmax), "=3Dr"(usr) : "r"(DF_SNaN), "r"(DF_SNaN) : "r2", "usr"); check64(minmax, DF_HEX_NAN); check_fpstatus(usr, FPINVF); @@ -244,10 +267,32 @@ static void check_dfminmax(void) asm (CLEAR_FPSTATUS "%0 =3D dfmax(%2, %3)\n\t" "%1 =3D usr\n\t" - : "=3Dr"(minmax), "=3Dr"(usr) : "r"(DF_NaN), "r"(DF_NaN) + : "=3Dr"(minmax), "=3Dr"(usr) : "r"(DF_SNaN), "r"(DF_SNaN) : "r2", "usr"); check64(minmax, DF_HEX_NAN); check_fpstatus(usr, FPINVF); + + /* + * Execute dfmin/dfmax instructions with both operands QNaN + * Check that + * Result is DF_HEX_NAN + * No bit in USR is set + */ + asm (CLEAR_FPSTATUS + "%0 =3D dfmin(%2, %3)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(minmax), "=3Dr"(usr) : "r"(DF_QNaN), "r"(DF_QNaN) + : "r2", "usr"); + check64(minmax, DF_HEX_NAN); + check_fpstatus(usr, 0); + + asm (CLEAR_FPSTATUS + "%0 =3D dfmax(%2, %3)\n\t" + "%1 =3D usr\n\t" + : "=3Dr"(minmax), "=3Dr"(usr) : "r"(DF_QNaN), "r"(DF_QNaN) + : "r2", "usr"); + check64(minmax, DF_HEX_NAN); + check_fpstatus(usr, 0); } =20 static void check_recip_exception(void) @@ -411,7 +456,7 @@ static void check_canonical_NaN(void) asm(CLEAR_FPSTATUS "%0 =3D convert_df2sf(%2)\n\t" "%1 =3D usr\n\t" - : "=3Dr"(sf_result), "=3Dr"(usr) : "r"(DF_NaN) + : "=3Dr"(sf_result), "=3Dr"(usr) : "r"(DF_QNaN) : "r2", "usr"); check32(sf_result, SF_HEX_NAN); check_fpstatus(usr, 0); @@ -419,7 +464,7 @@ static void check_canonical_NaN(void) asm(CLEAR_FPSTATUS "%0 =3D dfadd(%2, %3)\n\t" "%1 =3D usr\n\t" - : "=3Dr"(df_result), "=3Dr"(usr) : "r"(DF_NaN), "r"(DF_ANY) + : "=3Dr"(df_result), "=3Dr"(usr) : "r"(DF_QNaN), "r"(DF_ANY) : "r2", "usr"); check64(df_result, DF_HEX_NAN); check_fpstatus(usr, 0); @@ -427,7 +472,7 @@ static void check_canonical_NaN(void) asm(CLEAR_FPSTATUS "%0 =3D dfsub(%2, %3)\n\t" "%1 =3D usr\n\t" - : "=3Dr"(df_result), "=3Dr"(usr) : "r"(DF_NaN), "r"(DF_ANY) + : "=3Dr"(df_result), "=3Dr"(usr) : "r"(DF_QNaN), "r"(DF_ANY) : "r2", "usr"); check64(df_result, DF_HEX_NAN); check_fpstatus(usr, 0); @@ -567,7 +612,7 @@ static void check_float2int_convs() asm(CLEAR_FPSTATUS "%0 =3D convert_df2w(%2)\n\t" "%1 =3D usr\n\t" - : "=3Dr"(res32), "=3Dr"(usr) : "r"(DF_NaN) + : "=3Dr"(res32), "=3Dr"(usr) : "r"(DF_QNaN) : "r2", "usr"); check32(res32, -1); check_fpstatus(usr, FPINVF); @@ -575,7 +620,7 @@ static void check_float2int_convs() asm(CLEAR_FPSTATUS "%0 =3D convert_df2w(%2):chop\n\t" "%1 =3D usr\n\t" - : "=3Dr"(res32), "=3Dr"(usr) : "r"(DF_NaN) + : "=3Dr"(res32), "=3Dr"(usr) : "r"(DF_QNaN) : "r2", "usr"); check32(res32, -1); check_fpstatus(usr, FPINVF); @@ -583,7 +628,7 @@ static void check_float2int_convs() asm(CLEAR_FPSTATUS "%0 =3D convert_df2d(%2)\n\t" "%1 =3D usr\n\t" - : "=3Dr"(res64), "=3Dr"(usr) : "r"(DF_NaN) + : "=3Dr"(res64), "=3Dr"(usr) : "r"(DF_QNaN) : "r2", "usr"); check64(res64, -1); check_fpstatus(usr, FPINVF); @@ -591,7 +636,7 @@ static void check_float2int_convs() asm(CLEAR_FPSTATUS "%0 =3D convert_df2d(%2):chop\n\t" "%1 =3D usr\n\t" - : "=3Dr"(res64), "=3Dr"(usr) : "r"(DF_NaN) + : "=3Dr"(res64), "=3Dr"(usr) : "r"(DF_QNaN) : "r2", "usr"); check64(res64, -1); check_fpstatus(usr, FPINVF); --=20 2.17.1