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[50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sZ2C5DabhR4UWhlHHPl5YgAYQYqTqvWzN8pMZpMuTzI=; b=y4ulzfZJZOATKzy0+K9e4pRN7ZRqxKTSMsWUTGSRWzBeSvjsj9IrChMLeZVsPfpTY/ xscqdVA4ZQ/xt+S5KDz6ficmTPyx3KC5XovmH6URGcv7AFFKXEWVG2y4D4BVK+DEXy7m 7oLJp287MOBbaiO7e0/JrrCoy/P/h0czNuYBI7rSrCe6so+obBpUfbXxROoyIsEhPCm1 MTaO/0Ig4cEksrP8goMNGzbGDnECHP3tYQ2faQasXSjeSjgrMagICpOGNiEytgA+bLyQ ikfk9E/IDYlhafKXjdxh0/eWWdz/5xDvu/AObRPIgXDeMSFIGpqd/sI03Qw4Hws4MPS0 1I5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sZ2C5DabhR4UWhlHHPl5YgAYQYqTqvWzN8pMZpMuTzI=; b=WD+6+97ey+iQGw2YlzdZZ1n8FjJkAqkNy7xN6FQmK4GCJmr6MAvgv7NTS8UwXofojK pbGqj5nu1ajnxRm2QaVXUqNJCqfT0ENjpAZ7Z8xsyPWlu3eajQ4wra3NDUmfjfPchd/y 16pmbM0qqIBUbBP5MIvAoJ+prF8sg0it+SpjNEqV0pURj76cphqRQbZJ/IQ46TZatjTD 8borqkH539uiv2yztEIE2hOXGXJ9Vo14ryB56uguGqXQ6PojrcQyinsJ4QFYS76OSXiQ C7jE2T+pq9cskBjsJqv18wQy59piOT6OaWFWKXAqbUOEIMeZ06Db0mlWn6MsX+bGBcdN XdSA== X-Gm-Message-State: AOAM530bkSY5ZjpB8HcQicPWQ0RBWbk8CPc9EaHQ03tWshTGEpafKZZx Yr8mhmoKXsLxtfmeFkUn4Cu7yEuu5ngvJQ== X-Google-Smtp-Source: ABdhPJxOEoe0picZD1ycL1BXseTHt6v1OsfOYnylxEURXw/9EqC2S0WF4sKSk9vH2BGcKSGumeiODQ== X-Received: by 2002:a17:90b:4b51:b0:1bf:88c7:aecc with SMTP id mi17-20020a17090b4b5100b001bf88c7aeccmr2443669pjb.115.1646724053740; Mon, 07 Mar 2022 23:20:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 28/33] target/nios2: Clean up nios2_cpu_do_interrupt Date: Mon, 7 Mar 2022 21:20:00 -1000 Message-Id: <20220308072005.307955-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1035 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646726101905100001 Content-Type: text/plain; charset="utf-8" Sink the bulk of the interrupt processing to the end of the file. All of the internal interrupt and non-interrupt exception code shares EH processing. Signed-off-by: Richard Henderson --- target/nios2/helper.c | 100 +++++++++++------------------------------- 1 file changed, 25 insertions(+), 75 deletions(-) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index a338d02f6b..ccf2634c9b 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -53,48 +53,25 @@ void nios2_cpu_do_interrupt(CPUState *cs) { Nios2CPU *cpu =3D NIOS2_CPU(cs); CPUNios2State *env =3D &cpu->env; + uint32_t exception_addr =3D cpu->exception_addr; + unsigned r_ea =3D R_EA; + unsigned cr_estatus =3D CR_ESTATUS; =20 switch (cs->exception_index) { case EXCP_IRQ: - assert(env->status & CR_STATUS_PIE); - qemu_log_mask(CPU_LOG_INT, "interrupt at pc=3D%x\n", env->pc); - - env->estatus =3D env->status; - env->status |=3D CR_STATUS_IH; - env->status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); - - nios2_crs(env)[R_EA] =3D env->pc + 4; - env->pc =3D cpu->exception_addr; break; =20 case EXCP_TLBD: - if ((env->status & CR_STATUS_EH) =3D=3D 0) { + if (env->status & CR_STATUS_EH) { + qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=3D%x\n", e= nv->pc); + /* Double TLB miss */ + env->tlbmisc |=3D CR_TLBMISC_DBL; + } else { qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=3D%x\n", env= ->pc); - - /* Fast TLB miss */ - /* Variation from the spec. Table 3-35 of the cpu reference sh= ows - * estatus not being changed for TLB miss but this appears to - * be incorrect. */ - env->estatus =3D env->status; - env->status |=3D CR_STATUS_EH; - env->status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); - env->tlbmisc &=3D ~CR_TLBMISC_DBL; env->tlbmisc |=3D CR_TLBMISC_WR; - - nios2_crs(env)[R_EA] =3D env->pc + 4; - env->pc =3D cpu->fast_tlb_miss_addr; - } else { - qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=3D%x\n", e= nv->pc); - - /* Double TLB miss */ - env->status |=3D CR_STATUS_EH; - env->status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); - - env->tlbmisc |=3D CR_TLBMISC_DBL; - - env->pc =3D cpu->exception_addr; + exception_addr =3D cpu->fast_tlb_miss_addr; } break; =20 @@ -102,48 +79,18 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_TLBW: case EXCP_TLBX: qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=3D%x\n", env->pc); - - env->estatus =3D env->status; - env->status |=3D CR_STATUS_EH; - env->status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); - - if ((env->status & CR_STATUS_EH) =3D=3D 0) { - env->tlbmisc |=3D CR_TLBMISC_WR; - } - - nios2_crs(env)[R_EA] =3D env->pc + 4; - env->pc =3D cpu->exception_addr; + env->tlbmisc |=3D CR_TLBMISC_WR; break; =20 case EXCP_SUPERA: case EXCP_SUPERI: case EXCP_SUPERD: qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=3D%x\n", en= v->pc); - - if ((env->status & CR_STATUS_EH) =3D=3D 0) { - env->estatus =3D env->status; - nios2_crs(env)[R_EA] =3D env->pc + 4; - } - - env->status |=3D CR_STATUS_EH; - env->status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); - - env->pc =3D cpu->exception_addr; break; =20 case EXCP_ILLEGAL: case EXCP_TRAP: qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=3D%x\n", env->pc); - - if ((env->status & CR_STATUS_EH) =3D=3D 0) { - env->estatus =3D env->status; - nios2_crs(env)[R_EA] =3D env->pc + 4; - } - - env->status |=3D CR_STATUS_EH; - env->status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); - - env->pc =3D cpu->exception_addr; break; =20 case EXCP_SEMIHOST: @@ -154,23 +101,26 @@ void nios2_cpu_do_interrupt(CPUState *cs) =20 case EXCP_BREAK: qemu_log_mask(CPU_LOG_INT, "BREAK exception at pc=3D%x\n", env->pc= ); - if ((env->status & CR_STATUS_EH) =3D=3D 0) { - env->bstatus =3D env->status; - nios2_crs(env)[R_BA] =3D env->pc + 4; - } - - env->status |=3D CR_STATUS_EH; - env->status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); - - env->pc =3D cpu->exception_addr; + r_ea =3D R_BA; + cr_estatus =3D CR_BSTATUS; break; =20 default: - cpu_abort(cs, "unhandled exception type=3D%d\n", - cs->exception_index); - break; + cpu_abort(cs, "unhandled exception type=3D%d\n", cs->exception_ind= ex); } =20 + /* + * Finish Internal Interrupt or Noninterrupt Exception. + */ + + if (!(env->status & CR_STATUS_EH)) { + env->ctrl[cr_estatus] =3D env->status; + env->crs[r_ea] =3D env->pc + 4; + env->status |=3D CR_STATUS_EH; + } + env->status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); + + env->pc =3D exception_addr; env->exception =3D FIELD_DP32(env->exception, CR_EXCEPTION, CAUSE, cs->exception_index); } --=20 2.25.1