From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646724220961577.7073827532528; Mon, 7 Mar 2022 23:23:40 -0800 (PST) Received: from localhost ([::1]:55608 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nRUC3-0007t7-8Q for importer@patchew.org; Tue, 08 Mar 2022 02:23:39 -0500 Received: from eggs.gnu.org ([209.51.188.92]:44886) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nRU8m-00051D-9e for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:17 -0500 Received: from [2607:f8b0:4864:20::102a] (port=46022 helo=mail-pj1-x102a.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nRU8k-00063T-EY for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:15 -0500 Received: by mail-pj1-x102a.google.com with SMTP id m11-20020a17090a7f8b00b001beef6143a8so1580592pjl.4 for ; Mon, 07 Mar 2022 23:20:11 -0800 (PST) Received: from localhost.localdomain (cpe-50-113-46-110.hawaii.res.rr.com. [50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NA9HskFqPeLh+02a0cXnYrdAXovGtw+F2Po8AxVhC7E=; b=nHYJ9QGlcMLqmIbooL8I0acm0MFAn7jtSXsIGEtOTfObF2X++jLXIKZprmdFM6VAAf nOGR3wl8ItjIwkd19etXXS8vFmmsJBObOOHsneWnZryQtuV90if2Wk+jE4XmYs0dP63A P2w4QcPobGKhdTxeK9vTGhyRXzvN9CgF/Fk3OlqhDKM7Ua7EB1a398XSerlnSxEr8/lw cb3J+9zYtqV9bIqEYOzYE2LDMR6xnYwiidnv7g1tVr3dKtOKwTJkLqoOZ1DagUvejtmT U6PMnE3+rja/EhODBrYBYj61GLKyKlTcJdgBwP6SUctuOEOrg+REPBc6wSFSg6b3N4wh x9YQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NA9HskFqPeLh+02a0cXnYrdAXovGtw+F2Po8AxVhC7E=; b=dgQgQ1oSNpoFCTfdLu8rD10jBUw4joNES+m5/55wYT1pjlWGYbQa6H0zB1uKJyPKla /ci8BfxevgJCU/hlTL0C4UP2oUahR3DOp9DvDNcPBYUXfCZWjiFA0FjIWFRdredCcUvr 41LSEw1rpRc5z1tsibqR8Ky3i6obhx92kRRpyeK7a3pUgM5ykaPzpDcEUSibBloqbaQj CBn+umxUZaw3l5hUNddXVg/zhTak7YqaWHZstdb5svNiLwLHtkpI/X9jVbfgK5lNRlOA 113mPEuhEMbyw2H7eWXglSb8B98rHRuU+07Oi/sBeBHgW59PYqbRORsixREI2ikQHS+l WpCA== X-Gm-Message-State: AOAM533Ap34ZNtydO/Ps777RLY4EBin8r60XtLp3GuTkmrPiDRIxdhsC SqhaUkbhOy77ctjeezRL8ZFTQl2aY0Ck7Q== X-Google-Smtp-Source: ABdhPJzE6/Ix0ixon6Q7FJ7/JA5jEl4/2+5M8uUxnMzp00nkYSsMYrGlFUOGr21ViqGC2LRuBtrlpQ== X-Received: by 2002:a17:903:32c4:b0:151:c6ae:e24b with SMTP id i4-20020a17090332c400b00151c6aee24bmr16632491plr.85.1646724010861; Mon, 07 Mar 2022 23:20:10 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 01/33] target/nios2: Check supervisor on eret Date: Mon, 7 Mar 2022 21:19:33 -1000 Message-Id: <20220308072005.307955-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102a (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646724223242100001 Content-Type: text/plain; charset="utf-8" From: Amir Gonnen eret instruction is only allowed in supervisor mode. Reviewed-by: Peter Maydell Reviewed-by: Richard Henderson Signed-off-by: Amir Gonnen Message-Id: <20220303153906.2024748-2-amir.gonnen@neuroblade.ai> Signed-off-by: Richard Henderson --- target/nios2/translate.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index f89271dbed..341f3a8273 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -384,6 +384,8 @@ static const Nios2Instruction i_type_instructions[] =3D= { */ static void eret(DisasContext *dc, uint32_t code, uint32_t flags) { + gen_check_supervisor(dc); + tcg_gen_mov_tl(cpu_R[CR_STATUS], cpu_R[CR_ESTATUS]); tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_EA]); =20 --=20 2.25.1 From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646724412386646.5273203149939; Mon, 7 Mar 2022 23:26:52 -0800 (PST) Received: from localhost ([::1]:35870 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nRUF9-00058s-CI for importer@patchew.org; Tue, 08 Mar 2022 02:26:51 -0500 Received: from eggs.gnu.org ([209.51.188.92]:44934) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nRU8o-00052g-Nf for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:19 -0500 Received: from [2607:f8b0:4864:20::634] (port=38658 helo=mail-pl1-x634.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nRU8k-00063l-Jz for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:17 -0500 Received: by mail-pl1-x634.google.com with SMTP id t19so12714753plr.5 for ; Mon, 07 Mar 2022 23:20:13 -0800 (PST) Received: from localhost.localdomain (cpe-50-113-46-110.hawaii.res.rr.com. [50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:12 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7bmH4+iW733QmZWCHhiuFV3NePOOzi9ku1JFYZ2UlEE=; b=p75TLY35V5TImfaYqRUH61Ab5HUyVjxSbKXlrM1o2PCU9Ep+RSTsghSn3rdMi1U/G3 nuB8PVvPEF2Ofoqi5SUvyP0SVocPoj4gJWSgLg45HIEn9XTaOYASSQOFjt6jhp/Ir3tO z+lD12Dnoozzy5QVg6BdO4gccLmQR9dG3SC4wAdHu7W91QtVplt9wDw2bNE707y1mzEu 3/AQMfyCyStPsLO9R2VH9ZnA4G4e/hTYvwV961MlrYGEjMK1gx2N6tA3ovT7UzuBLMV9 tg7p+E5nJZ3fH9utbcBzc21078aCeLJQOkc/wPNqrcG1kODr95Koj9LVPQgjaXkIVUsV 4sRg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7bmH4+iW733QmZWCHhiuFV3NePOOzi9ku1JFYZ2UlEE=; b=tsWF1a7pZBXbcVy6Gkq+n8z/Bul4cV6wH5BOLWYNlOyujJMNpArk43q9uA8dDEslDH MwXU2JHTrTI84B+UsNtMG6k88SCltl7qCTxWmx/N/BBSV/OEkDJZeipZoPoz1ytQEiVT 8l9SEHDPoqjV/RsJmgdw+psGJWt6WfRu4tw+98hfzQnn99sN99vlQSQ7zP8auA2TbGTd ygo44OQ7zwKVBqLlA2YhVLpaPlWY/LyE5a6tkLU39QVr4V3cJmxa+dKP1PKDO+smeOOq taV2rKRw4lcs3vvfLD2kF1YZxOoKf6/51oFYEU17lXByfFr2cMBH2EEjgZU7mF5h0/KN xTyw== X-Gm-Message-State: AOAM531u1SQp5nOBlwfyXb0JYAQe0QbMOpyP67FUtgfNtJis9+a6cgRT FlqeBa1LZjJ6DQ8+0R4WYq7pE/9GqL5A+w== X-Google-Smtp-Source: ABdhPJxzudMRIRamP3YXnYYZFzn6VYjpQMdY3ix6rE4haVlqWDlATZnhwR4bRilt2XGPr1Hhw2pRuw== X-Received: by 2002:a17:90a:319:b0:1be:d55e:af43 with SMTP id 25-20020a17090a031900b001bed55eaf43mr3175384pje.231.1646724012797; Mon, 07 Mar 2022 23:20:12 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 02/33] target/nios2: Stop generating code if gen_check_supervisor fails Date: Mon, 7 Mar 2022 21:19:34 -1000 Message-Id: <20220308072005.307955-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::634 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646724414102100001 Content-Type: text/plain; charset="utf-8" Whether the cpu is in user-mode or not is something that we know at translation-time. We do not need to generate code after having raised an exception. Suggested-by: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/translate.c | 20 +++++++++++++++----- 1 file changed, 15 insertions(+), 5 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 341f3a8273..1e0ab686dc 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -169,12 +169,14 @@ static void gen_excp(DisasContext *dc, uint32_t code,= uint32_t flags) t_gen_helper_raise_exception(dc, flags); } =20 -static void gen_check_supervisor(DisasContext *dc) +static bool gen_check_supervisor(DisasContext *dc) { if (dc->base.tb->flags & CR_STATUS_U) { /* CPU in user mode, privileged instruction called, stop. */ t_gen_helper_raise_exception(dc, EXCP_SUPERI); + return false; } + return true; } =20 /* @@ -384,7 +386,9 @@ static const Nios2Instruction i_type_instructions[] =3D= { */ static void eret(DisasContext *dc, uint32_t code, uint32_t flags) { - gen_check_supervisor(dc); + if (!gen_check_supervisor(dc)) { + return; + } =20 tcg_gen_mov_tl(cpu_R[CR_STATUS], cpu_R[CR_ESTATUS]); tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_EA]); @@ -447,7 +451,9 @@ static void rdctl(DisasContext *dc, uint32_t code, uint= 32_t flags) { R_TYPE(instr, code); =20 - gen_check_supervisor(dc); + if (!gen_check_supervisor(dc)) { + return; + } =20 if (unlikely(instr.c =3D=3D R_ZERO)) { return; @@ -474,9 +480,13 @@ static void rdctl(DisasContext *dc, uint32_t code, uin= t32_t flags) /* ctlN <- rA */ static void wrctl(DisasContext *dc, uint32_t code, uint32_t flags) { - gen_check_supervisor(dc); + if (!gen_check_supervisor(dc)) { + return; + } =20 -#ifndef CONFIG_USER_ONLY +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else R_TYPE(instr, code); TCGv v =3D load_gpr(dc, instr.a); =20 --=20 2.25.1 From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646724650444216.70936364665693; Mon, 7 Mar 2022 23:30:50 -0800 (PST) Received: from localhost ([::1]:44250 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nRUIy-0002SV-Bq for importer@patchew.org; Tue, 08 Mar 2022 02:30:49 -0500 Received: from eggs.gnu.org ([209.51.188.92]:44936) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nRU8o-00052h-OM for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:19 -0500 Received: from [2607:f8b0:4864:20::1034] (port=42780 helo=mail-pj1-x1034.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nRU8l-000643-ET for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:17 -0500 Received: by mail-pj1-x1034.google.com with SMTP id c16-20020a17090aa61000b001befad2bfaaso1595251pjq.1 for ; Mon, 07 Mar 2022 23:20:15 -0800 (PST) Received: from localhost.localdomain (cpe-50-113-46-110.hawaii.res.rr.com. [50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:13 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=v5cuX7PyuKwfVmE1y8ht1UYEI7b12iFAXqSTc+0g5D4=; b=dUt8K19HuC+AL76lYrxCeHURZ0rNEq6y3I4dsLY5uBKBDKYpywH0DoTwQsftPR/y69 3WtLKlfPssPDcpnDvTMxJZrInTWc3HBT9aHnTLXbYy9hRTo008KdknDz2Zbyzdj0+sqY xwjjwf16kdV3QRXfm4F1MMWqexWPWDAqpSwjvYzvfuQcBtogD0C8TYO0qxTduoiX+v93 OrDVlIA4cHCrsSgT45rlatkxVToyyZEcl9EFKmahHWGG1z9mG1OWBCR4+aBDfk31RPN1 +gMl0Lm0O06k7ILejPsue8S6ioQOz/N/a3BgIr8e1GpCD6FqwB1PDtNe7sNwdwfLC/gl cvjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v5cuX7PyuKwfVmE1y8ht1UYEI7b12iFAXqSTc+0g5D4=; b=QjjPNbtYqIkxAURWdGKsN1M9LlShpM9xyZrPxmkhYU1peh/BfeHTUvY/pbqZhhFKN2 TAY5Y7boeFUStYDitXFvw5ABj7mk8kxHIhPMtfD311wqnabQu7gndCzU1qm/r42VTNcg 90P/RvH0hxwEAB3YOsFKJNJY2GsAJw28Wm25C/TNYPwS6SRQ+MHWsoim7gLSjKrIFyin mqtMo4uqZ764FLyilebkRZn79XGx+p2ksdByxtygn9d0S5WGN4ynzc+r7nHnukO4R6NW HcGQiX11rd4D9GQbzATS4pa7YYD8mVSJBu7R9GLMXPXwAVY4uSOT83h30XVlCOXETS/2 7FHg== X-Gm-Message-State: AOAM533iGQbS27RQeJ39JS6JuJJoZiXtSuOofYVJjhMxaT0QPOfEw6rq P7fiUY0n84X0HQxbrCYJOkbHT5KRRlidag== X-Google-Smtp-Source: ABdhPJwm4rV4qie4xgiL8eUsen87hOQDpyTv20DpmknCbf+6dVLUQIn1cENHMNGupm6JIpgbxVoq3A== X-Received: by 2002:a17:90a:2d6:b0:1b8:cd70:697d with SMTP id d22-20020a17090a02d600b001b8cd70697dmr3293806pjd.78.1646724014245; Mon, 07 Mar 2022 23:20:14 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 03/33] target/nios2: Add NUM_GP_REGS and NUM_CP_REGS Date: Mon, 7 Mar 2022 21:19:35 -1000 Message-Id: <20220308072005.307955-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1034 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646724651880100001 Content-Type: text/plain; charset="utf-8" From: Amir Gonnen Split NUM_CORE_REGS into components that can be used elsewhere. Signed-off-by: Amir Gonnen Message-Id: <20220303153906.2024748-3-amir.gonnen@neuroblade.ai> [rth: Split out of a larger patch for shadow register sets.] Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/cpu.h | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index a00e4229ce..655a440033 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -57,9 +57,11 @@ struct Nios2CPUClass { #define EXCEPTION_ADDRESS 0x00000004 #define FAST_TLB_MISS_ADDRESS 0x00000008 =20 +#define NUM_GP_REGS 32 +#define NUM_CR_REGS 32 =20 /* GP regs + CR regs + PC */ -#define NUM_CORE_REGS (32 + 32 + 1) +#define NUM_CORE_REGS (NUM_GP_REGS + NUM_CR_REGS + 1) =20 /* General purpose register aliases */ #define R_ZERO 0 @@ -80,7 +82,7 @@ struct Nios2CPUClass { #define R_RA 31 =20 /* Control register aliases */ -#define CR_BASE 32 +#define CR_BASE NUM_GP_REGS #define CR_STATUS (CR_BASE + 0) #define CR_STATUS_PIE (1 << 0) #define CR_STATUS_U (1 << 1) --=20 2.25.1 From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646724463838744.6524287818223; Mon, 7 Mar 2022 23:27:43 -0800 (PST) Received: from localhost ([::1]:38952 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nRUFz-0007I3-HN for importer@patchew.org; Tue, 08 Mar 2022 02:27:43 -0500 Received: from eggs.gnu.org ([209.51.188.92]:44970) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nRU8q-00053E-QS for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:22 -0500 Received: from [2607:f8b0:4864:20::1029] (port=42770 helo=mail-pj1-x1029.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nRU8o-0006EQ-Fo for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:20 -0500 Received: by mail-pj1-x1029.google.com with SMTP id c16-20020a17090aa61000b001befad2bfaaso1595317pjq.1 for ; Mon, 07 Mar 2022 23:20:16 -0800 (PST) Received: from localhost.localdomain (cpe-50-113-46-110.hawaii.res.rr.com. [50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:15 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=K7spU4QOgMYXFOcsYuyZeK5HKFS4OU5xF4gFnu01zGk=; b=ABPbx/FPkBnIkIt020vUemRdBOGWO0FkmE6dhoYCG8LNrhnTnivt0J1legD/nxwDzU 9MzsQUQq3js4Hn2Y555VhkoLE+FoUNDFsU/U0QQJh8iiq4Zn4Mlyfq6IaZIBK+/ChBt5 LyBzFvwG1nPomeDlV9y8TrhwoAYTMFpuOVOkzhT5Xv7mTrwGP7s/R/OmD1DT6kM4wOFN GB/pdUZTl0G2cR37xFVoVdkO3k4ckuk7EdsbBw4xCiBfTY5Htf+fcfZE9A5yaQrEWqDj gMvg3CQaUHgzlImLha5FzpPnLAFOBSGF3Pya0higLQwR9XpD0Ww7+ZjvXaokKs5zL5uh hdMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=K7spU4QOgMYXFOcsYuyZeK5HKFS4OU5xF4gFnu01zGk=; b=bvSquvM2xc7olCYn8py+xqvikgfPSRZWRZrTyE3fg9L8QUOcXljyz7Ndx566uKJrCW icHKzPF0sUpFT5+/fJND3qPZT2CkJUa/cuknIvzw5COlcCXtudwWSdqxR6ZuoVEj8H/e qIu77M5H9T1CZBS4chLLNlYYAri/eO00JyMxKMg8kGqpwV7OIPXQXbvgaQuE8p4HZTvC FUOwvWdtn/v/HqX411rGyQqng3nsdy38WYumE0pRGS1E/4XmVJDgrJSBLVwXOsy6tPBM WNnZpAwG7S6Q596+DK9mXmxZ7FOeCO2TzTuNfb3qDMOBgmBuGwhlWjqTFmoYRYwGLe/v zKGA== X-Gm-Message-State: AOAM531UztJT7QkHxOXNBYmKUyWTtM9oHgRBscj2lTiB9jXZKfP/6KbW 6h0vLnAQkWBpGrXD9KdizXcqUrKc31EyAQ== X-Google-Smtp-Source: ABdhPJw67AxLUicGX3bV4QQSljTCSAodvwPMIB4VMQlwjvMZbU4GRKXNaNRqttzOI3S1nZHgdQtW+Q== X-Received: by 2002:a17:903:2308:b0:151:8b3a:e43e with SMTP id d8-20020a170903230800b001518b3ae43emr16060011plh.30.1646724015692; Mon, 07 Mar 2022 23:20:15 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 04/33] target/nios2: Split PC out of env->regs[] Date: Mon, 7 Mar 2022 21:19:36 -1000 Message-Id: <20220308072005.307955-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1029 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646724477184100001 Content-Type: text/plain; charset="utf-8" It is cleaner to have a separate name for this variable. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/cpu.h | 10 +++----- linux-user/elfload.c | 2 +- linux-user/nios2/cpu_loop.c | 17 ++++++------- linux-user/nios2/signal.c | 6 ++--- target/nios2/cpu.c | 8 +++--- target/nios2/helper.c | 51 +++++++++++++++++-------------------- target/nios2/translate.c | 26 ++++++++++--------- 7 files changed, 57 insertions(+), 63 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 655a440033..727d31c427 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -60,8 +60,8 @@ struct Nios2CPUClass { #define NUM_GP_REGS 32 #define NUM_CR_REGS 32 =20 -/* GP regs + CR regs + PC */ -#define NUM_CORE_REGS (NUM_GP_REGS + NUM_CR_REGS + 1) +/* GP regs + CR regs */ +#define NUM_CORE_REGS (NUM_GP_REGS + NUM_CR_REGS) =20 /* General purpose register aliases */ #define R_ZERO 0 @@ -131,9 +131,6 @@ struct Nios2CPUClass { #define CR_MPUBASE (CR_BASE + 14) #define CR_MPUACC (CR_BASE + 15) =20 -/* Other registers */ -#define R_PC 64 - /* Exceptions */ #define EXCP_BREAK 0x1000 #define EXCP_RESET 0 @@ -159,6 +156,7 @@ struct Nios2CPUClass { =20 struct CPUNios2State { uint32_t regs[NUM_CORE_REGS]; + uint32_t pc; =20 #if !defined(CONFIG_USER_ONLY) Nios2MMU mmu; @@ -242,7 +240,7 @@ typedef Nios2CPU ArchCPU; static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *= pc, target_ulong *cs_base, uint32_t *f= lags) { - *pc =3D env->regs[R_PC]; + *pc =3D env->pc; *cs_base =3D 0; *flags =3D (env->regs[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U)); } diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 9628a38361..23ff9659a5 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1170,7 +1170,7 @@ static void elf_core_copy_regs(target_elf_gregset_t *= regs, (*regs)[30] =3D -1; /* R_SSTATUS */ (*regs)[31] =3D tswapreg(env->regs[R_RA]); =20 - (*regs)[32] =3D tswapreg(env->regs[R_PC]); + (*regs)[32] =3D tswapreg(env->pc); =20 (*regs)[33] =3D -1; /* R_STATUS */ (*regs)[34] =3D tswapreg(env->regs[CR_ESTATUS]); diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index 1e93ef34e6..7b20c024db 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -56,25 +56,24 @@ void cpu_loop(CPUNios2State *env) env->regs[2] =3D abs(ret); /* Return value is 0..4096 */ env->regs[7] =3D ret > 0xfffff000u; - env->regs[R_PC] +=3D 4; + env->pc +=3D 4; break; =20 case 1: qemu_log_mask(CPU_LOG_INT, "\nTrap 1\n"); - force_sig_fault(TARGET_SIGUSR1, 0, env->regs[R_PC]); + force_sig_fault(TARGET_SIGUSR1, 0, env->pc); break; case 2: qemu_log_mask(CPU_LOG_INT, "\nTrap 2\n"); - force_sig_fault(TARGET_SIGUSR2, 0, env->regs[R_PC]); + force_sig_fault(TARGET_SIGUSR2, 0, env->pc); break; case 31: qemu_log_mask(CPU_LOG_INT, "\nTrap 31\n"); - force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->re= gs[R_PC]); + force_sig_fault(TARGET_SIGTRAP, TARGET_TRAP_BRKPT, env->pc= ); break; default: qemu_log_mask(CPU_LOG_INT, "\nTrap %d\n", env->error_code); - force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLTRP, - env->regs[R_PC]); + force_sig_fault(TARGET_SIGILL, TARGET_ILL_ILLTRP, env->pc); break; =20 case 16: /* QEMU specific, for __kuser_cmpxchg */ @@ -99,7 +98,7 @@ void cpu_loop(CPUNios2State *env) o =3D env->regs[5]; n =3D env->regs[6]; env->regs[2] =3D qatomic_cmpxchg(h, o, n) - o; - env->regs[R_PC] +=3D 4; + env->pc +=3D 4; } break; } @@ -117,7 +116,7 @@ void cpu_loop(CPUNios2State *env) info.si_errno =3D 0; /* TODO: check env->error_code */ info.si_code =3D TARGET_SEGV_MAPERR; - info._sifields._sigfault._addr =3D env->regs[R_PC]; + info._sifields._sigfault._addr =3D env->pc; queue_signal(env, info.si_signo, QEMU_SI_FAULT, &info); } break; @@ -155,6 +154,6 @@ void target_cpu_copy_regs(CPUArchState *env, struct tar= get_pt_regs *regs) env->regs[R_SP] =3D regs->sp; env->regs[R_GP] =3D regs->gp; env->regs[CR_ESTATUS] =3D regs->estatus; - env->regs[R_PC] =3D regs->ea; + env->pc =3D regs->ea; /* TODO: unsigned long orig_r7; */ } diff --git a/linux-user/nios2/signal.c b/linux-user/nios2/signal.c index 517cd39270..ccfaa75d3b 100644 --- a/linux-user/nios2/signal.c +++ b/linux-user/nios2/signal.c @@ -73,7 +73,7 @@ static void rt_setup_ucontext(struct target_ucontext *uc,= CPUNios2State *env) __put_user(env->regs[R_RA], &gregs[23]); __put_user(env->regs[R_FP], &gregs[24]); __put_user(env->regs[R_GP], &gregs[25]); - __put_user(env->regs[R_PC], &gregs[27]); + __put_user(env->pc, &gregs[27]); __put_user(env->regs[R_SP], &gregs[28]); } =20 @@ -122,7 +122,7 @@ static int rt_restore_ucontext(CPUNios2State *env, stru= ct target_ucontext *uc, __get_user(env->regs[R_GP], &gregs[25]); /* Not really necessary no user settable bits */ __get_user(temp, &gregs[26]); - __get_user(env->regs[R_PC], &gregs[27]); + __get_user(env->pc, &gregs[27]); =20 __get_user(env->regs[R_RA], &gregs[23]); __get_user(env->regs[R_SP], &gregs[28]); @@ -180,7 +180,7 @@ void setup_rt_frame(int sig, struct target_sigaction *k= a, env->regs[4] =3D sig; env->regs[5] =3D frame_addr + offsetof(struct target_rt_sigframe, info= ); env->regs[6] =3D frame_addr + offsetof(struct target_rt_sigframe, uc); - env->regs[R_PC] =3D ka->_sa_handler; + env->pc =3D ka->_sa_handler; =20 unlock_user_struct(frame, frame_addr, 1); } diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 6975ae4bdb..40031c9f20 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -31,7 +31,7 @@ static void nios2_cpu_set_pc(CPUState *cs, vaddr value) Nios2CPU *cpu =3D NIOS2_CPU(cs); CPUNios2State *env =3D &cpu->env; =20 - env->regs[R_PC] =3D value; + env->pc =3D value; } =20 static bool nios2_cpu_has_work(CPUState *cs) @@ -54,7 +54,7 @@ static void nios2_cpu_reset(DeviceState *dev) ncc->parent_reset(dev); =20 memset(env->regs, 0, sizeof(uint32_t) * NUM_CORE_REGS); - env->regs[R_PC] =3D cpu->reset_addr; + env->pc =3D cpu->reset_addr; =20 #if defined(CONFIG_USER_ONLY) /* Start in user mode with interrupts enabled. */ @@ -161,7 +161,7 @@ static int nios2_cpu_gdb_read_register(CPUState *cs, GB= yteArray *mem_buf, int n) if (n < 32) { /* GP regs */ return gdb_get_reg32(mem_buf, env->regs[n]); } else if (n =3D=3D 32) { /* PC */ - return gdb_get_reg32(mem_buf, env->regs[R_PC]); + return gdb_get_reg32(mem_buf, env->pc); } else if (n < 49) { /* Status regs */ return gdb_get_reg32(mem_buf, env->regs[n - 1]); } @@ -183,7 +183,7 @@ static int nios2_cpu_gdb_write_register(CPUState *cs, u= int8_t *mem_buf, int n) if (n < 32) { /* GP regs */ env->regs[n] =3D ldl_p(mem_buf); } else if (n =3D=3D 32) { /* PC */ - env->regs[R_PC] =3D ldl_p(mem_buf); + env->pc =3D ldl_p(mem_buf); } else if (n < 49) { /* Status regs */ env->regs[n - 1] =3D ldl_p(mem_buf); } diff --git a/target/nios2/helper.c b/target/nios2/helper.c index e5c98650e1..31cec29e89 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -35,7 +35,7 @@ void nios2_cpu_do_interrupt(CPUState *cs) Nios2CPU *cpu =3D NIOS2_CPU(cs); CPUNios2State *env =3D &cpu->env; cs->exception_index =3D -1; - env->regs[R_EA] =3D env->regs[R_PC] + 4; + env->regs[R_EA] =3D env->pc + 4; } =20 void nios2_cpu_record_sigsegv(CPUState *cs, vaddr addr, @@ -58,7 +58,7 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_IRQ: assert(env->regs[CR_STATUS] & CR_STATUS_PIE); =20 - qemu_log_mask(CPU_LOG_INT, "interrupt at pc=3D%x\n", env->regs[R_P= C]); + qemu_log_mask(CPU_LOG_INT, "interrupt at pc=3D%x\n", env->pc); =20 env->regs[CR_ESTATUS] =3D env->regs[CR_STATUS]; env->regs[CR_STATUS] |=3D CR_STATUS_IH; @@ -67,14 +67,13 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[CR_EXCEPTION] &=3D ~(0x1F << 2); env->regs[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; =20 - env->regs[R_EA] =3D env->regs[R_PC] + 4; - env->regs[R_PC] =3D cpu->exception_addr; + env->regs[R_EA] =3D env->pc + 4; + env->pc =3D cpu->exception_addr; break; =20 case EXCP_TLBD: if ((env->regs[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { - qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=3D%x\n", - env->regs[R_PC]); + qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=3D%x\n", env= ->pc); =20 /* Fast TLB miss */ /* Variation from the spec. Table 3-35 of the cpu reference sh= ows @@ -90,11 +89,10 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[CR_TLBMISC] &=3D ~CR_TLBMISC_DBL; env->regs[CR_TLBMISC] |=3D CR_TLBMISC_WR; =20 - env->regs[R_EA] =3D env->regs[R_PC] + 4; - env->regs[R_PC] =3D cpu->fast_tlb_miss_addr; + env->regs[R_EA] =3D env->pc + 4; + env->pc =3D cpu->fast_tlb_miss_addr; } else { - qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=3D%x\n", - env->regs[R_PC]); + qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=3D%x\n", e= nv->pc); =20 /* Double TLB miss */ env->regs[CR_STATUS] |=3D CR_STATUS_EH; @@ -105,14 +103,14 @@ void nios2_cpu_do_interrupt(CPUState *cs) =20 env->regs[CR_TLBMISC] |=3D CR_TLBMISC_DBL; =20 - env->regs[R_PC] =3D cpu->exception_addr; + env->pc =3D cpu->exception_addr; } break; =20 case EXCP_TLBR: case EXCP_TLBW: case EXCP_TLBX: - qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=3D%x\n", env->regs[R_PC= ]); + qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=3D%x\n", env->pc); =20 env->regs[CR_ESTATUS] =3D env->regs[CR_STATUS]; env->regs[CR_STATUS] |=3D CR_STATUS_EH; @@ -125,19 +123,18 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[CR_TLBMISC] |=3D CR_TLBMISC_WR; } =20 - env->regs[R_EA] =3D env->regs[R_PC] + 4; - env->regs[R_PC] =3D cpu->exception_addr; + env->regs[R_EA] =3D env->pc + 4; + env->pc =3D cpu->exception_addr; break; =20 case EXCP_SUPERA: case EXCP_SUPERI: case EXCP_SUPERD: - qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=3D%x\n", - env->regs[R_PC]); + qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=3D%x\n", en= v->pc); =20 if ((env->regs[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { env->regs[CR_ESTATUS] =3D env->regs[CR_STATUS]; - env->regs[R_EA] =3D env->regs[R_PC] + 4; + env->regs[R_EA] =3D env->pc + 4; } =20 env->regs[CR_STATUS] |=3D CR_STATUS_EH; @@ -146,17 +143,16 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[CR_EXCEPTION] &=3D ~(0x1F << 2); env->regs[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; =20 - env->regs[R_PC] =3D cpu->exception_addr; + env->pc =3D cpu->exception_addr; break; =20 case EXCP_ILLEGAL: case EXCP_TRAP: - qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=3D%x\n", - env->regs[R_PC]); + qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=3D%x\n", env->pc); =20 if ((env->regs[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { env->regs[CR_ESTATUS] =3D env->regs[CR_STATUS]; - env->regs[R_EA] =3D env->regs[R_PC] + 4; + env->regs[R_EA] =3D env->pc + 4; } =20 env->regs[CR_STATUS] |=3D CR_STATUS_EH; @@ -165,24 +161,23 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[CR_EXCEPTION] &=3D ~(0x1F << 2); env->regs[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; =20 - env->regs[R_PC] =3D cpu->exception_addr; + env->pc =3D cpu->exception_addr; break; =20 case EXCP_BREAK: - qemu_log_mask(CPU_LOG_INT, "BREAK exception at pc=3D%x\n", - env->regs[R_PC]); + qemu_log_mask(CPU_LOG_INT, "BREAK exception at pc=3D%x\n", env->pc= ); /* The semihosting instruction is "break 1". */ if (semihosting_enabled() && - cpu_ldl_code(env, env->regs[R_PC]) =3D=3D 0x003da07a) { + cpu_ldl_code(env, env->pc) =3D=3D 0x003da07a) { qemu_log_mask(CPU_LOG_INT, "Entering semihosting\n"); - env->regs[R_PC] +=3D 4; + env->pc +=3D 4; do_nios2_semihosting(env); break; } =20 if ((env->regs[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { env->regs[CR_BSTATUS] =3D env->regs[CR_STATUS]; - env->regs[R_BA] =3D env->regs[R_PC] + 4; + env->regs[R_BA] =3D env->pc + 4; } =20 env->regs[CR_STATUS] |=3D CR_STATUS_EH; @@ -191,7 +186,7 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->regs[CR_EXCEPTION] &=3D ~(0x1F << 2); env->regs[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; =20 - env->regs[R_PC] =3D cpu->exception_addr; + env->pc =3D cpu->exception_addr; break; =20 default: diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 1e0ab686dc..7a33181c4b 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -104,6 +104,7 @@ typedef struct DisasContext { } DisasContext; =20 static TCGv cpu_R[NUM_CORE_REGS]; +static TCGv cpu_pc; =20 typedef struct Nios2Instruction { void (*handler)(DisasContext *dc, uint32_t code, uint32_t flags); @@ -144,7 +145,7 @@ static void t_gen_helper_raise_exception(DisasContext *= dc, { TCGv_i32 tmp =3D tcg_const_i32(index); =20 - tcg_gen_movi_tl(cpu_R[R_PC], dc->pc); + tcg_gen_movi_tl(cpu_pc, dc->pc); gen_helper_raise_exception(cpu_env, tmp); tcg_temp_free_i32(tmp); dc->base.is_jmp =3D DISAS_NORETURN; @@ -156,10 +157,10 @@ static void gen_goto_tb(DisasContext *dc, int n, uint= 32_t dest) =20 if (translator_use_goto_tb(&dc->base, dest)) { tcg_gen_goto_tb(n); - tcg_gen_movi_tl(cpu_R[R_PC], dest); + tcg_gen_movi_tl(cpu_pc, dest); tcg_gen_exit_tb(tb, n); } else { - tcg_gen_movi_tl(cpu_R[R_PC], dest); + tcg_gen_movi_tl(cpu_pc, dest); tcg_gen_exit_tb(NULL, 0); } } @@ -391,7 +392,7 @@ static void eret(DisasContext *dc, uint32_t code, uint3= 2_t flags) } =20 tcg_gen_mov_tl(cpu_R[CR_STATUS], cpu_R[CR_ESTATUS]); - tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_EA]); + tcg_gen_mov_tl(cpu_pc, cpu_R[R_EA]); =20 dc->base.is_jmp =3D DISAS_JUMP; } @@ -399,7 +400,7 @@ static void eret(DisasContext *dc, uint32_t code, uint3= 2_t flags) /* PC <- ra */ static void ret(DisasContext *dc, uint32_t code, uint32_t flags) { - tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_RA]); + tcg_gen_mov_tl(cpu_pc, cpu_R[R_RA]); =20 dc->base.is_jmp =3D DISAS_JUMP; } @@ -407,7 +408,7 @@ static void ret(DisasContext *dc, uint32_t code, uint32= _t flags) /* PC <- ba */ static void bret(DisasContext *dc, uint32_t code, uint32_t flags) { - tcg_gen_mov_tl(cpu_R[R_PC], cpu_R[R_BA]); + tcg_gen_mov_tl(cpu_pc, cpu_R[R_BA]); =20 dc->base.is_jmp =3D DISAS_JUMP; } @@ -417,7 +418,7 @@ static void jmp(DisasContext *dc, uint32_t code, uint32= _t flags) { R_TYPE(instr, code); =20 - tcg_gen_mov_tl(cpu_R[R_PC], load_gpr(dc, instr.a)); + tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a)); =20 dc->base.is_jmp =3D DISAS_JUMP; } @@ -440,7 +441,7 @@ static void callr(DisasContext *dc, uint32_t code, uint= 32_t flags) { R_TYPE(instr, code); =20 - tcg_gen_mov_tl(cpu_R[R_PC], load_gpr(dc, instr.a)); + tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a)); tcg_gen_movi_tl(cpu_R[R_RA], dc->base.pc_next); =20 dc->base.is_jmp =3D DISAS_JUMP; @@ -827,7 +828,7 @@ static void nios2_tr_tb_stop(DisasContextBase *dcbase, = CPUState *cs) case DISAS_TOO_MANY: case DISAS_UPDATE: /* Save the current PC back into the CPU register */ - tcg_gen_movi_tl(cpu_R[R_PC], dc->base.pc_next); + tcg_gen_movi_tl(cpu_pc, dc->base.pc_next); tcg_gen_exit_tb(NULL, 0); break; =20 @@ -876,8 +877,7 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int fl= ags) return; } =20 - qemu_fprintf(f, "IN: PC=3D%x %s\n", - env->regs[R_PC], lookup_symbol(env->regs[R_PC])); + qemu_fprintf(f, "IN: PC=3D%x %s\n", env->pc, lookup_symbol(env->pc)); =20 for (i =3D 0; i < NUM_CORE_REGS; i++) { qemu_fprintf(f, "%9s=3D%8.8x ", regnames[i], env->regs[i]); @@ -903,10 +903,12 @@ void nios2_tcg_init(void) offsetof(CPUNios2State, regs[i]), regnames[i]); } + cpu_pc =3D tcg_global_mem_new(cpu_env, + offsetof(CPUNios2State, pc), "pc"); } =20 void restore_state_to_opc(CPUNios2State *env, TranslationBlock *tb, target_ulong *data) { - env->regs[R_PC] =3D data[0]; + env->pc =3D data[0]; } --=20 2.25.1 From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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[50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:16 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=15hlNvkyzEehRLy4eHDGVhK7xmnt7sbQeH8nIQruRKI=; b=OcuPWW8CBK5KPIvopeaLtqgADr8x8lWQOTYM7mCvpDmTWljIkzXtuhl5on/b9pufXu dc9vpEC1+U/SopFjuufECiwlxJblgcL1RahGMQia+xG6T48KVvc8ldgIanKh7rvFJxaI dPYAm1yQx92FIluP25uZM+HmKtMkIZr57RwUcEtjtTGEgnY6xITa2a65nxevWblt8gpq 4mB1/8RXRxDppjk6j3mRbB+dbJrRrrWxN8QW4uBLGghaZExB6HNv09Z29BB5hVhhSDEl LxgVkjki+5dyBombZIDQS4qOwUb41DHTItjEq9XwTO/CQTp6tXit3y/tG7pbO3lYQL0q v37Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=15hlNvkyzEehRLy4eHDGVhK7xmnt7sbQeH8nIQruRKI=; b=tjXLsdgMVGQNcvtFttJ2NFJAVy5m5pHRqiujYjNFKuO4sUaAm8aLXiN+3w1eBB7M+v 4tg6QQiaQM3XxvwSMG/tJxuz/wSgqygcOKApHmc9C4OiaLMuI3PZGqEr4QeALHdiryPH LFI625zF/sAIyjUO3Ppo4uKJid1X2cthGtXu1abc41BJrk/8/F6vSekBQv9g77c1hZ+e pA4Yl3pTjC645S4qS9T3bn07dPSs1LFxYdp3O81ZLmumsEWRrUGXmPnBJFGAxsL/sUpN YFHd5mCqSQPsSjTqFzjpjl8xErsH4VkUHxnyK8kaPQQDugBuvX85QF/hrxQm1EOCZadb bZkw== X-Gm-Message-State: AOAM530Zf8YFnIxItKwqr9g/PRtmPQWiXCAM2Ddp7JlJ43KGaymBx68l sGw6lsmOe+Z/C8bJgcP4k7AVdlVtKudNAQ== X-Google-Smtp-Source: ABdhPJxWoMMuItrZdPMniD+QjjhT46husUjdCUCejuIXUmA8j6K2pJ6qMhB8dkwj/YmNgKIjhtcPrA== X-Received: by 2002:a05:6a00:244d:b0:4e0:1f65:d5da with SMTP id d13-20020a056a00244d00b004e01f65d5damr16909243pfj.6.1646724017243; Mon, 07 Mar 2022 23:20:17 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 05/33] target/nios2: Split out helper for eret instruction Date: Mon, 7 Mar 2022 21:19:37 -1000 Message-Id: <20220308072005.307955-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::432 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646724418174100001 Content-Type: text/plain; charset="utf-8" From: Amir Gonnen The implementation of eret will become much more complex with the introduction of shadow registers. Signed-off-by: Amir Gonnen Message-Id: <20220303153906.2024748-3-amir.gonnen@neuroblade.ai> [rth: Split out of a larger patch for shadow register sets. Directly exit to the cpu loop from the helper.] Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/helper.h | 1 + target/nios2/op_helper.c | 9 +++++++++ target/nios2/translate.c | 10 ++++++---- 3 files changed, 16 insertions(+), 4 deletions(-) diff --git a/target/nios2/helper.h b/target/nios2/helper.h index a44ecfdf7a..02797c384d 100644 --- a/target/nios2/helper.h +++ b/target/nios2/helper.h @@ -21,6 +21,7 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noreturn, env, i32) =20 #if !defined(CONFIG_USER_ONLY) +DEF_HELPER_2(eret, noreturn, env, i32) DEF_HELPER_2(mmu_write_tlbacc, void, env, i32) DEF_HELPER_2(mmu_write_tlbmisc, void, env, i32) DEF_HELPER_2(mmu_write_pteaddr, void, env, i32) diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index caa885f7b4..df48e82cc2 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -30,3 +30,12 @@ void helper_raise_exception(CPUNios2State *env, uint32_t= index) cs->exception_index =3D index; cpu_loop_exit(cs); } + +#ifndef CONFIG_USER_ONLY +void helper_eret(CPUNios2State *env, uint32_t new_pc) +{ + env->regs[CR_STATUS] =3D env->regs[CR_ESTATUS]; + env->pc =3D new_pc; + cpu_loop_exit(env_cpu(env)); +} +#endif /* !CONFIG_USER_ONLY */ diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 7a33181c4b..fe21bf45af 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -391,10 +391,12 @@ static void eret(DisasContext *dc, uint32_t code, uin= t32_t flags) return; } =20 - tcg_gen_mov_tl(cpu_R[CR_STATUS], cpu_R[CR_ESTATUS]); - tcg_gen_mov_tl(cpu_pc, cpu_R[R_EA]); - - dc->base.is_jmp =3D DISAS_JUMP; +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + gen_helper_eret(cpu_env, cpu_R[R_EA]); + dc->base.is_jmp =3D DISAS_NORETURN; +#endif } =20 /* PC <- ra */ --=20 2.25.1 From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646724754545372.0284199668183; Mon, 7 Mar 2022 23:32:34 -0800 (PST) Received: from localhost ([::1]:47486 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nRUKf-0004i2-ER for importer@patchew.org; Tue, 08 Mar 2022 02:32:33 -0500 Received: from eggs.gnu.org ([209.51.188.92]:44978) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nRU8r-00053S-JW for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:23 -0500 Received: from [2607:f8b0:4864:20::636] (port=33745 helo=mail-pl1-x636.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nRU8q-0006Gu-5E for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:21 -0500 Received: by mail-pl1-x636.google.com with SMTP id m2so10296940pll.0 for ; Mon, 07 Mar 2022 23:20:19 -0800 (PST) Received: from localhost.localdomain (cpe-50-113-46-110.hawaii.res.rr.com. [50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:18 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Hnm7ONwW3b6w8PSvN2V8w956oTjdf4vnzb4T0LKj/Ww=; b=NpafVhxgGT1tHKxyOFWMUigif028Z986BPrw0QzES9dwjx8d+jxCXF5x2TNQD3hfBx qU6wq2D8ftvYXfshIhDFXVIcn2Ypsem8xhptKz0TIbWdKEGLQC96qrokpWDaiRHyi81I cgN+UnAtR+7pFLzSKy36YcD3rb26yv6E+FchXOrjOjggVp9XnR9K9ZQOgvB8XEi2SIsR FUfK1BEMLJsvLiq5eoWeXWN1V2CqXXtCshKGN7CYoXN3fC4v9bLZkC6qyDK4CTs+nQcY XIGc7p89vWlEQB7kf3jeBg4qJB9Kmm96HColctzz//3Fon1qfKeIm4/pq0XeVpT6U69W yK9Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Hnm7ONwW3b6w8PSvN2V8w956oTjdf4vnzb4T0LKj/Ww=; b=gECztkH+66dPJKYw5r3aPSYA9wUbVgHZTT6hQUrFnHb5hI62qPjuP1QWCK0MyhlpiL yMq8MdWaAkDOX0FyZndQCo+7048QoACvrzBcTZUMzTMkAunldPMcnzgnt3ZOliMx3gAO vcuPWOzTFtGA+ZKSf+4uk31Tdt84YWLIWD9kO+PuGvszNJCItWHHsmka6j/SbuMVzeCg LQrPJIblnwRw3JseHj0VsTGEbBgOIWz5+unXWQxJgOnOWbTpR7StbxMLP2lJZk+KqFa7 cNFZP8i6DOOD/DXX0FYh++5DP46dYcLL39GbgmJ3PRn1PT0YVWe1YbkQ4SCS69MaI/CP Y4dA== X-Gm-Message-State: AOAM530q9gVPVa/JMmJWf4E96eUiwWg7npMIGQMX57/Lo8Vag7Z8+VVb tOcXh8hVo8mOYOQ1Iufjp9AO+YBmYUAhkQ== X-Google-Smtp-Source: ABdhPJxlvAd3g12NPD/NckVQxV9n5xxNN4w370JOlHoR0WtWW+bxpBmjN351j47COW66sBENw55jtw== X-Received: by 2002:a17:90a:1188:b0:1bd:36d0:d7b2 with SMTP id e8-20020a17090a118800b001bd36d0d7b2mr3151245pja.223.1646724018837; Mon, 07 Mar 2022 23:20:18 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 06/33] target/nios2: Do not create TCGv for control registers Date: Mon, 7 Mar 2022 21:19:38 -1000 Message-Id: <20220308072005.307955-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::636 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646724756378100001 Content-Type: text/plain; charset="utf-8" We don't need to reference them often, and when we do it is just as easy to load/store from cpu_env directly. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/translate.c | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index fe21bf45af..cefdcea81e 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -103,7 +103,7 @@ typedef struct DisasContext { int mem_idx; } DisasContext; =20 -static TCGv cpu_R[NUM_CORE_REGS]; +static TCGv cpu_R[NUM_GP_REGS]; static TCGv cpu_pc; =20 typedef struct Nios2Instruction { @@ -453,6 +453,7 @@ static void callr(DisasContext *dc, uint32_t code, uint= 32_t flags) static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, code); + TCGv t1, t2; =20 if (!gen_check_supervisor(dc)) { return; @@ -472,10 +473,19 @@ static void rdctl(DisasContext *dc, uint32_t code, ui= nt32_t flags) * must perform the AND here, and anywhere else we need the * guest value of ipending. */ - tcg_gen_and_tl(cpu_R[instr.c], cpu_R[CR_IPENDING], cpu_R[CR_IENABL= E]); + t1 =3D tcg_temp_new(); + t2 =3D tcg_temp_new(); + tcg_gen_ld_tl(t1, cpu_env, + offsetof(CPUNios2State, regs[CR_IPENDING])); + tcg_gen_ld_tl(t2, cpu_env, + offsetof(CPUNios2State, regs[CR_IENABLE])); + tcg_gen_and_tl(cpu_R[instr.c], t1, t2); + tcg_temp_free(t1); + tcg_temp_free(t2); break; default: - tcg_gen_mov_tl(cpu_R[instr.c], cpu_R[instr.imm5 + CR_BASE]); + tcg_gen_ld_tl(cpu_R[instr.c], cpu_env, + offsetof(CPUNios2State, regs[instr.imm5 + CR_BASE])); break; } } @@ -512,7 +522,8 @@ static void wrctl(DisasContext *dc, uint32_t code, uint= 32_t flags) dc->base.is_jmp =3D DISAS_UPDATE; /* fall through */ default: - tcg_gen_mov_tl(cpu_R[instr.imm5 + CR_BASE], v); + tcg_gen_st_tl(v, cpu_env, + offsetof(CPUNios2State, regs[instr.imm5 + CR_BASE])); break; } #endif @@ -900,7 +911,7 @@ void nios2_tcg_init(void) { int i; =20 - for (i =3D 0; i < NUM_CORE_REGS; i++) { + for (i =3D 0; i < NUM_GP_REGS; i++) { cpu_R[i] =3D tcg_global_mem_new(cpu_env, offsetof(CPUNios2State, regs[i]), regnames[i]); --=20 2.25.1 From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646724930065446.0060402834712; Mon, 7 Mar 2022 23:35:30 -0800 (PST) Received: from localhost ([::1]:56066 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nRUNU-0001zS-T6 for importer@patchew.org; Tue, 08 Mar 2022 02:35:28 -0500 Received: from eggs.gnu.org ([209.51.188.92]:44994) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nRU8t-00053f-8S for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:23 -0500 Received: from [2607:f8b0:4864:20::631] (port=39820 helo=mail-pl1-x631.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nRU8r-0006HO-Mz for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:22 -0500 Received: by mail-pl1-x631.google.com with SMTP id 9so16270797pll.6 for ; Mon, 07 Mar 2022 23:20:21 -0800 (PST) Received: from localhost.localdomain (cpe-50-113-46-110.hawaii.res.rr.com. [50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:20 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=R0uQojsF6Si9+ZGBrS1uBiVdf/vsBcUNuv5jEVpHMiw=; b=CaBb2t3i0XB2x91r+eFkXRZlMuEusdlfAVRpOqmUMgOP/BDfrgslv5WefG/spgbCgp QDyXY95oZPH92WQ0CIYN6FE57lhz4yubPUrb74r623fLy4r444vz7JEVhM0vMP3nVJ/s Wc8NtTFWL7nnMaa0Mq8RQqdqQsViHqqrNo6CDaHl+1sCXYaRDy+WR6bNoE1rtl3kWrbP iB20eyxcHKJGHXMD9VynwAaryZzGP0SobKZCQ0FhF3bM59B9ujFi1arFbPvXYv1aL1xk MLDAKxyckH5tKQbj26slGRkdjGbVCPyQb96657GzRmxZ2t83u2KcbhySFlwHyndP2fVu aDzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=R0uQojsF6Si9+ZGBrS1uBiVdf/vsBcUNuv5jEVpHMiw=; b=wvdtidK7IorUTxz32tfE89leJvaS9kz511bHyHy4/AusyEVHfw1UDPQ5wpO6AGoxER 6s/1OOnrbTyZy1eZpJbcLpBF/rSVkLu9sQryBGeSPUqD/GP7OfMJjjW9oGSDje2XLb0R kFO3nmYr0znSEVcQTzPsCaSG7D3kIoQbUGBt9KhBZBrarOF/SOAaTFQzCQSatq+6Z3Jv KAHtjRBl3cdKoVpM/LVKTWR9lRjdlgLmtHN0lG+dWapPqBJZ98ycUIjD5PnTSLt/wCqm R1T4IbgecPz5uTvVtOgd3Ctm61NG3/f1fu6wxIUztEQ5p4/WymGTLnt6yQpc9vxfvs5A W6XA== X-Gm-Message-State: AOAM531kD66l8VRZMYadoA1VqsxyVoi2tA84+/KqCwJgNxmTQd1zmmQV jv2YERL6IMCPZth5Yx/z2HG79mZA4sHhfg== X-Google-Smtp-Source: ABdhPJxUB0gi4gU0WYQvjEIPtPv7u/dbjKmWkVsNCQqkcrTjTS+60umD79qj4AS/TqhfDTPT2GmxSQ== X-Received: by 2002:a17:90a:7c09:b0:1bc:a2fd:d4d8 with SMTP id v9-20020a17090a7c0900b001bca2fdd4d8mr3249060pjf.73.1646724020475; Mon, 07 Mar 2022 23:20:20 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 07/33] linux-user/nios2: Trim target_pc_regs to sp and pc Date: Mon, 7 Mar 2022 21:19:39 -1000 Message-Id: <20220308072005.307955-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::631 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646724932339100001 Content-Type: text/plain; charset="utf-8" The only thing this struct is used for is passing startup values from elfload.c to the cpu. We do not need all registers to be represented, we do not need the kernel internal stack slots. The userland argc, argv, and envp values are passed on the stack, so only SP and PC need updating. Signed-off-by: Richard Henderson --- linux-user/nios2/target_syscall.h | 25 ++----------------------- linux-user/elfload.c | 3 +-- linux-user/nios2/cpu_loop.c | 24 +----------------------- 3 files changed, 4 insertions(+), 48 deletions(-) diff --git a/linux-user/nios2/target_syscall.h b/linux-user/nios2/target_sy= scall.h index 561b28d281..0999ce25fd 100644 --- a/linux-user/nios2/target_syscall.h +++ b/linux-user/nios2/target_syscall.h @@ -5,29 +5,8 @@ #define UNAME_MINIMUM_RELEASE "3.19.0" =20 struct target_pt_regs { - unsigned long r8; /* r8-r15 Caller-saved GP registers */ - unsigned long r9; - unsigned long r10; - unsigned long r11; - unsigned long r12; - unsigned long r13; - unsigned long r14; - unsigned long r15; - unsigned long r1; /* Assembler temporary */ - unsigned long r2; /* Retval LS 32bits */ - unsigned long r3; /* Retval MS 32bits */ - unsigned long r4; /* r4-r7 Register arguments */ - unsigned long r5; - unsigned long r6; - unsigned long r7; - unsigned long orig_r2; /* Copy of r2 ?? */ - unsigned long ra; /* Return address */ - unsigned long fp; /* Frame pointer */ - unsigned long sp; /* Stack pointer */ - unsigned long gp; /* Global pointer */ - unsigned long estatus; - unsigned long ea; /* Exception return address (pc) */ - unsigned long orig_r7; + target_ulong sp; + target_ulong pc; }; =20 #define TARGET_MCL_CURRENT 1 diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 23ff9659a5..cb14c5f786 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -1094,9 +1094,8 @@ static void elf_core_copy_regs(target_elf_gregset_t *= regs, const CPUMBState *env =20 static void init_thread(struct target_pt_regs *regs, struct image_info *in= fop) { - regs->ea =3D infop->entry; + regs->pc =3D infop->entry; regs->sp =3D infop->start_stack; - regs->estatus =3D 0x3; } =20 #define LO_COMMPAGE TARGET_PAGE_SIZE diff --git a/linux-user/nios2/cpu_loop.c b/linux-user/nios2/cpu_loop.c index 7b20c024db..37e1dfecfd 100644 --- a/linux-user/nios2/cpu_loop.c +++ b/linux-user/nios2/cpu_loop.c @@ -132,28 +132,6 @@ void cpu_loop(CPUNios2State *env) =20 void target_cpu_copy_regs(CPUArchState *env, struct target_pt_regs *regs) { - env->regs[0] =3D 0; - env->regs[1] =3D regs->r1; - env->regs[2] =3D regs->r2; - env->regs[3] =3D regs->r3; - env->regs[4] =3D regs->r4; - env->regs[5] =3D regs->r5; - env->regs[6] =3D regs->r6; - env->regs[7] =3D regs->r7; - env->regs[8] =3D regs->r8; - env->regs[9] =3D regs->r9; - env->regs[10] =3D regs->r10; - env->regs[11] =3D regs->r11; - env->regs[12] =3D regs->r12; - env->regs[13] =3D regs->r13; - env->regs[14] =3D regs->r14; - env->regs[15] =3D regs->r15; - /* TODO: unsigned long orig_r2; */ - env->regs[R_RA] =3D regs->ra; - env->regs[R_FP] =3D regs->fp; env->regs[R_SP] =3D regs->sp; - env->regs[R_GP] =3D regs->gp; - env->regs[CR_ESTATUS] =3D regs->estatus; - env->pc =3D regs->ea; - /* TODO: unsigned long orig_r7; */ + env->pc =3D regs->pc; } --=20 2.25.1 From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646724223258520.0047368948731; Mon, 7 Mar 2022 23:23:43 -0800 (PST) Received: from localhost ([::1]:55846 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nRUC5-00084h-Ss for importer@patchew.org; Tue, 08 Mar 2022 02:23:41 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45020) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nRU8u-000543-NG for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:25 -0500 Received: from [2607:f8b0:4864:20::432] (port=40552 helo=mail-pf1-x432.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nRU8t-0006HX-7p for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:24 -0500 Received: by mail-pf1-x432.google.com with SMTP id z15so16591677pfe.7 for ; Mon, 07 Mar 2022 23:20:22 -0800 (PST) Received: from localhost.localdomain (cpe-50-113-46-110.hawaii.res.rr.com. [50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:21 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=e3XWYwJGO3vo3kGqcNerNP/pWqNfUjJJeLFVpgy1IoI=; b=znPXSUpEsY1RUK6/908Q+Z+XBj4mQKT35Szu0tsWLiDznRtox+iByActGl4QztoLGW s9bkyGaA1n8FM8C2eAvqQwWkyDuQ3Nq4tLXqhoJzTj7VviIRm0d2kcu+9xcq/WkqC+91 auPUBZmGku0qzHW+arwybot6N+K0VKOCygRxaSSfx7kqizN9f311G6fhFP8IKna+nRV8 eVVVtis6GfLpePvmGCYxEQdrqrIlJJpSI4/FCuz9xx7HgUQfd4kjnncV3iRti6PZpmKF /sOtzAWAxokWTgGyX9AqU17ZXr9TmSRO98AEykh50E03gKoVlCQjlcf9y0HHeGZdEBvA vB/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=e3XWYwJGO3vo3kGqcNerNP/pWqNfUjJJeLFVpgy1IoI=; b=52fi9E3FwLPpm1ydkcV2Pxu6o+lG9BSuOH9NkG5efHTSVj2dRL8/p/phIWAlc5KKbR AAE8I90AUKWTjtPhw0EeYJi3U3T9HjmKlzkT1cdvLQEWu4eyNtx6Kh13Zv4Cfft84DEZ L1RI8YIXlOp3zm4vovQ5suhu3hwLwvBTA8byUJksYuqrJ7zMzdzwCWEqTQVrYWJX3Hlt jsfUPD8EohKr3yvQ4qC6V4JsEbkw2NHwR3WNeegqeDz3lHQ4YVUc4s2s3FyJWQyxy0ps d7oRJtDt8rdDqX7zEqSxijgV4o1OCi6Gv8GyvD+ivruqKHK3GHjET8TYpEcKH2inAhLR /8Zw== X-Gm-Message-State: AOAM530s4NcCpTLGhCiPTlg0HgoAj29tqK49uzWzC0kRqZLtD94Si7CI JiuqyihcOvtbYijQt6v/Gueo7XF+qBqqVw== X-Google-Smtp-Source: ABdhPJzQ2UHVrnTq+rjgTD5Pd4eCdFMGw99CO6mo7TUNQSpaEVem4ri8bNAHneZtY1XCT6sgDEZmXQ== X-Received: by 2002:a05:6a00:1747:b0:4f3:e449:4416 with SMTP id j7-20020a056a00174700b004f3e4494416mr17159733pfc.5.1646724021921; Mon, 07 Mar 2022 23:20:21 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 08/33] target/nios2: Remove cpu_interrupts_enabled Date: Mon, 7 Mar 2022 21:19:40 -1000 Message-Id: <20220308072005.307955-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::432 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646724224582100005 Content-Type: text/plain; charset="utf-8" This function is unused. The real computation of this value is located in nios2_cpu_exec_interrupt. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/cpu.h | 5 ----- 1 file changed, 5 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 727d31c427..14ed46959e 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -227,11 +227,6 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, bool probe, uintptr_t retaddr); #endif =20 -static inline int cpu_interrupts_enabled(CPUNios2State *env) -{ - return env->regs[CR_STATUS] & CR_STATUS_PIE; -} - typedef CPUNios2State CPUArchState; typedef Nios2CPU ArchCPU; =20 --=20 2.25.1 From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646724229050805.1005783133207; Mon, 7 Mar 2022 23:23:49 -0800 (PST) Received: from localhost ([::1]:56080 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nRUCA-0008E0-Jf for importer@patchew.org; Tue, 08 Mar 2022 02:23:46 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45074) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nRU8x-0005Am-W2 for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:28 -0500 Received: from [2607:f8b0:4864:20::629] (port=44570 helo=mail-pl1-x629.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nRU8v-0006If-AM for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:27 -0500 Received: by mail-pl1-x629.google.com with SMTP id q11so16256809pln.11 for ; Mon, 07 Mar 2022 23:20:24 -0800 (PST) Received: from localhost.localdomain (cpe-50-113-46-110.hawaii.res.rr.com. [50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:23 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PHw2y9jEMO4HNJw5xlyH1ECNJ5zOL06JjcE8T+b9GzY=; b=ut59PDrbanekw6CqbVC5bOtw11/YxffcogzlPiWgOT6S0JeVQ/eEB9kTDB9ceaaZkL mRnkTkR2kHfdFco0xSBx1aviAyz+J6BPzkBDqQAcQAweoThbBz9eUYWQc2Y9TxV5Ou9E jrohkrTighIvojLOtm9DsYcojKBPqfV+dVTUirM5oDhceD7/8MfEP7HrtPBn6v6SpFir JU1tLmMZC98CKFlAw3yP2WozLRVbpFZkYHzftW79RjDUSRMqYiP4Kfk7MTJSbh51APh9 KLgwX1CbJgrTxAYyvlYdaa3mOYl11xb48KCV41CMoIUjdiGDDpJtvMV15oqSsp3u9xDz 7Skw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PHw2y9jEMO4HNJw5xlyH1ECNJ5zOL06JjcE8T+b9GzY=; b=hVxRu9xermR185JAuiu10WpR8QqPlCp71Z97wuE9HAsT3vFmksS4P3spQDk9GQEUtQ pV91rt2M7QoIY1N8TXsltyKrAQeI00Jscuf7HblnFD58UuK/hvm/dNhWvYmzwveBrgQ8 lR7oK/CrBLVu/VqAwtEfP7v8jRgMTkzC2fX+W+lq/7lgV3AvGA5lQWNFEMi9DO90kI3u jDvA/2GkntGAdjZellIm4KMme0S/SLp2Ax+HfcaNxdhZMjfo8gpWQnasOu6kkxWw2vKG 0QvzTIoiLOy5ZvVFcCXVle3RnBv8+cyvsqoq8cAV59KLc+MVCqfu/PI0BXhO2J7QmkEX mK0g== X-Gm-Message-State: AOAM531Gsh8azEbu/q0GSU/OlPJbcxjW3QD2wW2N4hd5qv2ErvzaYKRz gFIGTJTfYnawtqqjs+GIDgbhSOh/o/+yZw== X-Google-Smtp-Source: ABdhPJxuON2xMMBciqdO5sl4hfSsw7NYZ+FxpX1EyMWbEerDmgzEBlVbyriLp+g0ic2PxyGP7N98GA== X-Received: by 2002:a17:903:2c7:b0:14f:522c:d33c with SMTP id s7-20020a17090302c700b0014f522cd33cmr15883737plk.143.1646724023613; Mon, 07 Mar 2022 23:20:23 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 09/33] target/nios2: Split control registers away from general registers Date: Mon, 7 Mar 2022 21:19:41 -1000 Message-Id: <20220308072005.307955-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::629 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646724230780100001 Content-Type: text/plain; charset="utf-8" Place the control registers into their own array, env->ctrl[]. Use an anonymous union and struct to give the entries in the array distinct names, so that one may write env->foo instead of env->ctrl[CR_FOO]. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/cpu.h | 64 ++++++++++++++--------- target/nios2/cpu.c | 19 +++---- target/nios2/helper.c | 106 +++++++++++++++++++-------------------- target/nios2/mmu.c | 26 +++++----- target/nios2/op_helper.c | 2 +- target/nios2/translate.c | 31 +++++++----- 6 files changed, 136 insertions(+), 112 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 14ed46959e..5bc0e353b4 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -60,9 +60,6 @@ struct Nios2CPUClass { #define NUM_GP_REGS 32 #define NUM_CR_REGS 32 =20 -/* GP regs + CR regs */ -#define NUM_CORE_REGS (NUM_GP_REGS + NUM_CR_REGS) - /* General purpose register aliases */ #define R_ZERO 0 #define R_AT 1 @@ -82,8 +79,7 @@ struct Nios2CPUClass { #define R_RA 31 =20 /* Control register aliases */ -#define CR_BASE NUM_GP_REGS -#define CR_STATUS (CR_BASE + 0) +#define CR_STATUS 0 #define CR_STATUS_PIE (1 << 0) #define CR_STATUS_U (1 << 1) #define CR_STATUS_EH (1 << 2) @@ -93,19 +89,19 @@ struct Nios2CPUClass { #define CR_STATUS_PRS (63 << 16) #define CR_STATUS_NMI (1 << 22) #define CR_STATUS_RSIE (1 << 23) -#define CR_ESTATUS (CR_BASE + 1) -#define CR_BSTATUS (CR_BASE + 2) -#define CR_IENABLE (CR_BASE + 3) -#define CR_IPENDING (CR_BASE + 4) -#define CR_CPUID (CR_BASE + 5) -#define CR_CTL6 (CR_BASE + 6) -#define CR_EXCEPTION (CR_BASE + 7) -#define CR_PTEADDR (CR_BASE + 8) +#define CR_ESTATUS 1 +#define CR_BSTATUS 2 +#define CR_IENABLE 3 +#define CR_IPENDING 4 +#define CR_CPUID 5 +#define CR_CTL6 6 +#define CR_EXCEPTION 7 +#define CR_PTEADDR 8 #define CR_PTEADDR_PTBASE_SHIFT 22 #define CR_PTEADDR_PTBASE_MASK (0x3FF << CR_PTEADDR_PTBASE_SHIFT) #define CR_PTEADDR_VPN_SHIFT 2 #define CR_PTEADDR_VPN_MASK (0xFFFFF << CR_PTEADDR_VPN_SHIFT) -#define CR_TLBACC (CR_BASE + 9) +#define CR_TLBACC 9 #define CR_TLBACC_IGN_SHIFT 25 #define CR_TLBACC_IGN_MASK (0x7F << CR_TLBACC_IGN_SHIFT) #define CR_TLBACC_C (1 << 24) @@ -114,7 +110,7 @@ struct Nios2CPUClass { #define CR_TLBACC_X (1 << 21) #define CR_TLBACC_G (1 << 20) #define CR_TLBACC_PFN_MASK 0x000FFFFF -#define CR_TLBMISC (CR_BASE + 10) +#define CR_TLBMISC 10 #define CR_TLBMISC_WAY_SHIFT 20 #define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT) #define CR_TLBMISC_RD (1 << 19) @@ -125,11 +121,11 @@ struct Nios2CPUClass { #define CR_TLBMISC_BAD (1 << 2) #define CR_TLBMISC_PERM (1 << 1) #define CR_TLBMISC_D (1 << 0) -#define CR_ENCINJ (CR_BASE + 11) -#define CR_BADADDR (CR_BASE + 12) -#define CR_CONFIG (CR_BASE + 13) -#define CR_MPUBASE (CR_BASE + 14) -#define CR_MPUACC (CR_BASE + 15) +#define CR_ENCINJ 11 +#define CR_BADADDR 12 +#define CR_CONFIG 13 +#define CR_MPUBASE 14 +#define CR_MPUACC 15 =20 /* Exceptions */ #define EXCP_BREAK 0x1000 @@ -155,7 +151,28 @@ struct Nios2CPUClass { #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 =20 struct CPUNios2State { - uint32_t regs[NUM_CORE_REGS]; + uint32_t regs[NUM_GP_REGS]; + union { + uint32_t ctrl[NUM_CR_REGS]; + struct { + uint32_t status; + uint32_t estatus; + uint32_t bstatus; + uint32_t ienable; + uint32_t ipending; + uint32_t cpuid; + uint32_t reserved6; + uint32_t exception; + uint32_t pteaddr; + uint32_t tlbacc; + uint32_t tlbmisc; + uint32_t eccinj; + uint32_t badaddr; + uint32_t config; + uint32_t mpubase; + uint32_t mpuacc; + }; + }; uint32_t pc; =20 #if !defined(CONFIG_USER_ONLY) @@ -213,8 +230,7 @@ void do_nios2_semihosting(CPUNios2State *env); =20 static inline int cpu_mmu_index(CPUNios2State *env, bool ifetch) { - return (env->regs[CR_STATUS] & CR_STATUS_U) ? MMU_USER_IDX : - MMU_SUPERVISOR_IDX; + return (env->status & CR_STATUS_U) ? MMU_USER_IDX : MMU_SUPERVISOR_IDX; } =20 #ifdef CONFIG_USER_ONLY @@ -237,7 +253,7 @@ static inline void cpu_get_tb_cpu_state(CPUNios2State *= env, target_ulong *pc, { *pc =3D env->pc; *cs_base =3D 0; - *flags =3D (env->regs[CR_STATUS] & (CR_STATUS_EH | CR_STATUS_U)); + *flags =3D env->status & (CR_STATUS_EH | CR_STATUS_U); } =20 #endif /* NIOS2_CPU_H */ diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 40031c9f20..f2813d3b47 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -53,14 +53,15 @@ static void nios2_cpu_reset(DeviceState *dev) =20 ncc->parent_reset(dev); =20 - memset(env->regs, 0, sizeof(uint32_t) * NUM_CORE_REGS); + memset(env->regs, 0, sizeof(env->regs)); + memset(env->ctrl, 0, sizeof(env->ctrl)); env->pc =3D cpu->reset_addr; =20 #if defined(CONFIG_USER_ONLY) /* Start in user mode with interrupts enabled. */ - env->regs[CR_STATUS] =3D CR_STATUS_U | CR_STATUS_PIE; + env->status =3D CR_STATUS_U | CR_STATUS_PIE; #else - env->regs[CR_STATUS] =3D 0; + env->status =3D 0; #endif } =20 @@ -71,9 +72,9 @@ static void nios2_cpu_set_irq(void *opaque, int irq, int = level) CPUNios2State *env =3D &cpu->env; CPUState *cs =3D CPU(cpu); =20 - env->regs[CR_IPENDING] =3D deposit32(env->regs[CR_IPENDING], irq, 1, != !level); + env->ipending =3D deposit32(env->ipending, irq, 1, !!level); =20 - if (env->regs[CR_IPENDING]) { + if (env->ipending) { cpu_interrupt(cs, CPU_INTERRUPT_HARD); } else { cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); @@ -131,8 +132,8 @@ static bool nios2_cpu_exec_interrupt(CPUState *cs, int = interrupt_request) CPUNios2State *env =3D &cpu->env; =20 if ((interrupt_request & CPU_INTERRUPT_HARD) && - (env->regs[CR_STATUS] & CR_STATUS_PIE) && - (env->regs[CR_IPENDING] & env->regs[CR_IENABLE])) { + (env->status & CR_STATUS_PIE) && + (env->ipending & env->ienable)) { cs->exception_index =3D EXCP_IRQ; nios2_cpu_do_interrupt(cs); return true; @@ -163,7 +164,7 @@ static int nios2_cpu_gdb_read_register(CPUState *cs, GB= yteArray *mem_buf, int n) } else if (n =3D=3D 32) { /* PC */ return gdb_get_reg32(mem_buf, env->pc); } else if (n < 49) { /* Status regs */ - return gdb_get_reg32(mem_buf, env->regs[n - 1]); + return gdb_get_reg32(mem_buf, env->ctrl[n - 33]); } =20 /* Invalid regs */ @@ -185,7 +186,7 @@ static int nios2_cpu_gdb_write_register(CPUState *cs, u= int8_t *mem_buf, int n) } else if (n =3D=3D 32) { /* PC */ env->pc =3D ldl_p(mem_buf); } else if (n < 49) { /* Status regs */ - env->regs[n - 1] =3D ldl_p(mem_buf); + env->ctrl[n - 33] =3D ldl_p(mem_buf); } =20 return 4; diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 31cec29e89..3c49b0cfbf 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -56,38 +56,38 @@ void nios2_cpu_do_interrupt(CPUState *cs) =20 switch (cs->exception_index) { case EXCP_IRQ: - assert(env->regs[CR_STATUS] & CR_STATUS_PIE); + assert(env->status & CR_STATUS_PIE); =20 qemu_log_mask(CPU_LOG_INT, "interrupt at pc=3D%x\n", env->pc); =20 - env->regs[CR_ESTATUS] =3D env->regs[CR_STATUS]; - env->regs[CR_STATUS] |=3D CR_STATUS_IH; - env->regs[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); + env->estatus =3D env->status; + env->status |=3D CR_STATUS_IH; + env->status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); =20 - env->regs[CR_EXCEPTION] &=3D ~(0x1F << 2); - env->regs[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; + env->exception &=3D ~(0x1F << 2); + env->exception |=3D (cs->exception_index & 0x1F) << 2; =20 env->regs[R_EA] =3D env->pc + 4; env->pc =3D cpu->exception_addr; break; =20 case EXCP_TLBD: - if ((env->regs[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { + if ((env->status & CR_STATUS_EH) =3D=3D 0) { qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=3D%x\n", env= ->pc); =20 /* Fast TLB miss */ /* Variation from the spec. Table 3-35 of the cpu reference sh= ows * estatus not being changed for TLB miss but this appears to * be incorrect. */ - env->regs[CR_ESTATUS] =3D env->regs[CR_STATUS]; - env->regs[CR_STATUS] |=3D CR_STATUS_EH; - env->regs[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); + env->estatus =3D env->status; + env->status |=3D CR_STATUS_EH; + env->status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); =20 - env->regs[CR_EXCEPTION] &=3D ~(0x1F << 2); - env->regs[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; + env->exception &=3D ~(0x1F << 2); + env->exception |=3D (cs->exception_index & 0x1F) << 2; =20 - env->regs[CR_TLBMISC] &=3D ~CR_TLBMISC_DBL; - env->regs[CR_TLBMISC] |=3D CR_TLBMISC_WR; + env->tlbmisc &=3D ~CR_TLBMISC_DBL; + env->tlbmisc |=3D CR_TLBMISC_WR; =20 env->regs[R_EA] =3D env->pc + 4; env->pc =3D cpu->fast_tlb_miss_addr; @@ -95,13 +95,13 @@ void nios2_cpu_do_interrupt(CPUState *cs) qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=3D%x\n", e= nv->pc); =20 /* Double TLB miss */ - env->regs[CR_STATUS] |=3D CR_STATUS_EH; - env->regs[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); + env->status |=3D CR_STATUS_EH; + env->status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); =20 - env->regs[CR_EXCEPTION] &=3D ~(0x1F << 2); - env->regs[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; + env->exception &=3D ~(0x1F << 2); + env->exception |=3D (cs->exception_index & 0x1F) << 2; =20 - env->regs[CR_TLBMISC] |=3D CR_TLBMISC_DBL; + env->tlbmisc |=3D CR_TLBMISC_DBL; =20 env->pc =3D cpu->exception_addr; } @@ -112,15 +112,15 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_TLBX: qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=3D%x\n", env->pc); =20 - env->regs[CR_ESTATUS] =3D env->regs[CR_STATUS]; - env->regs[CR_STATUS] |=3D CR_STATUS_EH; - env->regs[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); + env->estatus =3D env->status; + env->status |=3D CR_STATUS_EH; + env->status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); =20 - env->regs[CR_EXCEPTION] &=3D ~(0x1F << 2); - env->regs[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; + env->exception &=3D ~(0x1F << 2); + env->exception |=3D (cs->exception_index & 0x1F) << 2; =20 - if ((env->regs[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { - env->regs[CR_TLBMISC] |=3D CR_TLBMISC_WR; + if ((env->status & CR_STATUS_EH) =3D=3D 0) { + env->tlbmisc |=3D CR_TLBMISC_WR; } =20 env->regs[R_EA] =3D env->pc + 4; @@ -132,16 +132,16 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_SUPERD: qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=3D%x\n", en= v->pc); =20 - if ((env->regs[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { - env->regs[CR_ESTATUS] =3D env->regs[CR_STATUS]; + if ((env->status & CR_STATUS_EH) =3D=3D 0) { + env->estatus =3D env->status; env->regs[R_EA] =3D env->pc + 4; } =20 - env->regs[CR_STATUS] |=3D CR_STATUS_EH; - env->regs[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); + env->status |=3D CR_STATUS_EH; + env->status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); =20 - env->regs[CR_EXCEPTION] &=3D ~(0x1F << 2); - env->regs[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; + env->exception &=3D ~(0x1F << 2); + env->exception |=3D (cs->exception_index & 0x1F) << 2; =20 env->pc =3D cpu->exception_addr; break; @@ -150,16 +150,16 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_TRAP: qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=3D%x\n", env->pc); =20 - if ((env->regs[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { - env->regs[CR_ESTATUS] =3D env->regs[CR_STATUS]; + if ((env->status & CR_STATUS_EH) =3D=3D 0) { + env->estatus =3D env->status; env->regs[R_EA] =3D env->pc + 4; } =20 - env->regs[CR_STATUS] |=3D CR_STATUS_EH; - env->regs[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); + env->status |=3D CR_STATUS_EH; + env->status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); =20 - env->regs[CR_EXCEPTION] &=3D ~(0x1F << 2); - env->regs[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; + env->exception &=3D ~(0x1F << 2); + env->exception |=3D (cs->exception_index & 0x1F) << 2; =20 env->pc =3D cpu->exception_addr; break; @@ -175,16 +175,16 @@ void nios2_cpu_do_interrupt(CPUState *cs) break; } =20 - if ((env->regs[CR_STATUS] & CR_STATUS_EH) =3D=3D 0) { - env->regs[CR_BSTATUS] =3D env->regs[CR_STATUS]; + if ((env->status & CR_STATUS_EH) =3D=3D 0) { + env->bstatus =3D env->status; env->regs[R_BA] =3D env->pc + 4; } =20 - env->regs[CR_STATUS] |=3D CR_STATUS_EH; - env->regs[CR_STATUS] &=3D ~(CR_STATUS_PIE | CR_STATUS_U); + env->status |=3D CR_STATUS_EH; + env->status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); =20 - env->regs[CR_EXCEPTION] &=3D ~(0x1F << 2); - env->regs[CR_EXCEPTION] |=3D (cs->exception_index & 0x1F) << 2; + env->exception &=3D ~(0x1F << 2); + env->exception |=3D (cs->exception_index & 0x1F) << 2; =20 env->pc =3D cpu->exception_addr; break; @@ -227,8 +227,8 @@ void nios2_cpu_do_unaligned_access(CPUState *cs, vaddr = addr, Nios2CPU *cpu =3D NIOS2_CPU(cs); CPUNios2State *env =3D &cpu->env; =20 - env->regs[CR_BADADDR] =3D addr; - env->regs[CR_EXCEPTION] =3D EXCP_UNALIGN << 2; + env->badaddr =3D addr; + env->exception =3D EXCP_UNALIGN << 2; helper_raise_exception(env, EXCP_UNALIGN); } =20 @@ -266,7 +266,7 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, return false; } cs->exception_index =3D EXCP_SUPERA; - env->regs[CR_BADADDR] =3D address; + env->badaddr =3D address; cpu_loop_exit_restore(cs, retaddr); } } @@ -295,16 +295,16 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, = int size, } =20 if (access_type =3D=3D MMU_INST_FETCH) { - env->regs[CR_TLBMISC] &=3D ~CR_TLBMISC_D; + env->tlbmisc &=3D ~CR_TLBMISC_D; } else { - env->regs[CR_TLBMISC] |=3D CR_TLBMISC_D; + env->tlbmisc |=3D CR_TLBMISC_D; } - env->regs[CR_PTEADDR] &=3D CR_PTEADDR_PTBASE_MASK; - env->regs[CR_PTEADDR] |=3D (address >> 10) & CR_PTEADDR_VPN_MASK; - env->mmu.pteaddr_wr =3D env->regs[CR_PTEADDR]; + env->pteaddr &=3D CR_PTEADDR_PTBASE_MASK; + env->pteaddr |=3D (address >> 10) & CR_PTEADDR_VPN_MASK; + env->mmu.pteaddr_wr =3D env->pteaddr; =20 cs->exception_index =3D excp; - env->regs[CR_BADADDR] =3D address; + env->badaddr =3D address; cpu_loop_exit_restore(cs, retaddr); } #endif /* !CONFIG_USER_ONLY */ diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 4daab2a7ab..382b190ae7 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -95,8 +95,8 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t= v) v & CR_TLBACC_PFN_MASK); =20 /* if tlbmisc.WE =3D=3D 1 then trigger a TLB write on writes to TLBACC= */ - if (env->regs[CR_TLBMISC] & CR_TLBMISC_WR) { - int way =3D (env->regs[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT); + if (env->tlbmisc & CR_TLBMISC_WR) { + int way =3D (env->tlbmisc >> CR_TLBMISC_WAY_SHIFT); int vpn =3D (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2; int pid =3D (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; int g =3D (v & CR_TLBACC_G) ? 1 : 0; @@ -117,8 +117,8 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32= _t v) entry->data =3D newData; } /* Auto-increment tlbmisc.WAY */ - env->regs[CR_TLBMISC] =3D - (env->regs[CR_TLBMISC] & ~CR_TLBMISC_WAY_MASK) | + env->tlbmisc =3D + (env->tlbmisc & ~CR_TLBMISC_WAY_MASK) | (((way + 1) & (cpu->tlb_num_ways - 1)) << CR_TLBMISC_WAY_SHIFT); } @@ -153,17 +153,17 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uin= t32_t v) &env->mmu.tlb[(way * cpu->tlb_num_ways) + (vpn & env->mmu.tlb_entry_mask)]; =20 - env->regs[CR_TLBACC] &=3D CR_TLBACC_IGN_MASK; - env->regs[CR_TLBACC] |=3D entry->data; - env->regs[CR_TLBACC] |=3D (entry->tag & (1 << 11)) ? CR_TLBACC_G := 0; - env->regs[CR_TLBMISC] =3D + env->tlbacc &=3D CR_TLBACC_IGN_MASK; + env->tlbacc |=3D entry->data; + env->tlbacc |=3D (entry->tag & (1 << 11)) ? CR_TLBACC_G : 0; + env->tlbmisc =3D (v & ~CR_TLBMISC_PID_MASK) | ((entry->tag & ((1 << cpu->pid_num_bits) - 1)) << CR_TLBMISC_PID_SHIFT); - env->regs[CR_PTEADDR] &=3D ~CR_PTEADDR_VPN_MASK; - env->regs[CR_PTEADDR] |=3D (entry->tag >> 12) << CR_PTEADDR_VPN_SH= IFT; + env->pteaddr &=3D ~CR_PTEADDR_VPN_MASK; + env->pteaddr |=3D (entry->tag >> 12) << CR_PTEADDR_VPN_SHIFT; } else { - env->regs[CR_TLBMISC] =3D v; + env->tlbmisc =3D v; } =20 env->mmu.tlbmisc_wr =3D v; @@ -175,8 +175,8 @@ void helper_mmu_write_pteaddr(CPUNios2State *env, uint3= 2_t v) (v & CR_PTEADDR_VPN_MASK) >> CR_PTEADDR_= VPN_SHIFT); =20 /* Writes to PTEADDR don't change the read-back VPN value */ - env->regs[CR_PTEADDR] =3D (v & ~CR_PTEADDR_VPN_MASK) | - (env->regs[CR_PTEADDR] & CR_PTEADDR_VPN_MASK); + env->pteaddr =3D (v & ~CR_PTEADDR_VPN_MASK) | + (env->pteaddr & CR_PTEADDR_VPN_MASK); env->mmu.pteaddr_wr =3D v; } =20 diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index df48e82cc2..a1554ce349 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -34,7 +34,7 @@ void helper_raise_exception(CPUNios2State *env, uint32_t = index) #ifndef CONFIG_USER_ONLY void helper_eret(CPUNios2State *env, uint32_t new_pc) { - env->regs[CR_STATUS] =3D env->regs[CR_ESTATUS]; + env->status =3D env->estatus; env->pc =3D new_pc; cpu_loop_exit(env_cpu(env)); } diff --git a/target/nios2/translate.c b/target/nios2/translate.c index cefdcea81e..2942921724 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -463,7 +463,7 @@ static void rdctl(DisasContext *dc, uint32_t code, uint= 32_t flags) return; } =20 - switch (instr.imm5 + CR_BASE) { + switch (instr.imm5) { case CR_IPENDING: /* * The value of the ipending register is synthetic. @@ -475,17 +475,15 @@ static void rdctl(DisasContext *dc, uint32_t code, ui= nt32_t flags) */ t1 =3D tcg_temp_new(); t2 =3D tcg_temp_new(); - tcg_gen_ld_tl(t1, cpu_env, - offsetof(CPUNios2State, regs[CR_IPENDING])); - tcg_gen_ld_tl(t2, cpu_env, - offsetof(CPUNios2State, regs[CR_IENABLE])); + tcg_gen_ld_tl(t1, cpu_env, offsetof(CPUNios2State, ipending)); + tcg_gen_ld_tl(t2, cpu_env, offsetof(CPUNios2State, ienable)); tcg_gen_and_tl(cpu_R[instr.c], t1, t2); tcg_temp_free(t1); tcg_temp_free(t2); break; default: tcg_gen_ld_tl(cpu_R[instr.c], cpu_env, - offsetof(CPUNios2State, regs[instr.imm5 + CR_BASE])); + offsetof(CPUNios2State, ctrl[instr.imm5])); break; } } @@ -503,7 +501,7 @@ static void wrctl(DisasContext *dc, uint32_t code, uint= 32_t flags) R_TYPE(instr, code); TCGv v =3D load_gpr(dc, instr.a); =20 - switch (instr.imm5 + CR_BASE) { + switch (instr.imm5) { case CR_PTEADDR: gen_helper_mmu_write_pteaddr(cpu_env, v); break; @@ -523,7 +521,7 @@ static void wrctl(DisasContext *dc, uint32_t code, uint= 32_t flags) /* fall through */ default: tcg_gen_st_tl(v, cpu_env, - offsetof(CPUNios2State, regs[instr.imm5 + CR_BASE])); + offsetof(CPUNios2State, ctrl[instr.imm5])); break; } #endif @@ -756,7 +754,7 @@ illegal_op: t_gen_helper_raise_exception(dc, EXCP_ILLEGAL); } =20 -static const char * const regnames[] =3D { +static const char * const gr_regnames[] =3D { "zero", "at", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", @@ -765,6 +763,9 @@ static const char * const regnames[] =3D { "r20", "r21", "r22", "r23", "et", "bt", "gp", "sp", "fp", "ea", "ba", "ra", +}; + +static const char * const cr_regnames[] =3D { "status", "estatus", "bstatus", "ienable", "ipending", "cpuid", "reserved0", "exception", "pteaddr", "tlbacc", "tlbmisc", "reserved1", @@ -892,8 +893,14 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int f= lags) =20 qemu_fprintf(f, "IN: PC=3D%x %s\n", env->pc, lookup_symbol(env->pc)); =20 - for (i =3D 0; i < NUM_CORE_REGS; i++) { - qemu_fprintf(f, "%9s=3D%8.8x ", regnames[i], env->regs[i]); + for (i =3D 0; i < NUM_GP_REGS; i++) { + qemu_fprintf(f, "%9s=3D%8.8x ", gr_regnames[i], env->regs[i]); + if ((i + 1) % 4 =3D=3D 0) { + qemu_fprintf(f, "\n"); + } + } + for (i =3D 0; i < NUM_CR_REGS; i++) { + qemu_fprintf(f, "%9s=3D%8.8x ", cr_regnames[i], env->ctrl[i]); if ((i + 1) % 4 =3D=3D 0) { qemu_fprintf(f, "\n"); } @@ -914,7 +921,7 @@ void nios2_tcg_init(void) for (i =3D 0; i < NUM_GP_REGS; i++) { cpu_R[i] =3D tcg_global_mem_new(cpu_env, offsetof(CPUNios2State, regs[i]), - regnames[i]); + gr_regnames[i]); } cpu_pc =3D tcg_global_mem_new(cpu_env, offsetof(CPUNios2State, pc), "pc"); --=20 2.25.1 From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646724652431725.371262969786; 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[50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:24 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+3vLmi9mxL7cFMKRdu4UOiQru6HR/JU1cXc1YHcKyCQ=; b=MwCkyL59sQOH4eTJil2uh4zMEA9mb0N2g2SiZsw5VL/ScfJXiofrJGmTsk+X2uM2wC mKYZvfx7wsFX+EnlkhWbOjHeObtGjuUm9zTVR8yoLQrcxcivhZsgv8vnzfAWUClx2LdU igbDBfsipWZUHO+nKTvw8lXol6+GwtiC3ysYUNLZZIUIwU+IiJRijUnnmfA7I5Pg4fWE OKzdP86rnLdj4EPjoFRCaHrbV7QpfZr/UiVCceuIsobEJ2G6A6LVJsbGFBTwxdgnF8HL JUhKUQrp+0HddA2pIOBDuq7A2PhfsuOsPC3/j1iRv4xS+mPn3yfLOF5OJhInXwU0Dr3o XI9g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+3vLmi9mxL7cFMKRdu4UOiQru6HR/JU1cXc1YHcKyCQ=; b=EM70V9nP2aik7cXYGERIpVE4zYhSf3W2oKFhOikgrparndLfCMJwh6hvqGtAlgZkaM JkuQ6hHW899qurgbEh9eV2ZEJUzsNO5uLGaOo4mlTaog3mSGK+p1ZobV41qNfoiOpnxd uEoRlcONbnI7+TA3y6u5DAmXEEe4M44TQPB1915X2hLyiA/ck87ai56Cd88N7Id46aTL 8yGXYc8UuzWMQiZ5b4HrAcnqECLX/+k0xTzNpnzIvhNT5Gt51Yd6PuTwV4nhaT8WToHb BzeSqltn72FS5ecKADr9PodWoHsF1VjBnclEUKZUaSn7UL0UzuLunbq9YFk1Q39WcWVR 2sCA== X-Gm-Message-State: AOAM532ccGvYw5OdcdTwrHD8zX3Q94Y/Udgvqt5LNTwqJrPRdkg8BXXE nnxW2ZR+3ieCmczWjMS+e2eh/1+BI2NDjA== X-Google-Smtp-Source: ABdhPJzn7gi7R6DBHfAp9VQf+/od2/S5fGASAkyXyMuyVeKrGbckrX/qtH4+OKBHjn72k7myixf3VQ== X-Received: by 2002:a17:902:9682:b0:14e:fe33:64af with SMTP id n2-20020a170902968200b0014efe3364afmr15976856plp.160.1646724025180; Mon, 07 Mar 2022 23:20:25 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 10/33] target/nios2: Clean up nios2_cpu_dump_state Date: Mon, 7 Mar 2022 21:19:42 -1000 Message-Id: <20220308072005.307955-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::633 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646724653618100003 Content-Type: text/plain; charset="utf-8" Do not print control registers for user-only mode. Rename reserved control registers to "resN", where N is the control register index. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/translate.c | 20 +++++++++++--------- 1 file changed, 11 insertions(+), 9 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 2942921724..7a32e6626d 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -754,7 +754,7 @@ illegal_op: t_gen_helper_raise_exception(dc, EXCP_ILLEGAL); } =20 -static const char * const gr_regnames[] =3D { +static const char * const gr_regnames[NUM_GP_REGS] =3D { "zero", "at", "r2", "r3", "r4", "r5", "r6", "r7", "r8", "r9", "r10", "r11", @@ -765,17 +765,18 @@ static const char * const gr_regnames[] =3D { "fp", "ea", "ba", "ra", }; =20 -static const char * const cr_regnames[] =3D { +#ifndef CONFIG_USER_ONLY +static const char * const cr_regnames[NUM_CR_REGS] =3D { "status", "estatus", "bstatus", "ienable", - "ipending", "cpuid", "reserved0", "exception", + "ipending", "cpuid", "res6", "exception", "pteaddr", "tlbacc", "tlbmisc", "reserved1", "badaddr", "config", "mpubase", "mpuacc", - "reserved2", "reserved3", "reserved4", "reserved5", - "reserved6", "reserved7", "reserved8", "reserved9", - "reserved10", "reserved11", "reserved12", "reserved13", - "reserved14", "reserved15", "reserved16", "reserved17", - "rpc" + "res16", "res17", "res18", "res19", + "res20", "res21", "res22", "res23", + "res24", "res25", "res26", "res27", + "res28", "res29", "res30", "res31", }; +#endif =20 #include "exec/gen-icount.h" =20 @@ -899,13 +900,14 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int = flags) qemu_fprintf(f, "\n"); } } + +#if !defined(CONFIG_USER_ONLY) for (i =3D 0; i < NUM_CR_REGS; i++) { qemu_fprintf(f, "%9s=3D%8.8x ", cr_regnames[i], env->ctrl[i]); if ((i + 1) % 4 =3D=3D 0) { qemu_fprintf(f, "\n"); } } -#if !defined(CONFIG_USER_ONLY) qemu_fprintf(f, " mmu write: VPN=3D%05X PID %02X TLBACC %08X\n", env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK, (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4, --=20 2.25.1 From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646724827723697.2524963980353; Mon, 7 Mar 2022 23:33:47 -0800 (PST) Received: from localhost ([::1]:52890 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nRULq-0008Jb-MS for importer@patchew.org; Tue, 08 Mar 2022 02:33:46 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45114) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nRU8z-0005BE-GH for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:31 -0500 Received: from [2607:f8b0:4864:20::635] (port=34445 helo=mail-pl1-x635.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nRU8y-0006JW-2c for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:29 -0500 Received: by mail-pl1-x635.google.com with SMTP id s18so3041416plp.1 for ; Mon, 07 Mar 2022 23:20:27 -0800 (PST) Received: from localhost.localdomain (cpe-50-113-46-110.hawaii.res.rr.com. [50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.25 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:26 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JPTHTSr1fVu62i4usn5tZsGs9hYEq9+hrYhQRAip59M=; b=ZQjkmvvcElCrcLyEr7hn5CcI2AKV5/0TyNDtBKzevA29sDKIR+thgKIlL7oTRAwoS4 6Lj3tROQhq/O5CVyI6MfXh98eD7N65jftHCcRkyZ/+c/gl6OOWGNNh2TKD7ueyETB1wQ Yf16bW7VxVI91gBdGYZOVVPvQjwEnBUuNZAFgFAoTxJS/nvRETS0875uJxzXl1qWnuxH LTnB5qDeZiTADGfI0ITnGBKmGqIogXTcqB7g25S7jkThvAJvjMFvQhV+bXi9zATJhNku dwWwFbn1lU1hq55DR4KTVEGlg61Xm9zItH8b2655IIBpu+r9XMaBYl2LtKeiUa/trGWd npUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JPTHTSr1fVu62i4usn5tZsGs9hYEq9+hrYhQRAip59M=; b=bvR4+JI8hVx4fztKOaFmWV1vd0wRI8tFBism58dJupUq2RV9YOtpVZZcfOo1c3rDFS NdEflPPTkM6JYgl3DdNLsHNaHNj7pWEVhL6hwfFojBnaVVhN81W317aOUq9ZGWelcgDh nAVrpriM8XV6dila1m1GaDViC9eSQrS4I6L9pQMyTN4NaFISZ2QLK2DaJtHgWfhIO54i Ii3FPEl8z8L1Ke0JVzzcjSkHFRD6MSMaUPBigtgBcbfHCfftRdaTwplqBTdw0wdhHIY+ bSGYWLS0rg0n8Q42wt3oi9/tXHM9pW7bJdhMwNzaD8hds2+y24PwSKwUJPPbii0F9Mvy FzFg== X-Gm-Message-State: AOAM531n8dwZVKnv/FCrzYWX4ZhJjASNnXUo5IFlvdCSapEZmDuf95Tw wz/dNulESyNM5rrd0cFz1IJf2zFduoKEtA== X-Google-Smtp-Source: ABdhPJyNX1HGYX7oT4K1uPMbmxosmKelhMX6DZJlX8mu89+Vf0Yxi5ul/hoVCEg3SNw6G+iOtrOTLg== X-Received: by 2002:a17:902:7888:b0:148:adf2:9725 with SMTP id q8-20020a170902788800b00148adf29725mr16437305pll.136.1646724026808; Mon, 07 Mar 2022 23:20:26 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 11/33] target/nios2: Use hw/registerfields.h for CR_STATUS fields Date: Mon, 7 Mar 2022 21:19:43 -1000 Message-Id: <20220308072005.307955-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::635 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646724828920100003 Content-Type: text/plain; charset="utf-8" Add all fields; retain the helper macros for single bit fields. So far there are no uses of the multi-bit status fields. Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 27 ++++++++++++++++++--------- 1 file changed, 18 insertions(+), 9 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 5bc0e353b4..26618baa70 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -23,6 +23,7 @@ =20 #include "exec/cpu-defs.h" #include "hw/core/cpu.h" +#include "hw/registerfields.h" #include "qom/object.h" =20 typedef struct CPUNios2State CPUNios2State; @@ -80,15 +81,23 @@ struct Nios2CPUClass { =20 /* Control register aliases */ #define CR_STATUS 0 -#define CR_STATUS_PIE (1 << 0) -#define CR_STATUS_U (1 << 1) -#define CR_STATUS_EH (1 << 2) -#define CR_STATUS_IH (1 << 3) -#define CR_STATUS_IL (63 << 4) -#define CR_STATUS_CRS (63 << 10) -#define CR_STATUS_PRS (63 << 16) -#define CR_STATUS_NMI (1 << 22) -#define CR_STATUS_RSIE (1 << 23) + +FIELD(CR_STATUS, PIE, 0, 1) +FIELD(CR_STATUS, U, 1, 1) +FIELD(CR_STATUS, EH, 2, 1) +FIELD(CR_STATUS, IH, 3, 1) +FIELD(CR_STATUS, IL, 4, 6) +FIELD(CR_STATUS, CRS, 10, 6) +FIELD(CR_STATUS, PRS, 16, 6) +FIELD(CR_STATUS, NMI, 22, 1) + +#define CR_STATUS_PIE (1u << R_CR_STATUS_PIE_SHIFT) +#define CR_STATUS_U (1u << R_CR_STATUS_U_SHIFT) +#define CR_STATUS_EH (1u << R_CR_STATUS_EH_SHIFT) +#define CR_STATUS_IH (1u << R_CR_STATUS_IH_SHIFT) +#define CR_STATUS_NMI (1u << R_CR_STATUS_NMI_SHIFT) +#define CR_STATUS_RSIE (1u << R_CR_STATUS_RSIE_SHIFT) + #define CR_ESTATUS 1 #define CR_BSTATUS 2 #define CR_IENABLE 3 --=20 2.25.1 From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646725112144893.11513588331; Mon, 7 Mar 2022 23:38:32 -0800 (PST) Received: from localhost ([::1]:36406 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nRUQR-0007kU-Me for importer@patchew.org; Tue, 08 Mar 2022 02:38:31 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45138) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nRU91-0005BP-In for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:32 -0500 Received: from [2607:f8b0:4864:20::530] (port=38856 helo=mail-pg1-x530.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nRU8z-0006Jn-W8 for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:31 -0500 Received: by mail-pg1-x530.google.com with SMTP id 132so15683848pga.5 for ; Mon, 07 Mar 2022 23:20:29 -0800 (PST) Received: from localhost.localdomain (cpe-50-113-46-110.hawaii.res.rr.com. [50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:27 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ois2JoZ1sznM8822SyfVxQPmV9CSqStEGCSJaWikHEs=; b=gJdbN11Y6frWYAEA2OiUSlZTHPOV+1Oh64stV3JA50SQv7CrcMvmJvf/esq/1z681P mwNS0cwUvt8F7oWYElX4Et9QCWWAmiFUckunEWySMtxhLTG/6P3C310Ap9Tx2p23+9M5 +vcJW8iopjajnBZh2KMnOpJvgLuhLMO3QnCknc/r4t2HkmW0iD8KBgxz2oBagoo1WhkE HTpmd0oYsryJLOPP7f1Ssw6nauP/YhYAXYsE44XmlqWFfuMCoRlFhN8YYmd0ypqnQLBk Dch1SrbNps7L3U0TteBpjOLa4KWpLKt6s87YDrhLKowVHRMh3JQLs+qFgl7Gr773ibAE N0mA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ois2JoZ1sznM8822SyfVxQPmV9CSqStEGCSJaWikHEs=; b=TA+ZDBtrS37VdMDl84zVXKFRFksdSUgr4y+zW+WyBl8NOWjifegaklvIW1+SJrXf/P 6hTkChVAJX5Ttg+Z407cnfOSxmQoLwY/HiaPzRKuATn6yJn0PvVFjWs/FBZwmYQ8+5JK v7ut+bm6pYeFxpgClNoM+/XT8X1Bugr3X+YDENJDwrFlzaIGW0FFZnR5O3hC0SOGAW8+ eExfEVsYxicyzoZbN+b0TWsf1K/NUrD2DoxFC6ychuoZzs0Z/paanStyNViidy08FXSN tFZRIxoISou10jNT0sTu5YCGuR2JB1TkcesMFQdeGFus/p8D7UfzGPOuys5k8BtGFf64 skxw== X-Gm-Message-State: AOAM530+HbvNQPdI3zNLT2/XRG2+zWGifk+b6SzQeyTCjlEj6AF8InU9 9gXL8xix66ZJOnbelwQVsd7BnvPTBe4oqA== X-Google-Smtp-Source: ABdhPJzpbf32BHjWhqnKQ1gxsN2FOYyAoUd5nmFWZuY51AF9PlftlDb/6Za1gkibWuhiT/xTBAq12Q== X-Received: by 2002:a62:8085:0:b0:4df:443c:7227 with SMTP id j127-20020a628085000000b004df443c7227mr16942943pfd.34.1646724028262; Mon, 07 Mar 2022 23:20:28 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 12/33] target/nios2: Use hw/registerfields.h for CR_EXCEPTION fields Date: Mon, 7 Mar 2022 21:19:44 -1000 Message-Id: <20220308072005.307955-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::530 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646725113598100001 Content-Type: text/plain; charset="utf-8" Sink the set of env->exception to the end of nios2_cpu_do_interrupt. Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 4 ++++ target/nios2/helper.c | 24 +++--------------------- 2 files changed, 7 insertions(+), 21 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 26618baa70..35b4d88859 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -105,6 +105,10 @@ FIELD(CR_STATUS, NMI, 22, 1) #define CR_CPUID 5 #define CR_CTL6 6 #define CR_EXCEPTION 7 + +FIELD(CR_EXCEPTION, CAUSE, 2, 5) +FIELD(CR_EXCEPTION, ECCFTL, 31, 1) + #define CR_PTEADDR 8 #define CR_PTEADDR_PTBASE_SHIFT 22 #define CR_PTEADDR_PTBASE_MASK (0x3FF << CR_PTEADDR_PTBASE_SHIFT) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 3c49b0cfbf..eb354f78e2 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -64,9 +64,6 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->status |=3D CR_STATUS_IH; env->status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); =20 - env->exception &=3D ~(0x1F << 2); - env->exception |=3D (cs->exception_index & 0x1F) << 2; - env->regs[R_EA] =3D env->pc + 4; env->pc =3D cpu->exception_addr; break; @@ -83,9 +80,6 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->status |=3D CR_STATUS_EH; env->status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); =20 - env->exception &=3D ~(0x1F << 2); - env->exception |=3D (cs->exception_index & 0x1F) << 2; - env->tlbmisc &=3D ~CR_TLBMISC_DBL; env->tlbmisc |=3D CR_TLBMISC_WR; =20 @@ -98,9 +92,6 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->status |=3D CR_STATUS_EH; env->status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); =20 - env->exception &=3D ~(0x1F << 2); - env->exception |=3D (cs->exception_index & 0x1F) << 2; - env->tlbmisc |=3D CR_TLBMISC_DBL; =20 env->pc =3D cpu->exception_addr; @@ -116,9 +107,6 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->status |=3D CR_STATUS_EH; env->status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); =20 - env->exception &=3D ~(0x1F << 2); - env->exception |=3D (cs->exception_index & 0x1F) << 2; - if ((env->status & CR_STATUS_EH) =3D=3D 0) { env->tlbmisc |=3D CR_TLBMISC_WR; } @@ -140,9 +128,6 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->status |=3D CR_STATUS_EH; env->status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); =20 - env->exception &=3D ~(0x1F << 2); - env->exception |=3D (cs->exception_index & 0x1F) << 2; - env->pc =3D cpu->exception_addr; break; =20 @@ -158,9 +143,6 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->status |=3D CR_STATUS_EH; env->status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); =20 - env->exception &=3D ~(0x1F << 2); - env->exception |=3D (cs->exception_index & 0x1F) << 2; - env->pc =3D cpu->exception_addr; break; =20 @@ -183,9 +165,6 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->status |=3D CR_STATUS_EH; env->status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); =20 - env->exception &=3D ~(0x1F << 2); - env->exception |=3D (cs->exception_index & 0x1F) << 2; - env->pc =3D cpu->exception_addr; break; =20 @@ -194,6 +173,9 @@ void nios2_cpu_do_interrupt(CPUState *cs) cs->exception_index); break; } + + env->exception =3D FIELD_DP32(env->exception, CR_EXCEPTION, CAUSE, + cs->exception_index); } =20 hwaddr nios2_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) --=20 2.25.1 From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646725423066247.5325587865077; Mon, 7 Mar 2022 23:43:43 -0800 (PST) Received: from localhost ([::1]:44982 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nRUVR-0005Fi-TO for importer@patchew.org; Tue, 08 Mar 2022 02:43:41 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45146) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nRU92-0005Cl-K8 for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:32 -0500 Received: from [2607:f8b0:4864:20::1029] (port=35578 helo=mail-pj1-x1029.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nRU90-0006K5-RG for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:32 -0500 Received: by mail-pj1-x1029.google.com with SMTP id mg21-20020a17090b371500b001bef9e4657cso1503656pjb.0 for ; Mon, 07 Mar 2022 23:20:30 -0800 (PST) Received: from localhost.localdomain (cpe-50-113-46-110.hawaii.res.rr.com. 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charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/cpu.h | 8 ++++---- target/nios2/helper.c | 4 ++-- target/nios2/mmu.c | 16 ++++++++-------- target/nios2/translate.c | 2 +- 4 files changed, 15 insertions(+), 15 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 35b4d88859..84138000fa 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -110,10 +110,10 @@ FIELD(CR_EXCEPTION, CAUSE, 2, 5) FIELD(CR_EXCEPTION, ECCFTL, 31, 1) =20 #define CR_PTEADDR 8 -#define CR_PTEADDR_PTBASE_SHIFT 22 -#define CR_PTEADDR_PTBASE_MASK (0x3FF << CR_PTEADDR_PTBASE_SHIFT) -#define CR_PTEADDR_VPN_SHIFT 2 -#define CR_PTEADDR_VPN_MASK (0xFFFFF << CR_PTEADDR_VPN_SHIFT) + +FIELD(CR_PTEADDR, VPN, 2, 20) +FIELD(CR_PTEADDR, PTBASE, 22, 10) + #define CR_TLBACC 9 #define CR_TLBACC_IGN_SHIFT 25 #define CR_TLBACC_IGN_MASK (0x7F << CR_TLBACC_IGN_SHIFT) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index eb354f78e2..37fb53dadb 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -281,8 +281,8 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, in= t size, } else { env->tlbmisc |=3D CR_TLBMISC_D; } - env->pteaddr &=3D CR_PTEADDR_PTBASE_MASK; - env->pteaddr |=3D (address >> 10) & CR_PTEADDR_VPN_MASK; + env->pteaddr =3D FIELD_DP32(env->pteaddr, CR_PTEADDR, VPN, + address >> TARGET_PAGE_BITS); env->mmu.pteaddr_wr =3D env->pteaddr; =20 cs->exception_index =3D excp; diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 382b190ae7..8017f2af93 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -97,7 +97,7 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t= v) /* if tlbmisc.WE =3D=3D 1 then trigger a TLB write on writes to TLBACC= */ if (env->tlbmisc & CR_TLBMISC_WR) { int way =3D (env->tlbmisc >> CR_TLBMISC_WAY_SHIFT); - int vpn =3D (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2; + int vpn =3D FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN); int pid =3D (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; int g =3D (v & CR_TLBACC_G) ? 1 : 0; int valid =3D ((vpn & CR_TLBACC_PFN_MASK) < 0xC0000) ? 1 : 0; @@ -148,7 +148,7 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint3= 2_t v) /* if tlbmisc.RD =3D=3D 1 then trigger a TLB read on writes to TLBMISC= */ if (v & CR_TLBMISC_RD) { int way =3D (v >> CR_TLBMISC_WAY_SHIFT); - int vpn =3D (env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK) >> 2; + int vpn =3D FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN); Nios2TLBEntry *entry =3D &env->mmu.tlb[(way * cpu->tlb_num_ways) + (vpn & env->mmu.tlb_entry_mask)]; @@ -160,8 +160,8 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint3= 2_t v) (v & ~CR_TLBMISC_PID_MASK) | ((entry->tag & ((1 << cpu->pid_num_bits) - 1)) << CR_TLBMISC_PID_SHIFT); - env->pteaddr &=3D ~CR_PTEADDR_VPN_MASK; - env->pteaddr |=3D (entry->tag >> 12) << CR_PTEADDR_VPN_SHIFT; + env->pteaddr =3D FIELD_DP32(env->pteaddr, CR_PTEADDR, VPN, + entry->tag >> TARGET_PAGE_BITS); } else { env->tlbmisc =3D v; } @@ -171,12 +171,12 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uin= t32_t v) =20 void helper_mmu_write_pteaddr(CPUNios2State *env, uint32_t v) { - trace_nios2_mmu_write_pteaddr(v >> CR_PTEADDR_PTBASE_SHIFT, - (v & CR_PTEADDR_VPN_MASK) >> CR_PTEADDR_= VPN_SHIFT); + trace_nios2_mmu_write_pteaddr(FIELD_EX32(v, CR_PTEADDR, PTBASE), + FIELD_EX32(v, CR_PTEADDR, VPN)); =20 /* Writes to PTEADDR don't change the read-back VPN value */ - env->pteaddr =3D (v & ~CR_PTEADDR_VPN_MASK) | - (env->pteaddr & CR_PTEADDR_VPN_MASK); + env->pteaddr =3D (v & ~R_CR_PTEADDR_VPN_MASK) | + (env->pteaddr & R_CR_PTEADDR_VPN_MASK); env->mmu.pteaddr_wr =3D v; } =20 diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 7a32e6626d..3cdef16519 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -909,7 +909,7 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int fl= ags) } } qemu_fprintf(f, " mmu write: VPN=3D%05X PID %02X TLBACC %08X\n", - env->mmu.pteaddr_wr & CR_PTEADDR_VPN_MASK, + env->mmu.pteaddr_wr & R_CR_PTEADDR_VPN_MASK, (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4, env->mmu.tlbacc_wr); #endif --=20 2.25.1 From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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charset="utf-8" Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/cpu.h | 23 +++++++++++++++-------- target/nios2/mmu.c | 16 ++++++++-------- 2 files changed, 23 insertions(+), 16 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 84138000fa..024ef3ccc0 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -115,14 +115,21 @@ FIELD(CR_PTEADDR, VPN, 2, 20) FIELD(CR_PTEADDR, PTBASE, 22, 10) =20 #define CR_TLBACC 9 -#define CR_TLBACC_IGN_SHIFT 25 -#define CR_TLBACC_IGN_MASK (0x7F << CR_TLBACC_IGN_SHIFT) -#define CR_TLBACC_C (1 << 24) -#define CR_TLBACC_R (1 << 23) -#define CR_TLBACC_W (1 << 22) -#define CR_TLBACC_X (1 << 21) -#define CR_TLBACC_G (1 << 20) -#define CR_TLBACC_PFN_MASK 0x000FFFFF + +FIELD(CR_TLBACC, PFN, 0, 20) +FIELD(CR_TLBACC, G, 20, 1) +FIELD(CR_TLBACC, X, 21, 1) +FIELD(CR_TLBACC, W, 22, 1) +FIELD(CR_TLBACC, R, 23, 1) +FIELD(CR_TLBACC, C, 24, 1) +FIELD(CR_TLBACC, IG, 25, 7) + +#define CR_TLBACC_C (1u << R_CR_TLBACC_C_SHIFT) +#define CR_TLBACC_R (1u << R_CR_TLBACC_R_SHIFT) +#define CR_TLBACC_W (1u << R_CR_TLBACC_W_SHIFT) +#define CR_TLBACC_X (1u << R_CR_TLBACC_X_SHIFT) +#define CR_TLBACC_G (1u << R_CR_TLBACC_G_SHIFT) + #define CR_TLBMISC 10 #define CR_TLBMISC_WAY_SHIFT 20 #define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT) diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 8017f2af93..d6221936f7 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -49,7 +49,7 @@ unsigned int mmu_translate(CPUNios2State *env, } =20 lu->vaddr =3D vaddr & TARGET_PAGE_MASK; - lu->paddr =3D (entry->data & CR_TLBACC_PFN_MASK) << TARGET_PAGE_BI= TS; + lu->paddr =3D FIELD_EX32(entry->data, CR_TLBACC, PFN) << TARGET_PA= GE_BITS; lu->prot =3D ((entry->data & CR_TLBACC_R) ? PAGE_READ : 0) | ((entry->data & CR_TLBACC_W) ? PAGE_WRITE : 0) | ((entry->data & CR_TLBACC_X) ? PAGE_EXEC : 0); @@ -86,27 +86,27 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32= _t v) CPUState *cs =3D env_cpu(env); Nios2CPU *cpu =3D env_archcpu(env); =20 - trace_nios2_mmu_write_tlbacc(v >> CR_TLBACC_IGN_SHIFT, + trace_nios2_mmu_write_tlbacc(FIELD_EX32(v, CR_TLBACC, IG), (v & CR_TLBACC_C) ? 'C' : '.', (v & CR_TLBACC_R) ? 'R' : '.', (v & CR_TLBACC_W) ? 'W' : '.', (v & CR_TLBACC_X) ? 'X' : '.', (v & CR_TLBACC_G) ? 'G' : '.', - v & CR_TLBACC_PFN_MASK); + FIELD_EX32(v, CR_TLBACC, PFN)); =20 /* if tlbmisc.WE =3D=3D 1 then trigger a TLB write on writes to TLBACC= */ if (env->tlbmisc & CR_TLBMISC_WR) { int way =3D (env->tlbmisc >> CR_TLBMISC_WAY_SHIFT); int vpn =3D FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN); int pid =3D (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; - int g =3D (v & CR_TLBACC_G) ? 1 : 0; - int valid =3D ((vpn & CR_TLBACC_PFN_MASK) < 0xC0000) ? 1 : 0; + int g =3D FIELD_EX32(v, CR_TLBACC, G); + int valid =3D FIELD_EX32(vpn, CR_TLBACC, PFN) < 0xC0000; Nios2TLBEntry *entry =3D &env->mmu.tlb[(way * cpu->tlb_num_ways) + (vpn & env->mmu.tlb_entry_mask)]; uint32_t newTag =3D (vpn << 12) | (g << 11) | (valid << 10) | pid; uint32_t newData =3D v & (CR_TLBACC_C | CR_TLBACC_R | CR_TLBACC_W | - CR_TLBACC_X | CR_TLBACC_PFN_MASK); + CR_TLBACC_X | R_CR_TLBACC_PFN_MASK); =20 if ((entry->tag !=3D newTag) || (entry->data !=3D newData)) { if (entry->tag & (1 << 10)) { @@ -153,7 +153,7 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint3= 2_t v) &env->mmu.tlb[(way * cpu->tlb_num_ways) + (vpn & env->mmu.tlb_entry_mask)]; =20 - env->tlbacc &=3D CR_TLBACC_IGN_MASK; + env->tlbacc &=3D R_CR_TLBACC_IG_MASK; env->tlbacc |=3D entry->data; env->tlbacc |=3D (entry->tag & (1 << 11)) ? CR_TLBACC_G : 0; env->tlbmisc =3D @@ -207,7 +207,7 @@ void dump_mmu(CPUNios2State *env) entry->tag >> 12, entry->tag & ((1 << cpu->pid_num_bits) - 1), (entry->tag & (1 << 11)) ? 'G' : '-', - entry->data & CR_TLBACC_PFN_MASK, + FIELD_EX32(entry->data, CR_TLBACC, PFN), (entry->data & CR_TLBACC_C) ? 'C' : '-', (entry->data & CR_TLBACC_R) ? 'R' : '-', (entry->data & CR_TLBACC_W) ? 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charset="utf-8" Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 28 ++++++++++++++++++---------- target/nios2/helper.c | 7 ++----- target/nios2/mmu.c | 33 +++++++++++++++------------------ target/nios2/translate.c | 2 +- 4 files changed, 36 insertions(+), 34 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 024ef3ccc0..3857848f7c 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -131,16 +131,24 @@ FIELD(CR_TLBACC, IG, 25, 7) #define CR_TLBACC_G (1u << R_CR_TLBACC_G_SHIFT) =20 #define CR_TLBMISC 10 -#define CR_TLBMISC_WAY_SHIFT 20 -#define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT) -#define CR_TLBMISC_RD (1 << 19) -#define CR_TLBMISC_WR (1 << 18) -#define CR_TLBMISC_PID_SHIFT 4 -#define CR_TLBMISC_PID_MASK (0x3FFF << CR_TLBMISC_PID_SHIFT) -#define CR_TLBMISC_DBL (1 << 3) -#define CR_TLBMISC_BAD (1 << 2) -#define CR_TLBMISC_PERM (1 << 1) -#define CR_TLBMISC_D (1 << 0) + +FIELD(CR_TLBMISC, D, 0, 1) +FIELD(CR_TLBMISC, PERM, 1, 1) +FIELD(CR_TLBMISC, BAD, 2, 1) +FIELD(CR_TLBMISC, DBL, 3, 1) +FIELD(CR_TLBMISC, PID, 4, 14) +FIELD(CR_TLBMISC, WR, 18, 1) +FIELD(CR_TLBMISC, RD, 19, 1) +FIELD(CR_TLBMISC, WAY, 20, 4) +FIELD(CR_TLBMISC, EE, 24, 1) + +#define CR_TLBMISC_RD (1u << R_CR_TLBMISC_RD_SHIFT) +#define CR_TLBMISC_WR (1u << R_CR_TLBMISC_WR_SHIFT) +#define CR_TLBMISC_DBL (1u << R_CR_TLBMISC_DBL_SHIFT) +#define CR_TLBMISC_BAD (1u << R_CR_TLBMISC_BAD_SHIFT) +#define CR_TLBMISC_PERM (1u << R_CR_TLBMISC_PERM_SHIFT) +#define CR_TLBMISC_D (1u << R_CR_TLBMISC_D_SHIFT) + #define CR_ENCINJ 11 #define CR_BADADDR 12 #define CR_CONFIG 13 diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 37fb53dadb..93338e86f0 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -276,11 +276,8 @@ bool nios2_cpu_tlb_fill(CPUState *cs, vaddr address, i= nt size, return false; } =20 - if (access_type =3D=3D MMU_INST_FETCH) { - env->tlbmisc &=3D ~CR_TLBMISC_D; - } else { - env->tlbmisc |=3D CR_TLBMISC_D; - } + env->tlbmisc =3D FIELD_DP32(env->tlbmisc, CR_TLBMISC, D, + access_type =3D=3D MMU_INST_FETCH); env->pteaddr =3D FIELD_DP32(env->pteaddr, CR_PTEADDR, VPN, address >> TARGET_PAGE_BITS); env->mmu.pteaddr_wr =3D env->pteaddr; diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index d6221936f7..c8b74b5479 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -33,7 +33,7 @@ unsigned int mmu_translate(CPUNios2State *env, target_ulong vaddr, int rw, int mmu_idx) { Nios2CPU *cpu =3D env_archcpu(env); - int pid =3D (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; + int pid =3D FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID); int vpn =3D vaddr >> 12; int way, n_ways =3D cpu->tlb_num_ways; =20 @@ -96,9 +96,9 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32_t= v) =20 /* if tlbmisc.WE =3D=3D 1 then trigger a TLB write on writes to TLBACC= */ if (env->tlbmisc & CR_TLBMISC_WR) { - int way =3D (env->tlbmisc >> CR_TLBMISC_WAY_SHIFT); + int way =3D FIELD_EX32(env->tlbmisc, CR_TLBMISC, WAY); int vpn =3D FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN); - int pid =3D (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; + int pid =3D FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID); int g =3D FIELD_EX32(v, CR_TLBACC, G); int valid =3D FIELD_EX32(vpn, CR_TLBACC, PFN) < 0xC0000; Nios2TLBEntry *entry =3D @@ -117,10 +117,8 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint3= 2_t v) entry->data =3D newData; } /* Auto-increment tlbmisc.WAY */ - env->tlbmisc =3D - (env->tlbmisc & ~CR_TLBMISC_WAY_MASK) | - (((way + 1) & (cpu->tlb_num_ways - 1)) << - CR_TLBMISC_WAY_SHIFT); + env->tlbmisc =3D FIELD_DP32(env->tlbmisc, CR_TLBMISC, WAY, + (way + 1) & (cpu->tlb_num_ways - 1)); } =20 /* Writes to TLBACC don't change the read-back value */ @@ -130,24 +128,25 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint= 32_t v) void helper_mmu_write_tlbmisc(CPUNios2State *env, uint32_t v) { Nios2CPU *cpu =3D env_archcpu(env); + uint32_t new_pid =3D FIELD_EX32(v, CR_TLBMISC, PID); + uint32_t old_pid =3D FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID); + uint32_t way =3D FIELD_EX32(v, CR_TLBMISC, WAY); =20 - trace_nios2_mmu_write_tlbmisc(v >> CR_TLBMISC_WAY_SHIFT, + trace_nios2_mmu_write_tlbmisc(way, (v & CR_TLBMISC_RD) ? 'R' : '.', (v & CR_TLBMISC_WR) ? 'W' : '.', (v & CR_TLBMISC_DBL) ? '2' : '.', (v & CR_TLBMISC_BAD) ? 'B' : '.', (v & CR_TLBMISC_PERM) ? 'P' : '.', (v & CR_TLBMISC_D) ? 'D' : '.', - (v & CR_TLBMISC_PID_MASK) >> 4); + new_pid); =20 - if ((v & CR_TLBMISC_PID_MASK) !=3D - (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK)) { - mmu_flush_pid(env, (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> - CR_TLBMISC_PID_SHIFT); + if (new_pid !=3D old_pid) { + mmu_flush_pid(env, old_pid); } + /* if tlbmisc.RD =3D=3D 1 then trigger a TLB read on writes to TLBMISC= */ if (v & CR_TLBMISC_RD) { - int way =3D (v >> CR_TLBMISC_WAY_SHIFT); int vpn =3D FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN); Nios2TLBEntry *entry =3D &env->mmu.tlb[(way * cpu->tlb_num_ways) + @@ -156,10 +155,8 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint= 32_t v) env->tlbacc &=3D R_CR_TLBACC_IG_MASK; env->tlbacc |=3D entry->data; env->tlbacc |=3D (entry->tag & (1 << 11)) ? CR_TLBACC_G : 0; - env->tlbmisc =3D - (v & ~CR_TLBMISC_PID_MASK) | - ((entry->tag & ((1 << cpu->pid_num_bits) - 1)) << - CR_TLBMISC_PID_SHIFT); + env->tlbmisc =3D FIELD_DP32(v, CR_TLBMISC, PID, + entry->tag & ((1 << cpu->pid_num_bits) -= 1)); env->pteaddr =3D FIELD_DP32(env->pteaddr, CR_PTEADDR, VPN, entry->tag >> TARGET_PAGE_BITS); } else { diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 3cdef16519..77b3bf05f3 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -910,7 +910,7 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int fl= ags) } qemu_fprintf(f, " mmu write: VPN=3D%05X PID %02X TLBACC %08X\n", env->mmu.pteaddr_wr & R_CR_PTEADDR_VPN_MASK, - (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4, + FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID), env->mmu.tlbacc_wr); #endif qemu_fprintf(f, "\n\n"); --=20 2.25.1 From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646725298509645.6541364969479; Mon, 7 Mar 2022 23:41:38 -0800 (PST) Received: from localhost ([::1]:41928 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nRUTR-0003Fy-8r for importer@patchew.org; Tue, 08 Mar 2022 02:41:37 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45228) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nRU99-0005Eh-3T for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:42 -0500 Received: from [2607:f8b0:4864:20::102d] (port=53013 helo=mail-pj1-x102d.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nRU96-0006Ln-Ho for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:38 -0500 Received: by mail-pj1-x102d.google.com with SMTP id v4so16353597pjh.2 for ; Mon, 07 Mar 2022 23:20:35 -0800 (PST) Received: from localhost.localdomain (cpe-50-113-46-110.hawaii.res.rr.com. [50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:34 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hVtoqbC1gYoYHHn2DZhJOouijVB0naPV7yAJTXjEzIc=; b=vFdMzqmAiOXr4N3ZdM3PSH9hPhoimvTpZrMy5ZzZAa5p0tLx+emOOlUsduidGST7BJ UVgE3Q49Q5KsIBF5ZUcozZEBerIOOKJy0hfZQ6Qe4FgxBN4HJHSp+jRo2hJO+sHXjLuE RGioIH+PK6m1x/QQLyIEvDdmnfOZ//VBwMhwJVYFASpszh0WYg+Z2pejf8vW1jYTaIDF b57n/go+RYZy6rXWsiKdT6Tpm1uF2YJ72/qdjVhTjm7H7++0XlDLqs7IXhXfADLw4AfD 0UcJll2pydtVXa9H58JZoW6vG61/sSzW5Vv5CinnKGWiYmQJJkSAv6FV6oZEABr3ztCu LLnw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hVtoqbC1gYoYHHn2DZhJOouijVB0naPV7yAJTXjEzIc=; b=3+VAh/sLSV6nTcOAkRJvFDaVzbySCARwKEPRDnlrp/36UO9sdCSBXE1qMA09ADjNyr ZFG5BEhm03YA5u9/vob3ZlJN5JNf6FZv8B8eRlJ7+bD7xXxpR1kTLl1d5E+dKMxXV2JS 7odXY2NkmgdGmfcKRoghl52juF880r/2/xlIakD2p5hG5ahG8oAbeVwQlK1Ig1MyRgZm aPs0IA//v2XNBJM33OL0xM2QRMgZIjvmJILSiX6z0gRh4cP9wZeGeu+W0I2PI4HRPk1k zXxOVtYmx5M6zunHkv7tR6NP7UfqOBv6EJ185JWDsZK3XKshC0WUEDbEdMotUkaBrioj LLeg== X-Gm-Message-State: AOAM5338NMQCfm3tjZBLB/6c1bMFHkGmbdoh4l9FCY6xTQwRWd0ZcSWP KAL1liLdjNGgjMSNViKfb+VaXhHn/cW4gg== X-Google-Smtp-Source: ABdhPJw65j2xFwbja8MK47ScVrjDGPXgBAnIqIXOsUQcl+S2qw9+UOCoJ8JcCl5ZORTcVJTL/bVb9A== X-Received: by 2002:a17:902:c443:b0:151:ca88:684 with SMTP id m3-20020a170902c44300b00151ca880684mr16193129plm.80.1646724034610; Mon, 07 Mar 2022 23:20:34 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 16/33] target/nios2: Move R_FOO and CR_BAR into enumerations Date: Mon, 7 Mar 2022 21:19:48 -1000 Message-Id: <20220308072005.307955-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102d (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646725300317100001 Content-Type: text/plain; charset="utf-8" These symbols become available to the debugger. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/cpu.h | 72 ++++++++++++++++++++++------------------------ 1 file changed, 35 insertions(+), 37 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 3857848f7c..927c4aaa80 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -62,25 +62,43 @@ struct Nios2CPUClass { #define NUM_CR_REGS 32 =20 /* General purpose register aliases */ -#define R_ZERO 0 -#define R_AT 1 -#define R_RET0 2 -#define R_RET1 3 -#define R_ARG0 4 -#define R_ARG1 5 -#define R_ARG2 6 -#define R_ARG3 7 -#define R_ET 24 -#define R_BT 25 -#define R_GP 26 -#define R_SP 27 -#define R_FP 28 -#define R_EA 29 -#define R_BA 30 -#define R_RA 31 +enum { + R_ZERO =3D 0, + R_AT =3D 1, + R_RET0 =3D 2, + R_RET1 =3D 3, + R_ARG0 =3D 4, + R_ARG1 =3D 5, + R_ARG2 =3D 6, + R_ARG3 =3D 7, + R_ET =3D 24, + R_BT =3D 25, + R_GP =3D 26, + R_SP =3D 27, + R_FP =3D 28, + R_EA =3D 29, + R_BA =3D 30, + R_RA =3D 31, +}; =20 /* Control register aliases */ -#define CR_STATUS 0 +enum { + CR_STATUS =3D 0, + CR_ESTATUS =3D 1, + CR_BSTATUS =3D 2, + CR_IENABLE =3D 3, + CR_IPENDING =3D 4, + CR_CPUID =3D 5, + CR_EXCEPTION =3D 7, + CR_PTEADDR =3D 8, + CR_TLBACC =3D 9, + CR_TLBMISC =3D 10, + CR_ENCINJ =3D 11, + CR_BADADDR =3D 12, + CR_CONFIG =3D 13, + CR_MPUBASE =3D 14, + CR_MPUACC =3D 15, +}; =20 FIELD(CR_STATUS, PIE, 0, 1) FIELD(CR_STATUS, U, 1, 1) @@ -98,24 +116,12 @@ FIELD(CR_STATUS, NMI, 22, 1) #define CR_STATUS_NMI (1u << R_CR_STATUS_NMI_SHIFT) #define CR_STATUS_RSIE (1u << R_CR_STATUS_RSIE_SHIFT) =20 -#define CR_ESTATUS 1 -#define CR_BSTATUS 2 -#define CR_IENABLE 3 -#define CR_IPENDING 4 -#define CR_CPUID 5 -#define CR_CTL6 6 -#define CR_EXCEPTION 7 - FIELD(CR_EXCEPTION, CAUSE, 2, 5) FIELD(CR_EXCEPTION, ECCFTL, 31, 1) =20 -#define CR_PTEADDR 8 - FIELD(CR_PTEADDR, VPN, 2, 20) FIELD(CR_PTEADDR, PTBASE, 22, 10) =20 -#define CR_TLBACC 9 - FIELD(CR_TLBACC, PFN, 0, 20) FIELD(CR_TLBACC, G, 20, 1) FIELD(CR_TLBACC, X, 21, 1) @@ -130,8 +136,6 @@ FIELD(CR_TLBACC, IG, 25, 7) #define CR_TLBACC_X (1u << R_CR_TLBACC_X_SHIFT) #define CR_TLBACC_G (1u << R_CR_TLBACC_G_SHIFT) =20 -#define CR_TLBMISC 10 - FIELD(CR_TLBMISC, D, 0, 1) FIELD(CR_TLBMISC, PERM, 1, 1) FIELD(CR_TLBMISC, BAD, 2, 1) @@ -149,12 +153,6 @@ FIELD(CR_TLBMISC, EE, 24, 1) #define CR_TLBMISC_PERM (1u << R_CR_TLBMISC_PERM_SHIFT) #define CR_TLBMISC_D (1u << R_CR_TLBMISC_D_SHIFT) =20 -#define CR_ENCINJ 11 -#define CR_BADADDR 12 -#define CR_CONFIG 13 -#define CR_MPUBASE 14 -#define CR_MPUACC 15 - /* Exceptions */ #define EXCP_BREAK 0x1000 #define EXCP_RESET 0 --=20 2.25.1 From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646725052145351.217537588971; Mon, 7 Mar 2022 23:37:32 -0800 (PST) Received: from localhost ([::1]:33212 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nRUPS-0005e3-NW for importer@patchew.org; Tue, 08 Mar 2022 02:37:30 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45256) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nRU9F-0005GD-OG for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:46 -0500 Received: from [2607:f8b0:4864:20::102a] (port=36508 helo=mail-pj1-x102a.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nRU97-0006ND-RS for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:40 -0500 Received: by mail-pj1-x102a.google.com with SMTP id kx6-20020a17090b228600b001bf859159bfso1460479pjb.1 for ; Mon, 07 Mar 2022 23:20:37 -0800 (PST) Received: from localhost.localdomain (cpe-50-113-46-110.hawaii.res.rr.com. [50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QZ5JgxKTY6j7jOJgJ2ehiBZmm45GMeMFdXbMkDT92PE=; b=pL57muVPbQr3X7kkMQK/lQZjDhg9ssh0J9C0NNjEdu0CPI2fsGtZyuMsvMvgpZm9lY cQk9s1JM8UvufX2FYgozpSsnKlUsEkUaOFWFy7vkbr8RrKEBtYVJ0HgXhQMAfJy/NFFi QW4F5rPcXr/ZvtwjShsTB2EbvHONm3oBfmTsbd861XgaDBaE3ZLZYmDSlvmUJ29Q9sq0 5I18owchR9G75qOcG1IYdvRvZ73P8xYDHxFEqtL86cos85eBJN6t3l+qF7maC7KIU+Ry doz/X0+tI+H7sFT3RXHnPTkbLT3s1Dv1WAV/D3T3A2lFMhyYHDF63u3+R/YltC+NtEa+ Ly6w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QZ5JgxKTY6j7jOJgJ2ehiBZmm45GMeMFdXbMkDT92PE=; b=v+9Cxqe19O88sBmMrCo8lCKpZaLtmWe6UuMADyOjmEUtU+4vH2D59YzQbc1kyzzsaY TafUms4fXc2F1FoVbkdiOLjILT+DLc0mmeRqqmKGBUW/dz8bOQ7IXscrWjmnFLvxS9gO wJ0rdNZ1DIX9Xg0w9MVfasr+/7co1Qs966uh6EqVTu2/+BUPKHZEQ6Y97SbaF9Vik47a vU5+VAm1Ae4MshGQVJUzhJ3ciTA6gIlTeEX7EO+ELchmMrAygWbaJpQUoiV/4pVv8i7O uPuKn89KtNpwl8US8SXHw2L5pplNuyuJZhDcltTPC9x83FVMxYKpGbsYnNLMqb7PpqrD zolw== X-Gm-Message-State: AOAM532oIAzMHY0OnENe/sBaI3UNV+CuhFInlH3lJMZbXc8k4jBQyEBQ qf2Fj4ZjJ4fQ8vptP9f1ph4gKiW16xCSzw== X-Google-Smtp-Source: ABdhPJwQUj5TtnUCz7uxrD8yi9d7ALgHKXbSqz2AUg45C3YQTGxM+VuUdjq6UlFlgtLE0/w4+7AZ/Q== X-Received: by 2002:a17:90b:3a85:b0:1bf:929c:1b1e with SMTP id om5-20020a17090b3a8500b001bf929c1b1emr427661pjb.200.1646724036078; Mon, 07 Mar 2022 23:20:36 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 17/33] target/nios2: Prevent writes to read-only or reserved control fields Date: Mon, 7 Mar 2022 21:19:49 -1000 Message-Id: <20220308072005.307955-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102a (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646725079289100005 Content-Type: text/plain; charset="utf-8" Create an array of masks which detail the writable and readonly bits for each control register. Apply them when writing to control registers. Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 13 ++++++ target/nios2/cpu.c | 90 +++++++++++++++++++++++++++++++++------- target/nios2/translate.c | 80 ++++++++++++++++++++++++++++------- 3 files changed, 152 insertions(+), 31 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 927c4aaa80..7faec97d77 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -207,6 +207,11 @@ struct CPUNios2State { int error_code; }; =20 +typedef struct { + uint32_t writable; + uint32_t readonly; +} ControlRegState; + /** * Nios2CPU: * @env: #CPUNios2State @@ -230,9 +235,17 @@ struct Nios2CPU { uint32_t reset_addr; uint32_t exception_addr; uint32_t fast_tlb_miss_addr; + + /* Bits within each control register which are reserved or readonly. */ + ControlRegState cr_state[NUM_CR_REGS]; }; =20 =20 +static inline bool nios2_cr_reserved(const ControlRegState *s) +{ + return (s->writable | s->readonly) =3D=3D 0; +} + void nios2_tcg_init(void); void nios2_cpu_do_interrupt(CPUState *cs); void dump_mmu(CPUNios2State *env); diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index f2813d3b47..189adf111c 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -88,6 +88,55 @@ static void nios2_cpu_initfn(Object *obj) =20 cpu_set_cpustate_pointers(cpu); =20 + /* Begin with all fields of all registers are reserved. */ + memset(cpu->cr_state, 0, sizeof(cpu->cr_state)); + + /* + * The combination of writable and readonly is the set of all + * non-reserved fields. We apply writable as a mask to bits, + * and merge in existing readonly bits, before storing. + */ +#define WR_REG(C) cpu->cr_state[C].writable =3D -1 +#define RO_REG(C) cpu->cr_state[C].readonly =3D -1 +#define WR_FIELD(C, F) cpu->cr_state[C].writable |=3D R_##C##_##F##_MASK +#define RO_FIELD(C, F) cpu->cr_state[C].readonly |=3D R_##C##_##F##_MASK + + WR_FIELD(CR_STATUS, PIE); + WR_REG(CR_ESTATUS); + WR_REG(CR_BSTATUS); + RO_REG(CR_CPUID); + WR_FIELD(CR_EXCEPTION, CAUSE); + WR_REG(CR_BADADDR); + + /* TODO: These control registers are not present with the EIC. */ + WR_REG(CR_IENABLE); + RO_REG(CR_IPENDING); + + if (cpu->mmu_present) { + WR_FIELD(CR_STATUS, U); + WR_FIELD(CR_STATUS, EH); + + WR_FIELD(CR_PTEADDR, VPN); + WR_FIELD(CR_PTEADDR, PTBASE); + + RO_FIELD(CR_TLBMISC, D); + RO_FIELD(CR_TLBMISC, PERM); + RO_FIELD(CR_TLBMISC, BAD); + RO_FIELD(CR_TLBMISC, DBL); + WR_FIELD(CR_TLBMISC, WR); + WR_FIELD(CR_TLBMISC, RD); + WR_FIELD(CR_TLBMISC, WAY); + + WR_REG(CR_TLBACC); + } + + /* TODO: ECC and MPU not implemented. */ + +#undef WR_REG +#undef RO_REG +#undef WR_FIELD +#undef RO_FIELD + #if !defined(CONFIG_USER_ONLY) mmu_init(&cpu->env); =20 @@ -152,23 +201,26 @@ static void nios2_cpu_disas_set_info(CPUState *cpu, d= isassemble_info *info) static int nios2_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, = int n) { Nios2CPU *cpu =3D NIOS2_CPU(cs); - CPUClass *cc =3D CPU_GET_CLASS(cs); CPUNios2State *env =3D &cpu->env; + uint32_t val; =20 - if (n > cc->gdb_num_core_regs) { + if (n < 32) { /* GP regs */ + val =3D env->regs[n]; + } else if (n =3D=3D 32) { /* PC */ + val =3D env->pc; + } else if (n < 49) { /* Status regs */ + unsigned cr =3D n - 33; + if (nios2_cr_reserved(&cpu->cr_state[cr])) { + val =3D 0; + } else { + val =3D env->ctrl[n - 33]; + } + } else { + /* Invalid regs */ return 0; } =20 - if (n < 32) { /* GP regs */ - return gdb_get_reg32(mem_buf, env->regs[n]); - } else if (n =3D=3D 32) { /* PC */ - return gdb_get_reg32(mem_buf, env->pc); - } else if (n < 49) { /* Status regs */ - return gdb_get_reg32(mem_buf, env->ctrl[n - 33]); - } - - /* Invalid regs */ - return 0; + return gdb_get_reg32(mem_buf, val); } =20 static int nios2_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, in= t n) @@ -176,17 +228,25 @@ static int nios2_cpu_gdb_write_register(CPUState *cs,= uint8_t *mem_buf, int n) Nios2CPU *cpu =3D NIOS2_CPU(cs); CPUClass *cc =3D CPU_GET_CLASS(cs); CPUNios2State *env =3D &cpu->env; + uint32_t val; =20 if (n > cc->gdb_num_core_regs) { return 0; } + val =3D ldl_p(mem_buf); =20 if (n < 32) { /* GP regs */ - env->regs[n] =3D ldl_p(mem_buf); + env->regs[n] =3D val; } else if (n =3D=3D 32) { /* PC */ - env->pc =3D ldl_p(mem_buf); + env->pc =3D val; } else if (n < 49) { /* Status regs */ - env->ctrl[n - 33] =3D ldl_p(mem_buf); + unsigned cr =3D n - 33; + /* ??? Maybe allow the debugger to write to readonly fields. */ + val &=3D cpu->cr_state[cr].writable; + val |=3D cpu->cr_state[cr].readonly & env->ctrl[cr]; + env->ctrl[cr] =3D val; + } else { + g_assert_not_reached(); } =20 return 4; diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 77b3bf05f3..38e16df459 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -101,6 +101,7 @@ typedef struct DisasContext { TCGv_i32 zero; target_ulong pc; int mem_idx; + const ControlRegState *cr_state; } DisasContext; =20 static TCGv cpu_R[NUM_GP_REGS]; @@ -452,17 +453,26 @@ static void callr(DisasContext *dc, uint32_t code, ui= nt32_t flags) /* rC <- ctlN */ static void rdctl(DisasContext *dc, uint32_t code, uint32_t flags) { - R_TYPE(instr, code); - TCGv t1, t2; - if (!gen_check_supervisor(dc)) { return; } =20 +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + R_TYPE(instr, code); + TCGv t1, t2; + if (unlikely(instr.c =3D=3D R_ZERO)) { return; } =20 + /* Reserved registers read as zero. */ + if (nios2_cr_reserved(&dc->cr_state[instr.imm5])) { + tcg_gen_movi_tl(cpu_R[instr.c], 0); + return; + } + switch (instr.imm5) { case CR_IPENDING: /* @@ -486,6 +496,7 @@ static void rdctl(DisasContext *dc, uint32_t code, uint= 32_t flags) offsetof(CPUNios2State, ctrl[instr.imm5])); break; } +#endif } =20 /* ctlN <- rA */ @@ -500,6 +511,14 @@ static void wrctl(DisasContext *dc, uint32_t code, uin= t32_t flags) #else R_TYPE(instr, code); TCGv v =3D load_gpr(dc, instr.a); + uint32_t ofs =3D offsetof(CPUNios2State, ctrl[instr.imm5]); + uint32_t wr =3D dc->cr_state[instr.imm5].writable; + uint32_t ro =3D dc->cr_state[instr.imm5].readonly; + + /* Skip reserved or readonly registers. */ + if (wr =3D=3D 0) { + return; + } =20 switch (instr.imm5) { case CR_PTEADDR: @@ -511,17 +530,35 @@ static void wrctl(DisasContext *dc, uint32_t code, ui= nt32_t flags) case CR_TLBMISC: gen_helper_mmu_write_tlbmisc(cpu_env, v); break; - case CR_IPENDING: - /* ipending is read only, writes ignored. */ - break; case CR_STATUS: case CR_IENABLE: /* If interrupts were enabled using WRCTL, trigger them. */ dc->base.is_jmp =3D DISAS_UPDATE; /* fall through */ default: - tcg_gen_st_tl(v, cpu_env, - offsetof(CPUNios2State, ctrl[instr.imm5])); + if (wr =3D=3D -1) { + /* The register is entirely writable. */ + tcg_gen_st_tl(v, cpu_env, ofs); + } else { + /* + * The register is partially read-only or reserved: + * merge the value. + */ + TCGv n =3D tcg_temp_new(); + + tcg_gen_andi_tl(n, v, wr); + + if (ro !=3D 0) { + TCGv o =3D tcg_temp_new(); + tcg_gen_ld_tl(o, cpu_env, ofs); + tcg_gen_andi_tl(o, o, ro); + tcg_gen_or_tl(n, n, o); + tcg_temp_free(o); + } + + tcg_gen_st_tl(n, cpu_env, ofs); + tcg_temp_free(n); + } break; } #endif @@ -785,9 +822,11 @@ static void nios2_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) { DisasContext *dc =3D container_of(dcbase, DisasContext, base); CPUNios2State *env =3D cs->env_ptr; + Nios2CPU *cpu =3D env_archcpu(env); int page_insns; =20 dc->mem_idx =3D cpu_mmu_index(env, false); + dc->cr_state =3D cpu->cr_state; =20 /* Bound the number of insns to execute to those left on the page. */ page_insns =3D -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; @@ -902,16 +941,25 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int = flags) } =20 #if !defined(CONFIG_USER_ONLY) - for (i =3D 0; i < NUM_CR_REGS; i++) { - qemu_fprintf(f, "%9s=3D%8.8x ", cr_regnames[i], env->ctrl[i]); - if ((i + 1) % 4 =3D=3D 0) { - qemu_fprintf(f, "\n"); + int j; + + for (i =3D j =3D 0; i < NUM_CR_REGS; i++) { + if (!nios2_cr_reserved(&cpu->cr_state[i])) { + qemu_fprintf(f, "%9s=3D%8.8x ", cr_regnames[i], env->ctrl[i]); + if (++j % 4 =3D=3D 0) { + qemu_fprintf(f, "\n"); + } } } - qemu_fprintf(f, " mmu write: VPN=3D%05X PID %02X TLBACC %08X\n", - env->mmu.pteaddr_wr & R_CR_PTEADDR_VPN_MASK, - FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID), - env->mmu.tlbacc_wr); + if (j % 4 !=3D 0) { + qemu_fprintf(f, "\n"); + } + if (cpu->mmu_present) { + qemu_fprintf(f, " mmu write: VPN=3D%05X PID %02X TLBACC %08X\n", + env->mmu.pteaddr_wr & R_CR_PTEADDR_VPN_MASK, + FIELD_EX32(env->mmu.tlbmisc_wr, CR_TLBMISC, PID), + env->mmu.tlbacc_wr); + } #endif qemu_fprintf(f, "\n\n"); } --=20 2.25.1 From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646724873872102.5904072367872; Mon, 7 Mar 2022 23:34:33 -0800 (PST) Received: from localhost ([::1]:53380 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nRUMY-0000C8-9C for importer@patchew.org; Tue, 08 Mar 2022 02:34:31 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45296) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nRU9G-0005GL-Q3 for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:52 -0500 Received: from [2607:f8b0:4864:20::42e] (port=46756 helo=mail-pf1-x42e.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nRU9A-0006OG-Q9 for qemu-devel@nongnu.org; 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[50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=j21dTyIj41G0K43gYWwqQRtlgt2XT5TcX5RNUrMtfBI=; b=zZGkqOimN6rEFEy6wYLBE4Cc8UfQSiZmClq3qNgXtZCRUnuwaT61b01I1bdYaz+Bbs H9G394kAcH4S5cLL4FojyF6PHr6E88pbCVIxB08tcLPVsixVL0K4MzK/UcXAuJiHpBus jmIVcDPM5qSpycCc/tQPsczzu2oLB34zy+IMJ5BFNz/52CKqovopQ+H+BJAZOD8f4Prs thH3WnTpXSsyTyvYu00sRHLd4BLAJZNg2rpUJMMVfOpWDpZIGjnieQDsITiwR2azRT8A NZZSii49sA7h1zsJAL9PxL5D7SPgtMRcz3Fllzm6a/3PU5Ob4IXr56zBCWjIuEiT0WGm Mcdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=j21dTyIj41G0K43gYWwqQRtlgt2XT5TcX5RNUrMtfBI=; b=6Zx0SD8zygPXBnozOResDF7gkLuoh4F1GWAENlkKlrUv/SNb5eXmsRXaE0ZQIvYARb qtEQGrAbHl/XhHkqSE1/47SvJZSSMTm0yxGOygV6zBRqNbmKzuLNJLtIY+Mx2md7CJvc Y3SKcT6U3I8QXaHs/MuO+HWDL6YT3/5sXhU/3gT8unSMGl8OrIETzWs+QtJQlLYL6dq7 J1gnrXoeSUabQ41jLUBhNrUrskYU6sYOb1fJUqAIuvv1uD+Jkh7Y6XspRi/y7zgKbp1o vD7HrMj7sdGU4bA4LAmTTUnatLEcXTFXnejgiD+MbC6s41x5WtIgRuM4VMrfzK0gvqIq xzyA== X-Gm-Message-State: AOAM533dfHUZSu7zS0IWJTG3qoOlowEfv4ycGcx2VuYtBNs06/cowrJS v02bGVvpXRAm2GUKBWgpjhMC5uxOiQQ+0g== X-Google-Smtp-Source: ABdhPJxh7ZJBL5ZpwipjkFhQoYbwFpM6rmvn3gDrg6Ji5hihD2D2/ikpgoTM5zE54twkSlCUHZVurA== X-Received: by 2002:a63:513:0:b0:380:1180:9b48 with SMTP id 19-20020a630513000000b0038011809b48mr11112051pgf.623.1646724037772; Mon, 07 Mar 2022 23:20:37 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 18/33] target/nios2: Implement cpuid Date: Mon, 7 Mar 2022 21:19:50 -1000 Message-Id: <20220308072005.307955-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42e (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646724875639100001 Content-Type: text/plain; charset="utf-8" Copy the existing cpu_index into the space reserved for CR_CPUID. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/cpu.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 189adf111c..fbcb4da737 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -159,6 +159,7 @@ static ObjectClass *nios2_cpu_class_by_name(const char = *cpu_model) static void nios2_cpu_realizefn(DeviceState *dev, Error **errp) { CPUState *cs =3D CPU(dev); + Nios2CPU *cpu =3D NIOS2_CPU(cs); Nios2CPUClass *ncc =3D NIOS2_CPU_GET_CLASS(dev); Error *local_err =3D NULL; =20 @@ -171,6 +172,9 @@ static void nios2_cpu_realizefn(DeviceState *dev, Error= **errp) qemu_init_vcpu(cs); cpu_reset(cs); =20 + /* We have reserved storage for ctrl[CR_CPUID]; might as well use it. = */ + cpu->env.cpuid =3D cs->cpu_index; + ncc->parent_realize(dev, errp); } =20 --=20 2.25.1 From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646725548838289.5044025254738; Mon, 7 Mar 2022 23:45:48 -0800 (PST) Received: from localhost ([::1]:50588 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nRUXU-0000hJ-J5 for importer@patchew.org; Tue, 08 Mar 2022 02:45:48 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45326) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nRU9H-0005GN-P2 for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:52 -0500 Received: from [2607:f8b0:4864:20::42f] (port=37388 helo=mail-pf1-x42f.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nRU9D-0006Ow-CA for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:47 -0500 Received: by mail-pf1-x42f.google.com with SMTP id t5so16608144pfg.4 for ; Mon, 07 Mar 2022 23:20:40 -0800 (PST) Received: from localhost.localdomain (cpe-50-113-46-110.hawaii.res.rr.com. [50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:38 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=f4LFEjNzvKTomQ6aq5bDTV/uxlszeP0HWEDXmP1bzdw=; b=MtNGz9FGPuZ+E8BKRX2FVYeSTszP/wr/pc1yATnrs8I5/khY4Dl+BFTSk27IERPHyg qIyudnyQmr7gIfnJTD/V/VWq8mlLmn2tA+PA18bLuhrSrrxybBfXuxJSbkWeclB/8gZ4 Y8b0PdchpQjTEVHyUSGHE7FluWoe8Id6yMCPj0WdLEBTWhef9ZV1xAkBoRhNTpHXQ8kt em1f55zsIv8jwsRJNKOXwI05NVHYi6JW19NvFeclFavf8OfYAzpT+q4p0ZwXxQ3OEDRm iPRJBmBJJKulMJJMiSquW2fp8UryImVNpTvEjpIireF/ImRMo1Ub7bRXIE/qOX7m5diO c/EQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=f4LFEjNzvKTomQ6aq5bDTV/uxlszeP0HWEDXmP1bzdw=; b=4cNnFa1Ugpw+SLLZ8UM3UWPyrdGmjQAcQ3Wgheh7w34R/nBu50h+ThYU8vb98YkIjY HA2HrL3LUBNWzMp6TG47aeCpcocmxhCiwqNg2klBL9DUCC1GwFLIcZaj4l3af5dC0eL7 oEQGlGsJs8kwpzbm0WP3C/Oy+kaIq/s6i3YSskmmsfi5/mCoALRq4X4Gv+lFnZoUgaIJ nJ5ezQiswRMJ7mwrSAG3Agc8r3GWkaQpvL7XIVASAji6EOm7u9G9RtN3Qzo+PoXVJCks Ax/bW3vrfG3m7s+WaTBdG1EhGn89HSIjSo6gvNThEMPuJgaHKJbqqS9WOhzV8zwJ9kO0 ke3A== X-Gm-Message-State: AOAM532+1pfZioIUB4wFarBKG/rBGwu4FA2kzx+P+gCRPrcEJ8lDSr5B yz2moRv/D8Dq9yd3dvcydSXJQgoRZONmMg== X-Google-Smtp-Source: ABdhPJwGbj2dgIWrzODorg4Nn5obiwVAiTWSXU5q24cNNpSWNT7bJfgq8jfda/Vv23sKY635DXMSaQ== X-Received: by 2002:a05:6a00:228d:b0:4f6:d4a8:7f47 with SMTP id f13-20020a056a00228d00b004f6d4a87f47mr15922833pfe.66.1646724039336; Mon, 07 Mar 2022 23:20:39 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 19/33] target/nios2: Implement CR_STATUS.RSIE Date: Mon, 7 Mar 2022 21:19:51 -1000 Message-Id: <20220308072005.307955-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42f (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42f; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42f.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646725560820100001 Content-Type: text/plain; charset="utf-8" Without EIC, this bit is RES1. So set the bit at reset, and add it to the readonly fields of CR_STATUS. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/cpu.h | 1 + target/nios2/cpu.c | 5 +++-- 2 files changed, 4 insertions(+), 2 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 7faec97d77..b418deec4c 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -108,6 +108,7 @@ FIELD(CR_STATUS, IL, 4, 6) FIELD(CR_STATUS, CRS, 10, 6) FIELD(CR_STATUS, PRS, 16, 6) FIELD(CR_STATUS, NMI, 22, 1) +FIELD(CR_STATUS, RSIE, 23, 1) =20 #define CR_STATUS_PIE (1u << R_CR_STATUS_PIE_SHIFT) #define CR_STATUS_U (1u << R_CR_STATUS_U_SHIFT) diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index fbcb4da737..ed7b9f9459 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -59,9 +59,9 @@ static void nios2_cpu_reset(DeviceState *dev) =20 #if defined(CONFIG_USER_ONLY) /* Start in user mode with interrupts enabled. */ - env->status =3D CR_STATUS_U | CR_STATUS_PIE; + env->status =3D CR_STATUS_RSIE | CR_STATUS_U | CR_STATUS_PIE; #else - env->status =3D 0; + env->status =3D CR_STATUS_RSIE; #endif } =20 @@ -109,6 +109,7 @@ static void nios2_cpu_initfn(Object *obj) WR_REG(CR_BADADDR); =20 /* TODO: These control registers are not present with the EIC. */ + RO_FIELD(CR_STATUS, RSIE); WR_REG(CR_IENABLE); RO_REG(CR_IPENDING); =20 --=20 2.25.1 From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646724705653479.7047412276538; Mon, 7 Mar 2022 23:31:45 -0800 (PST) Received: from localhost ([::1]:44874 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nRUJs-0002sQ-D1 for importer@patchew.org; Tue, 08 Mar 2022 02:31:44 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45324) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nRU9H-0005GM-Oq for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:52 -0500 Received: from [2607:f8b0:4864:20::52d] (port=43929 helo=mail-pg1-x52d.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nRU9E-0006Pl-62 for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:47 -0500 Received: by mail-pg1-x52d.google.com with SMTP id 27so15658542pgk.10 for ; Mon, 07 Mar 2022 23:20:41 -0800 (PST) Received: from localhost.localdomain (cpe-50-113-46-110.hawaii.res.rr.com. [50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:40 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=bw6rFTkskI2G9XcqtKPw9z5w66+BAr5hIkSHPWYFPfw=; b=NUiUXiMyH5AnfXPGh1sDOaFmusDcGTOYhcQ4RF3bjgaUK+OyBCTAiqzztFVtWU3wMH JMki9ZWXQZbjoYzEkYr33pk+alVZZY28I2kydXD9zHKPip1V2058VvwhcR6UfrpCgYtY /l1LaO0PtafS64D0fgFinyZxjC7uSvNFn1b/4F1wXcEowYj88g/5uw2+GeiD1VKxJ4Ru 3RP4BN6kjo31YPmoPrtXlvEr3Ed3XZZ8sHyo1Tc60yWjCfH5PxeBnJeJ3YjdSJaGiF6J /TE4Ip37TipkhnmebTY4hVzkbtjE4XkfitgZysC9s0/AX7v062Si9y/ptS91LfDLdsTk LgzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bw6rFTkskI2G9XcqtKPw9z5w66+BAr5hIkSHPWYFPfw=; b=MvFRp3i8ImRAj+8ECpevrwE8V/05DMi3aet/Dz8yKor5ZntHgRc3rg4joNXBnWwypI YP5PSqiURxjl/lY9IuZf2snjMwZVj8Ox/+JPnL3yOYuPp6iSanF9V+zIR8ZNiV20TyKP ogw56Tuj/boWbuq6aortvH/nY7N562Au8ZZNA+dHjvseOOFJScz0Qz/u8T/UtTmNdh2K eyCV3fchaaZ7/i1mo+krA/NeCuDSKTG4JmU3yEKUvdsbDJ1heBLtuw6Uw6DH3U02A+Uc uP5WJjebPspvsErHQt9dutzHhEefIP6qEnNS72HVXeNzjCeRDlkXvhA7hs5bgErSvaAI unRg== X-Gm-Message-State: AOAM5335elpVERGQEcReB+rIJxx+XYG+qqUtPwnv31xfG4oqVCvVIe4T fcOFojsOoy0r23S8XX/FqNEd5RroVU42pA== X-Google-Smtp-Source: ABdhPJwohXfB405ihzR7q+eXDC/jKyE43hxRpgPEB1uN1j8duLj0bwsxjeEce6FnlfXBdot64r7JHA== X-Received: by 2002:a63:5a53:0:b0:373:9a98:6845 with SMTP id k19-20020a635a53000000b003739a986845mr13124801pgm.88.1646724040842; Mon, 07 Mar 2022 23:20:40 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 20/33] target/nios2: Remove CPU_INTERRUPT_NMI Date: Mon, 7 Mar 2022 21:19:52 -1000 Message-Id: <20220308072005.307955-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::52d (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52d; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52d.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646724707991100001 Content-Type: text/plain; charset="utf-8" This interrupt bit is never set, so testing it in nios2_cpu_has_work is pointless. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/cpu.h | 2 -- target/nios2/cpu.c | 2 +- 2 files changed, 1 insertion(+), 3 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index b418deec4c..f582e52aa4 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -175,8 +175,6 @@ FIELD(CR_TLBMISC, EE, 24, 1) #define EXCP_MPUI 16 #define EXCP_MPUD 17 =20 -#define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 - struct CPUNios2State { uint32_t regs[NUM_GP_REGS]; union { diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index ed7b9f9459..2779650128 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -36,7 +36,7 @@ static void nios2_cpu_set_pc(CPUState *cs, vaddr value) =20 static bool nios2_cpu_has_work(CPUState *cs) { - return cs->interrupt_request & (CPU_INTERRUPT_HARD | CPU_INTERRUPT_NMI= ); + return cs->interrupt_request & CPU_INTERRUPT_HARD; } =20 static void nios2_cpu_reset(DeviceState *dev) --=20 2.25.1 From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646725636110336.2173330451851; Mon, 7 Mar 2022 23:47:16 -0800 (PST) Received: from localhost ([::1]:53604 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nRUYt-0002qS-24 for importer@patchew.org; Tue, 08 Mar 2022 02:47:15 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45362) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nRU9K-0005GS-NF for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:52 -0500 Received: from [2607:f8b0:4864:20::52a] (port=39464 helo=mail-pg1-x52a.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nRU9G-0006QY-1M for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:48 -0500 Received: by mail-pg1-x52a.google.com with SMTP id q19so3062198pgm.6 for ; Mon, 07 Mar 2022 23:20:43 -0800 (PST) Received: from localhost.localdomain (cpe-50-113-46-110.hawaii.res.rr.com. [50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:41 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9OTzOulpMcp9+HOcbK241jx0Fw2zaG+2rEyo8QB0mMM=; b=UlB3Be4w/c+6RcqhxFkxq/UBhORlgJDwTpX3WnxL36FzAa0W/AVEsBw0Pm/vvram+x S6u0evDOhIidRT20LE5D554C7ta2Bj6OziV46Ws0b5EcU34shsFsNvVRbk6qXbTtNNqQ ZtxCNBsib3TSqZEJyQOsAE+UQTvwLaUQxymFh372mIJBh+wtF7H+h87qNelAVc+EVZ8i ejZew3Y14I9Z7q9D7V1L3wS3MWtxKyFNkWJ7xU9YuhbJIuq4wpVAJmjQ7pS/812VtkPS eukqSZELXNMzRF7y8UhS/Nim7UXvoodIBLBHDnjQYyOf+FR1Chg3uOPsHKGs9Ldo5XAt 6KjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9OTzOulpMcp9+HOcbK241jx0Fw2zaG+2rEyo8QB0mMM=; b=PlMrd7cehcA8BLDbZaDQNcOFTYaYxCvZUXYxKWipF4+1M5HnpvSJ5UqpR3RxG2CquN c+jyO1+QXfhg5IHrUo/jZ4zikAfd9m2m7gZOL+Q+/OLpc8W+QR1waxua9zBypfA8l42g t02y54VDhwayQj8fMc1W8Ooo1haVEyVq+DZh+t4qqMlG+aKWb4vpFKFTaCsoCBjaJRyJ 2lUPlqNg3RUno91wVBGCuSFgeF1+8cF7va1v7xzBnnX1paXCc+mlCDpR5nd6OtmU6HKn rTDLGi3moIliRnVt3sClOUFcJsYxqv0uL11nb/npBazF3e3dR/ngwufWB+4NqIOiYl/C OjSQ== X-Gm-Message-State: AOAM533LCQ+/xC6mG21ag5FrPkdpNl/gH3Svo0olmzdTmK4MDlSv972j WfuSe5D6yr6STvcrtxAxYxcEya6xwlIuSg== X-Google-Smtp-Source: ABdhPJxn2jgx79nGqYV7m6V2PrsRVbR1ofwk6nwOtshnPeoXnedXYfUNYIejNpRHskT4Z9u7HKUEIg== X-Received: by 2002:a63:8043:0:b0:380:959e:5bb7 with SMTP id j64-20020a638043000000b00380959e5bb7mr687890pgd.5.1646724042331; Mon, 07 Mar 2022 23:20:42 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 21/33] target/nios2: Use tcg_constant_tl Date: Mon, 7 Mar 2022 21:19:53 -1000 Message-Id: <20220308072005.307955-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::52a (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52a; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52a.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646725638292100001 Content-Type: text/plain; charset="utf-8" Replace current uses of tcg_const_tl, and remove the frees. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/translate.c | 36 ++++++++---------------------------- 1 file changed, 8 insertions(+), 28 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 38e16df459..6ff9c18502 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -98,7 +98,6 @@ =20 typedef struct DisasContext { DisasContextBase base; - TCGv_i32 zero; target_ulong pc; int mem_idx; const ControlRegState *cr_state; @@ -124,31 +123,20 @@ static uint8_t get_opxcode(uint32_t code) return instr.opx; } =20 -static TCGv load_zero(DisasContext *dc) +static TCGv load_gpr(DisasContext *dc, unsigned reg) { - if (!dc->zero) { - dc->zero =3D tcg_const_i32(0); - } - return dc->zero; -} - -static TCGv load_gpr(DisasContext *dc, uint8_t reg) -{ - if (likely(reg !=3D R_ZERO)) { - return cpu_R[reg]; - } else { - return load_zero(dc); + assert(reg < NUM_GP_REGS); + if (unlikely(reg =3D=3D R_ZERO)) { + return tcg_constant_tl(0); } + return cpu_R[reg]; } =20 static void t_gen_helper_raise_exception(DisasContext *dc, uint32_t index) { - TCGv_i32 tmp =3D tcg_const_i32(index); - tcg_gen_movi_tl(cpu_pc, dc->pc); - gen_helper_raise_exception(cpu_env, tmp); - tcg_temp_free_i32(tmp); + gen_helper_raise_exception(cpu_env, tcg_constant_i32(index)); dc->base.is_jmp =3D DISAS_NORETURN; } =20 @@ -675,8 +663,8 @@ static void divu(DisasContext *dc, uint32_t code, uint3= 2_t flags) =20 TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); - TCGv t2 =3D tcg_const_tl(0); - TCGv t3 =3D tcg_const_tl(1); + TCGv t2 =3D tcg_constant_tl(0); + TCGv t3 =3D tcg_constant_tl(1); =20 tcg_gen_ext32u_tl(t0, load_gpr(dc, instr.a)); tcg_gen_ext32u_tl(t1, load_gpr(dc, instr.b)); @@ -684,8 +672,6 @@ static void divu(DisasContext *dc, uint32_t code, uint3= 2_t flags) tcg_gen_divu_tl(cpu_R[instr.c], t0, t1); tcg_gen_ext32s_tl(cpu_R[instr.c], cpu_R[instr.c]); =20 - tcg_temp_free(t3); - tcg_temp_free(t2); tcg_temp_free(t1); tcg_temp_free(t0); } @@ -863,14 +849,8 @@ static void nios2_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) return; } =20 - dc->zero =3D NULL; - instr =3D &i_type_instructions[op]; instr->handler(dc, code, instr->flags); - - if (dc->zero) { - tcg_temp_free(dc->zero); - } } =20 static void nios2_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) --=20 2.25.1 From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646725761933833.0393303438849; Mon, 7 Mar 2022 23:49:21 -0800 (PST) Received: from localhost ([::1]:59242 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nRUav-0006ea-I9 for importer@patchew.org; Tue, 08 Mar 2022 02:49:21 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45378) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nRU9K-0005GV-UD for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:52 -0500 Received: from [2607:f8b0:4864:20::436] (port=36738 helo=mail-pf1-x436.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nRU9G-0006RS-IE for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:49 -0500 Received: by mail-pf1-x436.google.com with SMTP id z16so16597645pfh.3 for ; Mon, 07 Mar 2022 23:20:44 -0800 (PST) Received: from localhost.localdomain (cpe-50-113-46-110.hawaii.res.rr.com. [50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:43 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=m9ZxJ7xCPOqabHZoycs1bdRfS3ZU/NWAbCAcKP/hjkY=; b=ePZ6byWbM/fT4QRwzET7CjRJb8RGDhfff/PQNdN7IU8MkU6nVM8RqqQ15nQourK2Pn RQL+a4WNBdhjeQ9clXWdRG4PHIZFLn6/wM3fn5QCM7KZKRGCMMRDawr7Iw6neypsfIxG cL00rObJ8uQ1T9HaQoRb38asPuC4GTASRHk4GDIIT1TM25guN1lBfuWxd7NjXIYhqa52 51hKhHB7wX/4VKDYy/2T5r/Iu8Wr3j4rpRqwbXiKgq/BELZ0RHp0siWHW8fO8SCYh1J6 /zSkZRzJWvsfE/6qmotTQlU4FSdspwJbNelO/w90+MSBxuBKuVDJoMbA6Cpb9AVWKWhs 8/GQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=m9ZxJ7xCPOqabHZoycs1bdRfS3ZU/NWAbCAcKP/hjkY=; b=qxF8kEaHi7shodRuPdx1GcPKrAi5RlBcB1QswjkZoWNnlEt9YZxn3mNveZiTLEeNmQ pBJbntty6U+jn0AAXCGOrES0KxCdxLGmc7eMkbr7Jepyt8y6ShhW5ZgBBvMOIT19mCUF qFYAciQknlTBozrfn/Ck2nekvVrWaE8uyYQdzdEv+dNAzADoPcJIQjegxTU47aNurEQM 9QksVCv1iRFrcV8usREZL3hqCXGc1hpwezU0bqrK0Oa4q0svqYRxKlRropBRbhcj5AUY Hk9bHdsx8n2pnnjMVzIA2qH9skhPAGfe3s0AmghhvGSQXIwZyt/MVFVhYZmQ8bvp+bbJ jyJw== X-Gm-Message-State: AOAM531eNc9D/a/50bvLCX14oNIwMy3d+SYg6R7rzGzZP3k9EwPF4BgH Ty791p3x0Wrju0aiKwarU9mL1nFV9O3vRw== X-Google-Smtp-Source: ABdhPJwogS3BoovHr4H4HNPW+2/lmKq+wHWJSVimJ6Nyqd4QRMviCKqBfpwHvZSGcShU3lhXWPSNOQ== X-Received: by 2002:a63:4560:0:b0:370:1f21:36b8 with SMTP id u32-20020a634560000000b003701f2136b8mr12837221pgk.181.1646724043833; Mon, 07 Mar 2022 23:20:43 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 22/33] target/nios2: Introduce dest_gpr Date: Mon, 7 Mar 2022 21:19:54 -1000 Message-Id: <20220308072005.307955-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::436 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::436; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x436.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646725771764100003 Content-Type: text/plain; charset="utf-8" Constrain all references to cpu_R[] to load_gpr and dest_gpr. This will be required for supporting shadow register sets. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/translate.c | 144 +++++++++++++++------------------------ 1 file changed, 55 insertions(+), 89 deletions(-) diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 6ff9c18502..7c2ad02685 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -100,6 +100,7 @@ typedef struct DisasContext { DisasContextBase base; target_ulong pc; int mem_idx; + TCGv sink; const ControlRegState *cr_state; } DisasContext; =20 @@ -132,6 +133,18 @@ static TCGv load_gpr(DisasContext *dc, unsigned reg) return cpu_R[reg]; } =20 +static TCGv dest_gpr(DisasContext *dc, unsigned reg) +{ + assert(reg < NUM_GP_REGS); + if (unlikely(reg =3D=3D R_ZERO)) { + if (dc->sink =3D=3D NULL) { + dc->sink =3D tcg_temp_new(); + } + return dc->sink; + } + return cpu_R[reg]; +} + static void t_gen_helper_raise_exception(DisasContext *dc, uint32_t index) { @@ -190,7 +203,7 @@ static void jmpi(DisasContext *dc, uint32_t code, uint3= 2_t flags) =20 static void call(DisasContext *dc, uint32_t code, uint32_t flags) { - tcg_gen_movi_tl(cpu_R[R_RA], dc->base.pc_next); + tcg_gen_movi_tl(dest_gpr(dc, R_RA), dc->base.pc_next); jmpi(dc, code, flags); } =20 @@ -203,27 +216,10 @@ static void gen_ldx(DisasContext *dc, uint32_t code, = uint32_t flags) I_TYPE(instr, code); =20 TCGv addr =3D tcg_temp_new(); - TCGv data; - - /* - * WARNING: Loads into R_ZERO are ignored, but we must generate the - * memory access itself to emulate the CPU precisely. Load - * from a protected page to R_ZERO will cause SIGSEGV on - * the Nios2 CPU. - */ - if (likely(instr.b !=3D R_ZERO)) { - data =3D cpu_R[instr.b]; - } else { - data =3D tcg_temp_new(); - } + TCGv data =3D dest_gpr(dc, instr.b); =20 tcg_gen_addi_tl(addr, load_gpr(dc, instr.a), instr.imm16.s); tcg_gen_qemu_ld_tl(data, addr, dc->mem_idx, flags); - - if (unlikely(instr.b =3D=3D R_ZERO)) { - tcg_temp_free(data); - } - tcg_temp_free(addr); } =20 @@ -253,7 +249,7 @@ static void gen_bxx(DisasContext *dc, uint32_t code, ui= nt32_t flags) I_TYPE(instr, code); =20 TCGLabel *l1 =3D gen_new_label(); - tcg_gen_brcond_tl(flags, cpu_R[instr.a], cpu_R[instr.b], l1); + tcg_gen_brcond_tl(flags, load_gpr(dc, instr.a), load_gpr(dc, instr.b),= l1); gen_goto_tb(dc, 0, dc->base.pc_next); gen_set_label(l1); gen_goto_tb(dc, 1, dc->base.pc_next + (instr.imm16.s & -4)); @@ -261,11 +257,12 @@ static void gen_bxx(DisasContext *dc, uint32_t code, = uint32_t flags) } =20 /* Comparison instructions */ -#define gen_i_cmpxx(fname, op3) = \ -static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) = \ -{ = \ - I_TYPE(instr, (code)); = \ - tcg_gen_setcondi_tl(flags, cpu_R[instr.b], cpu_R[instr.a], (op3)); = \ +#define gen_i_cmpxx(fname, op3) \ +static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \ +{ \ + I_TYPE(instr, (code)); \ + tcg_gen_setcondi_tl(flags, dest_gpr(dc, instr.b), \ + load_gpr(dc, instr.a), (op3)); \ } =20 gen_i_cmpxx(gen_cmpxxsi, instr.imm16.s) @@ -276,13 +273,7 @@ gen_i_cmpxx(gen_cmpxxui, instr.imm16.u) static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) = \ { = \ I_TYPE(instr, (code)); = \ - if (unlikely(instr.b =3D=3D R_ZERO)) { /* Store to R_ZERO is ignored *= / \ - return; = \ - } else if (instr.a =3D=3D R_ZERO) { /* MOVxI optimizations */ = \ - tcg_gen_movi_tl(cpu_R[instr.b], (resimm) ? (op3) : 0); = \ - } else { = \ - tcg_gen_##insn##_tl(cpu_R[instr.b], cpu_R[instr.a], (op3)); = \ - } = \ + tcg_gen_##insn##_tl(dest_gpr(dc, instr.b), load_gpr(dc, instr.a), (op3= )); \ } =20 gen_i_math_logic(addi, addi, 1, instr.imm16.s) @@ -383,7 +374,7 @@ static void eret(DisasContext *dc, uint32_t code, uint3= 2_t flags) #ifdef CONFIG_USER_ONLY g_assert_not_reached(); #else - gen_helper_eret(cpu_env, cpu_R[R_EA]); + gen_helper_eret(cpu_env, load_gpr(dc, R_EA)); dc->base.is_jmp =3D DISAS_NORETURN; #endif } @@ -391,16 +382,14 @@ static void eret(DisasContext *dc, uint32_t code, uin= t32_t flags) /* PC <- ra */ static void ret(DisasContext *dc, uint32_t code, uint32_t flags) { - tcg_gen_mov_tl(cpu_pc, cpu_R[R_RA]); - + tcg_gen_mov_tl(cpu_pc, load_gpr(dc, R_RA)); dc->base.is_jmp =3D DISAS_JUMP; } =20 /* PC <- ba */ static void bret(DisasContext *dc, uint32_t code, uint32_t flags) { - tcg_gen_mov_tl(cpu_pc, cpu_R[R_BA]); - + tcg_gen_mov_tl(cpu_pc, load_gpr(dc, R_BA)); dc->base.is_jmp =3D DISAS_JUMP; } =20 @@ -410,7 +399,6 @@ static void jmp(DisasContext *dc, uint32_t code, uint32= _t flags) R_TYPE(instr, code); =20 tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a)); - dc->base.is_jmp =3D DISAS_JUMP; } =20 @@ -419,9 +407,7 @@ static void nextpc(DisasContext *dc, uint32_t code, uin= t32_t flags) { R_TYPE(instr, code); =20 - if (likely(instr.c !=3D R_ZERO)) { - tcg_gen_movi_tl(cpu_R[instr.c], dc->base.pc_next); - } + tcg_gen_movi_tl(dest_gpr(dc, instr.c), dc->base.pc_next); } =20 /* @@ -433,7 +419,7 @@ static void callr(DisasContext *dc, uint32_t code, uint= 32_t flags) R_TYPE(instr, code); =20 tcg_gen_mov_tl(cpu_pc, load_gpr(dc, instr.a)); - tcg_gen_movi_tl(cpu_R[R_RA], dc->base.pc_next); + tcg_gen_movi_tl(dest_gpr(dc, R_RA), dc->base.pc_next); =20 dc->base.is_jmp =3D DISAS_JUMP; } @@ -449,15 +435,11 @@ static void rdctl(DisasContext *dc, uint32_t code, ui= nt32_t flags) g_assert_not_reached(); #else R_TYPE(instr, code); - TCGv t1, t2; - - if (unlikely(instr.c =3D=3D R_ZERO)) { - return; - } + TCGv t1, t2, dest =3D dest_gpr(dc, instr.c); =20 /* Reserved registers read as zero. */ if (nios2_cr_reserved(&dc->cr_state[instr.imm5])) { - tcg_gen_movi_tl(cpu_R[instr.c], 0); + tcg_gen_movi_tl(dest, 0); return; } =20 @@ -475,12 +457,12 @@ static void rdctl(DisasContext *dc, uint32_t code, ui= nt32_t flags) t2 =3D tcg_temp_new(); tcg_gen_ld_tl(t1, cpu_env, offsetof(CPUNios2State, ipending)); tcg_gen_ld_tl(t2, cpu_env, offsetof(CPUNios2State, ienable)); - tcg_gen_and_tl(cpu_R[instr.c], t1, t2); + tcg_gen_and_tl(dest, t1, t2); tcg_temp_free(t1); tcg_temp_free(t2); break; default: - tcg_gen_ld_tl(cpu_R[instr.c], cpu_env, + tcg_gen_ld_tl(dest, cpu_env, offsetof(CPUNios2State, ctrl[instr.imm5])); break; } @@ -556,10 +538,8 @@ static void wrctl(DisasContext *dc, uint32_t code, uin= t32_t flags) static void gen_cmpxx(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, code); - if (likely(instr.c !=3D R_ZERO)) { - tcg_gen_setcond_tl(flags, cpu_R[instr.c], cpu_R[instr.a], - cpu_R[instr.b]); - } + tcg_gen_setcond_tl(flags, dest_gpr(dc, instr.c), + load_gpr(dc, instr.a), load_gpr(dc, instr.b)); } =20 /* Math/logic instructions */ @@ -567,9 +547,7 @@ static void gen_cmpxx(DisasContext *dc, uint32_t code, = uint32_t flags) static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) = \ { = \ R_TYPE(instr, (code)); = \ - if (likely(instr.c !=3D R_ZERO)) { = \ - tcg_gen_##insn(cpu_R[instr.c], load_gpr((dc), instr.a), (op3)); = \ - } = \ + tcg_gen_##insn(dest_gpr(dc, instr.c), load_gpr(dc, instr.a), (op3)); = \ } =20 gen_r_math_logic(add, add_tl, load_gpr(dc, instr.b)) @@ -590,28 +568,24 @@ gen_r_math_logic(roli, rotli_tl, instr.imm5) static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \ { \ R_TYPE(instr, (code)); \ - if (likely(instr.c !=3D R_ZERO)) { \ - TCGv t0 =3D tcg_temp_new(); \ - tcg_gen_##insn(t0, cpu_R[instr.c], \ - load_gpr(dc, instr.a), load_gpr(dc, instr.b)); \ - tcg_temp_free(t0); \ - } \ + TCGv t0 =3D tcg_temp_new(); \ + tcg_gen_##insn(t0, dest_gpr(dc, instr.c), \ + load_gpr(dc, instr.a), load_gpr(dc, instr.b)); \ + tcg_temp_free(t0); \ } =20 gen_r_mul(mulxss, muls2_tl) gen_r_mul(mulxuu, mulu2_tl) gen_r_mul(mulxsu, mulsu2_tl) =20 -#define gen_r_shift_s(fname, insn) = \ -static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) = \ -{ = \ - R_TYPE(instr, (code)); = \ - if (likely(instr.c !=3D R_ZERO)) { = \ - TCGv t0 =3D tcg_temp_new(); = \ - tcg_gen_andi_tl(t0, load_gpr((dc), instr.b), 31); = \ - tcg_gen_##insn(cpu_R[instr.c], load_gpr((dc), instr.a), t0); = \ - tcg_temp_free(t0); = \ - } = \ +#define gen_r_shift_s(fname, insn) \ +static void (fname)(DisasContext *dc, uint32_t code, uint32_t flags) \ +{ \ + R_TYPE(instr, (code)); \ + TCGv t0 =3D tcg_temp_new(); \ + tcg_gen_andi_tl(t0, load_gpr(dc, instr.b), 31); \ + tcg_gen_##insn(dest_gpr(dc, instr.c), load_gpr(dc, instr.a), t0); \ + tcg_temp_free(t0); \ } =20 gen_r_shift_s(sra, sar_tl) @@ -623,12 +597,6 @@ gen_r_shift_s(ror, rotr_tl) static void divs(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, (code)); - - /* Stores into R_ZERO are ignored */ - if (unlikely(instr.c =3D=3D R_ZERO)) { - return; - } - TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); TCGv t2 =3D tcg_temp_new(); @@ -643,8 +611,7 @@ static void divs(DisasContext *dc, uint32_t code, uint3= 2_t flags) tcg_gen_or_tl(t2, t2, t3); tcg_gen_movi_tl(t3, 0); tcg_gen_movcond_tl(TCG_COND_NE, t1, t2, t3, t2, t1); - tcg_gen_div_tl(cpu_R[instr.c], t0, t1); - tcg_gen_ext32s_tl(cpu_R[instr.c], cpu_R[instr.c]); + tcg_gen_div_tl(dest_gpr(dc, instr.c), t0, t1); =20 tcg_temp_free(t3); tcg_temp_free(t2); @@ -655,12 +622,6 @@ static void divs(DisasContext *dc, uint32_t code, uint= 32_t flags) static void divu(DisasContext *dc, uint32_t code, uint32_t flags) { R_TYPE(instr, (code)); - - /* Stores into R_ZERO are ignored */ - if (unlikely(instr.c =3D=3D R_ZERO)) { - return; - } - TCGv t0 =3D tcg_temp_new(); TCGv t1 =3D tcg_temp_new(); TCGv t2 =3D tcg_constant_tl(0); @@ -669,8 +630,7 @@ static void divu(DisasContext *dc, uint32_t code, uint3= 2_t flags) tcg_gen_ext32u_tl(t0, load_gpr(dc, instr.a)); tcg_gen_ext32u_tl(t1, load_gpr(dc, instr.b)); tcg_gen_movcond_tl(TCG_COND_EQ, t1, t1, t2, t3, t1); - tcg_gen_divu_tl(cpu_R[instr.c], t0, t1); - tcg_gen_ext32s_tl(cpu_R[instr.c], cpu_R[instr.c]); + tcg_gen_divu_tl(dest_gpr(dc, instr.c), t0, t1); =20 tcg_temp_free(t1); tcg_temp_free(t0); @@ -849,8 +809,14 @@ static void nios2_tr_translate_insn(DisasContextBase *= dcbase, CPUState *cs) return; } =20 + dc->sink =3D NULL; + instr =3D &i_type_instructions[op]; instr->handler(dc, code, instr->flags); + + if (dc->sink) { + tcg_temp_free(dc->sink); + } } =20 static void nios2_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) --=20 2.25.1 From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646724437887841.3432243015304; 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[50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=76wSnhUATfCAoGFxfO7Xhn6x4qRTiWJIe9Ic10rBGB8=; b=UVKiBP+jhEDxZ8D1pAFjSY0HMxLfbCHXhJvEwiyDHhTpU0zMOvyvcDFGpyTJmt6q4u 7T4IG0VQ/svablUOijRlLJ19SzK3vQgYQ0wmGg2+UdcithIFn1qKVUYSuhlWypxntxdL IWnhe3tF/xKQw45+lrgieha7I86OUzmnTIfm+S+vL7Xd0/olGOSQdLqsBXFlChP43hAA P/iO050pdq0+o09nE3hKoFM+Cj+7Do+wVPOTk8HnAWlnYE2qnL8Q9p51oze+vnS18YVs vMF8M3uDJR3s2RtmURqNk4yygcVuTzx/oWgCcwKvushU+7wBAk4CH4r71eEalpfJYzS9 Px2A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=76wSnhUATfCAoGFxfO7Xhn6x4qRTiWJIe9Ic10rBGB8=; b=zuPFA2vFUDWYaJu6IgD+P4oDHlYVE28KaG4f6bZkj19DCiKvq9xfxW6WAzY3xtnUaF mESC15kNSPA4RaZzi9WflOh7Wk4Pp8iVqiq1wlFJ4nrMNurxFef28Az7+pbfGRp6wcJ1 yL5b9MZDLmjicBtqi+tsV3Mn+vXZNjD+o+nFX1eb18a+iKuREbo2fBSET6Up16JtK8lK PoKWUf8od6wNbjYNi+BpU9T9KMs/VW1J+hJX+SNhkKSxHL1L9q0tLkMbTO40U7S1K6O4 cKU6kxu3Zc0t/l9L3Z0jbWHhaC41IACGBHk99XmrEGcAov4OqYYrYP6J19NO1oboljuO Fndg== X-Gm-Message-State: AOAM532AmWLXw/7rKw2fXDhNCo5FBp5dztF2MmhKePwpQKaf/ohmYagR B5/2bvNdN54dQZi6HUemH3Ssv2Kctfjctw== X-Google-Smtp-Source: ABdhPJxZCQ7mPE6lB9RhJ7zmpfOR2fxM3lyziPs2Dv21Xl1GI7Usf4nppMDk9lLhYYETWduReRoLGw== X-Received: by 2002:aa7:9730:0:b0:4f6:d6ee:cc0b with SMTP id k16-20020aa79730000000b004f6d6eecc0bmr15275657pfg.41.1646724045342; Mon, 07 Mar 2022 23:20:45 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 23/33] target/nios2: Drop CR_STATUS_EH from tb->flags Date: Mon, 7 Mar 2022 21:19:55 -1000 Message-Id: <20220308072005.307955-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42e (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42e; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42e.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646724438213100001 Content-Type: text/plain; charset="utf-8" There's nothing about EH that affects translation, so there's no need to include it in tb->flags. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/cpu.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index f582e52aa4..2a5e070960 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -291,7 +291,7 @@ static inline void cpu_get_tb_cpu_state(CPUNios2State *= env, target_ulong *pc, { *pc =3D env->pc; *cs_base =3D 0; - *flags =3D env->status & (CR_STATUS_EH | CR_STATUS_U); + *flags =3D env->status & CR_STATUS_U; } =20 #endif /* NIOS2_CPU_H */ --=20 2.25.1 From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646725302575110.49169984601156; Mon, 7 Mar 2022 23:41:42 -0800 (PST) Received: from localhost ([::1]:41954 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nRUTV-0003Gc-F6 for importer@patchew.org; Tue, 08 Mar 2022 02:41:41 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45412) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nRU9M-0005H4-U8 for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:52 -0500 Received: from [2607:f8b0:4864:20::52f] (port=36497 helo=mail-pg1-x52f.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nRU9K-0006Tb-Eq for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:52 -0500 Received: by mail-pg1-x52f.google.com with SMTP id t14so15690649pgr.3 for ; Mon, 07 Mar 2022 23:20:47 -0800 (PST) Received: from localhost.localdomain (cpe-50-113-46-110.hawaii.res.rr.com. [50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=jkUviBvx+bFZA8/fWqzx8zy4GO0niXzHqxJY8cqRC64=; b=I+xARbXjHbwAUAeFUANnlTKleisHy6QiGdFLhehGafUr9qgjSlG+iwtLPpZxnu08cb x/WJgBjuOTFayR+NxkIxDmuQVe3obed04rG7bogbKniGbzIFqqH/kK4Kio4GOUcdbgPh SlyOFK2XZ1QyiFl0D+Ibz+6GZC7EKJjVMbQqt14NLiQUP6oZWKc2+Rjde9lXnoP21G12 L8LF8xwwFOc0rV5stnxufN96fk81s1sAUuYFjhtX55swPo/Ko1mBa4ZIdhRThRNaPJNR p2OU/jxtXJvQlFrle0yAj8XG/VfOp8Q6dRJ6tKNKThPuQsOXXkHqq8BWp+koIe7TQ3jI IhUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=jkUviBvx+bFZA8/fWqzx8zy4GO0niXzHqxJY8cqRC64=; b=a1aWMSVKgPXmiIYbztDIvQtvk1l0pDAUFux2GDcdJLB6aDZc0y7X49mhsUIFkpmtLt 67SWDIZ+UCHDFkkAtETFDsT0AS3hQXLPfoxYRBEbCcqaNHAqYdgUOPBi/njOesr54U+1 TW1yhHDQClIirVkTD+wdWJJeWhD5wJh/fdEwP3IvG7uXCz8ZE0eB6IkgC7yAoEi8rooj r/OdKA45Ty/+NvWSeI9/e4Y/Fqe2hUp94RdMpJ249KLIaG84CU0Ve/klpfogPLKxr++d OJspbYrfBR1HKHWHKHR9/rKeNYhSLTRTznQ1XSll5Y6pKQzPYCwjoLIwPKeacrGiWeHd /o6A== X-Gm-Message-State: AOAM5321oUVFbBUIDUf3I2hAVX2MFQ0GrOrKe2OUN2ukVSnT3+zCY+Dk UXvtJJd25wZLVN0IX6a31fdS5rcq3Fuuag== X-Google-Smtp-Source: ABdhPJyvKKOgluodEfRYzR22OKBpNw3kC142/TofMjz0fIpbTzqIzgcg/rhYRuyCnH4Q027W6jIQ9Q== X-Received: by 2002:a62:55c4:0:b0:4f6:b396:9caa with SMTP id j187-20020a6255c4000000b004f6b3969caamr17199075pfb.19.1646724046922; Mon, 07 Mar 2022 23:20:46 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 24/33] target/nios2: Introduce shadow register sets Date: Mon, 7 Mar 2022 21:19:56 -1000 Message-Id: <20220308072005.307955-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::52f (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646725304545100001 Content-Type: text/plain; charset="utf-8" Do not actually enable them so far, but add all of the plumbing to address them. Do not enable them for user-only. Add an env->crs pointer that handles the indirection to the current register set. Add a nios2_crs() function to wrap this for normal uses, which hides the difference between user-only and system modes. From the notes on wrprs, which states that r0 must be initialized before use in shadow register sets, infer that R_ZERO is *not* hardwired to zero in shadow register sets. Adjust load_gpr and dest_gpr to reflect this. At the same time we might as well special case crs =3D=3D 0 to avoid the indirection through env->crs during translation as well. Given that this is intended to be the most common case for non-interrupt handlers. Drop the zeroing of env->regs at reset, as those are undefined. Do init env->crs at reset. Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 32 ++++++++++++++++++++ hw/nios2/boot.c | 8 ++--- target/nios2/cpu.c | 7 +++-- target/nios2/helper.c | 12 ++++---- target/nios2/nios2-semi.c | 13 ++++---- target/nios2/translate.c | 62 ++++++++++++++++++++++++++------------- 6 files changed, 95 insertions(+), 39 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 2a5e070960..f05536e04d 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -61,6 +61,11 @@ struct Nios2CPUClass { #define NUM_GP_REGS 32 #define NUM_CR_REGS 32 =20 +#ifndef CONFIG_USER_ONLY +/* 63 shadow register sets; index 0 is the primary register set. */ +#define NUM_REG_SETS 64 +#endif + /* General purpose register aliases */ enum { R_ZERO =3D 0, @@ -176,7 +181,13 @@ FIELD(CR_TLBMISC, EE, 24, 1) #define EXCP_MPUD 17 =20 struct CPUNios2State { +#ifdef CONFIG_USER_ONLY uint32_t regs[NUM_GP_REGS]; +#else + uint32_t shadow_regs[NUM_REG_SETS][NUM_GP_REGS]; + uint32_t *crs; +#endif + union { uint32_t ctrl[NUM_CR_REGS]; struct { @@ -245,6 +256,23 @@ static inline bool nios2_cr_reserved(const ControlRegS= tate *s) return (s->writable | s->readonly) =3D=3D 0; } =20 +static inline void nios2_update_crs(CPUNios2State *env) +{ +#ifndef CONFIG_USER_ONLY + unsigned crs =3D FIELD_EX32(env->status, CR_STATUS, CRS); + env->crs =3D env->shadow_regs[crs]; +#endif +} + +static inline uint32_t *nios2_crs(CPUNios2State *env) +{ +#ifdef CONFIG_USER_ONLY + return env->regs; +#else + return env->crs; +#endif +} + void nios2_tcg_init(void); void nios2_cpu_do_interrupt(CPUState *cs); void dump_mmu(CPUNios2State *env); @@ -286,12 +314,16 @@ typedef Nios2CPU ArchCPU; =20 #include "exec/cpu-all.h" =20 +FIELD(TBFLAGS, CRS0, 0, 1) +FIELD(TBFLAGS, U, 1, 1) /* Overlaps CR_STATUS_U */ + static inline void cpu_get_tb_cpu_state(CPUNios2State *env, target_ulong *= pc, target_ulong *cs_base, uint32_t *f= lags) { *pc =3D env->pc; *cs_base =3D 0; *flags =3D env->status & CR_STATUS_U; + *flags |=3D env->status & R_CR_STATUS_CRS_MASK ? 0 : R_TBFLAGS_CRS0_MA= SK; } =20 #endif /* NIOS2_CPU_H */ diff --git a/hw/nios2/boot.c b/hw/nios2/boot.c index 5b3e4efed5..96896f2ec5 100644 --- a/hw/nios2/boot.c +++ b/hw/nios2/boot.c @@ -62,10 +62,10 @@ static void main_cpu_reset(void *opaque) =20 cpu_reset(CPU(cpu)); =20 - env->regs[R_ARG0] =3D NIOS2_MAGIC; - env->regs[R_ARG1] =3D boot_info.initrd_start; - env->regs[R_ARG2] =3D boot_info.fdt; - env->regs[R_ARG3] =3D boot_info.cmdline; + nios2_crs(env)[R_ARG0] =3D NIOS2_MAGIC; + nios2_crs(env)[R_ARG1] =3D boot_info.initrd_start; + nios2_crs(env)[R_ARG2] =3D boot_info.fdt; + nios2_crs(env)[R_ARG3] =3D boot_info.cmdline; =20 cpu_set_pc(cs, boot_info.bootstrap_pc); if (boot_info.machine_cpu_reset) { diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 2779650128..05f4a7a93a 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -53,7 +53,6 @@ static void nios2_cpu_reset(DeviceState *dev) =20 ncc->parent_reset(dev); =20 - memset(env->regs, 0, sizeof(env->regs)); memset(env->ctrl, 0, sizeof(env->ctrl)); env->pc =3D cpu->reset_addr; =20 @@ -63,6 +62,8 @@ static void nios2_cpu_reset(DeviceState *dev) #else env->status =3D CR_STATUS_RSIE; #endif + + nios2_update_crs(env); } =20 #ifndef CONFIG_USER_ONLY @@ -210,7 +211,7 @@ static int nios2_cpu_gdb_read_register(CPUState *cs, GB= yteArray *mem_buf, int n) uint32_t val; =20 if (n < 32) { /* GP regs */ - val =3D env->regs[n]; + val =3D nios2_crs(env)[n]; } else if (n =3D=3D 32) { /* PC */ val =3D env->pc; } else if (n < 49) { /* Status regs */ @@ -241,7 +242,7 @@ static int nios2_cpu_gdb_write_register(CPUState *cs, u= int8_t *mem_buf, int n) val =3D ldl_p(mem_buf); =20 if (n < 32) { /* GP regs */ - env->regs[n] =3D val; + nios2_crs(env)[n] =3D val; } else if (n =3D=3D 32) { /* PC */ env->pc =3D val; } else if (n < 49) { /* Status regs */ diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 93338e86f0..007496b957 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -64,7 +64,7 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->status |=3D CR_STATUS_IH; env->status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); =20 - env->regs[R_EA] =3D env->pc + 4; + nios2_crs(env)[R_EA] =3D env->pc + 4; env->pc =3D cpu->exception_addr; break; =20 @@ -83,7 +83,7 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->tlbmisc &=3D ~CR_TLBMISC_DBL; env->tlbmisc |=3D CR_TLBMISC_WR; =20 - env->regs[R_EA] =3D env->pc + 4; + nios2_crs(env)[R_EA] =3D env->pc + 4; env->pc =3D cpu->fast_tlb_miss_addr; } else { qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=3D%x\n", e= nv->pc); @@ -111,7 +111,7 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->tlbmisc |=3D CR_TLBMISC_WR; } =20 - env->regs[R_EA] =3D env->pc + 4; + nios2_crs(env)[R_EA] =3D env->pc + 4; env->pc =3D cpu->exception_addr; break; =20 @@ -122,7 +122,7 @@ void nios2_cpu_do_interrupt(CPUState *cs) =20 if ((env->status & CR_STATUS_EH) =3D=3D 0) { env->estatus =3D env->status; - env->regs[R_EA] =3D env->pc + 4; + nios2_crs(env)[R_EA] =3D env->pc + 4; } =20 env->status |=3D CR_STATUS_EH; @@ -137,7 +137,7 @@ void nios2_cpu_do_interrupt(CPUState *cs) =20 if ((env->status & CR_STATUS_EH) =3D=3D 0) { env->estatus =3D env->status; - env->regs[R_EA] =3D env->pc + 4; + nios2_crs(env)[R_EA] =3D env->pc + 4; } =20 env->status |=3D CR_STATUS_EH; @@ -159,7 +159,7 @@ void nios2_cpu_do_interrupt(CPUState *cs) =20 if ((env->status & CR_STATUS_EH) =3D=3D 0) { env->bstatus =3D env->status; - env->regs[R_BA] =3D env->pc + 4; + nios2_crs(env)[R_BA] =3D env->pc + 4; } =20 env->status |=3D CR_STATUS_EH; diff --git a/target/nios2/nios2-semi.c b/target/nios2/nios2-semi.c index fe5598bae4..8495718de0 100644 --- a/target/nios2/nios2-semi.c +++ b/target/nios2/nios2-semi.c @@ -144,7 +144,7 @@ static bool translate_stat(CPUNios2State *env, target_u= long addr, static void nios2_semi_return_u32(CPUNios2State *env, uint32_t ret, uint32_t err) { - target_ulong args =3D env->regs[R_ARG1]; + target_ulong args =3D nios2_crs(env)[R_ARG1]; if (put_user_u32(ret, args) || put_user_u32(err, args + 4)) { /* @@ -160,7 +160,7 @@ static void nios2_semi_return_u32(CPUNios2State *env, u= int32_t ret, static void nios2_semi_return_u64(CPUNios2State *env, uint64_t ret, uint32_t err) { - target_ulong args =3D env->regs[R_ARG1]; + target_ulong args =3D nios2_crs(env)[R_ARG1]; if (put_user_u32(ret >> 32, args) || put_user_u32(ret, args + 4) || put_user_u32(err, args + 8)) { @@ -210,13 +210,14 @@ void do_nios2_semihosting(CPUNios2State *env) void *q; uint32_t len; uint32_t result; + uint32_t *crs =3D nios2_crs(env); =20 - nr =3D env->regs[R_ARG0]; - args =3D env->regs[R_ARG1]; + nr =3D crs[R_ARG0]; + args =3D crs[R_ARG1]; switch (nr) { case HOSTED_EXIT: - gdb_exit(env->regs[R_ARG0]); - exit(env->regs[R_ARG0]); + gdb_exit(crs[R_ARG0]); + exit(crs[R_ARG0]); case HOSTED_OPEN: GET_ARG(0); GET_ARG(1); diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 7c2ad02685..57913da3c9 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -100,12 +100,16 @@ typedef struct DisasContext { DisasContextBase base; target_ulong pc; int mem_idx; + bool crs0; TCGv sink; const ControlRegState *cr_state; } DisasContext; =20 static TCGv cpu_R[NUM_GP_REGS]; static TCGv cpu_pc; +#ifndef CONFIG_USER_ONLY +static TCGv cpu_crs_R[NUM_GP_REGS]; +#endif =20 typedef struct Nios2Instruction { void (*handler)(DisasContext *dc, uint32_t code, uint32_t flags); @@ -127,22 +131,36 @@ static uint8_t get_opxcode(uint32_t code) static TCGv load_gpr(DisasContext *dc, unsigned reg) { assert(reg < NUM_GP_REGS); - if (unlikely(reg =3D=3D R_ZERO)) { - return tcg_constant_tl(0); + if (dc->crs0) { + if (unlikely(reg =3D=3D R_ZERO)) { + return tcg_constant_tl(0); + } + return cpu_R[reg]; } - return cpu_R[reg]; +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + return cpu_crs_R[reg]; +#endif } =20 static TCGv dest_gpr(DisasContext *dc, unsigned reg) { assert(reg < NUM_GP_REGS); - if (unlikely(reg =3D=3D R_ZERO)) { - if (dc->sink =3D=3D NULL) { - dc->sink =3D tcg_temp_new(); + if (dc->crs0) { + if (unlikely(reg =3D=3D R_ZERO)) { + if (dc->sink =3D=3D NULL) { + dc->sink =3D tcg_temp_new(); + } + return dc->sink; } - return dc->sink; + return cpu_R[reg]; } - return cpu_R[reg]; +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + return cpu_crs_R[reg]; +#endif } =20 static void t_gen_helper_raise_exception(DisasContext *dc, @@ -174,7 +192,7 @@ static void gen_excp(DisasContext *dc, uint32_t code, u= int32_t flags) =20 static bool gen_check_supervisor(DisasContext *dc) { - if (dc->base.tb->flags & CR_STATUS_U) { + if (dc->base.tb->flags & R_TBFLAGS_U_MASK) { /* CPU in user mode, privileged instruction called, stop. */ t_gen_helper_raise_exception(dc, EXCP_SUPERI); return false; @@ -773,6 +791,7 @@ static void nios2_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) =20 dc->mem_idx =3D cpu_mmu_index(env, false); dc->cr_state =3D cpu->cr_state; + dc->crs0 =3D FIELD_EX32(dc->base.tb->flags, TBFLAGS, CRS0); =20 /* Bound the number of insns to execute to those left on the page. */ page_insns =3D -(dc->base.pc_first | TARGET_PAGE_MASK) / 4; @@ -871,16 +890,13 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int = flags) { Nios2CPU *cpu =3D NIOS2_CPU(cs); CPUNios2State *env =3D &cpu->env; + const uint32_t *crs =3D nios2_crs(env); int i; =20 - if (!env) { - return; - } - qemu_fprintf(f, "IN: PC=3D%x %s\n", env->pc, lookup_symbol(env->pc)); =20 for (i =3D 0; i < NUM_GP_REGS; i++) { - qemu_fprintf(f, "%9s=3D%8.8x ", gr_regnames[i], env->regs[i]); + qemu_fprintf(f, "%9s=3D%8.8x ", gr_regnames[i], crs[i]); if ((i + 1) % 4 =3D=3D 0) { qemu_fprintf(f, "\n"); } @@ -912,13 +928,19 @@ void nios2_cpu_dump_state(CPUState *cs, FILE *f, int = flags) =20 void nios2_tcg_init(void) { - int i; - - for (i =3D 0; i < NUM_GP_REGS; i++) { - cpu_R[i] =3D tcg_global_mem_new(cpu_env, - offsetof(CPUNios2State, regs[i]), - gr_regnames[i]); + for (int i =3D 0; i < NUM_GP_REGS; i++) { + cpu_R[i] =3D tcg_global_mem_new(cpu_env, 4 * i, gr_regnames[i]); } + +#ifndef CONFIG_USER_ONLY + TCGv_ptr crs =3D tcg_global_mem_new_ptr(cpu_env, + offsetof(CPUNios2State, crs), "c= rs"); + + for (int i =3D 0; i < NUM_GP_REGS; i++) { + cpu_crs_R[i] =3D tcg_global_mem_new(crs, 4 * i, gr_regnames[i]); + } +#endif + cpu_pc =3D tcg_global_mem_new(cpu_env, offsetof(CPUNios2State, pc), "pc"); } --=20 2.25.1 From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646725938194908.6036124747425; Mon, 7 Mar 2022 23:52:18 -0800 (PST) Received: from localhost ([::1]:39294 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nRUdk-0003sB-SL for importer@patchew.org; Tue, 08 Mar 2022 02:52:16 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45432) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nRU9N-0005Kk-PD for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:53 -0500 Received: from [2607:f8b0:4864:20::62e] (port=38656 helo=mail-pl1-x62e.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nRU9K-0006Tv-ML for qemu-devel@nongnu.org; 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[50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=HdR/1qr7iMJaAgIBHcAAReYqxBpkpXyTqeWj+X7iF1U=; b=Ll/TIwAZRt/mD4ziscINKMCXcu7wupqCELJd7j7LVAaS0csXCRcCTRdho6mKjFDY/U JzGAJ/sbdIdyWnIq9RkpJNH1P27Hf4gGUrv+znavqsN0ZhejVBCYZTvF43BrhoHqW5ER D3ugyan5fnGCjA7Bjv2dpHl29N4BU5ReXjexuaGtsPbruuaHjPBniWqkmu585i0/ZMCb yo6Ndrr5KPJ4gWoAmuhu9zrghNafXmn3o0soZy9GpHNyx3pkCRr6rKabp1xwIfBi8Ul4 vuSvwGowSN+ff/FL7lfbEFkzelbqvP+mRl0nptlmmN+/D8rxl6tcNYS7v3PzOvR2AmHX fiRw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HdR/1qr7iMJaAgIBHcAAReYqxBpkpXyTqeWj+X7iF1U=; b=tr0aPIdSUT9uJ0BANkUloIKHgaDB7sQTJolVnWHipdxyypLddRSH7NSDpnR9Mp/3vs 7tBnQvXvb0Rjsjz9VeRV/xyf7OBlNob2dBv6f2XmTgwP+OARgwxhdZl3TS5T9bTu4N6u hH+qelDmh/jYqg+sM/F5wvbOiO/fJwqcoBg4okqNQgscGEdCAamo+vLybL+Ky27YNOoX Mxri6Gc7N/3gRK+dFfRQIzj/Y57mnrYc8CwBUlECxmImAJEbvG7kMzpRfFg3Z2IgqkWO AdFu1k+/y4oG0WPfJyyQFln53SH40ir00rjvabB19usIV/yinuaiYeDddmnPBfrarOxJ yD1w== X-Gm-Message-State: AOAM5329bToKl2oxxCRlcPKYDNdg1d5Ak4IzpT71b3Ib1IpBCsjYUW+w GQwrCBc1OFvO0w5mwOvs5WuJnoln12p/1g== X-Google-Smtp-Source: ABdhPJwbK7Qh9/AU4PWIK7YEHcE9F973QhiwxRQorwQQwb7aY/SxihIlG+XLsrF7YT/JSBErBMpQ7A== X-Received: by 2002:a17:902:9682:b0:14e:fe33:64af with SMTP id n2-20020a170902968200b0014efe3364afmr15978069plp.160.1646724049214; Mon, 07 Mar 2022 23:20:49 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 25/33] target/nios2: Implement rdprs, wrprs Date: Mon, 7 Mar 2022 21:19:57 -1000 Message-Id: <20220308072005.307955-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62e (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646725940269100001 Content-Type: text/plain; charset="utf-8" Implement these out of line, so that tcg global temps (aka the architectural registers) are synced back to storage as required. This makes sure that we get the proper results when status.PRS =3D=3D status.CRS. Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 2 ++ target/nios2/helper.h | 2 ++ target/nios2/op_helper.c | 12 ++++++++++ target/nios2/translate.c | 47 ++++++++++++++++++++++++++++++++++++++-- 4 files changed, 61 insertions(+), 2 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index f05536e04d..efaac274aa 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -237,6 +237,8 @@ struct Nios2CPU { CPUNios2State env; =20 bool mmu_present; + bool eic_present; + uint32_t pid_num_bits; uint32_t tlb_num_ways; uint32_t tlb_num_entries; diff --git a/target/nios2/helper.h b/target/nios2/helper.h index 02797c384d..a8edca5194 100644 --- a/target/nios2/helper.h +++ b/target/nios2/helper.h @@ -22,6 +22,8 @@ DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_WG, noret= urn, env, i32) =20 #if !defined(CONFIG_USER_ONLY) DEF_HELPER_2(eret, noreturn, env, i32) +DEF_HELPER_FLAGS_2(rdprs, TCG_CALL_NO_WG, i32, env, i32) +DEF_HELPER_3(wrprs, void, env, i32, i32) DEF_HELPER_2(mmu_write_tlbacc, void, env, i32) DEF_HELPER_2(mmu_write_tlbmisc, void, env, i32) DEF_HELPER_2(mmu_write_pteaddr, void, env, i32) diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index a1554ce349..e656986e3c 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -38,4 +38,16 @@ void helper_eret(CPUNios2State *env, uint32_t new_pc) env->pc =3D new_pc; cpu_loop_exit(env_cpu(env)); } + +uint32_t helper_rdprs(CPUNios2State *env, uint32_t regno) +{ + unsigned prs =3D FIELD_EX32(env->status, CR_STATUS, PRS); + return env->shadow_regs[prs][regno]; +} + +void helper_wrprs(CPUNios2State *env, uint32_t regno, uint32_t val) +{ + unsigned prs =3D FIELD_EX32(env->status, CR_STATUS, PRS); + env->shadow_regs[prs][regno] =3D val; +} #endif /* !CONFIG_USER_ONLY */ diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 57913da3c9..7730735639 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -103,6 +103,7 @@ typedef struct DisasContext { bool crs0; TCGv sink; const ControlRegState *cr_state; + bool eic_present; } DisasContext; =20 static TCGv cpu_R[NUM_GP_REGS]; @@ -305,6 +306,27 @@ gen_i_math_logic(andhi, andi, 0, instr.imm16.u << 16) gen_i_math_logic(orhi , ori, 1, instr.imm16.u << 16) gen_i_math_logic(xorhi, xori, 1, instr.imm16.u << 16) =20 +/* rB <- prs.rA + sigma(IMM16) */ +static void rdprs(DisasContext *dc, uint32_t code, uint32_t flags) +{ + if (!dc->eic_present) { + t_gen_helper_raise_exception(dc, EXCP_ILLEGAL); + return; + } + if (!gen_check_supervisor(dc)) { + return; + } + +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + I_TYPE(instr, code); + TCGv dest =3D dest_gpr(dc, instr.b); + gen_helper_rdprs(dest, cpu_env, tcg_constant_i32(instr.a)); + tcg_gen_addi_tl(dest, dest, instr.imm16.s); +#endif +} + /* Prototype only, defined below */ static void handle_r_type_instr(DisasContext *dc, uint32_t code, uint32_t flags); @@ -366,7 +388,7 @@ static const Nios2Instruction i_type_instructions[] =3D= { INSTRUCTION_FLG(gen_stx, MO_SL), /* stwio */ INSTRUCTION_FLG(gen_bxx, TCG_COND_LTU), /* bltu */ INSTRUCTION_FLG(gen_ldx, MO_UL), /* ldwio */ - INSTRUCTION_UNIMPLEMENTED(), /* rdprs */ + INSTRUCTION(rdprs), /* rdprs */ INSTRUCTION_ILLEGAL(), INSTRUCTION_FLG(handle_r_type_instr, 0), /* R-Type */ INSTRUCTION_NOP(), /* flushd */ @@ -552,6 +574,26 @@ static void wrctl(DisasContext *dc, uint32_t code, uin= t32_t flags) #endif } =20 +/* prs.rC <- rA */ +static void wrprs(DisasContext *dc, uint32_t code, uint32_t flags) +{ + if (!dc->eic_present) { + t_gen_helper_raise_exception(dc, EXCP_ILLEGAL); + return; + } + if (!gen_check_supervisor(dc)) { + return; + } + +#ifdef CONFIG_USER_ONLY + g_assert_not_reached(); +#else + R_TYPE(instr, code); + gen_helper_wrprs(cpu_env, tcg_constant_i32(instr.c), + load_gpr(dc, instr.a)); +#endif +} + /* Comparison instructions */ static void gen_cmpxx(DisasContext *dc, uint32_t code, uint32_t flags) { @@ -690,7 +732,7 @@ static const Nios2Instruction r_type_instructions[] =3D= { INSTRUCTION_ILLEGAL(), INSTRUCTION(slli), /* slli */ INSTRUCTION(sll), /* sll */ - INSTRUCTION_UNIMPLEMENTED(), /* wrprs */ + INSTRUCTION(wrprs), /* wrprs */ INSTRUCTION_ILLEGAL(), INSTRUCTION(or), /* or */ INSTRUCTION(mulxsu), /* mulxsu */ @@ -791,6 +833,7 @@ static void nios2_tr_init_disas_context(DisasContextBas= e *dcbase, CPUState *cs) =20 dc->mem_idx =3D cpu_mmu_index(env, false); dc->cr_state =3D cpu->cr_state; + dc->eic_present =3D cpu->eic_present; dc->crs0 =3D FIELD_EX32(dc->base.tb->flags, TBFLAGS, CRS0); =20 /* Bound the number of insns to execute to those left on the page. */ --=20 2.25.1 From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ta/28CvyDoU7eRgMKLBRwX53uj2wXJ6ov5bazLvyx9o=; b=m7AlE6b9CFOGk+iiHhhOlYXQbmULrN2SHjdikBlv6i0VoSupXvpozaSAaM1f++Dh7v u9K5Xvr9HCioqWcKfdk3aL7FLnT+h2V0Lrp9kxiQg9JtKdnAWxGc0zEgiCMfa3bB5jPN RJGnFXwlisn9igbPCWA2t8jR/EEKYtk31sRKvDI/XNvh5YFsq6Ieb2VlKrk8xm0jJxtt VqECToXHW2pmkoULIt7B2CG7cC3egrZos9WkXh4QjRCSsx3V43JeJbOalsrkGOdb9rwS lDH54Jdm46Uo4TKhnOI3rj5S3AQQKC9ESUNSFBz1AZUXzZtgtwcxvFEPXeT7lI79wJp9 zsTg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ta/28CvyDoU7eRgMKLBRwX53uj2wXJ6ov5bazLvyx9o=; b=UovWt029hKpzcxJZ4TNRC9JNouWpWEj4SFO823zHHdSLiIfjESUhUnuvuMg/aXTYtt cithBMuIwF/Xzew0HJtVhq8NOYPrQq35sQw+pYU4flZlNzuhDVv2Lh0aV2s2o/hgBWGG kE+sY7ETfL75nk12JgUvh6zkNonnr+gPoYvA+wYj4EKYp9tBLugAE48UolKe8Ut/WHu4 emqM9XylL1LoLgEHAc350e0vapM/FQ1JDeUXS9cI4zoBviWm1q5A1nt0Xo1d5Lr0Z0gy gUamtqgoeoJunjGp/aOQGUBwQ/VjYYgqOhRxp4/+FGWDNlkR8/EyPQwRYz+63V2yUn5A JtnA== X-Gm-Message-State: AOAM533OCo77XVwFyNYnhULu+gMpv+IOvuBUJnAqwGdjd20YHgO2fG3i aIsM0wIkmhiXTVsSOZxMXHk3QSqK2aDjtg== X-Google-Smtp-Source: ABdhPJwf+X3kUuE2nxmmxA3mpRP2xr/kqo5Y541HS+7Jt95b4uNbCmEVTf1ZgrBQtHcYcev97dfUNg== X-Received: by 2002:a17:902:d481:b0:151:b6e0:34bf with SMTP id c1-20020a170902d48100b00151b6e034bfmr15896219plg.140.1646724050676; Mon, 07 Mar 2022 23:20:50 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 26/33] target/nios2: Update helper_eret for shadow registers Date: Mon, 7 Mar 2022 21:19:58 -1000 Message-Id: <20220308072005.307955-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1031 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646725077497100001 Content-Type: text/plain; charset="utf-8" When CRS =3D 0, we restore from estatus; otherwise from sstatus. Do not allow reserved status bits to be set via this restore. Add the fields defined for EIC to status. Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 1 + target/nios2/cpu.c | 16 ++++++++++++---- target/nios2/op_helper.c | 20 +++++++++++++++++++- 3 files changed, 32 insertions(+), 5 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index efaac274aa..c48daa5640 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -83,6 +83,7 @@ enum { R_FP =3D 28, R_EA =3D 29, R_BA =3D 30, + R_SSTATUS =3D 30, R_RA =3D 31, }; =20 diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 05f4a7a93a..6ece92a2b8 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -109,10 +109,18 @@ static void nios2_cpu_initfn(Object *obj) WR_FIELD(CR_EXCEPTION, CAUSE); WR_REG(CR_BADADDR); =20 - /* TODO: These control registers are not present with the EIC. */ - RO_FIELD(CR_STATUS, RSIE); - WR_REG(CR_IENABLE); - RO_REG(CR_IPENDING); + if (cpu->eic_present) { + WR_FIELD(CR_STATUS, RSIE); + RO_FIELD(CR_STATUS, NMI); + WR_FIELD(CR_STATUS, PRS); + RO_FIELD(CR_STATUS, CRS); + WR_FIELD(CR_STATUS, IL); + WR_FIELD(CR_STATUS, IH); + } else { + RO_FIELD(CR_STATUS, RSIE); + WR_REG(CR_IENABLE); + RO_REG(CR_IPENDING); + } =20 if (cpu->mmu_present) { WR_FIELD(CR_STATUS, U); diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index e656986e3c..42342f007f 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -34,7 +34,25 @@ void helper_raise_exception(CPUNios2State *env, uint32_t= index) #ifndef CONFIG_USER_ONLY void helper_eret(CPUNios2State *env, uint32_t new_pc) { - env->status =3D env->estatus; + Nios2CPU *cpu =3D env_archcpu(env); + unsigned crs =3D FIELD_EX32(env->status, CR_STATUS, CRS); + uint32_t val; + + if (crs =3D=3D 0) { + val =3D env->estatus; + } else { + val =3D env->shadow_regs[crs][R_SSTATUS]; + } + + /* + * Both estatus and sstatus have no constraints on write; + * do not allow reserved fields in status to be set. + */ + val &=3D (cpu->cr_state[CR_STATUS].writable | + cpu->cr_state[CR_STATUS].readonly); + env->status =3D val; + nios2_update_crs(env); + env->pc =3D new_pc; cpu_loop_exit(env_cpu(env)); } --=20 2.25.1 From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646725879422134.83909693957332; Mon, 7 Mar 2022 23:51:19 -0800 (PST) Received: from localhost ([::1]:36746 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nRUco-00024l-8m for importer@patchew.org; Tue, 08 Mar 2022 02:51:18 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45448) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nRU9P-0005Pe-68 for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:55 -0500 Received: from [2607:f8b0:4864:20::433] (port=36736 helo=mail-pf1-x433.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nRU9N-0006UP-Gb for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:54 -0500 Received: by mail-pf1-x433.google.com with SMTP id z16so16597919pfh.3 for ; Mon, 07 Mar 2022 23:20:53 -0800 (PST) Received: from localhost.localdomain (cpe-50-113-46-110.hawaii.res.rr.com. [50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:51 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xqZvZTH6wFGuxyM1NjswBFnNnEpmS+qPeWcZX7KLadU=; b=rIL1y4EQpEQ7X1sHZUXv4JidRXY804cQfIZePSa37qj60jaj6p8v5QryBdDWQoNhHI BNJ9ft5XEiLArOtNun3Nh3piAm3lX6uoxK9d/PQMmqRlT5nnvRQWbZQobkk+qOmTVPEb A7N7xSdiYCwCH6CquUmdcTqCt9PVGhEEtDg+nJ1s7cBI3O2YDxfgXcjnd1eSc5NdY2qz koVbNkaV7wY8BpMpVRF4LQRFZX9TmJ19JUyfKBdi+02Yf430FclSPSBknAwFXdL4CeQ0 dXuK1e8S7b3blObYLdeKXsZQR0sBaJXLB+QMxfhwJYq0kqW2+Xg1nublvaoG0hOW/1Ps LRXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xqZvZTH6wFGuxyM1NjswBFnNnEpmS+qPeWcZX7KLadU=; b=KHdenRqNSxEIye2qt7jNMFDVBCeRppkm1bF1Nb79rF3nfmplcByArtW3Jv+i7Qow/8 sX+eOUOTcMD/wkLuZ+B2djlvqtrSb9RstnUusPmaF7F0swy4vBoeezzdkwDrVz0RdY/9 wKAuCOLo6NFODZpphO8uomM0kL72woI9kxYX8aK/mNEfz8G41lJ05x7Odrl4rEbgD3wc 7K+mvHCvmW8k6wjCfgozocEgNuno4sjjsw9w/a4XwnuPK30Yx7eeLWwStoSnkAnqGpDl YAqvs3aZa3i3Qgmau6qdboOZAIVn/TLZF2v4i5Jco0IXvWu+n+oUPomDgT6v4BR1pyfx zzuw== X-Gm-Message-State: AOAM53387Obra18/E3vYa7yOioGgA5mOpcm+y00kTyvfps04sLDmtpa6 UJQfJeJo2KLL0WV5fHyHiWcRIcb7SBdURQ== X-Google-Smtp-Source: ABdhPJzV0ZBI7Qoj18AnfocDgmXUjvCJ5MH0bsq31W4Gol74YXJ0Y2Dhv17mZVPI8XkB9dp6PQPQ/Q== X-Received: by 2002:a63:2a89:0:b0:380:957a:790b with SMTP id q131-20020a632a89000000b00380957a790bmr742401pgq.438.1646724052240; Mon, 07 Mar 2022 23:20:52 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 27/33] target/nios2: Create EXCP_SEMIHOST for semi-hosting Date: Mon, 7 Mar 2022 21:19:59 -1000 Message-Id: <20220308072005.307955-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::433 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646725879770100001 Content-Type: text/plain; charset="utf-8" Decode 'break 1' during translation, rather than doing it again during exception processing. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/nios2/cpu.h | 1 + target/nios2/helper.c | 15 ++++++--------- target/nios2/translate.c | 17 ++++++++++++++++- 3 files changed, 23 insertions(+), 10 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index c48daa5640..13e1d49f38 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -162,6 +162,7 @@ FIELD(CR_TLBMISC, EE, 24, 1) =20 /* Exceptions */ #define EXCP_BREAK 0x1000 +#define EXCP_SEMIHOST 0x1001 #define EXCP_RESET 0 #define EXCP_PRESET 1 #define EXCP_IRQ 2 diff --git a/target/nios2/helper.c b/target/nios2/helper.c index 007496b957..a338d02f6b 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -146,17 +146,14 @@ void nios2_cpu_do_interrupt(CPUState *cs) env->pc =3D cpu->exception_addr; break; =20 + case EXCP_SEMIHOST: + qemu_log_mask(CPU_LOG_INT, "BREAK semihosting at pc=3D%x\n", env->= pc); + env->pc +=3D 4; + do_nios2_semihosting(env); + return; + case EXCP_BREAK: qemu_log_mask(CPU_LOG_INT, "BREAK exception at pc=3D%x\n", env->pc= ); - /* The semihosting instruction is "break 1". */ - if (semihosting_enabled() && - cpu_ldl_code(env, env->pc) =3D=3D 0x003da07a) { - qemu_log_mask(CPU_LOG_INT, "Entering semihosting\n"); - env->pc +=3D 4; - do_nios2_semihosting(env); - break; - } - if ((env->status & CR_STATUS_EH) =3D=3D 0) { env->bstatus =3D env->status; nios2_crs(env)[R_BA] =3D env->pc + 4; diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 7730735639..f9b84e31d7 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -33,6 +33,7 @@ #include "exec/translator.h" #include "qemu/qemu-print.h" #include "exec/gen-icount.h" +#include "semihosting/semihost.h" =20 /* is_jmp field values */ #define DISAS_JUMP DISAS_TARGET_0 /* only pc was modified dynamically */ @@ -711,6 +712,20 @@ static void trap(DisasContext *dc, uint32_t code, uint= 32_t flags) t_gen_helper_raise_exception(dc, EXCP_TRAP); } =20 +static void gen_break(DisasContext *dc, uint32_t code, uint32_t flags) +{ +#ifndef CONFIG_USER_ONLY + /* The semihosting instruction is "break 1". */ + R_TYPE(instr, code); + if (semihosting_enabled() && instr.imm5 =3D=3D 1) { + t_gen_helper_raise_exception(dc, EXCP_SEMIHOST); + return; + } +#endif + + t_gen_helper_raise_exception(dc, EXCP_BREAK); +} + static const Nios2Instruction r_type_instructions[] =3D { INSTRUCTION_ILLEGAL(), INSTRUCTION(eret), /* eret */ @@ -764,7 +779,7 @@ static const Nios2Instruction r_type_instructions[] =3D= { INSTRUCTION(add), /* add */ INSTRUCTION_ILLEGAL(), INSTRUCTION_ILLEGAL(), - INSTRUCTION_FLG(gen_excp, EXCP_BREAK), /* break */ + INSTRUCTION(gen_break), /* break */ INSTRUCTION_ILLEGAL(), INSTRUCTION(nop), /* nop */ INSTRUCTION_ILLEGAL(), --=20 2.25.1 From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646726099925413.45817968707127; Mon, 7 Mar 2022 23:54:59 -0800 (PST) Received: from localhost ([::1]:45186 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nRUgM-0007qz-Lo for importer@patchew.org; Tue, 08 Mar 2022 02:54:58 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45474) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nRU9Q-0005V8-NQ for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:56 -0500 Received: from [2607:f8b0:4864:20::1035] (port=40744 helo=mail-pj1-x1035.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nRU9P-0006VH-1q for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:56 -0500 Received: by mail-pj1-x1035.google.com with SMTP id mv5-20020a17090b198500b001bf2a039831so1419682pjb.5 for ; Mon, 07 Mar 2022 23:20:54 -0800 (PST) Received: from localhost.localdomain (cpe-50-113-46-110.hawaii.res.rr.com. [50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:53 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sZ2C5DabhR4UWhlHHPl5YgAYQYqTqvWzN8pMZpMuTzI=; b=y4ulzfZJZOATKzy0+K9e4pRN7ZRqxKTSMsWUTGSRWzBeSvjsj9IrChMLeZVsPfpTY/ xscqdVA4ZQ/xt+S5KDz6ficmTPyx3KC5XovmH6URGcv7AFFKXEWVG2y4D4BVK+DEXy7m 7oLJp287MOBbaiO7e0/JrrCoy/P/h0czNuYBI7rSrCe6so+obBpUfbXxROoyIsEhPCm1 MTaO/0Ig4cEksrP8goMNGzbGDnECHP3tYQ2faQasXSjeSjgrMagICpOGNiEytgA+bLyQ ikfk9E/IDYlhafKXjdxh0/eWWdz/5xDvu/AObRPIgXDeMSFIGpqd/sI03Qw4Hws4MPS0 1I5g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=sZ2C5DabhR4UWhlHHPl5YgAYQYqTqvWzN8pMZpMuTzI=; b=WD+6+97ey+iQGw2YlzdZZ1n8FjJkAqkNy7xN6FQmK4GCJmr6MAvgv7NTS8UwXofojK pbGqj5nu1ajnxRm2QaVXUqNJCqfT0ENjpAZ7Z8xsyPWlu3eajQ4wra3NDUmfjfPchd/y 16pmbM0qqIBUbBP5MIvAoJ+prF8sg0it+SpjNEqV0pURj76cphqRQbZJ/IQ46TZatjTD 8borqkH539uiv2yztEIE2hOXGXJ9Vo14ryB56uguGqXQ6PojrcQyinsJ4QFYS76OSXiQ C7jE2T+pq9cskBjsJqv18wQy59piOT6OaWFWKXAqbUOEIMeZ06Db0mlWn6MsX+bGBcdN XdSA== X-Gm-Message-State: AOAM530bkSY5ZjpB8HcQicPWQ0RBWbk8CPc9EaHQ03tWshTGEpafKZZx Yr8mhmoKXsLxtfmeFkUn4Cu7yEuu5ngvJQ== X-Google-Smtp-Source: ABdhPJxOEoe0picZD1ycL1BXseTHt6v1OsfOYnylxEURXw/9EqC2S0WF4sKSk9vH2BGcKSGumeiODQ== X-Received: by 2002:a17:90b:4b51:b0:1bf:88c7:aecc with SMTP id mi17-20020a17090b4b5100b001bf88c7aeccmr2443669pjb.115.1646724053740; Mon, 07 Mar 2022 23:20:53 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 28/33] target/nios2: Clean up nios2_cpu_do_interrupt Date: Mon, 7 Mar 2022 21:20:00 -1000 Message-Id: <20220308072005.307955-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1035 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646726101905100001 Content-Type: text/plain; charset="utf-8" Sink the bulk of the interrupt processing to the end of the file. All of the internal interrupt and non-interrupt exception code shares EH processing. Signed-off-by: Richard Henderson --- target/nios2/helper.c | 100 +++++++++++------------------------------- 1 file changed, 25 insertions(+), 75 deletions(-) diff --git a/target/nios2/helper.c b/target/nios2/helper.c index a338d02f6b..ccf2634c9b 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -53,48 +53,25 @@ void nios2_cpu_do_interrupt(CPUState *cs) { Nios2CPU *cpu =3D NIOS2_CPU(cs); CPUNios2State *env =3D &cpu->env; + uint32_t exception_addr =3D cpu->exception_addr; + unsigned r_ea =3D R_EA; + unsigned cr_estatus =3D CR_ESTATUS; =20 switch (cs->exception_index) { case EXCP_IRQ: - assert(env->status & CR_STATUS_PIE); - qemu_log_mask(CPU_LOG_INT, "interrupt at pc=3D%x\n", env->pc); - - env->estatus =3D env->status; - env->status |=3D CR_STATUS_IH; - env->status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); - - nios2_crs(env)[R_EA] =3D env->pc + 4; - env->pc =3D cpu->exception_addr; break; =20 case EXCP_TLBD: - if ((env->status & CR_STATUS_EH) =3D=3D 0) { + if (env->status & CR_STATUS_EH) { + qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=3D%x\n", e= nv->pc); + /* Double TLB miss */ + env->tlbmisc |=3D CR_TLBMISC_DBL; + } else { qemu_log_mask(CPU_LOG_INT, "TLB MISS (fast) at pc=3D%x\n", env= ->pc); - - /* Fast TLB miss */ - /* Variation from the spec. Table 3-35 of the cpu reference sh= ows - * estatus not being changed for TLB miss but this appears to - * be incorrect. */ - env->estatus =3D env->status; - env->status |=3D CR_STATUS_EH; - env->status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); - env->tlbmisc &=3D ~CR_TLBMISC_DBL; env->tlbmisc |=3D CR_TLBMISC_WR; - - nios2_crs(env)[R_EA] =3D env->pc + 4; - env->pc =3D cpu->fast_tlb_miss_addr; - } else { - qemu_log_mask(CPU_LOG_INT, "TLB MISS (double) at pc=3D%x\n", e= nv->pc); - - /* Double TLB miss */ - env->status |=3D CR_STATUS_EH; - env->status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); - - env->tlbmisc |=3D CR_TLBMISC_DBL; - - env->pc =3D cpu->exception_addr; + exception_addr =3D cpu->fast_tlb_miss_addr; } break; =20 @@ -102,48 +79,18 @@ void nios2_cpu_do_interrupt(CPUState *cs) case EXCP_TLBW: case EXCP_TLBX: qemu_log_mask(CPU_LOG_INT, "TLB PERM at pc=3D%x\n", env->pc); - - env->estatus =3D env->status; - env->status |=3D CR_STATUS_EH; - env->status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); - - if ((env->status & CR_STATUS_EH) =3D=3D 0) { - env->tlbmisc |=3D CR_TLBMISC_WR; - } - - nios2_crs(env)[R_EA] =3D env->pc + 4; - env->pc =3D cpu->exception_addr; + env->tlbmisc |=3D CR_TLBMISC_WR; break; =20 case EXCP_SUPERA: case EXCP_SUPERI: case EXCP_SUPERD: qemu_log_mask(CPU_LOG_INT, "SUPERVISOR exception at pc=3D%x\n", en= v->pc); - - if ((env->status & CR_STATUS_EH) =3D=3D 0) { - env->estatus =3D env->status; - nios2_crs(env)[R_EA] =3D env->pc + 4; - } - - env->status |=3D CR_STATUS_EH; - env->status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); - - env->pc =3D cpu->exception_addr; break; =20 case EXCP_ILLEGAL: case EXCP_TRAP: qemu_log_mask(CPU_LOG_INT, "TRAP exception at pc=3D%x\n", env->pc); - - if ((env->status & CR_STATUS_EH) =3D=3D 0) { - env->estatus =3D env->status; - nios2_crs(env)[R_EA] =3D env->pc + 4; - } - - env->status |=3D CR_STATUS_EH; - env->status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); - - env->pc =3D cpu->exception_addr; break; =20 case EXCP_SEMIHOST: @@ -154,23 +101,26 @@ void nios2_cpu_do_interrupt(CPUState *cs) =20 case EXCP_BREAK: qemu_log_mask(CPU_LOG_INT, "BREAK exception at pc=3D%x\n", env->pc= ); - if ((env->status & CR_STATUS_EH) =3D=3D 0) { - env->bstatus =3D env->status; - nios2_crs(env)[R_BA] =3D env->pc + 4; - } - - env->status |=3D CR_STATUS_EH; - env->status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); - - env->pc =3D cpu->exception_addr; + r_ea =3D R_BA; + cr_estatus =3D CR_BSTATUS; break; =20 default: - cpu_abort(cs, "unhandled exception type=3D%d\n", - cs->exception_index); - break; + cpu_abort(cs, "unhandled exception type=3D%d\n", cs->exception_ind= ex); } =20 + /* + * Finish Internal Interrupt or Noninterrupt Exception. + */ + + if (!(env->status & CR_STATUS_EH)) { + env->ctrl[cr_estatus] =3D env->status; + env->crs[r_ea] =3D env->pc + 4; + env->status |=3D CR_STATUS_EH; + } + env->status &=3D ~(CR_STATUS_PIE | CR_STATUS_U); + + env->pc =3D exception_addr; env->exception =3D FIELD_DP32(env->exception, CR_EXCEPTION, CAUSE, cs->exception_index); } --=20 2.25.1 From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646725317217805.2368541135842; Mon, 7 Mar 2022 23:41:57 -0800 (PST) Received: from localhost ([::1]:42542 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nRUTj-0003eL-W5 for importer@patchew.org; Tue, 08 Mar 2022 02:41:56 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45494) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nRU9S-0005bD-G3 for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:58 -0500 Received: from [2607:f8b0:4864:20::432] (port=38612 helo=mail-pf1-x432.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nRU9Q-0006Vr-Js for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:20:58 -0500 Received: by mail-pf1-x432.google.com with SMTP id f8so6113268pfj.5 for ; Mon, 07 Mar 2022 23:20:56 -0800 (PST) Received: from localhost.localdomain (cpe-50-113-46-110.hawaii.res.rr.com. [50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/6ZuOi1ySAWVrPIfU1Ik0D51IBcstR6GJi6kOb4zehc=; b=S8z83Y6BcUo5YQn8SwXy46EmYwR4DB/T/N0Dxp93MPdH5oAaJgNi7gNcpPjz/QesFz FCRl6ZES8c4kEJZnfs5tuMHQCGkr9hws79WxeY4M8QDRH9QZc6kvhXLpWR8RLqGmgh4P txOfkbMzV/+LAdbzx9VbNbkdD1kvNXN+4fPT8oSNkVP4pexRWdUXtq+b90UX5ZBirRzr vwyNeFmjnYMNS8f9lnlMjbJFPfkMJkglhcGc13E5OTx8GCuHrw+5PQ1QtjG4Sz0ezC3q 0xH0VjjXXGK11DDOWuZByE+Mz4w2SOSf/tiABvLQrGfNe+ooskOBwRt/3l+sUxVonz/u xHkg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/6ZuOi1ySAWVrPIfU1Ik0D51IBcstR6GJi6kOb4zehc=; b=ay5UHyNPvIW1olsMH6Ru7yBnjmaPKg3Qj98upuH5eYnV9DW3I6r3p6Yllqqyl8Mfpu 2hGSI+LCLXp6qBSqKODkb4BAsD96CpG2wZ7ZWoPnSgD2ERL6bqjvE+zzuHtYavJQEgcg N11HwCaxdBq7RmRtyoxYYFnEu3YI0X5T8rJBf45L6zWFMIEsXP7NxLeiX/aLJPW/crof PrxclbbfGDBFzRmkdZXdPnTE7b/9hvi3DJSsHtEmAHQvju6JaXBui5WDa6KA1T9P5lRK 7C386E/XfGGSt0VThvODjzg2QuPxIMppbn9ScQaNSzfZUxmajWPseanbF/J8DRf02C3B Z3pg== X-Gm-Message-State: AOAM533KVh099wzXhpRk3MSHza7nz+fvvSuJBn/KULO4SxulCEPJ6SRc VWMWvmYt7hesETtLRHGbExlu/ptzgIRvFw== X-Google-Smtp-Source: ABdhPJwpvat6wsT7rK3y+THB4uwcNoeiAgpz1t05LuC48HtTFFKE9Kf0elKXpLwxKUQPRyG6dTRIGg== X-Received: by 2002:a63:6802:0:b0:37c:6bc1:f602 with SMTP id d2-20020a636802000000b0037c6bc1f602mr13320984pgc.128.1646724055292; Mon, 07 Mar 2022 23:20:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 29/33] target/nios2: Implement EIC interrupt processing Date: Mon, 7 Mar 2022 21:20:01 -1000 Message-Id: <20220308072005.307955-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::432 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646725318345100001 Content-Type: text/plain; charset="utf-8" This is the cpu side of the operation. Register one irq line, called EIC. Split out the rather different processing to a separate function. Delay initialization of gpio irqs until realize. We need to provide a window after init in which the board can set eic_present. Signed-off-by: Richard Henderson --- target/nios2/cpu.h | 8 +++++ target/nios2/cpu.c | 75 +++++++++++++++++++++++++++++++++---------- target/nios2/helper.c | 37 +++++++++++++++++++++ 3 files changed, 103 insertions(+), 17 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index 13e1d49f38..89c575c26d 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -115,6 +115,7 @@ FIELD(CR_STATUS, CRS, 10, 6) FIELD(CR_STATUS, PRS, 16, 6) FIELD(CR_STATUS, NMI, 22, 1) FIELD(CR_STATUS, RSIE, 23, 1) +FIELD(CR_STATUS, SRS, 31, 1) =20 #define CR_STATUS_PIE (1u << R_CR_STATUS_PIE_SHIFT) #define CR_STATUS_U (1u << R_CR_STATUS_U_SHIFT) @@ -122,6 +123,7 @@ FIELD(CR_STATUS, RSIE, 23, 1) #define CR_STATUS_IH (1u << R_CR_STATUS_IH_SHIFT) #define CR_STATUS_NMI (1u << R_CR_STATUS_NMI_SHIFT) #define CR_STATUS_RSIE (1u << R_CR_STATUS_RSIE_SHIFT) +#define CR_STATUS_SRS (1u << R_CR_STATUS_SRS_SHIFT) =20 FIELD(CR_EXCEPTION, CAUSE, 2, 5) FIELD(CR_EXCEPTION, ECCFTL, 31, 1) @@ -252,6 +254,12 @@ struct Nios2CPU { =20 /* Bits within each control register which are reserved or readonly. */ ControlRegState cr_state[NUM_CR_REGS]; + + /* External Interrupt Controller Interface */ + uint32_t rha; /* Requested handler address */ + uint32_t ril; /* Requested interrupt level */ + uint32_t rrs; /* Requested register set */ + bool rnmi; /* Requested nonmaskable interrupt */ }; =20 =20 diff --git a/target/nios2/cpu.c b/target/nios2/cpu.c index 6ece92a2b8..65a900a7fb 100644 --- a/target/nios2/cpu.c +++ b/target/nios2/cpu.c @@ -67,7 +67,19 @@ static void nios2_cpu_reset(DeviceState *dev) } =20 #ifndef CONFIG_USER_ONLY -static void nios2_cpu_set_irq(void *opaque, int irq, int level) +static void eic_set_irq(void *opaque, int irq, int level) +{ + Nios2CPU *cpu =3D opaque; + CPUState *cs =3D CPU(cpu); + + if (level) { + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); + } +} + +static void iic_set_irq(void *opaque, int irq, int level) { Nios2CPU *cpu =3D opaque; CPUNios2State *env =3D &cpu->env; @@ -149,15 +161,6 @@ static void nios2_cpu_initfn(Object *obj) =20 #if !defined(CONFIG_USER_ONLY) mmu_init(&cpu->env); - - /* - * These interrupt lines model the IIC (internal interrupt - * controller). QEMU does not currently support the EIC - * (external interrupt controller) -- if we did it would be - * a separate device in hw/intc with a custom interface to - * the CPU, and boards using it would not wire up these IRQ lines. - */ - qdev_init_gpio_in_named(DEVICE(cpu), nios2_cpu_set_irq, "IRQ", 32); #endif } =20 @@ -173,6 +176,14 @@ static void nios2_cpu_realizefn(DeviceState *dev, Erro= r **errp) Nios2CPUClass *ncc =3D NIOS2_CPU_GET_CLASS(dev); Error *local_err =3D NULL; =20 +#ifndef CONFIG_USER_ONLY + if (cpu->eic_present) { + qdev_init_gpio_in_named(DEVICE(cpu), eic_set_irq, "EIC", 1); + } else { + qdev_init_gpio_in_named(DEVICE(cpu), iic_set_irq, "IRQ", 32); + } +#endif + cpu_exec_realizefn(cs, &local_err); if (local_err !=3D NULL) { error_propagate(errp, local_err); @@ -189,17 +200,47 @@ static void nios2_cpu_realizefn(DeviceState *dev, Err= or **errp) } =20 #ifndef CONFIG_USER_ONLY +static bool eic_take_interrupt(Nios2CPU *cpu) +{ + CPUNios2State *env =3D &cpu->env; + + if (cpu->rnmi) { + return !(env->status & CR_STATUS_NMI); + } + if (!(env->status & CR_STATUS_PIE)) { + return false; + } + if (cpu->ril <=3D FIELD_EX32(env->status, CR_STATUS, IL)) { + return false; + } + if (cpu->rrs !=3D FIELD_EX32(env->status, CR_STATUS, CRS)) { + return true; + } + return env->status & CR_STATUS_RSIE; +} + +static bool iic_take_interrupt(Nios2CPU *cpu) +{ + CPUNios2State *env =3D &cpu->env; + + if (!(env->status & CR_STATUS_PIE)) { + return false; + } + return env->ipending & env->ienable; +} + static bool nios2_cpu_exec_interrupt(CPUState *cs, int interrupt_request) { Nios2CPU *cpu =3D NIOS2_CPU(cs); - CPUNios2State *env =3D &cpu->env; =20 - if ((interrupt_request & CPU_INTERRUPT_HARD) && - (env->status & CR_STATUS_PIE) && - (env->ipending & env->ienable)) { - cs->exception_index =3D EXCP_IRQ; - nios2_cpu_do_interrupt(cs); - return true; + if (interrupt_request & CPU_INTERRUPT_HARD) { + if (cpu->eic_present + ? eic_take_interrupt(cpu) + : iic_take_interrupt(cpu)) { + cs->exception_index =3D EXCP_IRQ; + nios2_cpu_do_interrupt(cs); + return true; + } } return false; } diff --git a/target/nios2/helper.c b/target/nios2/helper.c index ccf2634c9b..11840496f7 100644 --- a/target/nios2/helper.c +++ b/target/nios2/helper.c @@ -49,6 +49,36 @@ void nios2_cpu_record_sigsegv(CPUState *cs, vaddr addr, =20 #else /* !CONFIG_USER_ONLY */ =20 +static void eic_do_interrupt(Nios2CPU *cpu) +{ + CPUNios2State *env =3D &cpu->env; + uint32_t old_status =3D env->status; + uint32_t old_rs =3D FIELD_EX32(old_status, CR_STATUS, CRS); + uint32_t new_rs =3D cpu->rrs; + + env->status =3D FIELD_DP32(env->status, CR_STATUS, CRS, new_rs); + env->status =3D FIELD_DP32(env->status, CR_STATUS, IL, cpu->ril); + env->status =3D FIELD_DP32(env->status, CR_STATUS, NMI, cpu->rnmi); + env->status &=3D ~(CR_STATUS_RSIE | CR_STATUS_U); + env->status |=3D CR_STATUS_IH; + nios2_update_crs(env); + + if (!(env->status & CR_STATUS_EH)) { + env->status =3D FIELD_DP32(env->status, CR_STATUS, PRS, old_rs); + if (new_rs =3D=3D 0) { + env->estatus =3D old_status; + } else { + if (new_rs !=3D old_rs) { + old_status |=3D CR_STATUS_SRS; + } + env->crs[R_SSTATUS] =3D old_status; + } + env->crs[R_EA] =3D env->pc + 4; + } + + env->pc =3D cpu->rha; +} + void nios2_cpu_do_interrupt(CPUState *cs) { Nios2CPU *cpu =3D NIOS2_CPU(cs); @@ -60,6 +90,10 @@ void nios2_cpu_do_interrupt(CPUState *cs) switch (cs->exception_index) { case EXCP_IRQ: qemu_log_mask(CPU_LOG_INT, "interrupt at pc=3D%x\n", env->pc); + if (cpu->eic_present) { + eic_do_interrupt(cpu); + return; + } break; =20 case EXCP_TLBD: @@ -113,6 +147,9 @@ void nios2_cpu_do_interrupt(CPUState *cs) * Finish Internal Interrupt or Noninterrupt Exception. */ =20 + env->status &=3D ~R_CR_STATUS_CRS_MASK; + nios2_update_crs(env); + if (!(env->status & CR_STATUS_EH)) { env->ctrl[cr_estatus] =3D env->status; env->crs[r_ea] =3D env->pc + 4; --=20 2.25.1 From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646725550463582.5450186468166; Mon, 7 Mar 2022 23:45:50 -0800 (PST) Received: from localhost ([::1]:50702 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nRUXU-0000mV-TC for importer@patchew.org; Tue, 08 Mar 2022 02:45:49 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45524) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nRU9U-0005ks-Rs for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:21:00 -0500 Received: from [2607:f8b0:4864:20::52c] (port=37623 helo=mail-pg1-x52c.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nRU9S-0006X5-H7 for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:21:00 -0500 Received: by mail-pg1-x52c.google.com with SMTP id bc27so15684716pgb.4 for ; Mon, 07 Mar 2022 23:20:57 -0800 (PST) Received: from localhost.localdomain (cpe-50-113-46-110.hawaii.res.rr.com. [50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=n9ebuKwb4wvCrnFZJ4tFllJX2fJkG+UUrCwzGOSPo4c=; b=WS2xy7200F++bdTDibmkd/4fuhgDXY3Wha4lDgsT9s6lrVP7fdxrNFYHSIWWtf2Ylj SO/73BLuEqbok62uicfaxapXsrK44A91y098bEa9ZIoOEcxOrHlTSfd8Y+v8gY6PJtn7 RPFQxO/0B0gsP5BMIedozabvKr5Yv5/Dtd2DSovWj+lga2+9yKJKg49kM410UfhFKw7D p04hiJAz8flzgkS/BT3Y2earrsXl1G8bx9WuF09C2WHM5T47MI8rSIrgLFgnWfhvF3xL j77YnE1gO3i9X8wy52KomVD+rnLbihUKFE+GhtLXLI1dyLwF0vmr6c8ftdEjl0QSTiqr FzqA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=n9ebuKwb4wvCrnFZJ4tFllJX2fJkG+UUrCwzGOSPo4c=; b=UlNyGCj+5nq+w0aKplGH7XgMyMNoh1bksWSPDZGpbq05F4IjyTbSPEM44nUmPe9oiY EJRmqXZnrbTIJ9XbPUNGalDQ9GIDVxJcXZ6+wDMfhP4+MUo1XhfHmgkO9fN430R2gaW+ BYZi5Bf1q8VHYD7G4PNU5PCTGuY5s5rPe34J6QXFF0/DEi0DKpONRTVzWV0rndHmBH4t SsWOkbY9+PF3exGnaOxY9mJrxYEsyt5Syw2J82ZTpuKPtZD3iEitmN5H9SoxEuokq+7f Ju9nkYEoAKGNwKyPQ+Uhp94T0Emt613zxtS/Gt8JLwkDlpfIvWf9aiNoOp+m9fk/bojt wsoA== X-Gm-Message-State: AOAM5328JGaRRX2fmmYaugQvna8qsTAtyREwUlnUIHFYo8B6xkJD89VU RcGecshwTLN+99Vnx8/7NVr9cAejsIA4Bw== X-Google-Smtp-Source: ABdhPJyvjni0TiMS9ZqLGLLeYIlsNigLNscVhMSmbKLP8UhYRE9qgP4tTUsQ6XU8utL5LRSRppnXrg== X-Received: by 2002:aa7:85d8:0:b0:4f6:8ae9:16a8 with SMTP id z24-20020aa785d8000000b004f68ae916a8mr16902734pfn.15.1646724056949; Mon, 07 Mar 2022 23:20:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 30/33] hw/intc: Vectored Interrupt Controller (VIC) Date: Mon, 7 Mar 2022 21:20:02 -1000 Message-Id: <20220308072005.307955-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::52c (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52c; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52c.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646725551725100001 From: Amir Gonnen Implement nios2 Vectored Interrupt Controller (VIC). VIC is connected to EIC. It needs to update rha, ril, rrs and rnmi fields on Nios2CPU before raising an IRQ. For that purpose, VIC has a "cpu" property which should refer to the nios2 cpu and set by the board that connects VIC. Signed-off-by: Amir Gonnen Message-Id: <20220303153906.2024748-5-amir.gonnen@neuroblade.ai> Signed-off-by: Richard Henderson --- hw/intc/nios2_vic.c | 341 ++++++++++++++++++++++++++++++++++++++++++++ hw/intc/Kconfig | 3 + hw/intc/meson.build | 1 + 3 files changed, 345 insertions(+) create mode 100644 hw/intc/nios2_vic.c diff --git a/hw/intc/nios2_vic.c b/hw/intc/nios2_vic.c new file mode 100644 index 0000000000..b59d3f6f4c --- /dev/null +++ b/hw/intc/nios2_vic.c @@ -0,0 +1,341 @@ +/* + * Vectored Interrupt Controller for nios2 processor + * + * Copyright (c) 2022 Neuroblade + * + * Interface: + * QOM property "cpu": link to the Nios2 CPU (must be set) + * Unnamed GPIO inputs 0..NIOS2_VIC_MAX_IRQ-1: input IRQ lines + * IRQ should be connected to nios2 IRQ0. + * + * Reference: "Embedded Peripherals IP User Guide + * for Intel=C2=AE Quartus=C2=AE Prime Design Suite: 21.4" + * Chapter 38 "Vectored Interrupt Controller Core" + * See: https://www.intel.com/content/www/us/en/docs/programmable/683130/2= 1-4/vectored-interrupt-controller-core.html + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" + +#include "hw/irq.h" +#include "hw/qdev-properties.h" +#include "hw/sysbus.h" +#include "migration/vmstate.h" +#include "qapi/error.h" +#include "qemu/bitops.h" +#include "qemu/log.h" +#include "qom/object.h" +#include "cpu.h" + +#define TYPE_NIOS2_VIC "nios2-vic" + +OBJECT_DECLARE_SIMPLE_TYPE(Nios2Vic, NIOS2_VIC) + +#define NIOS2_VIC_MAX_IRQ 32 + +enum { + INT_CONFIG0 =3D 0, + INT_CONFIG31 =3D 31, + INT_ENABLE =3D 32, + INT_ENABLE_SET =3D 33, + INT_ENABLE_CLR =3D 34, + INT_PENDING =3D 35, + INT_RAW_STATUS =3D 36, + SW_INTERRUPT =3D 37, + SW_INTERRUPT_SET =3D 38, + SW_INTERRUPT_CLR =3D 39, + VIC_CONFIG =3D 40, + VIC_STATUS =3D 41, + VEC_TBL_BASE =3D 42, + VEC_TBL_ADDR =3D 43, + CSR_COUNT /* Last! */ +}; + +struct Nios2Vic { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + qemu_irq output_int; + + /* properties */ + CPUState *cpu; + MemoryRegion csr; + + uint32_t int_config[32]; + uint32_t vic_config; + uint32_t int_raw_status; + uint32_t int_enable; + uint32_t sw_int; + uint32_t vic_status; + uint32_t vec_tbl_base; + uint32_t vec_tbl_addr; +}; + +/* Requested interrupt level (INT_CONFIG[0:5]) */ +static inline uint32_t vic_int_config_ril(const Nios2Vic *vic, int irq_num) +{ + return extract32(vic->int_config[irq_num], 0, 6); +} + +/* Requested NMI (INT_CONFIG[6]) */ +static inline uint32_t vic_int_config_rnmi(const Nios2Vic *vic, int irq_nu= m) +{ + return extract32(vic->int_config[irq_num], 6, 1); +} + +/* Requested register set (INT_CONFIG[7:12]) */ +static inline uint32_t vic_int_config_rrs(const Nios2Vic *vic, int irq_num) +{ + return extract32(vic->int_config[irq_num], 7, 6); +} + +static inline uint32_t vic_config_vec_size(const Nios2Vic *vic) +{ + return 1 << (2 + extract32(vic->vic_config, 0, 3)); +} + +static inline uint32_t vic_int_pending(const Nios2Vic *vic) +{ + return (vic->int_raw_status | vic->sw_int) & vic->int_enable; +} + +static void vic_update_irq(Nios2Vic *vic) +{ + Nios2CPU *cpu =3D NIOS2_CPU(vic->cpu); + uint32_t pending =3D vic_int_pending(vic); + int irq =3D -1; + int max_ril =3D 0; + /* Note that if RIL is 0 for an interrupt it is effectively disabled */ + + vic->vec_tbl_addr =3D 0; + vic->vic_status =3D 0; + + if (pending =3D=3D 0) { + qemu_irq_lower(vic->output_int); + return; + } + + for (int i =3D 0; i < NIOS2_VIC_MAX_IRQ; i++) { + if (pending & BIT(i)) { + int ril =3D vic_int_config_ril(vic, i); + if (ril > max_ril) { + irq =3D i; + max_ril =3D ril; + } + } + } + + if (irq < 0) { + qemu_irq_lower(vic->output_int); + return; + } + + vic->vec_tbl_addr =3D irq * vic_config_vec_size(vic) + vic->vec_tbl_ba= se; + vic->vic_status =3D irq | BIT(31); + + /* + * In hardware, the interface between the VIC and the CPU is via the + * External Interrupt Controller interface, where the interrupt contro= ller + * presents the CPU with a packet of data containing: + * - Requested Handler Address (RHA): 32 bits + * - Requested Register Set (RRS) : 6 bits + * - Requested Interrupt Level (RIL) : 6 bits + * - Requested NMI flag (RNMI) : 1 bit + * In our emulation, we implement this by writing the data directly to + * fields in the CPU object and then raising the IRQ line to tell + * the CPU that we've done so. + */ + + cpu->rha =3D vic->vec_tbl_addr; + cpu->ril =3D max_ril; + cpu->rrs =3D vic_int_config_rrs(vic, irq); + cpu->rnmi =3D vic_int_config_rnmi(vic, irq); + + qemu_irq_raise(vic->output_int); +} + +static void vic_set_irq(void *opaque, int irq_num, int level) +{ + Nios2Vic *vic =3D opaque; + + if (level) { + vic->int_raw_status |=3D BIT(irq_num); + } else { + vic->int_raw_status &=3D ~BIT(irq_num); + } + + vic_update_irq(vic); +} + +static void nios2_vic_reset(DeviceState *dev) +{ + Nios2Vic *vic =3D NIOS2_VIC(dev); + memset(&vic->int_config, 0, sizeof(vic->int_config)); + vic->vic_config =3D 0; + vic->int_raw_status =3D 0; + vic->int_enable =3D 0; + vic->sw_int =3D 0; + vic->vic_status =3D 0; + vic->vec_tbl_base =3D 0; + vic->vec_tbl_addr =3D 0; +} + +static uint64_t nios2_vic_csr_read(void *opaque, hwaddr offset, unsigned s= ize) +{ + Nios2Vic *vic =3D opaque; + int index =3D offset / 4; + + switch (index) { + case INT_CONFIG0 ... INT_CONFIG31: + return vic->int_config[index - INT_CONFIG0]; + case INT_ENABLE: + return vic->int_enable; + case INT_PENDING: + return vic_int_pending(vic); + case INT_RAW_STATUS: + return vic->int_raw_status; + case SW_INTERRUPT: + return vic->sw_int; + case VIC_CONFIG: + return vic->vic_config; + case VIC_STATUS: + return vic->vic_status; + case VEC_TBL_BASE: + return vic->vec_tbl_base; + case VEC_TBL_ADDR: + return vic->vec_tbl_addr; + default: + return 0; + } +} + +static void nios2_vic_csr_write(void *opaque, hwaddr offset, uint64_t valu= e, + unsigned size) +{ + Nios2Vic *vic =3D opaque; + int index =3D offset / 4; + + switch (index) { + case INT_CONFIG0 ... INT_CONFIG31: + vic->int_config[index - INT_CONFIG0] =3D value; + break; + case INT_ENABLE: + vic->int_enable =3D value; + break; + case INT_ENABLE_SET: + vic->int_enable |=3D value; + break; + case INT_ENABLE_CLR: + vic->int_enable &=3D ~value; + break; + case SW_INTERRUPT: + vic->sw_int =3D value; + break; + case SW_INTERRUPT_SET: + vic->sw_int |=3D value; + break; + case SW_INTERRUPT_CLR: + vic->sw_int &=3D ~value; + break; + case VIC_CONFIG: + vic->vic_config =3D value; + break; + case VEC_TBL_BASE: + vic->vec_tbl_base =3D value; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, + "nios2-vic: write to invalid CSR address 0x%x\n", (int)offset); + } + + vic_update_irq(vic); +} + +static const MemoryRegionOps nios2_vic_csr_ops =3D { + .read =3D nios2_vic_csr_read, + .write =3D nios2_vic_csr_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { .min_access_size =3D 4, .max_access_size =3D 4 } +}; + +static void nios2_vic_realize(DeviceState *dev, Error **errp) +{ + Nios2Vic *vic =3D NIOS2_VIC(dev); + + if (!vic->cpu) { + /* This is a programming error in the code using this device */ + error_setg(errp, "nios2-vic 'cpu' link property was not set"); + return; + } + + sysbus_init_irq(SYS_BUS_DEVICE(dev), &vic->output_int); + qdev_init_gpio_in(dev, vic_set_irq, NIOS2_VIC_MAX_IRQ); + + memory_region_init_io(&vic->csr, OBJECT(dev), &nios2_vic_csr_ops, vic, + "nios2.vic.csr", CSR_COUNT * sizeof(uint32_t)); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &vic->csr); +} + +static Property nios2_vic_properties[] =3D { + DEFINE_PROP_LINK("cpu", Nios2Vic, cpu, TYPE_CPU, CPUState *), + DEFINE_PROP_END_OF_LIST() +}; + +static const VMStateDescription nios2_vic_vmstate =3D { + .name =3D "nios2-vic", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]){ + VMSTATE_UINT32_ARRAY(int_config, Nios2Vic, 32), + VMSTATE_UINT32(vic_config, Nios2Vic), + VMSTATE_UINT32(int_raw_status, Nios2Vic), + VMSTATE_UINT32(int_enable, Nios2Vic), + VMSTATE_UINT32(sw_int, Nios2Vic), + VMSTATE_UINT32(vic_status, Nios2Vic), + VMSTATE_UINT32(vec_tbl_base, Nios2Vic), + VMSTATE_UINT32(vec_tbl_addr, Nios2Vic), + VMSTATE_END_OF_LIST() + }, +}; + +static void nios2_vic_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + dc->reset =3D nios2_vic_reset; + dc->realize =3D nios2_vic_realize; + dc->vmsd =3D &nios2_vic_vmstate; + device_class_set_props(dc, nios2_vic_properties); +} + +static const TypeInfo nios2_vic_info =3D { + .name =3D TYPE_NIOS2_VIC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(Nios2Vic), + .class_init =3D nios2_vic_class_init, +}; + +static void nios2_vic_register_types(void) +{ + type_register_static(&nios2_vic_info); +} + +type_init(nios2_vic_register_types); diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index ec8d4cec29..eeb2d6f428 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -84,3 +84,6 @@ config GOLDFISH_PIC =20 config M68K_IRQC bool + +config NIOS2_VIC + bool diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 81ccdb0d78..167755ac64 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -62,3 +62,4 @@ specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'], if_true: files('spapr_xive_kvm.c')) specific_ss.add(when: 'CONFIG_GOLDFISH_PIC', if_true: files('goldfish_pic.= c')) specific_ss.add(when: 'CONFIG_M68K_IRQC', if_true: files('m68k_irqc.c')) +specific_ss.add(when: 'CONFIG_NIOS2_VIC', if_true: files('nios2_vic.c')) --=20 2.25.1 From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646725586164289.6130236440662; Mon, 7 Mar 2022 23:46:26 -0800 (PST) Received: from localhost ([::1]:51190 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nRUY5-00016A-0C for importer@patchew.org; Tue, 08 Mar 2022 02:46:25 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45526) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nRU9V-0005mn-Bj for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:21:01 -0500 Received: from [2607:f8b0:4864:20::102e] (port=42779 helo=mail-pj1-x102e.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nRU9T-0006XL-P5 for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:21:01 -0500 Received: by mail-pj1-x102e.google.com with SMTP id c16-20020a17090aa61000b001befad2bfaaso1596695pjq.1 for ; Mon, 07 Mar 2022 23:20:59 -0800 (PST) Received: from localhost.localdomain (cpe-50-113-46-110.hawaii.res.rr.com. [50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=h+jQs21jGzokf3Yfc7d46eGEeMlYc/6pCsyk7NVMPxQ=; b=p9onNzxDSMZrCprXu6px+Rn8Tg7bSaGSL5bWJw93JwBcQuXtWsnZ0AfJ+uaL2PSifU xNHl539ufNvGh74yPFYrbtKbI1NzzK3W0N5AgOBL6IcXQxR8/cF8/pDNDDZUS5F8l4IQ el9vv1oWQEp7gfYgmwKCDkuxfm6ZwY0sfXYOQ5pFmK5WFXv6r2vFVYWSfMcawITZFQN/ ySt8Pn+nbAr4eF1Dqr7hWn///KXj6pQ/Mrs5bOviyAdMXkxl7omFdd/R7StU9OVsGR56 TI0aHklEZpP/bW3MqeIj/R41CGKuBHeXBUSAo+DDryWRM23uKrSaMSyqJKa4qheoimAX EPKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h+jQs21jGzokf3Yfc7d46eGEeMlYc/6pCsyk7NVMPxQ=; b=UjjlPZG1POqCamKuxt7JPPKeiDv1XpsK4k2N2jgfTwyKW3kTBG/QgdjAFQbZHYUgGP lwtoI6td8i8iwLRQbeUIJGU0HnJ2cSVZZjzJGb/0Lk7K2o4xYHf0lTz4JPSJyqcdBClQ a+H0yMLkaWt8lkWlu3jqGPEvIxHToIHTIG05RbMYPLNzJsn+GdEncZPRY5qG5sYYIWjr YaccXmLy19BU7XEdemsUOPKVc3i3Ng6DepO3PqMYvyfSZxfAweb/Cp134flEKyUELmNt u0qJ70cSgLbenaoldsON1DorvXSFvRP0YwTWaKoKgsCxa8XUjuAJZK2plTA7m9QlmxZv MJ3A== X-Gm-Message-State: AOAM531iWY23Oi7opWFhFSpRWDpmZRLjPRcjSB7gGJP+AmcvUVyX1c/8 2tjevO3MA9kie+cT/pMfVSCn2SQHiCfgTg== X-Google-Smtp-Source: ABdhPJyk+NtBJ5auKo7esvVxxZFrtp75T9oKfQxytsmUk+JTAicmnBu8Rt7+izMLYloW0JUbq8sU3Q== X-Received: by 2002:a17:90a:a594:b0:1bc:5def:a652 with SMTP id b20-20020a17090aa59400b001bc5defa652mr3187541pjq.167.1646724058484; Mon, 07 Mar 2022 23:20:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 31/33] hw/nios2: Introduce Nios2MachineState Date: Mon, 7 Mar 2022 21:20:03 -1000 Message-Id: <20220308072005.307955-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::102e (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646725587861100001 Content-Type: text/plain; charset="utf-8" We want to move data from the heap into Nios2MachineState, which is not possible with DEFINE_MACHINE. Signed-off-by: Richard Henderson --- hw/nios2/10m50_devboard.c | 28 +++++++++++++++++++++++++--- 1 file changed, 25 insertions(+), 3 deletions(-) diff --git a/hw/nios2/10m50_devboard.c b/hw/nios2/10m50_devboard.c index 3d1205b8bd..f245e0baa8 100644 --- a/hw/nios2/10m50_devboard.c +++ b/hw/nios2/10m50_devboard.c @@ -36,10 +36,18 @@ =20 #include "boot.h" =20 +struct Nios2MachineState { + MachineState parent_obj; +}; + +#define TYPE_NIOS2_MACHINE MACHINE_TYPE_NAME("10m50-ghrd") +OBJECT_DECLARE_TYPE(Nios2MachineState, MachineClass, NIOS2_MACHINE) + #define BINARY_DEVICE_TREE_FILE "10m50-devboard.dtb" =20 static void nios2_10m50_ghrd_init(MachineState *machine) { + Nios2MachineState *nms =3D NIOS2_MACHINE(machine); Nios2CPU *cpu; DeviceState *dev; MemoryRegion *address_space_mem =3D get_system_memory(); @@ -101,15 +109,29 @@ static void nios2_10m50_ghrd_init(MachineState *machi= ne) cpu->exception_addr =3D 0xc8000120; cpu->fast_tlb_miss_addr =3D 0xc0000100; =20 - nios2_load_kernel(cpu, ram_base, ram_size, machine->initrd_filename, + nios2_load_kernel(cpu, ram_base, ram_size, nms->parent_obj.initrd_file= name, BINARY_DEVICE_TREE_FILE, NULL); } =20 -static void nios2_10m50_ghrd_machine_init(struct MachineClass *mc) +static void nios2_10m50_ghrd_class_init(ObjectClass *oc, void *data) { + MachineClass *mc =3D MACHINE_CLASS(oc); + mc->desc =3D "Altera 10M50 GHRD Nios II design"; mc->init =3D nios2_10m50_ghrd_init; mc->is_default =3D true; } =20 -DEFINE_MACHINE("10m50-ghrd", nios2_10m50_ghrd_machine_init); +static const TypeInfo nios2_10m50_ghrd_type_info =3D { + .name =3D TYPE_NIOS2_MACHINE, + .parent =3D TYPE_MACHINE, + .instance_size =3D sizeof(Nios2MachineState), + .class_size =3D sizeof(MachineClass), + .class_init =3D nios2_10m50_ghrd_class_init, +}; + +static void nios2_10m50_ghrd_type_init(void) +{ + type_register_static(&nios2_10m50_ghrd_type_info); +} +type_init(nios2_10m50_ghrd_type_init); --=20 2.25.1 From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164672577458096.81904453484628; Mon, 7 Mar 2022 23:49:34 -0800 (PST) Received: from localhost ([::1]:59668 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nRUb8-0006vU-EL for importer@patchew.org; Tue, 08 Mar 2022 02:49:34 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45542) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nRU9W-0005uH-Q1 for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:21:02 -0500 Received: from [2607:f8b0:4864:20::1034] (port=51713 helo=mail-pj1-x1034.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nRU9V-0006Xg-8z for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:21:02 -0500 Received: by mail-pj1-x1034.google.com with SMTP id cx5so16375373pjb.1 for ; Mon, 07 Mar 2022 23:21:00 -0800 (PST) Received: from localhost.localdomain (cpe-50-113-46-110.hawaii.res.rr.com. [50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.20.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:20:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=DMNogBo/Kmk7IgcnHHoL3FUufdrXvnJqRT/umHXihDs=; b=HWatyJz204oF44MoMKtm7Ufic6IHXHs2KzYu9Wxc3Krxk5KVzAsd6aVlUzhtmGSdip og8wcV06YdUJIu26t7Kvv9Viks2hSio3UewOQUc9N0cIkOTdKkwjZ8h1xRgoiq/s/38z syiJoWdxqm0GliWQvHvL3S1Mg8Y2q4krIUUP185t+6T5wCQYew4ilDB7d0IsKM+XlBxW OJQpwRmkIR+Oln57as6Zu+8gwYsx4w8K6Q0J2YlwEEtA0GV1NCvTHtHhrEB/RzBEj4Y0 z3NHbiOZsoPHUvMQVcBxzSTw+g15M/mnKycpLOzr2JdSC68yr45+8hcdY6LfQ2fPxGfx kCbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=DMNogBo/Kmk7IgcnHHoL3FUufdrXvnJqRT/umHXihDs=; b=ULJG11s/fSBAZErbFFdvk8jJaKg06IkzONXT3xXvMLqhbVV60orkm1Zd979uH6cudl AfBCcyBsW2XSvmveCeCqX1cnP0MO5/kufm7bN6g27g2KUmDemVaGvBa1jlrQ7asNJZaZ vQwK7LeAApKFgN0eIyiHrbCt6AvVF3XhxcB/PIESRlKa53RPWWr8ul5iWrcBoBnQFaag dwIcLJwRS16MzIPWkC5T0lBBM7Ipmd5ereVmmr5H32vBSaEt0z72ecxoGcv2fkig1U+4 BaBdFWOvS8MorkGzK0udON7tNZuNK3ydnbPGqDE+nNe6oNP9V8pqi8lg+lXN95HSITcQ QL9g== X-Gm-Message-State: AOAM533aAbfSCK2QA9MBclx0m9VkzaDq0TY/mRKaswBe+RpFWcwrvw5U aQS2uvX0tkwJ0eXYXySoTvc76scwkYZT0A== X-Google-Smtp-Source: ABdhPJykXn+KzEP/qwhM9T81rVhv6bOiWLkq1CryfXwxwJvUleAoRQD3cYGXsgAHdIBnK9oFGlaLuA== X-Received: by 2002:a17:902:d4c5:b0:151:e69d:89fa with SMTP id o5-20020a170902d4c500b00151e69d89famr9726638plg.139.1646724060013; Mon, 07 Mar 2022 23:21:00 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 32/33] hw/nios2: Move memory regions into Nios2Machine Date: Mon, 7 Mar 2022 21:20:04 -1000 Message-Id: <20220308072005.307955-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1034 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646725776446100001 Content-Type: text/plain; charset="utf-8" Convert to contiguous allocation, as much as possible so far. The two timer objects are not exposed for subobject allocation. Signed-off-by: Richard Henderson Reviewed-by: Mark Cave-Ayland --- hw/nios2/10m50_devboard.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-) diff --git a/hw/nios2/10m50_devboard.c b/hw/nios2/10m50_devboard.c index f245e0baa8..f4931b8a67 100644 --- a/hw/nios2/10m50_devboard.c +++ b/hw/nios2/10m50_devboard.c @@ -38,6 +38,11 @@ =20 struct Nios2MachineState { MachineState parent_obj; + + MemoryRegion phys_tcm; + MemoryRegion phys_tcm_alias; + MemoryRegion phys_ram; + MemoryRegion phys_ram_alias; }; =20 #define TYPE_NIOS2_MACHINE MACHINE_TYPE_NAME("10m50-ghrd") @@ -51,10 +56,6 @@ static void nios2_10m50_ghrd_init(MachineState *machine) Nios2CPU *cpu; DeviceState *dev; MemoryRegion *address_space_mem =3D get_system_memory(); - MemoryRegion *phys_tcm =3D g_new(MemoryRegion, 1); - MemoryRegion *phys_tcm_alias =3D g_new(MemoryRegion, 1); - MemoryRegion *phys_ram =3D g_new(MemoryRegion, 1); - MemoryRegion *phys_ram_alias =3D g_new(MemoryRegion, 1); ram_addr_t tcm_base =3D 0x0; ram_addr_t tcm_size =3D 0x1000; /* 1 kiB, but QEMU limit is 4 kiB */ ram_addr_t ram_base =3D 0x08000000; @@ -63,22 +64,22 @@ static void nios2_10m50_ghrd_init(MachineState *machine) int i; =20 /* Physical TCM (tb_ram_1k) with alias at 0xc0000000 */ - memory_region_init_ram(phys_tcm, NULL, "nios2.tcm", tcm_size, + memory_region_init_ram(&nms->phys_tcm, NULL, "nios2.tcm", tcm_size, &error_abort); - memory_region_init_alias(phys_tcm_alias, NULL, "nios2.tcm.alias", - phys_tcm, 0, tcm_size); - memory_region_add_subregion(address_space_mem, tcm_base, phys_tcm); + memory_region_init_alias(&nms->phys_tcm_alias, NULL, "nios2.tcm.alias", + &nms->phys_tcm, 0, tcm_size); + memory_region_add_subregion(address_space_mem, tcm_base, &nms->phys_tc= m); memory_region_add_subregion(address_space_mem, 0xc0000000 + tcm_base, - phys_tcm_alias); + &nms->phys_tcm_alias); =20 /* Physical DRAM with alias at 0xc0000000 */ - memory_region_init_ram(phys_ram, NULL, "nios2.ram", ram_size, + memory_region_init_ram(&nms->phys_ram, NULL, "nios2.ram", ram_size, &error_abort); - memory_region_init_alias(phys_ram_alias, NULL, "nios2.ram.alias", - phys_ram, 0, ram_size); - memory_region_add_subregion(address_space_mem, ram_base, phys_ram); + memory_region_init_alias(&nms->phys_ram_alias, NULL, "nios2.ram.alias", + &nms->phys_ram, 0, ram_size); + memory_region_add_subregion(address_space_mem, ram_base, &nms->phys_ra= m); memory_region_add_subregion(address_space_mem, 0xc0000000 + ram_base, - phys_ram_alias); + &nms->phys_ram_alias); =20 /* Create CPU -- FIXME */ cpu =3D NIOS2_CPU(cpu_create(TYPE_NIOS2_CPU)); --=20 2.25.1 From nobody Sat May 18 19:47:57 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646725765877408.82148604783754; Mon, 7 Mar 2022 23:49:25 -0800 (PST) Received: from localhost ([::1]:59334 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nRUaz-0006hv-Nu for importer@patchew.org; Tue, 08 Mar 2022 02:49:25 -0500 Received: from eggs.gnu.org ([209.51.188.92]:45558) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nRU9Y-00060M-G1 for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:21:04 -0500 Received: from [2607:f8b0:4864:20::1034] (port=33337 helo=mail-pj1-x1034.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nRU9W-0006Xv-PD for qemu-devel@nongnu.org; Tue, 08 Mar 2022 02:21:04 -0500 Received: by mail-pj1-x1034.google.com with SMTP id v1-20020a17090a088100b001bf25f97c6eso1572406pjc.0 for ; Mon, 07 Mar 2022 23:21:02 -0800 (PST) Received: from localhost.localdomain (cpe-50-113-46-110.hawaii.res.rr.com. [50.113.46.110]) by smtp.gmail.com with ESMTPSA id p125-20020a622983000000b004f6c5d58225sm13790899pfp.90.2022.03.07.23.21.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Mar 2022 23:21:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gqQ9d0fGzI9y1pXacs8lImslbXY8EcC24UqzWPnojhY=; b=A6tpGikr8tiiVL1uqZHdbY3JyMCaAYlWpjNjh2uLodUbnbT1fO4eTqPLsqiQe1gwOg vKUFiLFDA5j7QsR8NLKlHxcr8jwLFLtDGIJv9o8SkQGXDre9XAt3eYhiJADcdN2ynaU0 YvaATCs/y9FH5IjpQ+KISnVBK/lZgJ68J2q3lIh4UIK33aTzaG+a+Q/YbU64XszLu2cm kb7owkPVJcJmC4g5sMKULZD8IKbmwVg51g6ayGnF24PgcLWbMFki+GO/zG0vmsczpOpk o0v5Ep81N7WXTkvgoBkmydpv0xosnNhbGvPYejRPtpTq1OnBmhgktz3a0Xk08BXv329+ QUNw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gqQ9d0fGzI9y1pXacs8lImslbXY8EcC24UqzWPnojhY=; b=7K0qfAuNQFCXbH6iIdhFVlAwwUq5D6IJXjIb/LvFQJs8RQnrrzMMQufS+17Mc8Pg7S i1lyrJjB3+xUzAkFZBBA0OxSiEKsjSKfr38LWi2FVuBr9XhyCIWvFRD17FpNqvChx0g0 77xPCc7J4glPgjE/y/jpcgKoBXoDEThiRgrJ2FEWALuSrPLLQeSj/8bBdqIkY9cYyx8c QFfT6nsjEQqIKQmR/rGmnexCa8uNL5G8CnoC+glFizkqLpJRQKMxZBH0oTZ6q84ZGsAH p4iUtelEKyMRixVKA7tNKRurclPhWSevQgEn2Lc1eZ9hXq9laBbenAC6w+Tp/vPuC9qr fcCQ== X-Gm-Message-State: AOAM531MFRlKFB+PguUXXdHCguDAzMFW2NBziRyYvzlIkmDfUochYTXI vIK2tBo0tdM/2wJFX4BBwcftRqtq0sqjng== X-Google-Smtp-Source: ABdhPJyPMWsKAAAQx3WiHQ/MMCfFVLhKCNeKn2zeOmPP6Z+RnYSld3lnbFMnwVTNcLF4JHZNKmwTdA== X-Received: by 2002:a17:90b:38c9:b0:1bf:871b:1a4d with SMTP id nn9-20020a17090b38c900b001bf871b1a4dmr3028086pjb.18.1646724061555; Mon, 07 Mar 2022 23:21:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 33/33] hw/nios2: Machine with a Vectored Interrupt Controller Date: Mon, 7 Mar 2022 21:20:05 -1000 Message-Id: <20220308072005.307955-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220308072005.307955-1-richard.henderson@linaro.org> References: <20220308072005.307955-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1034 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, peter.maydell@linaro.org, amir.gonnen@neuroblade.ai Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646725771662100001 Content-Type: text/plain; charset="utf-8" From: Amir Gonnen Demonstrate how to use nios2 VIC on a machine. Introduce a new machine property to attach a VIC. When VIC is present, let the CPU know that it should use the External Interrupt Interface instead of the Internal Interrupt Interface. The devices on the machine are attached to the VIC and not directly to cpu. To allow VIC update EIC fields, we set the "cpu" property of the VIC with a reference to the nios2 cpu. Signed-off-by: Amir Gonnen Message-Id: <20220303153906.2024748-6-amir.gonnen@neuroblade.ai> [rth: Put a property on the 10m50-ghrd machine, rather than create a new machine class.] Signed-off-by: Richard Henderson --- hw/nios2/10m50_devboard.c | 61 +++++++++++++++++++++++++++++++++------ hw/nios2/Kconfig | 1 + 2 files changed, 53 insertions(+), 9 deletions(-) diff --git a/hw/nios2/10m50_devboard.c b/hw/nios2/10m50_devboard.c index f4931b8a67..bdbc6539c9 100644 --- a/hw/nios2/10m50_devboard.c +++ b/hw/nios2/10m50_devboard.c @@ -43,6 +43,8 @@ struct Nios2MachineState { MemoryRegion phys_tcm_alias; MemoryRegion phys_ram; MemoryRegion phys_ram_alias; + + bool vic; }; =20 #define TYPE_NIOS2_MACHINE MACHINE_TYPE_NAME("10m50-ghrd") @@ -81,10 +83,40 @@ static void nios2_10m50_ghrd_init(MachineState *machine) memory_region_add_subregion(address_space_mem, 0xc0000000 + ram_base, &nms->phys_ram_alias); =20 - /* Create CPU -- FIXME */ - cpu =3D NIOS2_CPU(cpu_create(TYPE_NIOS2_CPU)); - for (i =3D 0; i < 32; i++) { - irq[i] =3D qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", i); + /* Create CPU. We need to set eic_present between init and realize. */ + cpu =3D NIOS2_CPU(object_new(TYPE_NIOS2_CPU)); + + /* Enable the External Interrupt Controller within the CPU. */ + cpu->eic_present =3D nms->vic; + + /* Configure new exception vectors. */ + cpu->reset_addr =3D 0xd4000000; + cpu->exception_addr =3D 0xc8000120; + cpu->fast_tlb_miss_addr =3D 0xc0000100; + + qdev_realize(DEVICE(cpu), NULL, &error_fatal); + object_unref(CPU(cpu)); + + if (nms->vic) { + DeviceState *dev =3D qdev_new("nios2-vic"); + MemoryRegion *dev_mr; + qemu_irq cpu_irq; + + object_property_set_link(OBJECT(dev), "cpu", OBJECT(cpu), &error_f= atal); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + + cpu_irq =3D qdev_get_gpio_in_named(DEVICE(cpu), "EIC", 0); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq); + for (int i =3D 0; i < 32; i++) { + irq[i] =3D qdev_get_gpio_in(dev, i); + } + + dev_mr =3D sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); + memory_region_add_subregion(address_space_mem, 0x18002000, dev_mr); + } else { + for (i =3D 0; i < 32; i++) { + irq[i] =3D qdev_get_gpio_in_named(DEVICE(cpu), "IRQ", i); + } } =20 /* Register: Altera 16550 UART */ @@ -105,15 +137,22 @@ static void nios2_10m50_ghrd_init(MachineState *machi= ne) sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xe0000880); sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[5]); =20 - /* Configure new exception vectors and reset CPU for it to take effect= . */ - cpu->reset_addr =3D 0xd4000000; - cpu->exception_addr =3D 0xc8000120; - cpu->fast_tlb_miss_addr =3D 0xc0000100; - nios2_load_kernel(cpu, ram_base, ram_size, nms->parent_obj.initrd_file= name, BINARY_DEVICE_TREE_FILE, NULL); } =20 +static bool get_vic(Object *obj, Error **errp) +{ + Nios2MachineState *nms =3D NIOS2_MACHINE(obj); + return nms->vic; +} + +static void set_vic(Object *obj, bool value, Error **errp) +{ + Nios2MachineState *nms =3D NIOS2_MACHINE(obj); + nms->vic =3D value; +} + static void nios2_10m50_ghrd_class_init(ObjectClass *oc, void *data) { MachineClass *mc =3D MACHINE_CLASS(oc); @@ -121,6 +160,10 @@ static void nios2_10m50_ghrd_class_init(ObjectClass *o= c, void *data) mc->desc =3D "Altera 10M50 GHRD Nios II design"; mc->init =3D nios2_10m50_ghrd_init; mc->is_default =3D true; + + object_class_property_add_bool(oc, "vic", get_vic, set_vic); + object_class_property_set_description(oc, "vic", + "Set on/off to enable/disable the Vectored Interrupt Controller"); } =20 static const TypeInfo nios2_10m50_ghrd_type_info =3D { diff --git a/hw/nios2/Kconfig b/hw/nios2/Kconfig index b10ea640da..4748ae27b6 100644 --- a/hw/nios2/Kconfig +++ b/hw/nios2/Kconfig @@ -3,6 +3,7 @@ config NIOS2_10M50 select NIOS2 select SERIAL select ALTERA_TIMER + select NIOS2_VIC =20 config NIOS2_GENERIC_NOMMU bool --=20 2.25.1