From nobody Mon Feb 9 09:16:23 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1646590119; cv=none; d=zohomail.com; s=zohoarc; b=DstdgycOjsOtExAb4u534/e0woarMdhgWx++z+XdC+4eXUSfkXi/H1IAR6mLtILnRcEfJWU9/dqE8iHKpbAr4j/vhd5o0z7aQx5J5Egmdf35zQarHTWQTczVDgQLKkrGhVhj5sKvIuUXVVI2VWrzyAyWwLqgZyhAKmZ9DB3Yum4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1646590119; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=uvz9IubPjVy05shJK3mCUrHO05IpkJpy2kx0HQzPa+Y=; b=FFSdjyegZvVPKKbo2hIAP+P2fV8HL1dzays5k23P//gup6GwiB3s4st4TLvJQIz4dxjW4tiGtlqTh0eqnOofECqbaIwb47Csv8iPXfelkfo6yWme0Ez51RzZFJ7BKJZwKqMLlmhbICRyzcUoBZxqXg4yN9P/bm8mfbFXZZGzQHk= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646590119824783.4012576095239; Sun, 6 Mar 2022 10:08:39 -0800 (PST) Received: from localhost ([::1]:51616 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nQvJ9-0002XU-Hf for importer@patchew.org; Sun, 06 Mar 2022 13:08:39 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60340) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nQv7k-0007lv-DB for qemu-devel@nongnu.org; Sun, 06 Mar 2022 12:56:54 -0500 Received: from frasgout.his.huawei.com ([185.176.79.56]:2368) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nQv7i-0004B7-UK for qemu-devel@nongnu.org; Sun, 06 Mar 2022 12:56:52 -0500 Received: from fraeml705-chm.china.huawei.com (unknown [172.18.147.226]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4KBTmX5GBTz67Gvv; Mon, 7 Mar 2022 01:56:28 +0800 (CST) Received: from lhreml710-chm.china.huawei.com (10.201.108.61) by fraeml705-chm.china.huawei.com (10.206.15.54) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2308.21; Sun, 6 Mar 2022 18:56:48 +0100 Received: from SecurePC-101-06.china.huawei.com (10.122.247.231) by lhreml710-chm.china.huawei.com (10.201.108.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2308.21; Sun, 6 Mar 2022 17:56:47 +0000 To: , , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Marcel Apfelbaum , "Michael S . Tsirkin" , Igor Mammedov , Markus Armbruster CC: , Ben Widawsky , "Peter Maydell" , Shameerali Kolothum Thodi , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Saransh Gupta1 , Shreyas Shah , Chris Browy , Samarth Saxena , "Dan Williams" Subject: [PATCH v7 30/46] pci/pcie_port: Add pci_find_port_by_pn() Date: Sun, 6 Mar 2022 17:41:21 +0000 Message-ID: <20220306174137.5707-31-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220306174137.5707-1-Jonathan.Cameron@huawei.com> References: <20220306174137.5707-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.247.231] X-ClientProxiedBy: lhreml706-chm.china.huawei.com (10.201.108.55) To lhreml710-chm.china.huawei.com (10.201.108.61) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Jonathan Cameron From: Jonathan Cameron via X-ZM-MESSAGEID: 1646590122364100001 From: Jonathan Cameron Simple function to search a PCIBus to find a port by it's port number. CXL interleave decoding uses the port number as a target so it is necessary to locate the port when doing interleave decoding. Signed-off-by: Jonathan Cameron Reviewed-by: Alex Benn=C3=A9e --- hw/pci/pcie_port.c | 25 +++++++++++++++++++++++++ include/hw/pci/pcie_port.h | 2 ++ 2 files changed, 27 insertions(+) diff --git a/hw/pci/pcie_port.c b/hw/pci/pcie_port.c index e95c1e5519..687e4e763a 100644 --- a/hw/pci/pcie_port.c +++ b/hw/pci/pcie_port.c @@ -136,6 +136,31 @@ static void pcie_port_class_init(ObjectClass *oc, void= *data) device_class_set_props(dc, pcie_port_props); } =20 +PCIDevice *pcie_find_port_by_pn(PCIBus *bus, uint8_t pn) +{ + int devfn; + + for (devfn =3D 0; devfn < ARRAY_SIZE(bus->devices); devfn++) { + PCIDevice *d =3D bus->devices[devfn]; + PCIEPort *port; + + if (!d || !pci_is_express(d) || !d->exp.exp_cap) { + continue; + } + + if (!object_dynamic_cast(OBJECT(d), TYPE_PCIE_PORT)) { + continue; + } + + port =3D PCIE_PORT(d); + if (port->port =3D=3D pn) { + return d; + } + } + + return NULL; +} + static const TypeInfo pcie_port_type_info =3D { .name =3D TYPE_PCIE_PORT, .parent =3D TYPE_PCI_BRIDGE, diff --git a/include/hw/pci/pcie_port.h b/include/hw/pci/pcie_port.h index e25b289ce8..7b8193061a 100644 --- a/include/hw/pci/pcie_port.h +++ b/include/hw/pci/pcie_port.h @@ -39,6 +39,8 @@ struct PCIEPort { =20 void pcie_port_init_reg(PCIDevice *d); =20 +PCIDevice *pcie_find_port_by_pn(PCIBus *bus, uint8_t pn); + #define TYPE_PCIE_SLOT "pcie-slot" OBJECT_DECLARE_SIMPLE_TYPE(PCIESlot, PCIE_SLOT) =20 --=20 2.32.0