From nobody Mon Feb 9 09:09:12 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1646588592; cv=none; d=zohomail.com; s=zohoarc; b=GJ15XvEgd3Y2fwJRKMYorST5DYITfqwsE7Es2YjxbwgahDuFxyX6HajS92ScbPeJoOU2WkFe42wrtVDWl4IsG5IQysrbdU9sCnHAHG4Gt++ATK6X+9tid9pkirPofBl56J2HPxc5b2FoSxVUQJITmOlp/7gsrFYvnHAYC7Xm+m0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1646588592; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:Reply-To:References:Sender:Subject:To; bh=NqpuImWcwhFRvHVeKwyp7msKcD4OFv4wUnUEVauRoLQ=; b=O2Iw24pxogCJB64NAbgNp4PJPP4EVIDcx49Up94rdZSX6l5CrAgOPOKMiyXNJ9HIlSe7fd98glgneNtxAgDpSzH/jzpW2Qsf2+WqXhZw6HO2hdARuvsl4GhvT5+UYlzHvD2Uk6QC2sLnow6yaiidonVxYuSOjoDsZP4wKmgGwFA= ARC-Authentication-Results: i=1; mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164658859276177.86609805070373; Sun, 6 Mar 2022 09:43:12 -0800 (PST) Received: from localhost ([::1]:34562 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nQuuV-0003fh-3t for importer@patchew.org; Sun, 06 Mar 2022 12:43:11 -0500 Received: from eggs.gnu.org ([209.51.188.92]:57800) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nQutO-000215-3o for qemu-devel@nongnu.org; Sun, 06 Mar 2022 12:42:02 -0500 Received: from frasgout.his.huawei.com ([185.176.79.56]:2339) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nQutM-0001wz-CP for qemu-devel@nongnu.org; Sun, 06 Mar 2022 12:42:01 -0500 Received: from fraeml734-chm.china.huawei.com (unknown [172.18.147.207]) by frasgout.his.huawei.com (SkyGuard) with ESMTP id 4KBTQG65BSz67WtW; Mon, 7 Mar 2022 01:40:38 +0800 (CST) Received: from lhreml710-chm.china.huawei.com (10.201.108.61) by fraeml734-chm.china.huawei.com (10.206.15.215) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2308.21; Sun, 6 Mar 2022 18:41:57 +0100 Received: from SecurePC-101-06.china.huawei.com (10.122.247.231) by lhreml710-chm.china.huawei.com (10.201.108.61) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256) id 15.1.2308.21; Sun, 6 Mar 2022 17:41:56 +0000 To: , , =?UTF-8?q?Alex=20Benn=C3=A9e?= , Marcel Apfelbaum , "Michael S . Tsirkin" , Igor Mammedov , Markus Armbruster CC: , Ben Widawsky , "Peter Maydell" , Shameerali Kolothum Thodi , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Saransh Gupta1 , Shreyas Shah , Chris Browy , Samarth Saxena , "Dan Williams" Subject: [PATCH v7 01/46] hw/pci/cxl: Add a CXL component type (interface) Date: Sun, 6 Mar 2022 17:40:52 +0000 Message-ID: <20220306174137.5707-2-Jonathan.Cameron@huawei.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220306174137.5707-1-Jonathan.Cameron@huawei.com> References: <20220306174137.5707-1-Jonathan.Cameron@huawei.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Originating-IP: [10.122.247.231] X-ClientProxiedBy: lhreml706-chm.china.huawei.com (10.201.108.55) To lhreml710-chm.china.huawei.com (10.201.108.61) X-CFilter-Loop: Reflected Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=185.176.79.56; envelope-from=jonathan.cameron@huawei.com; helo=frasgout.his.huawei.com X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" Reply-to: Jonathan Cameron From: Jonathan Cameron via X-ZM-MESSAGEID: 1646588593799100001 From: Ben Widawsky A CXL component is a hardware entity that implements CXL component registers from the CXL 2.0 spec (8.2.3). Currently these represent 3 general types. 1. Host Bridge 2. Ports (root, upstream, downstream) 3. Devices (memory, other) A CXL component can be conceptually thought of as a PCIe device with extra functionality when enumerated and enabled. For this reason, CXL does here, and will continue to add on to existing PCI code paths. Host bridges will typically need to be handled specially and so they can implement this newly introduced interface or not. All other components should implement this interface. Implementing this interface allows the core PCI code to treat these devices as special where appropriate. Signed-off-by: Ben Widawsky Signed-off-by: Jonathan Cameron Reviewed-by: Alex Benn=C3=A9e --- hw/pci/pci.c | 10 ++++++++++ include/hw/pci/pci.h | 8 ++++++++ 2 files changed, 18 insertions(+) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 5d30f9ca60..474ea98c1d 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -201,6 +201,11 @@ static const TypeInfo pci_bus_info =3D { .class_init =3D pci_bus_class_init, }; =20 +static const TypeInfo cxl_interface_info =3D { + .name =3D INTERFACE_CXL_DEVICE, + .parent =3D TYPE_INTERFACE, +}; + static const TypeInfo pcie_interface_info =3D { .name =3D INTERFACE_PCIE_DEVICE, .parent =3D TYPE_INTERFACE, @@ -2128,6 +2133,10 @@ static void pci_qdev_realize(DeviceState *qdev, Erro= r **errp) pci_dev->cap_present |=3D QEMU_PCI_CAP_EXPRESS; } =20 + if (object_class_dynamic_cast(klass, INTERFACE_CXL_DEVICE)) { + pci_dev->cap_present |=3D QEMU_PCIE_CAP_CXL; + } + pci_dev =3D do_pci_register_device(pci_dev, object_get_typename(OBJECT(qdev)), pci_dev->devfn, errp); @@ -2884,6 +2893,7 @@ static void pci_register_types(void) type_register_static(&pci_bus_info); type_register_static(&pcie_bus_info); type_register_static(&conventional_pci_interface_info); + type_register_static(&cxl_interface_info); type_register_static(&pcie_interface_info); type_register_static(&pci_device_type_info); } diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h index c3f3c90473..305df7add6 100644 --- a/include/hw/pci/pci.h +++ b/include/hw/pci/pci.h @@ -196,6 +196,8 @@ enum { QEMU_PCIE_LNKSTA_DLLLA =3D (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR), #define QEMU_PCIE_EXTCAP_INIT_BITNR 9 QEMU_PCIE_EXTCAP_INIT =3D (1 << QEMU_PCIE_EXTCAP_INIT_BITNR), +#define QEMU_PCIE_CXL_BITNR 10 + QEMU_PCIE_CAP_CXL =3D (1 << QEMU_PCIE_CXL_BITNR), }; =20 #define TYPE_PCI_DEVICE "pci-device" @@ -203,6 +205,12 @@ typedef struct PCIDeviceClass PCIDeviceClass; DECLARE_OBJ_CHECKERS(PCIDevice, PCIDeviceClass, PCI_DEVICE, TYPE_PCI_DEVICE) =20 +/* + * Implemented by devices that can be plugged on CXL buses. In the spec, t= his is + * actually a "CXL Component, but we name it device to match the PCI namin= g. + */ +#define INTERFACE_CXL_DEVICE "cxl-device" + /* Implemented by devices that can be plugged on PCI Express buses */ #define INTERFACE_PCIE_DEVICE "pci-express-device" =20 --=20 2.32.0