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Sun, 06 Mar 2022 05:00:09 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Eduardo Habkost , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 01/33] accel: Restrict sysemu stubs to system emulation Date: Sun, 6 Mar 2022 13:59:28 +0100 Message-Id: <20220306130000.8104-2-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> References: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571611687100001 From: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Thomas Huth Reviewed-by: Paolo Bonzini Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220207075426.81934-2-f4bug@amsat.org> --- accel/stubs/meson.build | 11 +++++++---- 1 file changed, 7 insertions(+), 4 deletions(-) diff --git a/accel/stubs/meson.build b/accel/stubs/meson.build index 12dd1539afa..0249b9258fd 100644 --- a/accel/stubs/meson.build +++ b/accel/stubs/meson.build @@ -1,4 +1,7 @@ -specific_ss.add(when: 'CONFIG_HAX', if_false: files('hax-stub.c')) -specific_ss.add(when: 'CONFIG_XEN', if_false: files('xen-stub.c')) -specific_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) -specific_ss.add(when: 'CONFIG_TCG', if_false: files('tcg-stub.c')) +sysemu_stubs_ss =3D ss.source_set() +sysemu_stubs_ss.add(when: 'CONFIG_HAX', if_false: files('hax-stub.c')) +sysemu_stubs_ss.add(when: 'CONFIG_XEN', if_false: files('xen-stub.c')) +sysemu_stubs_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) +sysemu_stubs_ss.add(when: 'CONFIG_TCG', if_false: files('tcg-stub.c')) + +specific_ss.add_all(when: ['CONFIG_SOFTMMU'], if_true: sysemu_stubs_ss) --=20 2.35.1 From nobody Sun Feb 8 05:08:15 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.48 as permitted sender) client-ip=209.85.221.48; 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Sun, 06 Mar 2022 05:00:14 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Eduardo Habkost , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 02/33] accel/meson: Only build hw virtualization with system emulation Date: Sun, 6 Mar 2022 13:59:29 +0100 Message-Id: <20220306130000.8104-3-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> References: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571628408100003 From: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Paolo Bonzini Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220207075426.81934-3-f4bug@amsat.org> --- accel/meson.build | 12 +++++++----- 1 file changed, 7 insertions(+), 5 deletions(-) diff --git a/accel/meson.build b/accel/meson.build index dfd808d2c8e..b9a963cf80c 100644 --- a/accel/meson.build +++ b/accel/meson.build @@ -2,12 +2,14 @@ softmmu_ss.add(files('accel-softmmu.c')) user_ss.add(files('accel-user.c')) =20 -subdir('hvf') -subdir('qtest') -subdir('kvm') subdir('tcg') -subdir('xen') -subdir('stubs') +if have_system + subdir('hvf') + subdir('qtest') + subdir('kvm') + subdir('xen') + subdir('stubs') +endif =20 dummy_ss =3D ss.source_set() dummy_ss.add(files( --=20 2.35.1 From nobody Sun Feb 8 05:08:15 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) client-ip=209.85.221.44; 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Sun, 06 Mar 2022 05:00:19 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Eduardo Habkost , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 03/33] exec: Declare vaddr as a generic target-agnostic type Date: Sun, 6 Mar 2022 13:59:30 +0100 Message-Id: <20220306130000.8104-4-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> References: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571622138100001 From: Philippe Mathieu-Daud=C3=A9 Move vaddr type declaration to the generic "exec/cpu-common.h" header. Reviewed-by: Paolo Bonzini Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220207075426.81934-4-f4bug@amsat.org> --- include/exec/cpu-common.h | 12 ++++++++++++ include/hw/core/cpu.h | 13 +------------ 2 files changed, 13 insertions(+), 12 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index de5f444b193..cd1d7328a1d 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -7,6 +7,18 @@ #include "exec/hwaddr.h" #endif =20 +/** + * vaddr: + * Type wide enough to contain any #target_ulong virtual address. + */ +typedef uint64_t vaddr; +#define VADDR_PRId PRId64 +#define VADDR_PRIu PRIu64 +#define VADDR_PRIo PRIo64 +#define VADDR_PRIx PRIx64 +#define VADDR_PRIX PRIX64 +#define VADDR_MAX UINT64_MAX + /* Using intptr_t ensures that qemu_*_page_mask is sign-extended even * when intptr_t is 32-bit and we are aligning a long long. */ diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 76ab3b851c8..3f2b681281c 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -22,6 +22,7 @@ =20 #include "hw/qdev-core.h" #include "disas/dis-asm.h" +#include "exec/cpu-common.h" #include "exec/hwaddr.h" #include "exec/memattrs.h" #include "qapi/qapi-types-run-state.h" @@ -35,18 +36,6 @@ typedef int (*WriteCoreDumpFunction)(const void *buf, size_t size, void *opaque); =20 -/** - * vaddr: - * Type wide enough to contain any #target_ulong virtual address. - */ -typedef uint64_t vaddr; -#define VADDR_PRId PRId64 -#define VADDR_PRIu PRIu64 -#define VADDR_PRIo PRIo64 -#define VADDR_PRIx PRIx64 -#define VADDR_PRIX PRIX64 -#define VADDR_MAX UINT64_MAX - /** * SECTION:cpu * @section_id: QEMU-cpu --=20 2.35.1 From nobody Sun Feb 8 05:08:15 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) client-ip=209.85.128.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1646571625; cv=none; d=zohomail.com; s=zohoarc; b=IwK60nkFkdolb9erqSpGzFkWlHY7LPJauBwlE52JlQWCqyY4P1hN+dl1fCIxkkxFonmRzMlW79rGBJlVQ4UkJL2FIzSqOg0Wfl0tzge7WLlGqo06HA9Z8nBeixLlz2a5cPZyvgz3tpC0vCTI6iAT215WMobu8AYmKktPI3lCw/M= ARC-Message-Signature: i=1; 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Sun, 06 Mar 2022 05:00:24 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Eduardo Habkost , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 04/33] exec: Make cpu_memory_rw_debug() target agnostic Date: Sun, 6 Mar 2022 13:59:31 +0100 Message-Id: <20220306130000.8104-5-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> References: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571627928100001 From: Philippe Mathieu-Daud=C3=A9 cpu_memory_rw_debug() is declared in "exec/cpu-all.h" which contains target-specific declarations. To be able to use it from target agnostic source, move the declaration to the generic "exec/cpu-common.h" header. Replace the target-specific 'target_ulong' type by 'vaddr' which better reflects the argument type, and is target agnostic. Suggested-by: Richard Henderson Reviewed-by: Paolo Bonzini Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220207075426.81934-5-f4bug@amsat.org> --- include/exec/cpu-all.h | 4 ---- include/exec/cpu-common.h | 4 ++++ cpu.c | 6 +++--- softmmu/cpus.c | 2 +- softmmu/physmem.c | 6 +++--- 5 files changed, 11 insertions(+), 11 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 84caf5c3d9f..c0f0fab28a1 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -433,10 +433,6 @@ int cpu_exec(CPUState *cpu); void tcg_exec_realizefn(CPUState *cpu, Error **errp); void tcg_exec_unrealizefn(CPUState *cpu); =20 -/* Returns: 0 on success, -1 on error */ -int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, - void *ptr, target_ulong len, bool is_write); - /** * cpu_set_cpustate_pointers(cpu) * @cpu: The cpu object diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index cd1d7328a1d..8031ebc680c 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -128,6 +128,10 @@ int ram_block_discard_range(RAMBlock *rb, uint64_t sta= rt, size_t length); =20 #endif =20 +/* Returns: 0 on success, -1 on error */ +int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, + void *ptr, size_t len, bool is_write); + /* vl.c */ extern int singlestep; =20 diff --git a/cpu.c b/cpu.c index 3ea38aea707..d5d4cbf8cb7 100644 --- a/cpu.c +++ b/cpu.c @@ -415,11 +415,11 @@ void cpu_abort(CPUState *cpu, const char *fmt, ...) =20 /* physical memory access (slow version, mainly for debug) */ #if defined(CONFIG_USER_ONLY) -int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, - void *ptr, target_ulong len, bool is_write) +int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, + void *ptr, size_t len, bool is_write) { int flags; - target_ulong l, page; + vaddr l, page; void * p; uint8_t *buf =3D ptr; =20 diff --git a/softmmu/cpus.c b/softmmu/cpus.c index 1681844b61d..3f8fae43ba6 100644 --- a/softmmu/cpus.c +++ b/softmmu/cpus.c @@ -33,7 +33,7 @@ #include "qapi/qmp/qerror.h" #include "exec/gdbstub.h" #include "sysemu/hw_accel.h" -#include "exec/exec-all.h" +#include "exec/cpu-common.h" #include "qemu/thread.h" #include "qemu/plugin.h" #include "sysemu/cpus.h" diff --git a/softmmu/physmem.c b/softmmu/physmem.c index a13289a594a..cf6b2b48995 100644 --- a/softmmu/physmem.c +++ b/softmmu/physmem.c @@ -3436,11 +3436,11 @@ address_space_write_cached_slow(MemoryRegionCache *= cache, hwaddr addr, #include "memory_ldst.c.inc" =20 /* virtual memory access for debug (includes writing to ROM) */ -int cpu_memory_rw_debug(CPUState *cpu, target_ulong addr, - void *ptr, target_ulong len, bool is_write) +int cpu_memory_rw_debug(CPUState *cpu, vaddr addr, + void *ptr, size_t len, bool is_write) { hwaddr phys_addr; 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Sun, 06 Mar 2022 05:00:30 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Eduardo Habkost , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 05/33] sysemu/memory_mapping: Become target-agnostic Date: Sun, 6 Mar 2022 13:59:32 +0100 Message-Id: <20220306130000.8104-6-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> References: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571633818100001 From: Philippe Mathieu-Daud=C3=A9 target_ulong is target-specific, while vaddr isn't. Remove the unnecessary "exec/cpu-defs.h" target-speficic header from "memory_mapping.h" and use the target-agnostic "hw/core/cpu.h" locally in memory_mapping.c. Remove "exec/memory.h" since MemoryRegion is forward-declared in "qemu/typedefs.h". Reviewed-by: Richard Henderson Reviewed-by: Paolo Bonzini Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220207075426.81934-6-f4bug@amsat.org> --- include/sysemu/memory_mapping.h | 5 ++--- softmmu/memory_mapping.c | 1 + 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/include/sysemu/memory_mapping.h b/include/sysemu/memory_mappin= g.h index 4b20f1a639e..3bbeb1bcb41 100644 --- a/include/sysemu/memory_mapping.h +++ b/include/sysemu/memory_mapping.h @@ -15,8 +15,7 @@ #define MEMORY_MAPPING_H =20 #include "qemu/queue.h" -#include "exec/cpu-defs.h" -#include "exec/memory.h" +#include "exec/cpu-common.h" =20 typedef struct GuestPhysBlock { /* visible to guest, reflects PCI hole, etc */ @@ -43,7 +42,7 @@ typedef struct GuestPhysBlockList { /* The physical and virtual address in the memory mapping are contiguous. = */ typedef struct MemoryMapping { hwaddr phys_addr; - target_ulong virt_addr; + vaddr virt_addr; ram_addr_t length; QTAILQ_ENTRY(MemoryMapping) next; } MemoryMapping; diff --git a/softmmu/memory_mapping.c b/softmmu/memory_mapping.c index a62eaa49ccb..8320165ea24 100644 --- a/softmmu/memory_mapping.c +++ b/softmmu/memory_mapping.c @@ -17,6 +17,7 @@ #include "sysemu/memory_mapping.h" #include "exec/memory.h" #include "exec/address-spaces.h" +#include "hw/core/cpu.h" =20 //#define DEBUG_GUEST_PHYS_REGION_ADD =20 --=20 2.35.1 From nobody Sun Feb 8 05:08:15 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.46 as permitted sender) client-ip=209.85.221.46; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f46.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.46 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1646571636; cv=none; d=zohomail.com; s=zohoarc; b=HKqnILggw7cNXOti6jvNWtFnCx+gj0cV8vEuTOifJpcCfUiQrTCv2DNXxoGeewx8a7GenjTsPkIhAvckrzO73Eu2PYLNsFJeZxz/AN77iDiRrvjRyoe6u1eylRd95i/Gcaeo0FliwyqYTzy6ZFm1+t4BCz7t9fnYMmsY+tvpKsA= ARC-Message-Signature: i=1; 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Sun, 06 Mar 2022 05:00:35 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Eduardo Habkost , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 06/33] sysemu/kvm: Make kvm_on_sigbus() / kvm_on_sigbus_vcpu() target agnostic Date: Sun, 6 Mar 2022 13:59:33 +0100 Message-Id: <20220306130000.8104-7-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> References: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571637993100001 From: Philippe Mathieu-Daud=C3=A9 kvm_on_sigbus() and kvm_on_sigbus_vcpu() prototypes don't have to be target specific. Remove this limitation to be able to build softmmu/cpus.c once for all targets. Reviewed-by: Richard Henderson Reviewed-by: Paolo Bonzini Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220207075426.81934-7-f4bug@amsat.org> --- include/sysemu/kvm.h | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h index 6eb39a088b2..a5bec96fb01 100644 --- a/include/sysemu/kvm.h +++ b/include/sysemu/kvm.h @@ -249,6 +249,9 @@ int kvm_has_intx_set_mask(void); bool kvm_arm_supports_user_irq(void); =20 =20 +int kvm_on_sigbus_vcpu(CPUState *cpu, int code, void *addr); +int kvm_on_sigbus(int code, void *addr); + #ifdef NEED_CPU_H #include "cpu.h" =20 @@ -261,9 +264,6 @@ int kvm_remove_breakpoint(CPUState *cpu, target_ulong a= ddr, void kvm_remove_all_breakpoints(CPUState *cpu); int kvm_update_guest_debug(CPUState *cpu, unsigned long reinject_trap); =20 -int kvm_on_sigbus_vcpu(CPUState *cpu, int code, void *addr); -int kvm_on_sigbus(int code, void *addr); - /* internal API */ =20 int kvm_ioctl(KVMState *s, int type, ...); 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Sun, 06 Mar 2022 05:00:40 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Eduardo Habkost , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 07/33] accel/kvm: Simplify user-mode #ifdef'ry Date: Sun, 6 Mar 2022 13:59:34 +0100 Message-Id: <20220306130000.8104-8-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> References: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571658722100001 From: Philippe Mathieu-Daud=C3=A9 Now than we only build this stub with system emulation, remove the user-mode #ifdef'ry. Reviewed-by: Richard Henderson Reviewed-by: Paolo Bonzini Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220207075426.81934-8-f4bug@amsat.org> --- accel/stubs/kvm-stub.c | 5 ----- 1 file changed, 5 deletions(-) diff --git a/accel/stubs/kvm-stub.c b/accel/stubs/kvm-stub.c index 5319573e003..7e0fb884b93 100644 --- a/accel/stubs/kvm-stub.c +++ b/accel/stubs/kvm-stub.c @@ -12,10 +12,7 @@ =20 #include "qemu/osdep.h" #include "sysemu/kvm.h" - -#ifndef CONFIG_USER_ONLY #include "hw/pci/msi.h" -#endif =20 KVMState *kvm_state; bool kvm_kernel_irqchip; @@ -80,7 +77,6 @@ int kvm_on_sigbus(int code, void *addr) return 1; } =20 -#ifndef CONFIG_USER_ONLY int kvm_irqchip_add_msi_route(KVMState *s, int vector, PCIDevice *dev) { return -ENOSYS; @@ -152,4 +148,3 @@ bool kvm_dirty_ring_enabled(void) { return false; } -#endif --=20 2.35.1 From nobody Sun Feb 8 05:08:15 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.41 as permitted sender) client-ip=209.85.128.41; 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Sun, 06 Mar 2022 05:00:45 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Eduardo Habkost , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 08/33] accel/hax: Introduce CONFIG_HAX_IS_POSSIBLE Date: Sun, 6 Mar 2022 13:59:35 +0100 Message-Id: <20220306130000.8104-9-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> References: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571647901100001 From: Philippe Mathieu-Daud=C3=A9 Mirror "sysemu/kvm.h" #ifdef'ry to define CONFIG_HAX_IS_POSSIBLE, expose hax_allowed to hax_enabled() macro. Suggested-by: Richard Henderson Reviewed-by: Paolo Bonzini Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220207075426.81934-9-f4bug@amsat.org> --- include/sysemu/hax.h | 18 ++++++++++++------ accel/stubs/hax-stub.c | 2 ++ target/i386/hax/hax-all.c | 7 +------ 3 files changed, 15 insertions(+), 12 deletions(-) diff --git a/include/sysemu/hax.h b/include/sysemu/hax.h index 247f0661d12..bf8f99a8246 100644 --- a/include/sysemu/hax.h +++ b/include/sysemu/hax.h @@ -25,17 +25,23 @@ int hax_sync_vcpus(void); =20 #ifdef NEED_CPU_H +# ifdef CONFIG_HAX +# define CONFIG_HAX_IS_POSSIBLE +# endif +#else /* !NEED_CPU_H */ +# define CONFIG_HAX_IS_POSSIBLE +#endif =20 -#ifdef CONFIG_HAX +#ifdef CONFIG_HAX_IS_POSSIBLE =20 -int hax_enabled(void); +extern bool hax_allowed; =20 -#else /* CONFIG_HAX */ +#define hax_enabled() (hax_allowed) =20 -#define hax_enabled() (0) +#else /* !CONFIG_HAX_IS_POSSIBLE */ =20 -#endif /* CONFIG_HAX */ +#define hax_enabled() (0) =20 -#endif /* NEED_CPU_H */ +#endif /* CONFIG_HAX_IS_POSSIBLE */ =20 #endif /* QEMU_HAX_H */ diff --git a/accel/stubs/hax-stub.c b/accel/stubs/hax-stub.c index 49077f88e3c..2fe31aaa9ab 100644 --- a/accel/stubs/hax-stub.c +++ b/accel/stubs/hax-stub.c @@ -16,6 +16,8 @@ #include "qemu/osdep.h" #include "sysemu/hax.h" =20 +bool hax_allowed; + int hax_sync_vcpus(void) { return 0; diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c index bf65ed6fa92..ccdcb6afabc 100644 --- a/target/i386/hax/hax-all.c +++ b/target/i386/hax/hax-all.c @@ -49,18 +49,13 @@ const uint32_t hax_cur_version =3D 0x4; /* API v4: unma= pping and MMIO moves */ /* Minimum HAX kernel version */ const uint32_t hax_min_version =3D 0x4; /* API v4: supports unmapping */ =20 -static bool hax_allowed; +bool hax_allowed; =20 struct hax_state hax_global; =20 static void hax_vcpu_sync_state(CPUArchState *env, int modified); static int hax_arch_get_registers(CPUArchState *env); =20 -int hax_enabled(void) -{ - return hax_allowed; -} - int valid_hax_tunnel_size(uint16_t size) { return size >=3D sizeof(struct hax_tunnel); --=20 2.35.1 From nobody Sun Feb 8 05:08:15 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.43 as permitted sender) client-ip=209.85.221.43; envelope-from=philippe.mathieu.daude@gmail.com; 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Sun, 06 Mar 2022 05:00:51 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Eduardo Habkost , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 09/33] softmmu/cpus: Code movement Date: Sun, 6 Mar 2022 13:59:36 +0100 Message-Id: <20220306130000.8104-10-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> References: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571654137100001 From: Philippe Mathieu-Daud=C3=A9 We want cpu_thread_is_idle() to use cpus_accel, so declare this variable earlier. Reviewed-by: Paolo Bonzini Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220207075426.81934-10-f4bug@amsat.org> --- softmmu/cpus.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-) diff --git a/softmmu/cpus.c b/softmmu/cpus.c index 3f8fae43ba6..ac6bec56038 100644 --- a/softmmu/cpus.c +++ b/softmmu/cpus.c @@ -67,6 +67,11 @@ =20 static QemuMutex qemu_global_mutex; =20 +/* + * The chosen accelerator is supposed to register this. + */ +static const AccelOpsClass *cpus_accel; + bool cpu_is_stopped(CPUState *cpu) { return cpu->stopped || !runstate_is_running(); @@ -122,11 +127,6 @@ void hw_error(const char *fmt, ...) abort(); } =20 -/* - * The chosen accelerator is supposed to register this. - */ -static const AccelOpsClass *cpus_accel; - void cpu_synchronize_all_states(void) { CPUState *cpu; --=20 2.35.1 From nobody Sun Feb 8 05:08:15 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.47 as permitted sender) client-ip=209.85.128.47; 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Sun, 06 Mar 2022 05:00:57 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Eduardo Habkost , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 10/33] accel: Introduce AccelOpsClass::cpu_thread_is_idle() Date: Sun, 6 Mar 2022 13:59:37 +0100 Message-Id: <20220306130000.8104-11-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> References: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571660016100003 From: Philippe Mathieu-Daud=C3=A9 Add cpu_thread_is_idle() to AccelOps, and implement it for the KVM / WHPX accelerators. Suggested-by: Richard Henderson Reviewed-by: Paolo Bonzini Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220207075426.81934-11-f4bug@amsat.org> --- include/sysemu/accel-ops.h | 1 + accel/kvm/kvm-accel-ops.c | 6 ++++++ softmmu/cpus.c | 6 ++++-- target/i386/whpx/whpx-accel-ops.c | 6 ++++++ 4 files changed, 17 insertions(+), 2 deletions(-) diff --git a/include/sysemu/accel-ops.h b/include/sysemu/accel-ops.h index 032f6979d76..50c72540c73 100644 --- a/include/sysemu/accel-ops.h +++ b/include/sysemu/accel-ops.h @@ -30,6 +30,7 @@ struct AccelOpsClass { =20 void (*create_vcpu_thread)(CPUState *cpu); /* MANDATORY NON-NULL */ void (*kick_vcpu_thread)(CPUState *cpu); + bool (*cpu_thread_is_idle)(CPUState *cpu); =20 void (*synchronize_post_reset)(CPUState *cpu); void (*synchronize_post_init)(CPUState *cpu); diff --git a/accel/kvm/kvm-accel-ops.c b/accel/kvm/kvm-accel-ops.c index 7516c67a3f5..95b7b080202 100644 --- a/accel/kvm/kvm-accel-ops.c +++ b/accel/kvm/kvm-accel-ops.c @@ -74,11 +74,17 @@ static void kvm_start_vcpu_thread(CPUState *cpu) cpu, QEMU_THREAD_JOINABLE); } =20 +static bool kvm_vcpu_thread_is_idle(CPUState *cpu) +{ + return !kvm_halt_in_kernel(); +} + static void kvm_accel_ops_class_init(ObjectClass *oc, void *data) { AccelOpsClass *ops =3D ACCEL_OPS_CLASS(oc); =20 ops->create_vcpu_thread =3D kvm_start_vcpu_thread; + ops->cpu_thread_is_idle =3D kvm_vcpu_thread_is_idle; ops->synchronize_post_reset =3D kvm_cpu_synchronize_post_reset; ops->synchronize_post_init =3D kvm_cpu_synchronize_post_init; ops->synchronize_state =3D kvm_cpu_synchronize_state; diff --git a/softmmu/cpus.c b/softmmu/cpus.c index ac6bec56038..b17033d3bce 100644 --- a/softmmu/cpus.c +++ b/softmmu/cpus.c @@ -90,10 +90,12 @@ bool cpu_thread_is_idle(CPUState *cpu) if (cpu_is_stopped(cpu)) { return true; } - if (!cpu->halted || cpu_has_work(cpu) || - kvm_halt_in_kernel() || whpx_apic_in_platform()) { + if (!cpu->halted || cpu_has_work(cpu)) { return false; } + if (cpus_accel->cpu_thread_is_idle) { + return cpus_accel->cpu_thread_is_idle(cpu); + } return true; } =20 diff --git a/target/i386/whpx/whpx-accel-ops.c b/target/i386/whpx/whpx-acce= l-ops.c index 6bc47c53098..1d30e4e2ed2 100644 --- a/target/i386/whpx/whpx-accel-ops.c +++ b/target/i386/whpx/whpx-accel-ops.c @@ -83,12 +83,18 @@ static void whpx_kick_vcpu_thread(CPUState *cpu) } } =20 +static bool whpx_vcpu_thread_is_idle(CPUState *cpu) +{ + return !whpx_apic_in_platform(); +} + static void whpx_accel_ops_class_init(ObjectClass *oc, void *data) { AccelOpsClass *ops =3D ACCEL_OPS_CLASS(oc); =20 ops->create_vcpu_thread =3D whpx_start_vcpu_thread; ops->kick_vcpu_thread =3D whpx_kick_vcpu_thread; + ops->cpu_thread_is_idle =3D whpx_vcpu_thread_is_idle; =20 ops->synchronize_post_reset =3D whpx_cpu_synchronize_post_reset; ops->synchronize_post_init =3D whpx_cpu_synchronize_post_init; --=20 2.35.1 From nobody Sun Feb 8 05:08:15 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) client-ip=209.85.128.52; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f52.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.52 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1646571663; cv=none; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571666180100001 From: Philippe Mathieu-Daud=C3=A9 Add cpus_are_resettable() to AccelOps, and implement it for the KVM accelerator. Suggested-by: Richard Henderson Reviewed-by: Paolo Bonzini Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220207075426.81934-12-f4bug@amsat.org> --- include/sysemu/accel-ops.h | 2 ++ include/sysemu/hw_accel.h | 5 ----- accel/kvm/kvm-accel-ops.c | 6 ++++++ softmmu/cpus.c | 5 ++++- 4 files changed, 12 insertions(+), 6 deletions(-) diff --git a/include/sysemu/accel-ops.h b/include/sysemu/accel-ops.h index 50c72540c73..6013c9444cc 100644 --- a/include/sysemu/accel-ops.h +++ b/include/sysemu/accel-ops.h @@ -28,6 +28,8 @@ struct AccelOpsClass { /* initialization function called when accel is chosen */ void (*ops_init)(AccelOpsClass *ops); =20 + bool (*cpus_are_resettable)(void); + void (*create_vcpu_thread)(CPUState *cpu); /* MANDATORY NON-NULL */ void (*kick_vcpu_thread)(CPUState *cpu); bool (*cpu_thread_is_idle)(CPUState *cpu); diff --git a/include/sysemu/hw_accel.h b/include/sysemu/hw_accel.h index 01b5ebf442a..22903a55f70 100644 --- a/include/sysemu/hw_accel.h +++ b/include/sysemu/hw_accel.h @@ -23,9 +23,4 @@ void cpu_synchronize_post_reset(CPUState *cpu); void cpu_synchronize_post_init(CPUState *cpu); void cpu_synchronize_pre_loadvm(CPUState *cpu); =20 -static inline bool cpu_check_are_resettable(void) -{ - return kvm_enabled() ? kvm_cpu_check_are_resettable() : true; -} - #endif /* QEMU_HW_ACCEL_H */ diff --git a/accel/kvm/kvm-accel-ops.c b/accel/kvm/kvm-accel-ops.c index 95b7b080202..c4244a23c65 100644 --- a/accel/kvm/kvm-accel-ops.c +++ b/accel/kvm/kvm-accel-ops.c @@ -79,12 +79,18 @@ static bool kvm_vcpu_thread_is_idle(CPUState *cpu) return !kvm_halt_in_kernel(); } =20 +static bool kvm_cpus_are_resettable(void) +{ + return !kvm_enabled() || kvm_cpu_check_are_resettable(); +} + static void kvm_accel_ops_class_init(ObjectClass *oc, void *data) { AccelOpsClass *ops =3D ACCEL_OPS_CLASS(oc); =20 ops->create_vcpu_thread =3D kvm_start_vcpu_thread; ops->cpu_thread_is_idle =3D kvm_vcpu_thread_is_idle; + ops->cpus_are_resettable =3D kvm_cpus_are_resettable; ops->synchronize_post_reset =3D kvm_cpu_synchronize_post_reset; ops->synchronize_post_init =3D kvm_cpu_synchronize_post_init; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571670071100001 From: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Paolo Bonzini Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220207075426.81934-13-f4bug@amsat.org> --- softmmu/globals.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/softmmu/globals.c b/softmmu/globals.c index 7d0fc811835..3ebd718e35d 100644 --- a/softmmu/globals.c +++ b/softmmu/globals.c @@ -25,8 +25,6 @@ #include "qemu/osdep.h" #include "exec/cpu-common.h" #include "hw/display/vga.h" -#include "hw/i386/pc.h" -#include "hw/i386/x86.h" #include "hw/loader.h" #include "hw/xen/xen.h" #include "net/net.h" --=20 2.35.1 From nobody Sun Feb 8 05:08:15 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) client-ip=209.85.221.45; envelope-from=philippe.mathieu.daude@gmail.com; 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Sun, 06 Mar 2022 05:01:11 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Eduardo Habkost , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 13/33] softmmu/physmem: Remove unnecessary include Date: Sun, 6 Mar 2022 13:59:40 +0100 Message-Id: <20220306130000.8104-14-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> References: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571674150100001 From: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Paolo Bonzini Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220207075426.81934-14-f4bug@amsat.org> --- softmmu/physmem.c | 1 - 1 file changed, 1 deletion(-) diff --git a/softmmu/physmem.c b/softmmu/physmem.c index cf6b2b48995..364d563ee42 100644 --- a/softmmu/physmem.c +++ b/softmmu/physmem.c @@ -61,7 +61,6 @@ =20 #include "exec/memory-internal.h" #include "exec/ram_addr.h" -#include "exec/log.h" =20 #include "qemu/pmem.h" =20 --=20 2.35.1 From nobody Sun Feb 8 05:08:15 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) client-ip=209.85.221.54; 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Sun, 06 Mar 2022 05:01:17 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Eduardo Habkost , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 14/33] softmmu/cpu-timers: Remove unused 'exec/exec-all.h' header Date: Sun, 6 Mar 2022 13:59:41 +0100 Message-Id: <20220306130000.8104-15-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> References: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571680185100001 From: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Reviewed-by: Paolo Bonzini Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220207075426.81934-16-f4bug@amsat.org> --- softmmu/cpu-timers.c | 1 - 1 file changed, 1 deletion(-) diff --git a/softmmu/cpu-timers.c b/softmmu/cpu-timers.c index 34ddfa02f1e..204d946a172 100644 --- a/softmmu/cpu-timers.c +++ b/softmmu/cpu-timers.c @@ -28,7 +28,6 @@ #include "migration/vmstate.h" #include "qapi/error.h" #include "qemu/error-report.h" -#include "exec/exec-all.h" #include "sysemu/cpus.h" #include "qemu/main-loop.h" #include "qemu/option.h" --=20 2.35.1 From nobody Sun Feb 8 05:08:15 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.47 as permitted sender) client-ip=209.85.128.47; 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Sun, 06 Mar 2022 05:01:23 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Eduardo Habkost , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 15/33] misc: Remove unnecessary "sysemu/cpu-timers.h" include Date: Sun, 6 Mar 2022 13:59:42 +0100 Message-Id: <20220306130000.8104-16-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> References: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571686267100001 From: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Paolo Bonzini Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220207075426.81934-17-f4bug@amsat.org> --- accel/qtest/qtest.c | 1 - target/alpha/translate.c | 1 - tests/unit/ptimer-test-stubs.c | 1 - 3 files changed, 3 deletions(-) diff --git a/accel/qtest/qtest.c b/accel/qtest/qtest.c index 7e6b8110d52..f6056ac8361 100644 --- a/accel/qtest/qtest.c +++ b/accel/qtest/qtest.c @@ -20,7 +20,6 @@ #include "qemu/accel.h" #include "sysemu/qtest.h" #include "sysemu/cpus.h" -#include "sysemu/cpu-timers.h" #include "qemu/guest-random.h" #include "qemu/main-loop.h" #include "hw/core/cpu.h" diff --git a/target/alpha/translate.c b/target/alpha/translate.c index ca78a0faed0..66768ab47ad 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -20,7 +20,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "sysemu/cpus.h" -#include "sysemu/cpu-timers.h" #include "disas/disas.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" diff --git a/tests/unit/ptimer-test-stubs.c b/tests/unit/ptimer-test-stubs.c index 2a3ef587991..f5e75a96b6d 100644 --- a/tests/unit/ptimer-test-stubs.c +++ b/tests/unit/ptimer-test-stubs.c @@ -12,7 +12,6 @@ #include "qemu/main-loop.h" #include "sysemu/replay.h" #include "migration/vmstate.h" -#include "sysemu/cpu-timers.h" =20 #include "ptimer-test.h" =20 --=20 2.35.1 From nobody Sun Feb 8 05:08:15 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.48 as permitted sender) client-ip=209.85.128.48; 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Sun, 06 Mar 2022 05:01:28 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Eduardo Habkost , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 16/33] misc: Add missing "sysemu/cpu-timers.h" include Date: Sun, 6 Mar 2022 13:59:43 +0100 Message-Id: <20220306130000.8104-17-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> References: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571690305100001 From: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Paolo Bonzini Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220207075426.81934-18-f4bug@amsat.org> --- include/exec/exec-all.h | 1 - accel/tcg/tcg-accel-ops-icount.c | 1 + accel/tcg/tcg-accel-ops-mttcg.c | 1 + accel/tcg/tcg-accel-ops-rr.c | 1 + accel/tcg/tcg-accel-ops.c | 1 + target/riscv/csr.c | 1 + 6 files changed, 5 insertions(+), 1 deletion(-) diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index 227e10ba560..edc8e5fa1ec 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -24,7 +24,6 @@ #ifdef CONFIG_TCG #include "exec/cpu_ldst.h" #endif -#include "sysemu/cpu-timers.h" =20 /* allow to see translation results - the slowdown should be negligible, s= o we leave it */ #define DEBUG_DISAS diff --git a/accel/tcg/tcg-accel-ops-icount.c b/accel/tcg/tcg-accel-ops-ico= unt.c index ea42d1d51b1..bdaf2c943b4 100644 --- a/accel/tcg/tcg-accel-ops-icount.c +++ b/accel/tcg/tcg-accel-ops-icount.c @@ -27,6 +27,7 @@ #include "qemu-common.h" #include "sysemu/tcg.h" #include "sysemu/replay.h" +#include "sysemu/cpu-timers.h" #include "qemu/main-loop.h" #include "qemu/guest-random.h" #include "exec/exec-all.h" diff --git a/accel/tcg/tcg-accel-ops-mttcg.c b/accel/tcg/tcg-accel-ops-mttc= g.c index 29632bd4c0a..dc421c8fd71 100644 --- a/accel/tcg/tcg-accel-ops-mttcg.c +++ b/accel/tcg/tcg-accel-ops-mttcg.c @@ -27,6 +27,7 @@ #include "qemu-common.h" #include "sysemu/tcg.h" #include "sysemu/replay.h" +#include "sysemu/cpu-timers.h" #include "qemu/main-loop.h" #include "qemu/notify.h" #include "qemu/guest-random.h" diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c index bf59f53dbc2..a805fb6bddc 100644 --- a/accel/tcg/tcg-accel-ops-rr.c +++ b/accel/tcg/tcg-accel-ops-rr.c @@ -27,6 +27,7 @@ #include "qemu-common.h" #include "sysemu/tcg.h" #include "sysemu/replay.h" +#include "sysemu/cpu-timers.h" #include "qemu/main-loop.h" #include "qemu/notify.h" #include "qemu/guest-random.h" diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 1a8e8390bd6..ea7dcad674c 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -29,6 +29,7 @@ #include "qemu-common.h" #include "sysemu/tcg.h" #include "sysemu/replay.h" +#include "sysemu/cpu-timers.h" #include "qemu/main-loop.h" #include "qemu/guest-random.h" #include "exec/exec-all.h" diff --git a/target/riscv/csr.c b/target/riscv/csr.c index aea82dff4af..0606cd0ea80 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -23,6 +23,7 @@ #include "cpu.h" #include "qemu/main-loop.h" #include "exec/exec-all.h" +#include "sysemu/cpu-timers.h" =20 /* CSR function table public API */ void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) --=20 2.35.1 From nobody Sun Feb 8 05:08:15 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.47 as permitted sender) client-ip=209.85.221.47; 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Sun, 06 Mar 2022 05:01:33 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Eduardo Habkost , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 17/33] exec/gdbstub: Make gdb_exit() / gdb_set_stop_cpu() target agnostic Date: Sun, 6 Mar 2022 13:59:44 +0100 Message-Id: <20220306130000.8104-18-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> References: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571697410100001 From: Philippe Mathieu-Daud=C3=A9 gdb_exit() and gdb_set_stop_cpu() prototypes don't have to be target specific. Remove this limitation to be able to build softmmu/cpus.c and softmmu/runstate.c once for all targets. Reviewed-by: Richard Henderson Reviewed-by: Paolo Bonzini Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220207075426.81934-19-f4bug@amsat.org> --- include/exec/gdbstub.h | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-) diff --git a/include/exec/gdbstub.h b/include/exec/gdbstub.h index a024a0350df..89edf94d286 100644 --- a/include/exec/gdbstub.h +++ b/include/exec/gdbstub.h @@ -45,17 +45,6 @@ void gdb_do_syscall(gdb_syscall_complete_cb cb, const ch= ar *fmt, ...); */ void gdb_do_syscallv(gdb_syscall_complete_cb cb, const char *fmt, va_list = va); int use_gdb_syscalls(void); -void gdb_set_stop_cpu(CPUState *cpu); - -/** - * gdb_exit: exit gdb session, reporting inferior status - * @code: exit code reported - * - * This closes the session and sends a final packet to GDB reporting - * the exit status of the program. It also cleans up any connections - * detritus before returning. - */ -void gdb_exit(int code); =20 #ifdef CONFIG_USER_ONLY /** @@ -165,7 +154,7 @@ static inline uint8_t * gdb_get_reg_ptr(GByteArray *buf= , int len) #define ldtul_p(addr) ldl_p(addr) #endif =20 -#endif +#endif /* NEED_CPU_H */ =20 /** * gdbserver_start: start the gdb server @@ -177,6 +166,18 @@ static inline uint8_t * gdb_get_reg_ptr(GByteArray *bu= f, int len) */ int gdbserver_start(const char *port_or_device); =20 +/** + * gdb_exit: exit gdb session, reporting inferior status + * @code: exit code reported + * + * This closes the session and sends a final packet to GDB reporting + * the exit status of the program. It also cleans up any connections + * detritus before returning. + */ +void gdb_exit(int code); + +void gdb_set_stop_cpu(CPUState *cpu); + /** * gdb_has_xml: * This is an ugly hack to cope with both new and old gdb. --=20 2.35.1 From nobody Sun Feb 8 05:08:15 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) client-ip=209.85.221.44; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f44.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1646571700; cv=none; d=zohomail.com; s=zohoarc; b=cP+W01kNIuX21GuVaEMRqTmhkoKUmZdIPE90hRwZpNZI0Zfj+rr9anUYfMPtNtxdAY/B4bKVmLIrs+tjn3qon+cdWX9J3nx+cp/msDDgxmoqYq4WHgKjNOnrAoffxqn78nGp+T6utn2UmdksGNOdfINS608rpkAqAFf9jD0GRkM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1646571700; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:MIME-Version:Message-ID:References:Subject:To; bh=ts4YmLK8kGBvQFnNbWDOwfqmzK4vYB4IrYwQhSsjG/8=; b=jc/RxN+J5PoEXDcvDjkVgknV7KOJjcidcQ1JKD6n2RLccbDFZZKgljhl70Oyy2m5/jT3V5yCZZOj1rA1GDLrQnktq6R1RZoI0CT9FTTH3NU5XfBGxgDvu9recOfC5ogr7zE7lOcC2mK3zB0OC5Dzy6v5IKDMnFGmSNV+3OgRUt4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=pass header.from= (p=none dis=none) Received: from mail-wr1-f44.google.com (mail-wr1-f44.google.com [209.85.221.44]) by mx.zohomail.com with SMTPS id 1646571700349568.3827454933189; Sun, 6 Mar 2022 05:01:40 -0800 (PST) Received: by mail-wr1-f44.google.com with SMTP id e24so6346112wrc.10 for ; Sun, 06 Mar 2022 05:01:39 -0800 (PST) Return-Path: Return-Path: Received: from nuc.lan ([185.126.107.38]) by smtp.gmail.com with ESMTPSA id p2-20020a1c7402000000b0038159076d30sm16971269wmc.22.2022.03.06.05.01.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 06 Mar 2022 05:01:37 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ts4YmLK8kGBvQFnNbWDOwfqmzK4vYB4IrYwQhSsjG/8=; b=aU5/3hK3RQ2Z8/2PIwBt8GBViKi32t+G2QWTX7TsavnCQPhgy6ann7vMl3i9p0EhoZ y2hgNi6eCtIAeDQPKDP93W5rh32fBGZG0TsGGKsZckv3aYJEue9LAPcT45QaAkL0KsNt +Qvz2ko5jQepz2u16VRPRSJdnNqW7PgIeFXezqoCVmbdzM/Kwpaso/VnagiPJb84R6PA YKNZ9EnGCCuMSTubI5hHe9gzDIjossNCDr0GV52c6p2vop8lhSotQVsuUcS4gQI+KvLC Ba8x3mnUecDw9H1rRdiNp2SM7WvRSyG7ksfMWkMEs8VFrYctVjhN03rf7HhUEFOOczU5 kggg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ts4YmLK8kGBvQFnNbWDOwfqmzK4vYB4IrYwQhSsjG/8=; b=5fYh8Mo+0571Il4tILyAq9BdT7sNdfcS+ataUb3uBptagg0pPOnSOiXeW3SRODuTA/ z958z/XiXFmf1e+vuANA3m1MzQ3r31r4TamlBxrUEo52Wbfh5ceydQxbOXyEx7z9XepB RmpNM3ff2miO2nrB0S1B2TC6QZTDmoqKcvkeb3Yru1eP10fO42qwyzXchk0TU2cSkr36 Wqh7QjYVMl/AY6qw7ZmrzH8UGRXN69VeW0DYx9HVY2SD08Z4xzmiQmnHcTjXFgg/6e3R qSZkP2vwbxaUCicXf60DMeghTVlZWW2JtRv9FRnmMU+eKaa5rreSTx9cdGsP0sRBSwgT 2siA== X-Gm-Message-State: AOAM533AK7LvuUSMDmxBccE27HeDpIfh5zHjI1R8ywaLPtyEdf6lRb6b g9rKISVmfsQsh8B5puWDXvw= X-Google-Smtp-Source: ABdhPJzJ4GdLoL9YldDUuZWIEibQfgkPZDWOr/yKCBGEpZklwp0Rpw44fACMtS+K5jeTfCx1R5334g== X-Received: by 2002:a05:6000:2cf:b0:1f0:47a0:a482 with SMTP id o15-20020a05600002cf00b001f047a0a482mr5228936wry.192.1646571698488; Sun, 06 Mar 2022 05:01:38 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Eduardo Habkost , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 18/33] exec/cpu: Make address_space_init/reloading_memory_map target agnostic Date: Sun, 6 Mar 2022 13:59:45 +0100 Message-Id: <20220306130000.8104-19-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> References: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571702348100001 From: Philippe Mathieu-Daud=C3=A9 cpu_address_space_init() and cpu_reloading_memory_map() are target-agnostic, but are declared in "exec/exec-all.h" which contains target-specific declarations. Any target-agnostic source including "exec/exec-all.h" becomes target-specific and we have to compile it N times for the N targets built. In order to avoid that, move the declarations to "exec/cpu-common.h" which only contains target-agnostic declarations. Reviewed-by: Paolo Bonzini Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220207075426.81934-20-f4bug@amsat.org> --- include/exec/cpu-common.h | 23 +++++++++++++++++++++++ include/exec/exec-all.h | 25 ------------------------- 2 files changed, 23 insertions(+), 25 deletions(-) diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h index 8031ebc680c..7f7b5943c7b 100644 --- a/include/exec/cpu-common.h +++ b/include/exec/cpu-common.h @@ -90,6 +90,28 @@ void qemu_ram_unset_migratable(RAMBlock *rb); size_t qemu_ram_pagesize(RAMBlock *block); size_t qemu_ram_pagesize_largest(void); =20 +/** + * cpu_address_space_init: + * @cpu: CPU to add this address space to + * @asidx: integer index of this address space + * @prefix: prefix to be used as name of address space + * @mr: the root memory region of address space + * + * Add the specified address space to the CPU's cpu_ases list. + * The address space added with @asidx 0 is the one used for the + * convenience pointer cpu->as. + * The target-specific code which registers ASes is responsible + * for defining what semantics address space 0, 1, 2, etc have. + * + * Before the first call to this function, the caller must set + * cpu->num_ases to the total number of address spaces it needs + * to support. + * + * Note that with KVM only one address space is supported. + */ +void cpu_address_space_init(CPUState *cpu, int asidx, + const char *prefix, MemoryRegion *mr); + void cpu_physical_memory_rw(hwaddr addr, void *buf, hwaddr len, bool is_write); static inline void cpu_physical_memory_read(hwaddr addr, @@ -102,6 +124,7 @@ static inline void cpu_physical_memory_write(hwaddr add= r, { cpu_physical_memory_rw(addr, (void *)buf, len, true); } +void cpu_reloading_memory_map(void); void *cpu_physical_memory_map(hwaddr addr, hwaddr *plen, bool is_write); diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index edc8e5fa1ec..d2cb0981f40 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -80,31 +80,6 @@ static inline bool cpu_loop_exit_requested(CPUState *cpu) return (int32_t)qatomic_read(&cpu_neg(cpu)->icount_decr.u32) < 0; } =20 -#if !defined(CONFIG_USER_ONLY) -void cpu_reloading_memory_map(void); -/** - * cpu_address_space_init: - * @cpu: CPU to add this address space to - * @asidx: integer index of this address space - * @prefix: prefix to be used as name of address space - * @mr: the root memory region of address space - * - * Add the specified address space to the CPU's cpu_ases list. - * The address space added with @asidx 0 is the one used for the - * convenience pointer cpu->as. - * The target-specific code which registers ASes is responsible - * for defining what semantics address space 0, 1, 2, etc have. - * - * Before the first call to this function, the caller must set - * cpu->num_ases to the total number of address spaces it needs - * to support. - * - * Note that with KVM only one address space is supported. - */ -void cpu_address_space_init(CPUState *cpu, int asidx, - const char *prefix, MemoryRegion *mr); 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Sun, 06 Mar 2022 05:01:43 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Eduardo Habkost , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 19/33] softmmu: Add qemu_init_arch_modules() Date: Sun, 6 Mar 2022 13:59:46 +0100 Message-Id: <20220306130000.8104-20-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> References: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571706348100001 From: Philippe Mathieu-Daud=C3=A9 module_allow_arch() is the single target-specific call in the whole vl.c file. Move the module initialization out to arch_init.c, that way we'll be able to build vl.o once for all targets (the next commit). Reviewed-by: Paolo Bonzini Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220207075426.81934-21-f4bug@amsat.org> --- include/sysemu/arch_init.h | 2 ++ softmmu/arch_init.c | 9 +++++++++ softmmu/vl.c | 5 +---- 3 files changed, 12 insertions(+), 4 deletions(-) diff --git a/include/sysemu/arch_init.h b/include/sysemu/arch_init.h index 70c579560ad..79c2591425f 100644 --- a/include/sysemu/arch_init.h +++ b/include/sysemu/arch_init.h @@ -28,4 +28,6 @@ enum { =20 extern const uint32_t arch_type; =20 +void qemu_init_arch_modules(void); + #endif diff --git a/softmmu/arch_init.c b/softmmu/arch_init.c index 8919405c7b2..79716f959ba 100644 --- a/softmmu/arch_init.c +++ b/softmmu/arch_init.c @@ -22,6 +22,7 @@ * THE SOFTWARE. */ #include "qemu/osdep.h" +#include "qemu/module.h" #include "sysemu/arch_init.h" =20 #ifdef TARGET_SPARC @@ -39,3 +40,11 @@ int graphic_depth =3D 32; #endif =20 const uint32_t arch_type =3D QEMU_ARCH; + +void qemu_init_arch_modules(void) +{ +#ifdef CONFIG_MODULES + module_init_info(qemu_modinfo); + module_allow_arch(TARGET_NAME); +#endif +} diff --git a/softmmu/vl.c b/softmmu/vl.c index 1fe028800fd..0b81f615354 100644 --- a/softmmu/vl.c +++ b/softmmu/vl.c @@ -2815,10 +2815,7 @@ void qemu_init(int argc, char **argv, char **envp) error_init(argv[0]); qemu_init_exec_dir(argv[0]); =20 -#ifdef CONFIG_MODULES - module_init_info(qemu_modinfo); - module_allow_arch(TARGET_NAME); -#endif + qemu_init_arch_modules(); =20 qemu_init_subsystems(); =20 --=20 2.35.1 From nobody Sun Feb 8 05:08:15 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) client-ip=209.85.221.42; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f42.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.42 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571710402100001 From: Philippe Mathieu-Daud=C3=A9 Various softmmu objects aren't target specific. Move them to the generic softmmu source set. For our 31 softmmu targets, this is in total 330 objects less to build! Reviewed-by: Richard Henderson Reviewed-by: Paolo Bonzini Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220207075426.81934-22-f4bug@amsat.org> --- softmmu/meson.build | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/softmmu/meson.build b/softmmu/meson.build index 39f766ce7c1..8138248661a 100644 --- a/softmmu/meson.build +++ b/softmmu/meson.build @@ -1,20 +1,9 @@ specific_ss.add(when: 'CONFIG_SOFTMMU', if_true: [files( 'arch_init.c', - 'balloon.c', - 'cpus.c', - 'cpu-throttle.c', - 'datadir.c', - 'globals.c', - 'physmem.c', 'ioport.c', - 'rtc.c', - 'runstate.c', 'memory.c', - 'memory_mapping.c', + 'physmem.c', 'qtest.c', - 'vl.c', - 'cpu-timers.c', - 'runstate-action.c', )]) =20 specific_ss.add(when: ['CONFIG_SOFTMMU', 'CONFIG_TCG'], if_true: [files( @@ -22,9 +11,20 @@ )]) =20 softmmu_ss.add(files( + 'balloon.c', 'bootdevice.c', + 'cpus.c', + 'cpu-throttle.c', + 'cpu-timers.c', + 'datadir.c', 'dma-helpers.c', + 'globals.c', + 'memory_mapping.c', 'qdev-monitor.c', + 'rtc.c', + 'runstate-action.c', + 'runstate.c', + 'vl.c', ), sdl, libpmem, libdaxctl) =20 if have_tpm --=20 2.35.1 From nobody Sun Feb 8 05:08:15 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) client-ip=209.85.221.51; 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Sun, 06 Mar 2022 05:01:53 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Eduardo Habkost , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 21/33] meson: Display libfdt as disabled when system emulation is disabled Date: Sun, 6 Mar 2022 13:59:48 +0100 Message-Id: <20220306130000.8104-22-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> References: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571716437100001 From: Philippe Mathieu-Daud=C3=A9 When configuring QEMU with --disable-system, meson keeps showing libfdt as "auto". Mark it as disabled instead. Acked-by: Paolo Bonzini Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220214183144.27402-2-f4bug@amsat.org> --- meson.build | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/meson.build b/meson.build index 038502714ab..746ce478e03 100644 --- a/meson.build +++ b/meson.build @@ -2432,8 +2432,8 @@ endif =20 fdt =3D not_found -fdt_opt =3D get_option('fdt') if have_system + fdt_opt =3D get_option('fdt') if fdt_opt in ['enabled', 'auto', 'system'] have_internal =3D fs.exists(meson.current_source_dir() / 'dtc/libfdt/M= akefile.libfdt') fdt =3D cc.find_library('fdt', kwargs: static_kwargs, @@ -2476,6 +2476,8 @@ fdt =3D declare_dependency(link_with: libfdt, include_directories: fdt_inc) endif +else + fdt_opt =3D 'disabled' endif if not fdt.found() and fdt_required.length() > 0 error('fdt not available but required by targets ' + ', '.join(fdt_requi= red)) --=20 2.35.1 From nobody Sun Feb 8 05:08:15 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.47 as permitted sender) client-ip=209.85.128.47; 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Sun, 06 Mar 2022 05:01:58 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Eduardo Habkost , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 22/33] exec/cpu_ldst: Include 'cpu.h' to get target_ulong definition Date: Sun, 6 Mar 2022 13:59:49 +0100 Message-Id: <20220306130000.8104-23-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> References: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571720450100001 From: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220214183144.27402-5-f4bug@amsat.org> --- include/exec/cpu_ldst.h | 1 + 1 file changed, 1 insertion(+) diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index da987fe8ad1..6adacf89280 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -64,6 +64,7 @@ =20 #include "exec/memopidx.h" #include "qemu/int128.h" +#include "cpu.h" =20 #if defined(CONFIG_USER_ONLY) /* sparc32plus has 64bit long but 32bit space address --=20 2.35.1 From nobody Sun Feb 8 05:08:15 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.49 as permitted sender) client-ip=209.85.221.49; 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Sun, 06 Mar 2022 05:02:03 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Eduardo Habkost , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 23/33] cpu: Add missing 'exec/exec-all.h' and 'qemu/accel.h' headers Date: Sun, 6 Mar 2022 13:59:50 +0100 Message-Id: <20220306130000.8104-24-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> References: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571726487100001 From: Philippe Mathieu-Daud=C3=A9 cpu.c requires "exec/exec-all.h" to call tlb_flush() and "qemu/accel.h" to call accel_cpu_realizefn(). Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220214183144.27402-6-f4bug@amsat.org> --- cpu.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/cpu.c b/cpu.c index d5d4cbf8cb7..d5648861490 100644 --- a/cpu.c +++ b/cpu.c @@ -35,10 +35,12 @@ #include "sysemu/tcg.h" #include "sysemu/kvm.h" #include "sysemu/replay.h" +#include "exec/exec-all.h" #include "exec/translate-all.h" #include "exec/log.h" #include "hw/core/accel-cpu.h" #include "trace/trace-root.h" +#include "qemu/accel.h" =20 uintptr_t qemu_host_page_size; intptr_t qemu_host_page_mask; --=20 2.35.1 From nobody Sun Feb 8 05:08:15 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) client-ip=209.85.221.45; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f45.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.45 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571730632100001 From: Philippe Mathieu-Daud=C3=A9 excp_helper.c requires "exec/exec-all.h" for tlb_set_page_with_attrs() and misc_helper.c for tlb_flush(). Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220214183144.27402-8-f4bug@amsat.org> --- target/i386/tcg/sysemu/excp_helper.c | 1 + target/i386/tcg/sysemu/misc_helper.c | 1 + 2 files changed, 2 insertions(+) diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/= excp_helper.c index 5ba739fbed9..5627772e7c3 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -19,6 +19,7 @@ =20 #include "qemu/osdep.h" #include "cpu.h" +#include "exec/exec-all.h" #include "tcg/helper-tcg.h" =20 int get_pg_mode(CPUX86State *env) diff --git a/target/i386/tcg/sysemu/misc_helper.c b/target/i386/tcg/sysemu/= misc_helper.c index 9ccaa054c4c..3715c1e2625 100644 --- a/target/i386/tcg/sysemu/misc_helper.c +++ b/target/i386/tcg/sysemu/misc_helper.c @@ -23,6 +23,7 @@ #include "exec/helper-proto.h" #include "exec/cpu_ldst.h" #include "exec/address-spaces.h" +#include "exec/exec-all.h" #include "tcg/helper-tcg.h" =20 void helper_outb(CPUX86State *env, uint32_t port, uint32_t data) --=20 2.35.1 From nobody Sun Feb 8 05:08:15 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.44 as permitted sender) client-ip=209.85.221.44; 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Sun, 06 Mar 2022 05:02:13 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Eduardo Habkost , Richard Henderson , Taylor Simpson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 25/33] Hexagon (target/hexagon) convert to OBJECT_DECLARE_TYPE Date: Sun, 6 Mar 2022 13:59:52 +0100 Message-Id: <20220306130000.8104-26-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> References: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571736549100001 From: Taylor Simpson Suggested-by: Richard Henderson Signed-off-by: Taylor Simpson Reviewed-by: Richard Henderson Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220211033034.21107-1-tsimpson@quicinc.com> [PMD: Add missing "qom/object.h" include] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- target/hexagon/cpu.h | 10 +++------- 1 file changed, 3 insertions(+), 7 deletions(-) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 58a0d3870bb..096aa2deb6c 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -1,5 +1,5 @@ /* - * Copyright(c) 2019-2021 Qualcomm Innovation Center, Inc. All Rights Res= erved. + * Copyright(c) 2019-2022 Qualcomm Innovation Center, Inc. All Rights Res= erved. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -26,6 +26,7 @@ typedef struct CPUHexagonState CPUHexagonState; #include "exec/cpu-defs.h" #include "hex_regs.h" #include "mmvec/mmvec.h" +#include "qom/object.h" =20 #define NUM_PREGS 4 #define TOTAL_PER_THREAD_REGS 64 @@ -131,12 +132,7 @@ struct CPUHexagonState { VTCMStoreLog vtcm_log; }; =20 -#define HEXAGON_CPU_CLASS(klass) \ - OBJECT_CLASS_CHECK(HexagonCPUClass, (klass), TYPE_HEXAGON_CPU) -#define HEXAGON_CPU(obj) \ - OBJECT_CHECK(HexagonCPU, (obj), TYPE_HEXAGON_CPU) -#define HEXAGON_CPU_GET_CLASS(obj) \ - OBJECT_GET_CLASS(HexagonCPUClass, (obj), TYPE_HEXAGON_CPU) +OBJECT_DECLARE_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU) =20 typedef struct HexagonCPUClass { /*< private >*/ --=20 2.35.1 From nobody Sun Feb 8 05:08:15 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.51 as permitted sender) client-ip=209.85.128.51; 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Sun, 06 Mar 2022 05:02:18 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Eduardo Habkost , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 26/33] target: Include missing 'cpu.h' Date: Sun, 6 Mar 2022 13:59:53 +0100 Message-Id: <20220306130000.8104-27-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> References: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571742575100001 From: Philippe Mathieu-Daud=C3=A9 These target-specific files use the target-specific CPU state but lack to include "cpu.h"; i.e.: ../target/riscv/pmp.h:61:23: error: unknown type name 'CPURISCVState' void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, ^ ../target/nios2/mmu.h:43:18: error: unknown type name 'CPUNios2State' void mmu_flip_um(CPUNios2State *env, unsigned int um); ^ ../target/microblaze/mmu.h:88:19: error: unknown type name 'CPUMBState'= ; did you mean 'CPUState'? uint32_t mmu_read(CPUMBState *env, bool ea, uint32_t rn); ^~~~~~~~~~ CPUState Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220214183144.27402-10-f4bug@amsat.org> --- target/microblaze/mmu.h | 2 ++ target/mips/internal.h | 1 + target/nios2/mmu.h | 2 ++ target/riscv/pmp.h | 2 ++ 4 files changed, 7 insertions(+) diff --git a/target/microblaze/mmu.h b/target/microblaze/mmu.h index b6b4b9ad603..1068bd2d52b 100644 --- a/target/microblaze/mmu.h +++ b/target/microblaze/mmu.h @@ -20,6 +20,8 @@ #ifndef TARGET_MICROBLAZE_MMU_H #define TARGET_MICROBLAZE_MMU_H =20 +#include "cpu.h" + #define MMU_R_PID 0 #define MMU_R_ZPR 1 #define MMU_R_TLBX 2 diff --git a/target/mips/internal.h b/target/mips/internal.h index daddb05fd43..f705d6bfa61 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -12,6 +12,7 @@ #ifdef CONFIG_TCG #include "tcg/tcg-internal.h" #endif +#include "cpu.h" =20 /* * MMU types, the first four entries have the same layout as the diff --git a/target/nios2/mmu.h b/target/nios2/mmu.h index b7785b46c01..5b085900fbf 100644 --- a/target/nios2/mmu.h +++ b/target/nios2/mmu.h @@ -21,6 +21,8 @@ #ifndef NIOS2_MMU_H #define NIOS2_MMU_H =20 +#include "cpu.h" + typedef struct Nios2TLBEntry { target_ulong tag; target_ulong data; diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h index a9a0b363a77..fcb6b7c4677 100644 --- a/target/riscv/pmp.h +++ b/target/riscv/pmp.h @@ -22,6 +22,8 @@ #ifndef RISCV_PMP_H #define RISCV_PMP_H =20 +#include "cpu.h" + typedef enum { PMP_READ =3D 1 << 0, PMP_WRITE =3D 1 << 1, --=20 2.35.1 From nobody Sun Feb 8 05:08:15 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) client-ip=209.85.221.53; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f53.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; t=1646571745; cv=none; d=zohomail.com; s=zohoarc; b=ezjUmChRdvnJ3WfecOkijVGxIQ3/VQNeTQS1wpqlOcjYDezm+qAj1eYtwBEvmsL3h0ruwIJ4/w0/bOA7Ej7otU49uVS6NnDGEek6YewI2Jq44K8fO7VL+VIsV5fWhsicYhhvNTg/IP8YjE2uv1UmrUefWzsa0KN6Xas8jzkuD4U= ARC-Message-Signature: i=1; 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Sun, 06 Mar 2022 05:02:23 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Eduardo Habkost , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Damien Hedde Subject: [PULL 27/33] target/hexagon: Add missing 'hw/core/cpu.h' include Date: Sun, 6 Mar 2022 13:59:54 +0100 Message-Id: <20220306130000.8104-28-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> References: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571746726100001 From: Philippe Mathieu-Daud=C3=A9 HexagonCPU field parent_class is of type CPUClass, which is declared in "hw/core/cpu.h". Reviewed-by: Damien Hedde Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220214183144.27402-11-f4bug@amsat.org> --- target/hexagon/cpu.h | 1 + 1 file changed, 1 insertion(+) diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 096aa2deb6c..76cd1d50219 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -27,6 +27,7 @@ typedef struct CPUHexagonState CPUHexagonState; #include "hex_regs.h" #include "mmvec/mmvec.h" #include "qom/object.h" +#include "hw/core/cpu.h" =20 #define NUM_PREGS 4 #define TOTAL_PER_THREAD_REGS 64 --=20 2.35.1 From nobody Sun Feb 8 05:08:15 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) client-ip=209.85.221.54; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wr1-f54.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.221.54 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571752621100001 From: Philippe Mathieu-Daud=C3=A9 The CPU / CPU state are forward declared. $ git grep -E 'struct [A-Za-z]+CPU\ \*' target/arm/hvf_arm.h:16:void hvf_arm_set_cpu_features_from_host(struct AR= MCPU *cpu); target/openrisc/cpu.h:234: int (*cpu_openrisc_map_address_code)(struct= OpenRISCCPU *cpu, target/openrisc/cpu.h:238: int (*cpu_openrisc_map_address_data)(struct= OpenRISCCPU *cpu, $ git grep -E 'struct CPU[A-Za-z]+State\ \*' target/mips/internal.h:137: int (*map_address)(struct CPUMIPSState *en= v, hwaddr *physical, int *prot, target/mips/internal.h:139: void (*helper_tlbwi)(struct CPUMIPSState *= env); target/mips/internal.h:140: void (*helper_tlbwr)(struct CPUMIPSState *= env); target/mips/internal.h:141: void (*helper_tlbp)(struct CPUMIPSState *e= nv); target/mips/internal.h:142: void (*helper_tlbr)(struct CPUMIPSState *e= nv); target/mips/internal.h:143: void (*helper_tlbinv)(struct CPUMIPSState = *env); target/mips/internal.h:144: void (*helper_tlbinvf)(struct CPUMIPSState= *env); target/xtensa/cpu.h:347: struct CPUXtensaState *env; Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220214183144.27402-12-f4bug@amsat.org> --- target/arm/hvf_arm.h | 2 +- target/mips/internal.h | 14 +++++++------- target/openrisc/cpu.h | 4 ++-- target/xtensa/cpu.h | 2 +- target/i386/nvmm/nvmm-all.c | 14 +++++++------- target/i386/whpx/whpx-all.c | 18 +++++++++--------- 6 files changed, 27 insertions(+), 27 deletions(-) diff --git a/target/arm/hvf_arm.h b/target/arm/hvf_arm.h index ea238cff83f..9a9d1a0bf59 100644 --- a/target/arm/hvf_arm.h +++ b/target/arm/hvf_arm.h @@ -13,6 +13,6 @@ =20 #include "cpu.h" =20 -void hvf_arm_set_cpu_features_from_host(struct ARMCPU *cpu); +void hvf_arm_set_cpu_features_from_host(ARMCPU *cpu); =20 #endif diff --git a/target/mips/internal.h b/target/mips/internal.h index f705d6bfa61..ac6e03e2f25 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -134,14 +134,14 @@ struct r4k_tlb_t { struct CPUMIPSTLBContext { uint32_t nb_tlb; uint32_t tlb_in_use; - int (*map_address)(struct CPUMIPSState *env, hwaddr *physical, int *pr= ot, + int (*map_address)(CPUMIPSState *env, hwaddr *physical, int *prot, target_ulong address, MMUAccessType access_type); - void (*helper_tlbwi)(struct CPUMIPSState *env); - void (*helper_tlbwr)(struct CPUMIPSState *env); - void (*helper_tlbp)(struct CPUMIPSState *env); - void (*helper_tlbr)(struct CPUMIPSState *env); - void (*helper_tlbinv)(struct CPUMIPSState *env); - void (*helper_tlbinvf)(struct CPUMIPSState *env); + void (*helper_tlbwi)(CPUMIPSState *env); + void (*helper_tlbwr)(CPUMIPSState *env); + void (*helper_tlbp)(CPUMIPSState *env); + void (*helper_tlbr)(CPUMIPSState *env); + void (*helper_tlbinv)(CPUMIPSState *env); + void (*helper_tlbinvf)(CPUMIPSState *env); union { struct { r4k_tlb_t tlb[MIPS_TLB_MAX]; diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index ee069b080c9..5711591520d 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -231,11 +231,11 @@ typedef struct CPUOpenRISCTLBContext { OpenRISCTLBEntry itlb[TLB_SIZE]; OpenRISCTLBEntry dtlb[TLB_SIZE]; =20 - int (*cpu_openrisc_map_address_code)(struct OpenRISCCPU *cpu, + int (*cpu_openrisc_map_address_code)(OpenRISCCPU *cpu, hwaddr *physical, int *prot, target_ulong address, int rw); - int (*cpu_openrisc_map_address_data)(struct OpenRISCCPU *cpu, + int (*cpu_openrisc_map_address_data)(OpenRISCCPU *cpu, hwaddr *physical, int *prot, target_ulong address, int rw); diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 02143f2f776..f2165b17e2d 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -344,7 +344,7 @@ typedef struct XtensaGdbRegmap { } XtensaGdbRegmap; =20 typedef struct XtensaCcompareTimer { - struct CPUXtensaState *env; + CPUXtensaState *env; QEMUTimer *timer; } XtensaCcompareTimer; =20 diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c index 9af261eea32..e159dd2b939 100644 --- a/target/i386/nvmm/nvmm-all.c +++ b/target/i386/nvmm/nvmm-all.c @@ -85,7 +85,7 @@ nvmm_set_segment(struct nvmm_x64_state_seg *nseg, const S= egmentCache *qseg) static void nvmm_set_registers(CPUState *cpu) { - struct CPUX86State *env =3D (CPUArchState *)cpu->env_ptr; + CPUX86State *env =3D (CPUArchState *)cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; @@ -222,7 +222,7 @@ nvmm_get_segment(SegmentCache *qseg, const struct nvmm_= x64_state_seg *nseg) static void nvmm_get_registers(CPUState *cpu) { - struct CPUX86State *env =3D (CPUArchState *)cpu->env_ptr; + CPUX86State *env =3D (CPUArchState *)cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; @@ -347,7 +347,7 @@ nvmm_get_registers(CPUState *cpu) static bool nvmm_can_take_int(CPUState *cpu) { - struct CPUX86State *env =3D (CPUArchState *)cpu->env_ptr; + CPUX86State *env =3D (CPUArchState *)cpu->env_ptr; struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; struct nvmm_machine *mach =3D get_nvmm_mach(); @@ -394,7 +394,7 @@ nvmm_can_take_nmi(CPUState *cpu) static void nvmm_vcpu_pre_run(CPUState *cpu) { - struct CPUX86State *env =3D (CPUArchState *)cpu->env_ptr; + CPUX86State *env =3D (CPUArchState *)cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; @@ -480,7 +480,7 @@ static void nvmm_vcpu_post_run(CPUState *cpu, struct nvmm_vcpu_exit *exit) { struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); - struct CPUX86State *env =3D (CPUArchState *)cpu->env_ptr; + CPUX86State *env =3D (CPUArchState *)cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); uint64_t tpr; =20 @@ -652,7 +652,7 @@ static int nvmm_handle_halted(struct nvmm_machine *mach, CPUState *cpu, struct nvmm_vcpu_exit *exit) { - struct CPUX86State *env =3D (CPUArchState *)cpu->env_ptr; + CPUX86State *env =3D (CPUArchState *)cpu->env_ptr; int ret =3D 0; =20 qemu_mutex_lock_iothread(); @@ -685,7 +685,7 @@ nvmm_inject_ud(struct nvmm_machine *mach, struct nvmm_v= cpu *vcpu) static int nvmm_vcpu_loop(CPUState *cpu) { - struct CPUX86State *env =3D (CPUArchState *)cpu->env_ptr; + CPUX86State *env =3D (CPUArchState *)cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index ef896da0a21..a8222461440 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -221,7 +221,7 @@ static SegmentCache whpx_seg_h2q(const WHV_X64_SEGMENT_= REGISTER *hs) =20 static int whpx_set_tsc(CPUState *cpu) { - struct CPUX86State *env =3D (CPUArchState *)(cpu->env_ptr); + CPUX86State *env =3D (CPUArchState *)(cpu->env_ptr); WHV_REGISTER_NAME tsc_reg =3D WHvX64RegisterTsc; WHV_REGISTER_VALUE tsc_val; HRESULT hr; @@ -260,7 +260,7 @@ static void whpx_set_registers(CPUState *cpu, int level) { struct whpx_state *whpx =3D &whpx_global; struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); - struct CPUX86State *env =3D (CPUArchState *)(cpu->env_ptr); + CPUX86State *env =3D (CPUArchState *)(cpu->env_ptr); X86CPU *x86_cpu =3D X86_CPU(cpu); struct whpx_register_set vcxt; HRESULT hr; @@ -428,7 +428,7 @@ static void whpx_set_registers(CPUState *cpu, int level) =20 static int whpx_get_tsc(CPUState *cpu) { - struct CPUX86State *env =3D (CPUArchState *)(cpu->env_ptr); + CPUX86State *env =3D (CPUArchState *)(cpu->env_ptr); WHV_REGISTER_NAME tsc_reg =3D WHvX64RegisterTsc; WHV_REGISTER_VALUE tsc_val; HRESULT hr; @@ -449,7 +449,7 @@ static void whpx_get_registers(CPUState *cpu) { struct whpx_state *whpx =3D &whpx_global; struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); - struct CPUX86State *env =3D (CPUArchState *)(cpu->env_ptr); + CPUX86State *env =3D (CPUArchState *)(cpu->env_ptr); X86CPU *x86_cpu =3D X86_CPU(cpu); struct whpx_register_set vcxt; uint64_t tpr, apic_base; @@ -760,7 +760,7 @@ static int whpx_handle_portio(CPUState *cpu, =20 static int whpx_handle_halt(CPUState *cpu) { - struct CPUX86State *env =3D (CPUArchState *)(cpu->env_ptr); + CPUX86State *env =3D (CPUArchState *)(cpu->env_ptr); int ret =3D 0; =20 qemu_mutex_lock_iothread(); @@ -781,7 +781,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) HRESULT hr; struct whpx_state *whpx =3D &whpx_global; struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); - struct CPUX86State *env =3D (CPUArchState *)(cpu->env_ptr); + CPUX86State *env =3D (CPUArchState *)(cpu->env_ptr); X86CPU *x86_cpu =3D X86_CPU(cpu); int irq; uint8_t tpr; @@ -903,7 +903,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) static void whpx_vcpu_post_run(CPUState *cpu) { struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); - struct CPUX86State *env =3D (CPUArchState *)(cpu->env_ptr); + CPUX86State *env =3D (CPUArchState *)(cpu->env_ptr); X86CPU *x86_cpu =3D X86_CPU(cpu); =20 env->eflags =3D vcpu->exit_ctx.VpContext.Rflags; @@ -927,7 +927,7 @@ static void whpx_vcpu_post_run(CPUState *cpu) =20 static void whpx_vcpu_process_async_events(CPUState *cpu) { - struct CPUX86State *env =3D (CPUArchState *)(cpu->env_ptr); + CPUX86State *env =3D (CPUArchState *)(cpu->env_ptr); X86CPU *x86_cpu =3D X86_CPU(cpu); struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); =20 @@ -1333,7 +1333,7 @@ int whpx_init_vcpu(CPUState *cpu) struct whpx_state *whpx =3D &whpx_global; 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Sun, 06 Mar 2022 05:02:34 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Eduardo Habkost , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 29/33] target: Use CPUArchState as interface to target-specific CPU state Date: Sun, 6 Mar 2022 13:59:56 +0100 Message-Id: <20220306130000.8104-30-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> References: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571756767100001 From: Philippe Mathieu-Daud=C3=A9 While CPUState is our interface with generic code, CPUArchState is our interface with target-specific code. Use CPUArchState as an abstract type, defined by each target. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220214183144.27402-13-f4bug@amsat.org> --- include/exec/poison.h | 2 -- include/hw/core/cpu.h | 2 +- include/qemu/typedefs.h | 1 + target/alpha/cpu.h | 7 ++----- target/arm/cpu.h | 3 +-- target/avr/cpu.h | 7 ++----- target/cris/cpu.h | 3 +-- target/hexagon/cpu.h | 8 ++------ target/hppa/cpu.h | 8 ++------ target/i386/cpu.h | 3 +-- target/m68k/cpu.h | 3 +-- target/microblaze/cpu.h | 5 ++--- target/mips/cpu.h | 6 ++---- target/nios2/cpu.h | 4 ++-- target/openrisc/cpu.h | 3 +-- target/ppc/cpu-qom.h | 2 +- target/ppc/cpu.h | 3 +-- target/riscv/cpu.h | 5 ++--- target/rx/cpu-qom.h | 2 -- target/rx/cpu.h | 2 +- target/s390x/cpu-qom.h | 4 ++-- target/s390x/cpu.h | 3 +-- target/sh4/cpu.h | 3 +-- target/sparc/cpu.h | 5 ++--- target/tricore/cpu.h | 6 ++---- target/xtensa/cpu.h | 7 +++---- 26 files changed, 37 insertions(+), 70 deletions(-) diff --git a/include/exec/poison.h b/include/exec/poison.h index 7ad4ad18e8e..7c5c02f03f0 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -51,8 +51,6 @@ #pragma GCC poison TARGET_PAGE_BITS #pragma GCC poison TARGET_PAGE_ALIGN =20 -#pragma GCC poison CPUArchState - #pragma GCC poison CPU_INTERRUPT_HARD #pragma GCC poison CPU_INTERRUPT_EXITTB #pragma GCC poison CPU_INTERRUPT_HALT diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 3f2b681281c..c9d41e4ece5 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -340,7 +340,7 @@ struct CPUState { AddressSpace *as; MemoryRegion *memory; =20 - void *env_ptr; /* CPUArchState */ + CPUArchState *env_ptr; IcountDecr *icount_decr_ptr; =20 /* Accessed in parallel; all accesses must be atomic */ diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index ee60eb3de47..c6f692b0dd5 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -39,6 +39,7 @@ typedef struct CompatProperty CompatProperty; typedef struct CoMutex CoMutex; typedef struct ConfidentialGuestSupport ConfidentialGuestSupport; typedef struct CPUAddressSpace CPUAddressSpace; +typedef struct CPUArchState CPUArchState; typedef struct CPUState CPUState; typedef struct DeviceListener DeviceListener; typedef struct DeviceState DeviceState; diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index e8192115039..cfd17fd265a 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -197,9 +197,7 @@ enum { #define MMU_USER_IDX 1 #define MMU_PHYS_IDX 2 =20 -typedef struct CPUAlphaState CPUAlphaState; - -struct CPUAlphaState { +typedef struct CPUArchState { uint64_t ir[31]; float64 fir[31]; uint64_t pc; @@ -251,7 +249,7 @@ struct CPUAlphaState { uint32_t features; uint32_t amask; int implver; -}; +} CPUAlphaState; =20 /** * AlphaCPU: @@ -285,7 +283,6 @@ int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t= *buf, int reg); =20 #define cpu_list alpha_cpu_list =20 -typedef CPUAlphaState CPUArchState; typedef AlphaCPU ArchCPU; =20 #include "exec/cpu-all.h" diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 24d9fff1705..fe55ca80be4 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -232,7 +232,7 @@ typedef struct CPUARMTBFlags { target_ulong flags2; } CPUARMTBFlags; =20 -typedef struct CPUARMState { +typedef struct CPUArchState { /* Regs for current mode. */ uint32_t regs[16]; =20 @@ -3410,7 +3410,6 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMS= tate *env) } } =20 -typedef CPUARMState CPUArchState; typedef ARMCPU ArchCPU; =20 #include "exec/cpu-all.h" diff --git a/target/avr/cpu.h b/target/avr/cpu.h index dceacf3cd72..e4a990556b3 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -108,9 +108,7 @@ typedef enum AVRFeature { AVR_FEATURE_RAMPZ, } AVRFeature; =20 -typedef struct CPUAVRState CPUAVRState; - -struct CPUAVRState { +typedef struct CPUArchState { uint32_t pc_w; /* 0x003fffff up to 22 bits */ =20 uint32_t sregC; /* 0x00000001 1 bit */ @@ -137,7 +135,7 @@ struct CPUAVRState { bool fullacc; /* CPU/MEM if true MEM only otherwise */ =20 uint64_t features; -}; +} CPUAVRState; =20 /** * AVRCPU: @@ -247,7 +245,6 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); =20 -typedef CPUAVRState CPUArchState; typedef AVRCPU ArchCPU; =20 #include "exec/cpu-all.h" diff --git a/target/cris/cpu.h b/target/cris/cpu.h index b445b194ea5..763d4f882ef 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -105,7 +105,7 @@ typedef struct { uint32_t lo; } TLBSet; =20 -typedef struct CPUCRISState { +typedef struct CPUArchState { uint32_t regs[16]; /* P0 - P15 are referred to as special registers in the docs. */ uint32_t pregs[16]; @@ -265,7 +265,6 @@ static inline int cpu_mmu_index (CPUCRISState *env, boo= l ifetch) #define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5 #define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6 =20 -typedef CPUCRISState CPUArchState; typedef CRISCPU ArchCPU; =20 #include "exec/cpu-all.h" diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 76cd1d50219..a65bd935c3f 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -18,9 +18,6 @@ #ifndef HEXAGON_CPU_H #define HEXAGON_CPU_H =20 -/* Forward declaration needed by some of the header files */ -typedef struct CPUHexagonState CPUHexagonState; - #include "fpu/softfloat-types.h" =20 #include "exec/cpu-defs.h" @@ -77,7 +74,7 @@ typedef struct { /* Maximum number of vector temps in a packet */ #define VECTOR_TEMPS_MAX 4 =20 -struct CPUHexagonState { +typedef struct CPUArchState { target_ulong gpr[TOTAL_PER_THREAD_REGS]; target_ulong pred[NUM_PREGS]; target_ulong branch_taken; @@ -131,7 +128,7 @@ struct CPUHexagonState { target_ulong vstore_pending[VSTORES_MAX]; bool vtcm_pending; VTCMStoreLog vtcm_log; -}; +} CPUHexagonState; =20 OBJECT_DECLARE_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU) =20 @@ -177,7 +174,6 @@ static inline int cpu_mmu_index(CPUHexagonState *env, b= ool ifetch) #endif } =20 -typedef struct CPUHexagonState CPUArchState; typedef HexagonCPU ArchCPU; =20 void hexagon_translate_init(void); diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 93c119532a2..d36e5c170cd 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -138,8 +138,6 @@ #define CR_IPSW 22 #define CR_EIRR 23 =20 -typedef struct CPUHPPAState CPUHPPAState; - #if TARGET_REGISTER_BITS =3D=3D 32 typedef uint32_t target_ureg; typedef int32_t target_sreg; @@ -168,7 +166,7 @@ typedef struct { unsigned access_id : 16; } hppa_tlb_entry; =20 -struct CPUHPPAState { +typedef struct CPUArchState { target_ureg gr[32]; uint64_t fr[32]; uint64_t sr[8]; /* stored shifted into place for gva */ @@ -207,7 +205,7 @@ struct CPUHPPAState { /* ??? We should use a more intelligent data structure. */ hppa_tlb_entry tlb[HPPA_TLB_ENTRIES]; uint32_t tlb_last; -}; +} CPUHPPAState; =20 /** * HPPACPU: @@ -225,8 +223,6 @@ struct HPPACPU { QEMUTimer *alarm_timer; }; =20 - -typedef CPUHPPAState CPUArchState; typedef HPPACPU ArchCPU; =20 #include "exec/cpu-all.h" diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e69ab5dd783..5c2cf38cab9 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1431,7 +1431,7 @@ typedef struct HVFX86LazyFlags { target_ulong auxbits; } HVFX86LazyFlags; =20 -typedef struct CPUX86State { +typedef struct CPUArchState { /* standard registers */ target_ulong regs[CPU_NB_REGS]; target_ulong eip; @@ -2074,7 +2074,6 @@ static inline int cpu_mmu_index_kernel(CPUX86State *e= nv) #define CC_SRC2 (env->cc_src2) #define CC_OP (env->cc_op) =20 -typedef CPUX86State CPUArchState; typedef X86CPU ArchCPU; =20 #include "exec/cpu-all.h" diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index a3423729ef0..02453982301 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -79,7 +79,7 @@ =20 typedef CPU_LDoubleU FPReg; =20 -typedef struct CPUM68KState { +typedef struct CPUArchState { uint32_t dregs[8]; uint32_t aregs[8]; uint32_t pc; @@ -574,7 +574,6 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr p= hysaddr, vaddr addr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr); =20 -typedef CPUM68KState CPUArchState; typedef M68kCPU ArchCPU; =20 #include "exec/cpu-all.h" diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index e9cd0b88dea..acfd35d3f7f 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -24,7 +24,7 @@ #include "exec/cpu-defs.h" #include "fpu/softfloat-types.h" =20 -typedef struct CPUMBState CPUMBState; +typedef struct CPUArchState CPUMBState; #if !defined(CONFIG_USER_ONLY) #include "mmu.h" #endif @@ -239,7 +239,7 @@ typedef struct CPUMBState CPUMBState; #define USE_NON_SECURE_M_AXI_DC_MASK 0x4 #define USE_NON_SECURE_M_AXI_IC_MASK 0x8 =20 -struct CPUMBState { +struct CPUArchState { uint32_t bvalue; /* TCG temporary, only valid during a TB */ uint32_t btarget; /* Full resolved branch destination */ =20 @@ -394,7 +394,6 @@ void mb_tcg_init(void); #define MMU_USER_IDX 2 /* See NB_MMU_MODES further up the file. */ =20 -typedef CPUMBState CPUArchState; typedef MicroBlazeCPU ArchCPU; =20 #include "exec/cpu-all.h" diff --git a/target/mips/cpu.h b/target/mips/cpu.h index 56b1cbd091d..d4f5d7099af 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -524,8 +524,7 @@ struct TCState { }; =20 struct MIPSITUState; -typedef struct CPUMIPSState CPUMIPSState; -struct CPUMIPSState { +typedef struct CPUArchState { TCState active_tc; CPUMIPSFPUContext active_fpu; =20 @@ -1161,7 +1160,7 @@ struct CPUMIPSState { QEMUTimer *timer; /* Internal timer */ target_ulong exception_base; /* ExceptionBase input to the core */ uint64_t cp0_count_ns; /* CP0_Count clock period (in nanoseconds) */ -}; +} CPUMIPSState; =20 /** * MIPSCPU: @@ -1218,7 +1217,6 @@ static inline int cpu_mmu_index(CPUMIPSState *env, bo= ol ifetch) return hflags_mmu_index(env->hflags); } =20 -typedef CPUMIPSState CPUArchState; typedef MIPSCPU ArchCPU; =20 #include "exec/cpu-all.h" diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index a00e4229ce9..a354ff4bea7 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -25,7 +25,7 @@ #include "hw/core/cpu.h" #include "qom/object.h" =20 -typedef struct CPUNios2State CPUNios2State; +typedef struct CPUArchState CPUNios2State; #if !defined(CONFIG_USER_ONLY) #include "mmu.h" #endif @@ -155,7 +155,7 @@ struct Nios2CPUClass { =20 #define CPU_INTERRUPT_NMI CPU_INTERRUPT_TGT_EXT_3 =20 -struct CPUNios2State { +struct CPUArchState { uint32_t regs[NUM_CORE_REGS]; =20 #if !defined(CONFIG_USER_ONLY) diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index 5711591520d..a218e49f0e4 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -242,7 +242,7 @@ typedef struct CPUOpenRISCTLBContext { } CPUOpenRISCTLBContext; #endif =20 -typedef struct CPUOpenRISCState { +typedef struct CPUArchState { target_ulong shadow_gpr[16][32]; /* Shadow registers */ =20 target_ulong pc; /* Program counter */ @@ -348,7 +348,6 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu); #define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU =20 -typedef CPUOpenRISCState CPUArchState; typedef OpenRISCCPU ArchCPU; =20 #include "exec/cpu-all.h" diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 98facee9fa9..78b19a5cdb8 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -32,7 +32,7 @@ OBJECT_DECLARE_TYPE(PowerPCCPU, PowerPCCPUClass, POWERPC_CPU) =20 -typedef struct CPUPPCState CPUPPCState; +typedef struct CPUArchState CPUPPCState; typedef struct ppc_tb_t ppc_tb_t; typedef struct ppc_dcr_t ppc_dcr_t; =20 diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 1b687521c76..7be5ca2085e 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1077,7 +1077,7 @@ struct ppc_radix_page_info { #define PPC_CPU_OPCODES_LEN 0x40 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20 =20 -struct CPUPPCState { +struct CPUArchState { /* Most commonly used resources during translated code execution first= */ target_ulong gpr[32]; /* general purpose registers */ target_ulong gprh[32]; /* storage for GPR MSB, used by the SPE extensi= on */ @@ -1477,7 +1477,6 @@ void ppc_compat_add_property(Object *obj, const char = *name, uint32_t *compat_pvr, const char *basedesc); #endif /* defined(TARGET_PPC64) */ =20 -typedef CPUPPCState CPUArchState; typedef PowerPCCPU ArchCPU; =20 #include "exec/cpu-all.h" diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9ba05042ede..c28cbe6868e 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -98,7 +98,7 @@ enum { =20 #define MAX_RISCV_PMPS (16) =20 -typedef struct CPURISCVState CPURISCVState; +typedef struct CPUArchState CPURISCVState; =20 #if !defined(CONFIG_USER_ONLY) #include "pmp.h" @@ -113,7 +113,7 @@ FIELD(VTYPE, VMA, 7, 1) FIELD(VTYPE, VEDIV, 8, 2) FIELD(VTYPE, RESERVED, 10, sizeof(target_ulong) * 8 - 11) =20 -struct CPURISCVState { +struct CPUArchState { target_ulong gpr[32]; target_ulong gprh[32]; /* 64 top bits of the 128-bit registers */ uint64_t fpr[32]; /* assume both F and D extensions */ @@ -499,7 +499,6 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ul= ong); #define TB_FLAGS_MSTATUS_FS MSTATUS_FS #define TB_FLAGS_MSTATUS_VS MSTATUS_VS =20 -typedef CPURISCVState CPUArchState; typedef RISCVCPU ArchCPU; #include "exec/cpu-all.h" =20 diff --git a/target/rx/cpu-qom.h b/target/rx/cpu-qom.h index 7310558e0cf..f918c46b003 100644 --- a/target/rx/cpu-qom.h +++ b/target/rx/cpu-qom.h @@ -45,6 +45,4 @@ struct RXCPUClass { DeviceReset parent_reset; }; =20 -#define CPUArchState struct CPURXState - #endif diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 58adf9edf69..0f3d9d5bd97 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -65,7 +65,7 @@ enum { NUM_REGS =3D 16, }; =20 -typedef struct CPURXState { +typedef struct CPUArchState { /* CPU registers */ uint32_t regs[NUM_REGS]; /* general registers */ uint32_t psw_o; /* O bit of status register */ diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h index 9f3a0d86c50..04d5b3012cd 100644 --- a/target/s390x/cpu-qom.h +++ b/target/s390x/cpu-qom.h @@ -31,6 +31,8 @@ OBJECT_DECLARE_TYPE(S390CPU, S390CPUClass, typedef struct S390CPUModel S390CPUModel; typedef struct S390CPUDef S390CPUDef; =20 +typedef struct CPUArchState CPUS390XState; + typedef enum cpu_reset_type { S390_CPU_RESET_NORMAL, S390_CPU_RESET_INITIAL, @@ -63,6 +65,4 @@ struct S390CPUClass { void (*reset)(CPUState *cpu, cpu_reset_type type); }; =20 -typedef struct CPUS390XState CPUS390XState; - #endif diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index a75e559134c..b668c1b0c75 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -51,7 +51,7 @@ typedef struct PSW { uint64_t addr; } PSW; =20 -struct CPUS390XState { +struct CPUArchState { uint64_t regs[16]; /* GP registers */ /* * The floating point registers are part of the vector registers. @@ -840,7 +840,6 @@ uint64_t s390_cpu_get_psw_mask(CPUS390XState *env); /* outside of target/s390x/ */ S390CPU *s390_cpu_addr2state(uint16_t cpu_addr); =20 -typedef CPUS390XState CPUArchState; typedef S390CPU ArchCPU; =20 #include "exec/cpu-all.h" diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index fb9dd9db2ff..9a89d2d038c 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -130,7 +130,7 @@ typedef struct memory_content { struct memory_content *next; } memory_content; =20 -typedef struct CPUSH4State { +typedef struct CPUArchState { uint32_t flags; /* general execution flags */ uint32_t gregs[24]; /* general registers */ float32 fregs[32]; /* floating point registers */ @@ -264,7 +264,6 @@ static inline int cpu_mmu_index (CPUSH4State *env, bool= ifetch) } } =20 -typedef CPUSH4State CPUArchState; typedef SuperHCPU ArchCPU; =20 #include "exec/cpu-all.h" diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 5a7f1ed5d61..938efb72bf7 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -420,7 +420,7 @@ struct CPUTimer =20 typedef struct CPUTimer CPUTimer; =20 -typedef struct CPUSPARCState CPUSPARCState; +typedef struct CPUArchState CPUSPARCState; #if defined(TARGET_SPARC64) typedef union { uint64_t mmuregs[16]; @@ -439,7 +439,7 @@ typedef union { }; } SparcV9MMU; #endif -struct CPUSPARCState { +struct CPUArchState { target_ulong gregs[8]; /* general registers */ target_ulong *regwptr; /* pointer to current register window */ target_ulong pc; /* program counter */ @@ -743,7 +743,6 @@ static inline int cpu_pil_allowed(CPUSPARCState *env1, = int pil) #endif } =20 -typedef CPUSPARCState CPUArchState; typedef SPARCCPU ArchCPU; =20 #include "exec/cpu-all.h" diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index c461387e71b..398d5076be8 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -28,8 +28,7 @@ struct tricore_boot_info; =20 typedef struct tricore_def_t tricore_def_t; =20 -typedef struct CPUTriCoreState CPUTriCoreState; -struct CPUTriCoreState { +typedef struct CPUArchState { /* GPR Register */ uint32_t gpr_a[16]; uint32_t gpr_d[16]; @@ -189,7 +188,7 @@ struct CPUTriCoreState { const tricore_def_t *cpu_model; void *irq[8]; struct QEMUTimer *timer; /* Internal timer */ -}; +} CPUTriCoreState; =20 /** * TriCoreCPU: @@ -369,7 +368,6 @@ static inline int cpu_mmu_index(CPUTriCoreState *env, b= ool ifetch) return 0; } =20 -typedef CPUTriCoreState CPUArchState; typedef TriCoreCPU ArchCPU; =20 #include "exec/cpu-all.h" diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index f2165b17e2d..44963259704 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -306,7 +306,7 @@ typedef enum { INTTYPE_MAX } interrupt_type; =20 -struct CPUXtensaState; +typedef struct CPUArchState CPUXtensaState; =20 typedef struct xtensa_tlb_entry { uint32_t vaddr; @@ -506,7 +506,7 @@ enum { }; #endif =20 -typedef struct CPUXtensaState { +struct CPUArchState { const XtensaConfig *config; uint32_t regs[16]; uint32_t pc; @@ -545,7 +545,7 @@ typedef struct CPUXtensaState { =20 /* Watchpoints for DBREAK registers */ struct CPUWatchpoint *cpu_watchpoint[MAX_NDBREAK]; -} CPUXtensaState; +}; =20 /** * XtensaCPU: @@ -722,7 +722,6 @@ static inline int cpu_mmu_index(CPUXtensaState *env, bo= ol ifetch) #define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000 #define XTENSA_CSBASE_LBEG_OFF_SHIFT 16 =20 -typedef CPUXtensaState CPUArchState; typedef XtensaCPU ArchCPU; =20 #include "exec/cpu-all.h" --=20 2.35.1 From nobody Sun Feb 8 05:08:15 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.50 as permitted sender) client-ip=209.85.221.50; envelope-from=philippe.mathieu.daude@gmail.com; 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Sun, 06 Mar 2022 05:02:39 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Eduardo Habkost , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 30/33] target: Introduce and use OBJECT_DECLARE_CPU_TYPE() macro Date: Sun, 6 Mar 2022 13:59:57 +0100 Message-Id: <20220306130000.8104-31-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> References: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571762686100001 From: Philippe Mathieu-Daud=C3=A9 Replace the boilerplate code to declare CPU QOM types and macros, and forward-declare the CPU instance type. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220214183144.27402-14-f4bug@amsat.org> --- include/hw/core/cpu.h | 18 ++++++++++++++++++ target/alpha/cpu-qom.h | 3 +-- target/alpha/cpu.h | 2 -- target/arm/cpu-qom.h | 3 +-- target/arm/cpu.h | 2 -- target/avr/cpu-qom.h | 3 +-- target/avr/cpu.h | 6 ++---- target/cris/cpu-qom.h | 3 +-- target/cris/cpu.h | 2 -- target/hexagon/cpu.h | 6 +++--- target/hppa/cpu-qom.h | 3 +-- target/hppa/cpu.h | 2 -- target/i386/cpu-qom.h | 3 +-- target/i386/cpu.h | 2 -- target/m68k/cpu-qom.h | 3 +-- target/m68k/cpu.h | 2 -- target/microblaze/cpu-qom.h | 3 +-- target/microblaze/cpu.h | 2 -- target/mips/cpu-qom.h | 3 +-- target/mips/cpu.h | 2 -- target/nios2/cpu.h | 3 +-- target/openrisc/cpu.h | 8 +------- target/ppc/cpu-qom.h | 3 +-- target/ppc/cpu.h | 2 -- target/riscv/cpu.h | 4 +--- target/rx/cpu-qom.h | 3 +-- target/rx/cpu.h | 2 -- target/s390x/cpu-qom.h | 3 +-- target/s390x/cpu.h | 2 -- target/sh4/cpu-qom.h | 3 +-- target/sh4/cpu.h | 2 -- target/sparc/cpu-qom.h | 3 +-- target/sparc/cpu.h | 2 -- target/tricore/cpu-qom.h | 3 +-- target/tricore/cpu.h | 2 -- target/xtensa/cpu-qom.h | 3 +-- target/xtensa/cpu.h | 2 -- 37 files changed, 42 insertions(+), 81 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index c9d41e4ece5..2a0893b1dc7 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -55,6 +55,24 @@ typedef struct CPUClass CPUClass; DECLARE_CLASS_CHECKERS(CPUClass, CPU, TYPE_CPU) =20 +/** + * OBJECT_DECLARE_CPU_TYPE: + * @CpuInstanceType: instance struct name + * @CpuClassType: class struct name + * @CPU_MODULE_OBJ_NAME: the CPU name in uppercase with underscore separat= ors + * + * This macro is typically used in "cpu-qom.h" header file, and will: + * + * - create the typedefs for the CPU object and class structs + * - register the type for use with g_autoptr + * - provide three standard type cast functions + * + * The object struct and class struct need to be declared manually. + */ +#define OBJECT_DECLARE_CPU_TYPE(CpuInstanceType, CpuClassType, CPU_MODULE_= OBJ_NAME) \ + OBJECT_DECLARE_TYPE(CpuInstanceType, CpuClassType, CPU_MODULE_OBJ_NAME= ); \ + typedef CpuInstanceType ArchCPU; + typedef enum MMUAccessType { MMU_DATA_LOAD =3D 0, MMU_DATA_STORE =3D 1, diff --git a/target/alpha/cpu-qom.h b/target/alpha/cpu-qom.h index 7bb9173c57f..1f200724b67 100644 --- a/target/alpha/cpu-qom.h +++ b/target/alpha/cpu-qom.h @@ -25,8 +25,7 @@ =20 #define TYPE_ALPHA_CPU "alpha-cpu" =20 -OBJECT_DECLARE_TYPE(AlphaCPU, AlphaCPUClass, - ALPHA_CPU) +OBJECT_DECLARE_CPU_TYPE(AlphaCPU, AlphaCPUClass, ALPHA_CPU) =20 /** * AlphaCPUClass: diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index cfd17fd265a..84430aff421 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -283,8 +283,6 @@ int alpha_cpu_gdb_write_register(CPUState *cpu, uint8_t= *buf, int reg); =20 #define cpu_list alpha_cpu_list =20 -typedef AlphaCPU ArchCPU; - #include "exec/cpu-all.h" =20 enum { diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h index a22bd506d07..64c44cef2dd 100644 --- a/target/arm/cpu-qom.h +++ b/target/arm/cpu-qom.h @@ -27,8 +27,7 @@ struct arm_boot_info; =20 #define TYPE_ARM_CPU "arm-cpu" =20 -OBJECT_DECLARE_TYPE(ARMCPU, ARMCPUClass, - ARM_CPU) +OBJECT_DECLARE_CPU_TYPE(ARMCPU, ARMCPUClass, ARM_CPU) =20 #define TYPE_ARM_MAX_CPU "max-" TYPE_ARM_CPU =20 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index fe55ca80be4..af89509f5a9 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3410,8 +3410,6 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMS= tate *env) } } =20 -typedef ARMCPU ArchCPU; - #include "exec/cpu-all.h" =20 /* diff --git a/target/avr/cpu-qom.h b/target/avr/cpu-qom.h index 14e5b3ce72f..32a1c762e64 100644 --- a/target/avr/cpu-qom.h +++ b/target/avr/cpu-qom.h @@ -26,8 +26,7 @@ =20 #define TYPE_AVR_CPU "avr-cpu" =20 -OBJECT_DECLARE_TYPE(AVRCPU, AVRCPUClass, - AVR_CPU) +OBJECT_DECLARE_CPU_TYPE(AVRCPU, AVRCPUClass, AVR_CPU) =20 /** * AVRCPUClass: diff --git a/target/avr/cpu.h b/target/avr/cpu.h index e4a990556b3..a833799fc14 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -143,14 +143,14 @@ typedef struct CPUArchState { * * A AVR CPU. */ -typedef struct AVRCPU { +struct AVRCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ =20 CPUNegativeOffsetState neg; CPUAVRState env; -} AVRCPU; +}; =20 extern const struct VMStateDescription vms_avr_cpu; =20 @@ -245,8 +245,6 @@ bool avr_cpu_tlb_fill(CPUState *cs, vaddr address, int = size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); =20 -typedef AVRCPU ArchCPU; - #include "exec/cpu-all.h" =20 #endif /* !defined (QEMU_AVR_CPU_H) */ diff --git a/target/cris/cpu-qom.h b/target/cris/cpu-qom.h index 2596edc7e31..71e8af0e70a 100644 --- a/target/cris/cpu-qom.h +++ b/target/cris/cpu-qom.h @@ -25,8 +25,7 @@ =20 #define TYPE_CRIS_CPU "cris-cpu" =20 -OBJECT_DECLARE_TYPE(CRISCPU, CRISCPUClass, - CRIS_CPU) +OBJECT_DECLARE_CPU_TYPE(CRISCPU, CRISCPUClass, CRIS_CPU) =20 /** * CRISCPUClass: diff --git a/target/cris/cpu.h b/target/cris/cpu.h index 763d4f882ef..af7121bba06 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -265,8 +265,6 @@ static inline int cpu_mmu_index (CPUCRISState *env, boo= l ifetch) #define SFR_RW_MM_TLB_LO env->pregs[PR_SRS]][5 #define SFR_RW_MM_TLB_HI env->pregs[PR_SRS]][6 =20 -typedef CRISCPU ArchCPU; - #include "exec/cpu-all.h" =20 static inline void cpu_get_tb_cpu_state(CPUCRISState *env, target_ulong *p= c, diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index a65bd935c3f..8db0aa542d6 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -130,7 +130,7 @@ typedef struct CPUArchState { VTCMStoreLog vtcm_log; } CPUHexagonState; =20 -OBJECT_DECLARE_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU) +OBJECT_DECLARE_CPU_TYPE(HexagonCPU, HexagonCPUClass, HEXAGON_CPU) =20 typedef struct HexagonCPUClass { /*< private >*/ @@ -140,7 +140,7 @@ typedef struct HexagonCPUClass { DeviceReset parent_reset; } HexagonCPUClass; =20 -typedef struct HexagonCPU { +struct HexagonCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ @@ -149,7 +149,7 @@ typedef struct HexagonCPU { =20 bool lldb_compat; target_ulong lldb_stack_adjust; -} HexagonCPU; +}; =20 #include "cpu_bits.h" =20 diff --git a/target/hppa/cpu-qom.h b/target/hppa/cpu-qom.h index d424f88370c..b96e0318c77 100644 --- a/target/hppa/cpu-qom.h +++ b/target/hppa/cpu-qom.h @@ -25,8 +25,7 @@ =20 #define TYPE_HPPA_CPU "hppa-cpu" =20 -OBJECT_DECLARE_TYPE(HPPACPU, HPPACPUClass, - HPPA_CPU) +OBJECT_DECLARE_CPU_TYPE(HPPACPU, HPPACPUClass, HPPA_CPU) =20 /** * HPPACPUClass: diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index d36e5c170cd..73a3f323895 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -223,8 +223,6 @@ struct HPPACPU { QEMUTimer *alarm_timer; }; =20 -typedef HPPACPU ArchCPU; - #include "exec/cpu-all.h" =20 static inline int cpu_mmu_index(CPUHPPAState *env, bool ifetch) diff --git a/target/i386/cpu-qom.h b/target/i386/cpu-qom.h index f9923cee046..c557a522e1e 100644 --- a/target/i386/cpu-qom.h +++ b/target/i386/cpu-qom.h @@ -30,8 +30,7 @@ #define TYPE_X86_CPU "i386-cpu" #endif =20 -OBJECT_DECLARE_TYPE(X86CPU, X86CPUClass, - X86_CPU) +OBJECT_DECLARE_CPU_TYPE(X86CPU, X86CPUClass, X86_CPU) =20 typedef struct X86CPUModel X86CPUModel; =20 diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 5c2cf38cab9..d99e175e17c 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2074,8 +2074,6 @@ static inline int cpu_mmu_index_kernel(CPUX86State *e= nv) #define CC_SRC2 (env->cc_src2) #define CC_OP (env->cc_op) =20 -typedef X86CPU ArchCPU; - #include "exec/cpu-all.h" #include "svm.h" =20 diff --git a/target/m68k/cpu-qom.h b/target/m68k/cpu-qom.h index 1ceb160ecb0..cd9687192cd 100644 --- a/target/m68k/cpu-qom.h +++ b/target/m68k/cpu-qom.h @@ -25,8 +25,7 @@ =20 #define TYPE_M68K_CPU "m68k-cpu" =20 -OBJECT_DECLARE_TYPE(M68kCPU, M68kCPUClass, - M68K_CPU) +OBJECT_DECLARE_CPU_TYPE(M68kCPU, M68kCPUClass, M68K_CPU) =20 /* * M68kCPUClass: diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 02453982301..76a7cc70b4f 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -574,8 +574,6 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr p= hysaddr, vaddr addr, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr); =20 -typedef M68kCPU ArchCPU; - #include "exec/cpu-all.h" =20 /* TB flags */ diff --git a/target/microblaze/cpu-qom.h b/target/microblaze/cpu-qom.h index e520eefb127..255b39a45df 100644 --- a/target/microblaze/cpu-qom.h +++ b/target/microblaze/cpu-qom.h @@ -25,8 +25,7 @@ =20 #define TYPE_MICROBLAZE_CPU "microblaze-cpu" =20 -OBJECT_DECLARE_TYPE(MicroBlazeCPU, MicroBlazeCPUClass, - MICROBLAZE_CPU) +OBJECT_DECLARE_CPU_TYPE(MicroBlazeCPU, MicroBlazeCPUClass, MICROBLAZE_CPU) =20 /** * MicroBlazeCPUClass: diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index acfd35d3f7f..6e4e90a41ed 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -394,8 +394,6 @@ void mb_tcg_init(void); #define MMU_USER_IDX 2 /* See NB_MMU_MODES further up the file. */ =20 -typedef MicroBlazeCPU ArchCPU; - #include "exec/cpu-all.h" =20 /* Ensure there is no overlap between the two masks. */ diff --git a/target/mips/cpu-qom.h b/target/mips/cpu-qom.h index dda0c911fa7..e28b5296073 100644 --- a/target/mips/cpu-qom.h +++ b/target/mips/cpu-qom.h @@ -29,8 +29,7 @@ #define TYPE_MIPS_CPU "mips-cpu" #endif =20 -OBJECT_DECLARE_TYPE(MIPSCPU, MIPSCPUClass, - MIPS_CPU) +OBJECT_DECLARE_CPU_TYPE(MIPSCPU, MIPSCPUClass, MIPS_CPU) =20 /** * MIPSCPUClass: diff --git a/target/mips/cpu.h b/target/mips/cpu.h index d4f5d7099af..c361408cc81 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1217,8 +1217,6 @@ static inline int cpu_mmu_index(CPUMIPSState *env, bo= ol ifetch) return hflags_mmu_index(env->hflags); } =20 -typedef MIPSCPU ArchCPU; - #include "exec/cpu-all.h" =20 /* Exceptions */ diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index a354ff4bea7..e07da73df0d 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -32,8 +32,7 @@ typedef struct CPUArchState CPUNios2State; =20 #define TYPE_NIOS2_CPU "nios2-cpu" =20 -OBJECT_DECLARE_TYPE(Nios2CPU, Nios2CPUClass, - NIOS2_CPU) +OBJECT_DECLARE_CPU_TYPE(Nios2CPU, Nios2CPUClass, NIOS2_CPU) =20 /** * Nios2CPUClass: diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index a218e49f0e4..bcd28802e49 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -24,13 +24,9 @@ #include "hw/core/cpu.h" #include "qom/object.h" =20 -/* cpu_openrisc_map_address_* in CPUOpenRISCTLBContext need this decl. */ -struct OpenRISCCPU; - #define TYPE_OPENRISC_CPU "or1k-cpu" =20 -OBJECT_DECLARE_TYPE(OpenRISCCPU, OpenRISCCPUClass, - OPENRISC_CPU) +OBJECT_DECLARE_CPU_TYPE(OpenRISCCPU, OpenRISCCPUClass, OPENRISC_CPU) =20 /** * OpenRISCCPUClass: @@ -348,8 +344,6 @@ void cpu_openrisc_count_stop(OpenRISCCPU *cpu); #define OPENRISC_CPU_TYPE_NAME(model) model OPENRISC_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_OPENRISC_CPU =20 -typedef OpenRISCCPU ArchCPU; - #include "exec/cpu-all.h" =20 #define TB_FLAGS_SM SR_SM diff --git a/target/ppc/cpu-qom.h b/target/ppc/cpu-qom.h index 78b19a5cdb8..ad7e3c3db90 100644 --- a/target/ppc/cpu-qom.h +++ b/target/ppc/cpu-qom.h @@ -29,8 +29,7 @@ #define TYPE_POWERPC_CPU "powerpc-cpu" #endif =20 -OBJECT_DECLARE_TYPE(PowerPCCPU, PowerPCCPUClass, - POWERPC_CPU) +OBJECT_DECLARE_CPU_TYPE(PowerPCCPU, PowerPCCPUClass, POWERPC_CPU) =20 typedef struct CPUArchState CPUPPCState; typedef struct ppc_tb_t ppc_tb_t; diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 7be5ca2085e..03bba61c8b4 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1477,8 +1477,6 @@ void ppc_compat_add_property(Object *obj, const char = *name, uint32_t *compat_pvr, const char *basedesc); #endif /* defined(TARGET_PPC64) */ =20 -typedef PowerPCCPU ArchCPU; - #include "exec/cpu-all.h" =20 /*************************************************************************= ****/ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index c28cbe6868e..2810389fddb 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -320,8 +320,7 @@ struct CPUArchState { uint64_t kvm_timer_frequency; }; =20 -OBJECT_DECLARE_TYPE(RISCVCPU, RISCVCPUClass, - RISCV_CPU) +OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) =20 /** * RISCVCPUClass: @@ -499,7 +498,6 @@ void riscv_cpu_set_fflags(CPURISCVState *env, target_ul= ong); #define TB_FLAGS_MSTATUS_FS MSTATUS_FS #define TB_FLAGS_MSTATUS_VS MSTATUS_VS =20 -typedef RISCVCPU ArchCPU; #include "exec/cpu-all.h" =20 FIELD(TB_FLAGS, MEM_IDX, 0, 3) diff --git a/target/rx/cpu-qom.h b/target/rx/cpu-qom.h index f918c46b003..4533759d966 100644 --- a/target/rx/cpu-qom.h +++ b/target/rx/cpu-qom.h @@ -26,8 +26,7 @@ =20 #define TYPE_RX62N_CPU RX_CPU_TYPE_NAME("rx62n") =20 -OBJECT_DECLARE_TYPE(RXCPU, RXCPUClass, - RX_CPU) +OBJECT_DECLARE_CPU_TYPE(RXCPU, RXCPUClass, RX_CPU) =20 /* * RXCPUClass: diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 0f3d9d5bd97..f81bf5b592a 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -114,8 +114,6 @@ struct RXCPU { CPURXState env; }; =20 -typedef RXCPU ArchCPU; - #define RX_CPU_TYPE_SUFFIX "-" TYPE_RX_CPU #define RX_CPU_TYPE_NAME(model) model RX_CPU_TYPE_SUFFIX #define CPU_RESOLVING_TYPE TYPE_RX_CPU diff --git a/target/s390x/cpu-qom.h b/target/s390x/cpu-qom.h index 04d5b3012cd..00cae2b1311 100644 --- a/target/s390x/cpu-qom.h +++ b/target/s390x/cpu-qom.h @@ -25,8 +25,7 @@ =20 #define TYPE_S390_CPU "s390x-cpu" =20 -OBJECT_DECLARE_TYPE(S390CPU, S390CPUClass, - S390_CPU) +OBJECT_DECLARE_CPU_TYPE(S390CPU, S390CPUClass, S390_CPU) =20 typedef struct S390CPUModel S390CPUModel; typedef struct S390CPUDef S390CPUDef; diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index b668c1b0c75..bdf3f7d4feb 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -840,8 +840,6 @@ uint64_t s390_cpu_get_psw_mask(CPUS390XState *env); /* outside of target/s390x/ */ S390CPU *s390_cpu_addr2state(uint16_t cpu_addr); =20 -typedef S390CPU ArchCPU; - #include "exec/cpu-all.h" =20 #endif diff --git a/target/sh4/cpu-qom.h b/target/sh4/cpu-qom.h index 8903b4b9c7c..d4192d10908 100644 --- a/target/sh4/cpu-qom.h +++ b/target/sh4/cpu-qom.h @@ -29,8 +29,7 @@ #define TYPE_SH7751R_CPU SUPERH_CPU_TYPE_NAME("sh7751r") #define TYPE_SH7785_CPU SUPERH_CPU_TYPE_NAME("sh7785") =20 -OBJECT_DECLARE_TYPE(SuperHCPU, SuperHCPUClass, - SUPERH_CPU) +OBJECT_DECLARE_CPU_TYPE(SuperHCPU, SuperHCPUClass, SUPERH_CPU) =20 /** * SuperHCPUClass: diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index 9a89d2d038c..dd477ba5771 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -264,8 +264,6 @@ static inline int cpu_mmu_index (CPUSH4State *env, bool= ifetch) } } =20 -typedef SuperHCPU ArchCPU; - #include "exec/cpu-all.h" =20 /* MMU control register */ diff --git a/target/sparc/cpu-qom.h b/target/sparc/cpu-qom.h index f33949aaeec..86ed37d9333 100644 --- a/target/sparc/cpu-qom.h +++ b/target/sparc/cpu-qom.h @@ -29,8 +29,7 @@ #define TYPE_SPARC_CPU "sparc-cpu" #endif =20 -OBJECT_DECLARE_TYPE(SPARCCPU, SPARCCPUClass, - SPARC_CPU) +OBJECT_DECLARE_CPU_TYPE(SPARCCPU, SPARCCPUClass, SPARC_CPU) =20 typedef struct sparc_def_t sparc_def_t; /** diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 938efb72bf7..2a7fd47da3e 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -743,8 +743,6 @@ static inline int cpu_pil_allowed(CPUSPARCState *env1, = int pil) #endif } =20 -typedef SPARCCPU ArchCPU; - #include "exec/cpu-all.h" =20 #ifdef TARGET_SPARC64 diff --git a/target/tricore/cpu-qom.h b/target/tricore/cpu-qom.h index 59bfd01bbcf..ee24e9fa76a 100644 --- a/target/tricore/cpu-qom.h +++ b/target/tricore/cpu-qom.h @@ -24,8 +24,7 @@ =20 #define TYPE_TRICORE_CPU "tricore-cpu" =20 -OBJECT_DECLARE_TYPE(TriCoreCPU, TriCoreCPUClass, - TRICORE_CPU) +OBJECT_DECLARE_CPU_TYPE(TriCoreCPU, TriCoreCPUClass, TRICORE_CPU) =20 struct TriCoreCPUClass { /*< private >*/ diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index 398d5076be8..cd1954aa9ed 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -368,8 +368,6 @@ static inline int cpu_mmu_index(CPUTriCoreState *env, b= ool ifetch) return 0; } =20 -typedef TriCoreCPU ArchCPU; - #include "exec/cpu-all.h" =20 void cpu_state_reset(CPUTriCoreState *s); diff --git a/target/xtensa/cpu-qom.h b/target/xtensa/cpu-qom.h index 41d98596734..4fc35ee49b8 100644 --- a/target/xtensa/cpu-qom.h +++ b/target/xtensa/cpu-qom.h @@ -34,8 +34,7 @@ =20 #define TYPE_XTENSA_CPU "xtensa-cpu" =20 -OBJECT_DECLARE_TYPE(XtensaCPU, XtensaCPUClass, - XTENSA_CPU) +OBJECT_DECLARE_CPU_TYPE(XtensaCPU, XtensaCPUClass, XTENSA_CPU) =20 typedef struct XtensaConfig XtensaConfig; =20 diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 44963259704..a361ab87859 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -722,8 +722,6 @@ static inline int cpu_mmu_index(CPUXtensaState *env, bo= ol ifetch) #define XTENSA_CSBASE_LBEG_OFF_MASK 0x00ff0000 #define XTENSA_CSBASE_LBEG_OFF_SHIFT 16 =20 -typedef XtensaCPU ArchCPU; - #include "exec/cpu-all.h" =20 static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong = *pc, --=20 2.35.1 From nobody Sun Feb 8 05:08:15 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.221.51 as permitted sender) client-ip=209.85.221.51; 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Sun, 06 Mar 2022 05:02:45 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Eduardo Habkost , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 31/33] target: Use ArchCPU as interface to target CPU Date: Sun, 6 Mar 2022 13:59:58 +0100 Message-Id: <20220306130000.8104-32-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> References: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571768859100001 From: Philippe Mathieu-Daud=C3=A9 ArchCPU is our interface with target-specific code. Use it as a forward-declared opaque pointer (abstract type), having its structure defined by each target. Reviewed-by: Richard Henderson Signed-off-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220214183144.27402-15-f4bug@amsat.org> --- include/hw/core/cpu.h | 4 ++-- include/qemu/typedefs.h | 1 + target/alpha/cpu.h | 2 +- target/arm/cpu.h | 2 +- target/avr/cpu.h | 2 +- target/cris/cpu.h | 2 +- target/hexagon/cpu.h | 2 +- target/hppa/cpu.h | 2 +- target/i386/cpu.h | 2 +- target/m68k/cpu.h | 2 +- target/microblaze/cpu.h | 2 +- target/mips/cpu.h | 2 +- target/nios2/cpu.h | 2 +- target/openrisc/cpu.h | 2 +- target/ppc/cpu.h | 2 +- target/riscv/cpu.h | 2 +- target/rx/cpu.h | 2 +- target/s390x/cpu.h | 2 +- target/sh4/cpu.h | 2 +- target/sparc/cpu.h | 2 +- target/tricore/cpu.h | 2 +- target/xtensa/cpu.h | 2 +- 22 files changed, 23 insertions(+), 22 deletions(-) diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index 2a0893b1dc7..0efc6153ed0 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -70,8 +70,8 @@ DECLARE_CLASS_CHECKERS(CPUClass, CPU, * The object struct and class struct need to be declared manually. */ #define OBJECT_DECLARE_CPU_TYPE(CpuInstanceType, CpuClassType, CPU_MODULE_= OBJ_NAME) \ - OBJECT_DECLARE_TYPE(CpuInstanceType, CpuClassType, CPU_MODULE_OBJ_NAME= ); \ - typedef CpuInstanceType ArchCPU; + typedef struct ArchCPU CpuInstanceType; \ + OBJECT_DECLARE_TYPE(ArchCPU, CpuClassType, CPU_MODULE_OBJ_NAME); =20 typedef enum MMUAccessType { MMU_DATA_LOAD =3D 0, diff --git a/include/qemu/typedefs.h b/include/qemu/typedefs.h index c6f692b0dd5..c564f54c112 100644 --- a/include/qemu/typedefs.h +++ b/include/qemu/typedefs.h @@ -26,6 +26,7 @@ typedef struct AddressSpace AddressSpace; typedef struct AioContext AioContext; typedef struct Aml Aml; typedef struct AnnounceTimer AnnounceTimer; +typedef struct ArchCPU ArchCPU; typedef struct BdrvDirtyBitmap BdrvDirtyBitmap; typedef struct BdrvDirtyBitmapIter BdrvDirtyBitmapIter; typedef struct BlockBackend BlockBackend; diff --git a/target/alpha/cpu.h b/target/alpha/cpu.h index 84430aff421..58f00b7814f 100644 --- a/target/alpha/cpu.h +++ b/target/alpha/cpu.h @@ -257,7 +257,7 @@ typedef struct CPUArchState { * * An Alpha CPU. */ -struct AlphaCPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index af89509f5a9..0b4b5bbf54c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -774,7 +774,7 @@ typedef struct ARMISARegisters ARMISARegisters; * * An ARM CPU core. */ -struct ARMCPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ diff --git a/target/avr/cpu.h b/target/avr/cpu.h index a833799fc14..55497f851dc 100644 --- a/target/avr/cpu.h +++ b/target/avr/cpu.h @@ -143,7 +143,7 @@ typedef struct CPUArchState { * * A AVR CPU. */ -struct AVRCPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ diff --git a/target/cris/cpu.h b/target/cris/cpu.h index af7121bba06..e6776f25b17 100644 --- a/target/cris/cpu.h +++ b/target/cris/cpu.h @@ -173,7 +173,7 @@ typedef struct CPUArchState { * * A CRIS CPU. */ -struct CRISCPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 8db0aa542d6..2a65a57bab3 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -140,7 +140,7 @@ typedef struct HexagonCPUClass { DeviceReset parent_reset; } HexagonCPUClass; =20 -struct HexagonCPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index 73a3f323895..4cc936b6bfd 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -213,7 +213,7 @@ typedef struct CPUArchState { * * An HPPA CPU. */ -struct HPPACPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d99e175e17c..e11734ba866 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1707,7 +1707,7 @@ struct kvm_msrs; * * An x86 CPU. */ -struct X86CPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ diff --git a/target/m68k/cpu.h b/target/m68k/cpu.h index 76a7cc70b4f..872e8ce6375 100644 --- a/target/m68k/cpu.h +++ b/target/m68k/cpu.h @@ -156,7 +156,7 @@ typedef struct CPUArchState { * * A Motorola 68k CPU. */ -struct M68kCPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 6e4e90a41ed..0a0ce71b6a5 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -339,7 +339,7 @@ typedef struct { * * A MicroBlaze CPU. */ -struct MicroBlazeCPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; =20 diff --git a/target/mips/cpu.h b/target/mips/cpu.h index c361408cc81..09e98f64de5 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1171,7 +1171,7 @@ typedef struct CPUArchState { * * A MIPS CPU. */ -struct MIPSCPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index e07da73df0d..ca0f3420cd1 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -169,7 +169,7 @@ struct CPUArchState { * * A Nios2 CPU. */ -struct Nios2CPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ diff --git a/target/openrisc/cpu.h b/target/openrisc/cpu.h index bcd28802e49..bdf29d2dc4c 100644 --- a/target/openrisc/cpu.h +++ b/target/openrisc/cpu.h @@ -297,7 +297,7 @@ typedef struct CPUArchState { * * A OpenRISC CPU. */ -struct OpenRISCCPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 03bba61c8b4..047b24ba50e 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1275,7 +1275,7 @@ typedef struct PPCVirtualHypervisorClass PPCVirtualHy= pervisorClass; * * A PowerPC CPU. */ -struct PowerPCCPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 2810389fddb..c069fe85fa1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -394,7 +394,7 @@ typedef struct RISCVCPUConfig RISCVCPUConfig; * * A RISCV CPU. */ -struct RISCVCPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ diff --git a/target/rx/cpu.h b/target/rx/cpu.h index f81bf5b592a..b4abd90ccd1 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -105,7 +105,7 @@ typedef struct CPUArchState { * * A RX CPU */ -struct RXCPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index bdf3f7d4feb..c49c8466e74 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -163,7 +163,7 @@ static inline uint64_t *get_freg(CPUS390XState *cs, int= nr) * * An S/390 CPU. */ -struct S390CPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h index dd477ba5771..c72a30edfd4 100644 --- a/target/sh4/cpu.h +++ b/target/sh4/cpu.h @@ -195,7 +195,7 @@ typedef struct CPUArchState { * * A SuperH CPU. */ -struct SuperHCPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 2a7fd47da3e..abb38db6749 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -556,7 +556,7 @@ struct CPUArchState { * * A SPARC CPU. */ -struct SPARCCPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ diff --git a/target/tricore/cpu.h b/target/tricore/cpu.h index cd1954aa9ed..108d6b8288f 100644 --- a/target/tricore/cpu.h +++ b/target/tricore/cpu.h @@ -196,7 +196,7 @@ typedef struct CPUArchState { * * A TriCore CPU. */ -struct TriCoreCPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; /*< public >*/ diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index a361ab87859..4515f682aa2 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -553,7 +553,7 @@ struct CPUArchState { * * An Xtensa CPU. */ -struct XtensaCPU { +struct ArchCPU { /*< private >*/ CPUState parent_obj; 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Sun, 06 Mar 2022 05:02:50 -0800 (PST) From: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= To: qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , Eduardo Habkost , Richard Henderson , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Subject: [PULL 32/33] target/i386: Remove pointless CPUArchState casts Date: Sun, 6 Mar 2022 13:59:59 +0100 Message-Id: <20220306130000.8104-33-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> References: <20220306130000.8104-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571774779100001 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20220305233415.64627-3-philippe.mathieu.daude@gmail.com> --- target/i386/hax/hax-all.c | 4 ++-- target/i386/nvmm/nvmm-all.c | 14 +++++++------- target/i386/whpx/whpx-all.c | 18 +++++++++--------- 3 files changed, 18 insertions(+), 18 deletions(-) diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c index ccdcb6afabc..81f665e2124 100644 --- a/target/i386/hax/hax-all.c +++ b/target/i386/hax/hax-all.c @@ -222,7 +222,7 @@ int hax_init_vcpu(CPUState *cpu) =20 cpu->hax_vcpu =3D hax_global.vm->vcpus[cpu->cpu_index]; cpu->vcpu_dirty =3D true; - qemu_register_reset(hax_reset_vcpu_state, (CPUArchState *) (cpu->env_p= tr)); + qemu_register_reset(hax_reset_vcpu_state, cpu->env_ptr); =20 return ret; } @@ -669,7 +669,7 @@ void hax_cpu_synchronize_pre_loadvm(CPUState *cpu) =20 int hax_smp_cpu_exec(CPUState *cpu) { - CPUArchState *env =3D (CPUArchState *) (cpu->env_ptr); + CPUArchState *env =3D cpu->env_ptr; int fatal; int ret; =20 diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c index e159dd2b939..b97d091a502 100644 --- a/target/i386/nvmm/nvmm-all.c +++ b/target/i386/nvmm/nvmm-all.c @@ -85,7 +85,7 @@ nvmm_set_segment(struct nvmm_x64_state_seg *nseg, const S= egmentCache *qseg) static void nvmm_set_registers(CPUState *cpu) { - CPUX86State *env =3D (CPUArchState *)cpu->env_ptr; + CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; @@ -222,7 +222,7 @@ nvmm_get_segment(SegmentCache *qseg, const struct nvmm_= x64_state_seg *nseg) static void nvmm_get_registers(CPUState *cpu) { - CPUX86State *env =3D (CPUArchState *)cpu->env_ptr; + CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; @@ -347,7 +347,7 @@ nvmm_get_registers(CPUState *cpu) static bool nvmm_can_take_int(CPUState *cpu) { - CPUX86State *env =3D (CPUArchState *)cpu->env_ptr; + CPUX86State *env =3D cpu->env_ptr; struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; struct nvmm_machine *mach =3D get_nvmm_mach(); @@ -394,7 +394,7 @@ nvmm_can_take_nmi(CPUState *cpu) static void nvmm_vcpu_pre_run(CPUState *cpu) { - CPUX86State *env =3D (CPUArchState *)cpu->env_ptr; + CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; @@ -480,7 +480,7 @@ static void nvmm_vcpu_post_run(CPUState *cpu, struct nvmm_vcpu_exit *exit) { struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); - CPUX86State *env =3D (CPUArchState *)cpu->env_ptr; + CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); uint64_t tpr; =20 @@ -652,7 +652,7 @@ static int nvmm_handle_halted(struct nvmm_machine *mach, CPUState *cpu, struct nvmm_vcpu_exit *exit) { - CPUX86State *env =3D (CPUArchState *)cpu->env_ptr; + CPUX86State *env =3D cpu->env_ptr; int ret =3D 0; =20 qemu_mutex_lock_iothread(); @@ -685,7 +685,7 @@ nvmm_inject_ud(struct nvmm_machine *mach, struct nvmm_v= cpu *vcpu) static int nvmm_vcpu_loop(CPUState *cpu) { - CPUX86State *env =3D (CPUArchState *)cpu->env_ptr; + CPUX86State *env =3D cpu->env_ptr; struct nvmm_machine *mach =3D get_nvmm_mach(); struct qemu_vcpu *qcpu =3D get_qemu_vcpu(cpu); struct nvmm_vcpu *vcpu =3D &qcpu->vcpu; diff --git a/target/i386/whpx/whpx-all.c b/target/i386/whpx/whpx-all.c index a8222461440..c7e25abf42c 100644 --- a/target/i386/whpx/whpx-all.c +++ b/target/i386/whpx/whpx-all.c @@ -221,7 +221,7 @@ static SegmentCache whpx_seg_h2q(const WHV_X64_SEGMENT_= REGISTER *hs) =20 static int whpx_set_tsc(CPUState *cpu) { - CPUX86State *env =3D (CPUArchState *)(cpu->env_ptr); + CPUX86State *env =3D cpu->env_ptr; WHV_REGISTER_NAME tsc_reg =3D WHvX64RegisterTsc; WHV_REGISTER_VALUE tsc_val; HRESULT hr; @@ -260,7 +260,7 @@ static void whpx_set_registers(CPUState *cpu, int level) { struct whpx_state *whpx =3D &whpx_global; struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); - CPUX86State *env =3D (CPUArchState *)(cpu->env_ptr); + CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); struct whpx_register_set vcxt; HRESULT hr; @@ -428,7 +428,7 @@ static void whpx_set_registers(CPUState *cpu, int level) =20 static int whpx_get_tsc(CPUState *cpu) { - CPUX86State *env =3D (CPUArchState *)(cpu->env_ptr); + CPUX86State *env =3D cpu->env_ptr; WHV_REGISTER_NAME tsc_reg =3D WHvX64RegisterTsc; WHV_REGISTER_VALUE tsc_val; HRESULT hr; @@ -449,7 +449,7 @@ static void whpx_get_registers(CPUState *cpu) { struct whpx_state *whpx =3D &whpx_global; struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); - CPUX86State *env =3D (CPUArchState *)(cpu->env_ptr); + CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); struct whpx_register_set vcxt; uint64_t tpr, apic_base; @@ -760,7 +760,7 @@ static int whpx_handle_portio(CPUState *cpu, =20 static int whpx_handle_halt(CPUState *cpu) { - CPUX86State *env =3D (CPUArchState *)(cpu->env_ptr); + CPUX86State *env =3D cpu->env_ptr; int ret =3D 0; =20 qemu_mutex_lock_iothread(); @@ -781,7 +781,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) HRESULT hr; struct whpx_state *whpx =3D &whpx_global; struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); - CPUX86State *env =3D (CPUArchState *)(cpu->env_ptr); + CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); int irq; uint8_t tpr; @@ -903,7 +903,7 @@ static void whpx_vcpu_pre_run(CPUState *cpu) static void whpx_vcpu_post_run(CPUState *cpu) { struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); - CPUX86State *env =3D (CPUArchState *)(cpu->env_ptr); + CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); =20 env->eflags =3D vcpu->exit_ctx.VpContext.Rflags; @@ -927,7 +927,7 @@ static void whpx_vcpu_post_run(CPUState *cpu) =20 static void whpx_vcpu_process_async_events(CPUState *cpu) { - CPUX86State *env =3D (CPUArchState *)(cpu->env_ptr); + CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); struct whpx_vcpu *vcpu =3D get_whpx_vcpu(cpu); =20 @@ -1333,7 +1333,7 @@ int whpx_init_vcpu(CPUState *cpu) struct whpx_state *whpx =3D &whpx_global; struct whpx_vcpu *vcpu =3D NULL; Error *local_error =3D NULL; - CPUX86State *env =3D (CPUArchState *)(cpu->env_ptr); + CPUX86State *env =3D cpu->env_ptr; X86CPU *x86_cpu =3D X86_CPU(cpu); UINT64 freq =3D 0; int ret; --=20 2.35.1 From nobody Sun Feb 8 05:08:15 2026 Delivered-To: importer@patchew.org Received-SPF: pass (zohomail.com: domain of _spf.google.com designates 209.85.128.53 as permitted sender) client-ip=209.85.128.53; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-wm1-f53.google.com; Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of _spf.google.com designates 209.85.128.53 as permitted sender) smtp.mailfrom=philippe.mathieu.daude@gmail.com; dmarc=pass(p=none dis=none) header.from=gmail.com ARC-Seal: i=1; a=rsa-sha256; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1646571778831100001 From: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Richard Henderson Message-Id: <20220305233415.64627-2-philippe.mathieu.daude@gmail.com> --- accel/tcg/cpu-exec.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index c68270f7945..c997c2e8e01 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -422,7 +422,7 @@ static void cpu_exec_exit(CPUState *cpu) =20 void cpu_exec_step_atomic(CPUState *cpu) { - CPUArchState *env =3D (CPUArchState *)cpu->env_ptr; + CPUArchState *env =3D cpu->env_ptr; TranslationBlock *tb; target_ulong cs_base, pc; uint32_t flags, cflags; @@ -532,7 +532,7 @@ TranslationBlock *tb_htable_lookup(CPUState *cpu, targe= t_ulong pc, struct tb_desc desc; uint32_t h; =20 - desc.env =3D (CPUArchState *)cpu->env_ptr; + desc.env =3D cpu->env_ptr; desc.cs_base =3D cs_base; desc.flags =3D flags; desc.cflags =3D cflags; --=20 2.35.1