From nobody Sun May 19 00:17:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646414913366314.77165445058563; Fri, 4 Mar 2022 09:28:33 -0800 (PST) Received: from localhost ([::1]:48514 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nQBjE-0004Lf-Ul for importer@patchew.org; Fri, 04 Mar 2022 12:28:33 -0500 Received: from eggs.gnu.org ([209.51.188.92]:54376) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nQBCO-0008Px-AM; Fri, 04 Mar 2022 11:54:37 -0500 Received: from [187.72.171.209] (port=61123 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nQBCM-0004rt-NE; Fri, 04 Mar 2022 11:54:36 -0500 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Fri, 4 Mar 2022 13:54:26 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id D5B17800502; Fri, 4 Mar 2022 13:54:25 -0300 (-03) From: matheus.ferst@eldorado.org.br To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v3 1/5] tests/tcg/ppc64le: use inline asm instead of __builtin_mtfsf Date: Fri, 4 Mar 2022 13:54:13 -0300 Message-Id: <20220304165417.1981159-2-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220304165417.1981159-1-matheus.ferst@eldorado.org.br> References: <20220304165417.1981159-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 04 Mar 2022 16:54:26.0288 (UTC) FILETIME=[81BB3F00:01D82FE8] X-Host-Lookup-Failed: Reverse DNS lookup failed for 187.72.171.209 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=187.72.171.209; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.659, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thuth@redhat.com, Matheus Ferst , danielhb413@gmail.com, richard.henderson@linaro.org, groug@kaod.org, philippe.mathieu.daude@gmail.com, clg@kaod.org, mrezanin@redhat.com, alex.bennee@linaro.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1646414916393100003 From: Matheus Ferst LLVM/Clang does not support __builtin_mtfsf. Acked-by: Alex Benn=C3=A9e Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- tests/tcg/ppc64le/mtfsf.c | 19 +++++++++---------- 1 file changed, 9 insertions(+), 10 deletions(-) diff --git a/tests/tcg/ppc64le/mtfsf.c b/tests/tcg/ppc64le/mtfsf.c index b3d31f3637..bed5b1afa4 100644 --- a/tests/tcg/ppc64le/mtfsf.c +++ b/tests/tcg/ppc64le/mtfsf.c @@ -1,8 +1,12 @@ #include +#include #include #include #include =20 +#define MTFSF(FLM, FRB) asm volatile ("mtfsf %0, %1" :: "i" (FLM), "f" (FR= B)) +#define MFFS(FRT) asm("mffs %0" : "=3Df" (FRT)) + #define FPSCR_VE 7 /* Floating-point invalid operation exception enab= le */ #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (sof= t) */ #define FPSCR_FI 17 /* Floating-point fraction inexact = */ @@ -21,10 +25,7 @@ void sigfpe_handler(int sig, siginfo_t *si, void *uconte= xt) =20 int main(void) { - union { - double d; - long long ll; - } fpscr; + uint64_t fpscr; =20 struct sigaction sa =3D { .sa_sigaction =3D sigfpe_handler, @@ -40,10 +41,9 @@ int main(void) prctl(PR_SET_FPEXC, PR_FP_EXC_PRECISE); =20 /* First test if the FI bit is being set correctly */ - fpscr.ll =3D FP_FI; - __builtin_mtfsf(0b11111111, fpscr.d); - fpscr.d =3D __builtin_mffs(); - assert((fpscr.ll & FP_FI) !=3D 0); + MTFSF(0b11111111, FP_FI); + MFFS(fpscr); + assert((fpscr & FP_FI) !=3D 0); =20 /* Then test if the deferred exception is being called correctly */ sigaction(SIGFPE, &sa, NULL); @@ -54,8 +54,7 @@ int main(void) * But if a different exception is chosen si_code check should * change accordingly. */ - fpscr.ll =3D FP_VE | FP_VXSOFT; - __builtin_mtfsf(0b11111111, fpscr.d); + MTFSF(0b11111111, FP_VE | FP_VXSOFT); =20 return 1; } --=20 2.25.1 From nobody Sun May 19 00:17:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646417376655201.93502859951434; Fri, 4 Mar 2022 10:09:36 -0800 (PST) Received: from localhost ([::1]:37754 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nQCMx-00066X-7c for importer@patchew.org; Fri, 04 Mar 2022 13:09:35 -0500 Received: from eggs.gnu.org ([209.51.188.92]:54390) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nQBCQ-0008Up-QK; Fri, 04 Mar 2022 11:54:38 -0500 Received: from [187.72.171.209] (port=61123 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nQBCP-0004rt-5o; Fri, 04 Mar 2022 11:54:38 -0500 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Fri, 4 Mar 2022 13:54:26 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id 3C5BD8001C2; Fri, 4 Mar 2022 13:54:26 -0300 (-03) From: matheus.ferst@eldorado.org.br To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v3 2/5] target/ppc: change xs[n]madd[am]sp to use float64r32_muladd Date: Fri, 4 Mar 2022 13:54:14 -0300 Message-Id: <20220304165417.1981159-3-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220304165417.1981159-1-matheus.ferst@eldorado.org.br> References: <20220304165417.1981159-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 04 Mar 2022 16:54:26.0617 (UTC) FILETIME=[81ED7290:01D82FE8] X-Host-Lookup-Failed: Reverse DNS lookup failed for 187.72.171.209 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=187.72.171.209; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.659, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thuth@redhat.com, Matheus Ferst , danielhb413@gmail.com, richard.henderson@linaro.org, groug@kaod.org, philippe.mathieu.daude@gmail.com, clg@kaod.org, mrezanin@redhat.com, alex.bennee@linaro.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1646417377817100001 Content-Type: text/plain; charset="utf-8" From: Matheus Ferst Change VSX Scalar Multiply-Add/Subtract Type-A/M Single Precision helpers to use float64r32_muladd. This method should correctly handle all rounding modes, so the workaround for float_round_nearest_even can be dropped. Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- v3: - Removed unrelated changes; --- target/ppc/fpu_helper.c | 54 ++++++++++++++--------------------------- 1 file changed, 18 insertions(+), 36 deletions(-) diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c index 8f970288f5..2cad05c9cf 100644 --- a/target/ppc/fpu_helper.c +++ b/target/ppc/fpu_helper.c @@ -2156,9 +2156,8 @@ VSX_TSQRT(xvtsqrtsp, 4, float32, VsrW(i), -126, 23) * maddflgs - flags for the float*muladd routine that control the * various forms (madd, msub, nmadd, nmsub) * sfprf - set FPRF - * r2sp - round intermediate double precision result to single precision */ -#define VSX_MADD(op, nels, tp, fld, maddflgs, sfprf, r2sp) = \ +#define VSX_MADD(op, nels, tp, fld, maddflgs, sfprf) = \ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, = \ ppc_vsr_t *s1, ppc_vsr_t *s2, ppc_vsr_t *s3) = \ { = \ @@ -2170,20 +2169,7 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, = \ for (i =3D 0; i < nels; i++) { = \ float_status tstat =3D env->fp_status; = \ set_float_exception_flags(0, &tstat); = \ - if (r2sp && (tstat.float_rounding_mode =3D=3D float_round_nearest_= even)) {\ - /* = \ - * Avoid double rounding errors by rounding the intermediate = \ - * result to odd. = \ - */ = \ - set_float_rounding_mode(float_round_to_zero, &tstat); = \ - t.fld =3D tp##_muladd(s1->fld, s3->fld, s2->fld, = \ - maddflgs, &tstat); = \ - t.fld |=3D (get_float_exception_flags(&tstat) & = \ - float_flag_inexact) !=3D 0; = \ - } else { = \ - t.fld =3D tp##_muladd(s1->fld, s3->fld, s2->fld, = \ - maddflgs, &tstat); = \ - } = \ + t.fld =3D tp##_muladd(s1->fld, s3->fld, s2->fld, maddflgs, &tstat)= ; \ env->fp_status.float_exception_flags |=3D tstat.float_exception_fl= ags; \ = \ if (unlikely(tstat.float_exception_flags & float_flag_invalid)) { = \ @@ -2191,10 +2177,6 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, = \ sfprf, GETPC()); = \ } = \ = \ - if (r2sp) { = \ - t.fld =3D do_frsp(env, t.fld, GETPC()); = \ - } = \ - = \ if (sfprf) { = \ helper_compute_fprf_float64(env, t.fld); = \ } = \ @@ -2203,24 +2185,24 @@ void helper_##op(CPUPPCState *env, ppc_vsr_t *xt, = \ do_float_check_status(env, GETPC()); = \ } =20 -VSX_MADD(XSMADDDP, 1, float64, VsrD(0), MADD_FLGS, 1, 0) -VSX_MADD(XSMSUBDP, 1, float64, VsrD(0), MSUB_FLGS, 1, 0) -VSX_MADD(XSNMADDDP, 1, float64, VsrD(0), NMADD_FLGS, 1, 0) -VSX_MADD(XSNMSUBDP, 1, float64, VsrD(0), NMSUB_FLGS, 1, 0) -VSX_MADD(XSMADDSP, 1, float64, VsrD(0), MADD_FLGS, 1, 1) -VSX_MADD(XSMSUBSP, 1, float64, VsrD(0), MSUB_FLGS, 1, 1) -VSX_MADD(XSNMADDSP, 1, float64, VsrD(0), NMADD_FLGS, 1, 1) -VSX_MADD(XSNMSUBSP, 1, float64, VsrD(0), NMSUB_FLGS, 1, 1) +VSX_MADD(XSMADDDP, 1, float64, VsrD(0), MADD_FLGS, 1) +VSX_MADD(XSMSUBDP, 1, float64, VsrD(0), MSUB_FLGS, 1) +VSX_MADD(XSNMADDDP, 1, float64, VsrD(0), NMADD_FLGS, 1) +VSX_MADD(XSNMSUBDP, 1, float64, VsrD(0), NMSUB_FLGS, 1) +VSX_MADD(XSMADDSP, 1, float64r32, VsrD(0), MADD_FLGS, 1) +VSX_MADD(XSMSUBSP, 1, float64r32, VsrD(0), MSUB_FLGS, 1) +VSX_MADD(XSNMADDSP, 1, float64r32, VsrD(0), NMADD_FLGS, 1) +VSX_MADD(XSNMSUBSP, 1, float64r32, VsrD(0), NMSUB_FLGS, 1) =20 -VSX_MADD(xvmadddp, 2, float64, VsrD(i), MADD_FLGS, 0, 0) -VSX_MADD(xvmsubdp, 2, float64, VsrD(i), MSUB_FLGS, 0, 0) -VSX_MADD(xvnmadddp, 2, float64, VsrD(i), NMADD_FLGS, 0, 0) -VSX_MADD(xvnmsubdp, 2, float64, VsrD(i), NMSUB_FLGS, 0, 0) +VSX_MADD(xvmadddp, 2, float64, VsrD(i), MADD_FLGS, 0) +VSX_MADD(xvmsubdp, 2, float64, VsrD(i), MSUB_FLGS, 0) +VSX_MADD(xvnmadddp, 2, float64, VsrD(i), NMADD_FLGS, 0) +VSX_MADD(xvnmsubdp, 2, float64, VsrD(i), NMSUB_FLGS, 0) =20 -VSX_MADD(xvmaddsp, 4, float32, VsrW(i), MADD_FLGS, 0, 0) -VSX_MADD(xvmsubsp, 4, float32, VsrW(i), MSUB_FLGS, 0, 0) -VSX_MADD(xvnmaddsp, 4, float32, VsrW(i), NMADD_FLGS, 0, 0) -VSX_MADD(xvnmsubsp, 4, float32, VsrW(i), NMSUB_FLGS, 0, 0) +VSX_MADD(xvmaddsp, 4, float32, VsrW(i), MADD_FLGS, 0) +VSX_MADD(xvmsubsp, 4, float32, VsrW(i), MSUB_FLGS, 0) +VSX_MADD(xvnmaddsp, 4, float32, VsrW(i), NMADD_FLGS, 0) +VSX_MADD(xvnmsubsp, 4, float32, VsrW(i), NMSUB_FLGS, 0) =20 /* * VSX_MADDQ - VSX floating point quad-precision muliply/add --=20 2.25.1 From nobody Sun May 19 00:17:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646415293019817.7545977133124; Fri, 4 Mar 2022 09:34:53 -0800 (PST) Received: from localhost ([::1]:60710 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nQBpM-0004aO-Fr for importer@patchew.org; Fri, 04 Mar 2022 12:34:52 -0500 Received: from eggs.gnu.org ([209.51.188.92]:54404) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nQBCT-0000Du-Bv; Fri, 04 Mar 2022 11:54:41 -0500 Received: from [187.72.171.209] (port=61123 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nQBCR-0004rt-O1; Fri, 04 Mar 2022 11:54:41 -0500 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Fri, 4 Mar 2022 13:54:26 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id 90E0C800502; Fri, 4 Mar 2022 13:54:26 -0300 (-03) From: matheus.ferst@eldorado.org.br To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v3 3/5] tests/tcg/ppc64le: drop __int128 usage in bcdsub Date: Fri, 4 Mar 2022 13:54:15 -0300 Message-Id: <20220304165417.1981159-4-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220304165417.1981159-1-matheus.ferst@eldorado.org.br> References: <20220304165417.1981159-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 04 Mar 2022 16:54:26.0992 (UTC) FILETIME=[8226AB00:01D82FE8] X-Host-Lookup-Failed: Reverse DNS lookup failed for 187.72.171.209 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=187.72.171.209; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.659, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thuth@redhat.com, Matheus Ferst , danielhb413@gmail.com, richard.henderson@linaro.org, groug@kaod.org, philippe.mathieu.daude@gmail.com, clg@kaod.org, mrezanin@redhat.com, alex.bennee@linaro.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1646415294673100001 Content-Type: text/plain; charset="utf-8" From: Matheus Ferst Using __int128 with inline asm constraints like "v" generates incorrect code when compiling with LLVM/Clang (e.g., only one doubleword of the VSR is loaded). Instead, use a GPR pair to pass the 128-bits value and load the VSR with mtvsrd/xxmrghd. Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- tests/tcg/ppc64le/bcdsub.c | 123 +++++++++++++++++-------------------- 1 file changed, 58 insertions(+), 65 deletions(-) diff --git a/tests/tcg/ppc64le/bcdsub.c b/tests/tcg/ppc64le/bcdsub.c index 8c188cae6d..12da19b78e 100644 --- a/tests/tcg/ppc64le/bcdsub.c +++ b/tests/tcg/ppc64le/bcdsub.c @@ -1,6 +1,7 @@ #include #include #include +#include =20 #define CRF_LT (1 << 3) #define CRF_GT (1 << 2) @@ -8,24 +9,39 @@ #define CRF_SO (1 << 0) #define UNDEF 0 =20 -#define BCDSUB(vra, vrb, ps) \ - asm ("bcdsub. %1,%2,%3,%4;" \ - "mfocrf %0,0b10;" \ - : "=3Dr" (cr), "=3Dv" (vrt) \ - : "v" (vra), "v" (vrb), "i" (ps) \ - : ); +/* + * Use GPR pairs to load the VSR values and place the resulting VSR and CR= 6 in + * th, tl, and cr. Note that we avoid newer instructions (e.g., mtvsrdd/mf= vsrld) + * so we can run this test on POWER8 machines. + */ +#define BCDSUB(AH, AL, BH, BL, PS) \ + asm ("mtvsrd 32, %3\n\t" \ + "mtvsrd 33, %4\n\t" \ + "xxmrghd 32, 32, 33\n\t" \ + "mtvsrd 33, %5\n\t" \ + "mtvsrd 34, %6\n\t" \ + "xxmrghd 33, 33, 34\n\t" \ + "bcdsub. 0, 0, 1, %7\n\t" \ + "mfocrf %0, 0b10\n\t" \ + "mfvsrd %1, 32\n\t" \ + "xxswapd 32, 32\n\t" \ + "mfvsrd %2, 32\n\t" \ + : "=3Dr" (cr), "=3Dr" (th), "=3Dr" (tl) \ + : "r" (AH), "r" (AL), "r" (BH), "r" (BL), "i" (PS) \ + : "v0", "v1", "v2"); =20 -#define TEST(vra, vrb, ps, exp_res, exp_cr6) \ +#define TEST(AH, AL, BH, BL, PS, TH, TL, CR6) \ do { \ - __int128 vrt =3D 0; \ int cr =3D 0; \ - BCDSUB(vra, vrb, ps); \ - if (exp_res) \ - assert(vrt =3D=3D exp_res); \ - assert((cr >> 4) =3D=3D exp_cr6); \ + uint64_t th, tl; \ + BCDSUB(AH, AL, BH, BL, PS); \ + if (TH !=3D UNDEF || TL !=3D UNDEF) { \ + assert(tl =3D=3D TL); \ + assert(th =3D=3D TH); \ + } \ + assert((cr >> 4) =3D=3D CR6); \ } while (0) =20 - /* * Unbounded result is equal to zero: * sign =3D (PS) ? 0b1111 : 0b1100 @@ -33,13 +49,13 @@ */ void test_bcdsub_eq(void) { - __int128 a, b; - /* maximum positive BCD value */ - a =3D b =3D (((__int128) 0x9999999999999999) << 64 | 0x999999999999999= c); - - TEST(a, b, 0, 0xc, CRF_EQ); - TEST(a, b, 1, 0xf, CRF_EQ); + TEST(0x9999999999999999, 0x999999999999999c, + 0x9999999999999999, 0x999999999999999c, + 0, 0x0, 0xc, CRF_EQ); + TEST(0x9999999999999999, 0x999999999999999c, + 0x9999999999999999, 0x999999999999999c, + 1, 0x0, 0xf, CRF_EQ); } =20 /* @@ -49,21 +65,16 @@ void test_bcdsub_eq(void) */ void test_bcdsub_gt(void) { - __int128 a, b, c; + /* maximum positive and negative one BCD values */ + TEST(0x9999999999999999, 0x999999999999999c, 0x0, 0x1d, 0, + 0x0, 0xc, (CRF_GT | CRF_SO)); + TEST(0x9999999999999999, 0x999999999999999c, 0x0, 0x1d, 1, + 0x0, 0xf, (CRF_GT | CRF_SO)); =20 - /* maximum positive BCD value */ - a =3D (((__int128) 0x9999999999999999) << 64 | 0x999999999999999c); - - /* negative one BCD value */ - b =3D (__int128) 0x1d; - - TEST(a, b, 0, 0xc, (CRF_GT | CRF_SO)); - TEST(a, b, 1, 0xf, (CRF_GT | CRF_SO)); - - c =3D (((__int128) 0x9999999999999999) << 64 | 0x999999999999998c); - - TEST(c, b, 0, a, CRF_GT); - TEST(c, b, 1, (a | 0x3), CRF_GT); + TEST(0x9999999999999999, 0x999999999999998c, 0x0, 0x1d, 0, + 0x9999999999999999, 0x999999999999999c, CRF_GT); + TEST(0x9999999999999999, 0x999999999999998c, 0x0, 0x1d, 1, + 0x9999999999999999, 0x999999999999999f, CRF_GT); } =20 /* @@ -73,45 +84,27 @@ void test_bcdsub_gt(void) */ void test_bcdsub_lt(void) { - __int128 a, b; + /* positive zero and positive one BCD values */ + TEST(0x0, 0xc, 0x0, 0x1c, 0, 0x0, 0x1d, CRF_LT); + TEST(0x0, 0xc, 0x0, 0x1c, 1, 0x0, 0x1d, CRF_LT); =20 - /* positive zero BCD value */ - a =3D (__int128) 0xc; - - /* positive one BCD value */ - b =3D (__int128) 0x1c; - - TEST(a, b, 0, 0x1d, CRF_LT); - TEST(a, b, 1, 0x1d, CRF_LT); - - /* maximum negative BCD value */ - a =3D (((__int128) 0x9999999999999999) << 64 | 0x999999999999999d); - - /* positive one BCD value */ - b =3D (__int128) 0x1c; - - TEST(a, b, 0, 0xd, (CRF_LT | CRF_SO)); - TEST(a, b, 1, 0xd, (CRF_LT | CRF_SO)); + /* maximum negative and positive one BCD values */ + TEST(0x9999999999999999, 0x999999999999999d, 0x0, 0x1c, 0, + 0x0, 0xd, (CRF_LT | CRF_SO)); + TEST(0x9999999999999999, 0x999999999999999d, 0x0, 0x1c, 1, + 0x0, 0xd, (CRF_LT | CRF_SO)); } =20 void test_bcdsub_invalid(void) { - __int128 a, b; + TEST(0x0, 0x1c, 0x0, 0xf00, 0, UNDEF, UNDEF, CRF_SO); + TEST(0x0, 0x1c, 0x0, 0xf00, 1, UNDEF, UNDEF, CRF_SO); =20 - /* positive one BCD value */ - a =3D (__int128) 0x1c; - b =3D 0xf00; + TEST(0x0, 0xf00, 0x0, 0x1c, 0, UNDEF, UNDEF, CRF_SO); + TEST(0x0, 0xf00, 0x0, 0x1c, 1, UNDEF, UNDEF, CRF_SO); =20 - TEST(a, b, 0, UNDEF, CRF_SO); - TEST(a, b, 1, UNDEF, CRF_SO); - - TEST(b, a, 0, UNDEF, CRF_SO); - TEST(b, a, 1, UNDEF, CRF_SO); - - a =3D 0xbad; - - TEST(a, b, 0, UNDEF, CRF_SO); - TEST(a, b, 1, UNDEF, CRF_SO); + TEST(0x0, 0xbad, 0x0, 0xf00, 0, UNDEF, UNDEF, CRF_SO); + TEST(0x0, 0xbad, 0x0, 0xf00, 1, UNDEF, UNDEF, CRF_SO); } =20 int main(void) --=20 2.25.1 From nobody Sun May 19 00:17:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646416561699797.6086950174397; Fri, 4 Mar 2022 09:56:01 -0800 (PST) Received: from localhost ([::1]:45316 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nQC9p-0007zT-4J for importer@patchew.org; Fri, 04 Mar 2022 12:56:01 -0500 Received: from eggs.gnu.org ([209.51.188.92]:54418) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nQBCW-0000Mz-0M; Fri, 04 Mar 2022 11:54:44 -0500 Received: from [187.72.171.209] (port=61123 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nQBCU-0004rt-B0; Fri, 04 Mar 2022 11:54:43 -0500 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Fri, 4 Mar 2022 13:54:27 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id EC16E8001C2; Fri, 4 Mar 2022 13:54:26 -0300 (-03) From: matheus.ferst@eldorado.org.br To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v3 4/5] tests/tcg/ppc64le: emit bcdsub with .long when needed Date: Fri, 4 Mar 2022 13:54:16 -0300 Message-Id: <20220304165417.1981159-5-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220304165417.1981159-1-matheus.ferst@eldorado.org.br> References: <20220304165417.1981159-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 04 Mar 2022 16:54:27.0382 (UTC) FILETIME=[82622D60:01D82FE8] X-Host-Lookup-Failed: Reverse DNS lookup failed for 187.72.171.209 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=187.72.171.209; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.659, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thuth@redhat.com, Matheus Ferst , danielhb413@gmail.com, richard.henderson@linaro.org, groug@kaod.org, philippe.mathieu.daude@gmail.com, clg@kaod.org, mrezanin@redhat.com, alex.bennee@linaro.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1646416564196100001 Content-Type: text/plain; charset="utf-8" From: Matheus Ferst Based on GCC docs[1], we use the '-mpower8-vector' flag at config-time to detect the toolchain support to the bcdsub instruction. LLVM/Clang supports this flag since version 3.6[2], but the instruction and related builtins were only added in LLVM 14[3]. In the absence of other means to detect this support at config-time, we resort to __has_builtin to identify the presence of __builtin_bcdsub at compile-time. If the builtin is not available, the instruction is emitted with a ".long". [1] https://gcc.gnu.org/onlinedocs/gcc-8.3.0/gcc/PowerPC-AltiVec_002fVSX-Bu= ilt-in-Functions.html [2] https://github.com/llvm/llvm-project/commit/59eb767e11d4ffefb5f55409524= e5c8416b2b0db [3] https://github.com/llvm/llvm-project/commit/c933c2eb334660c131f4afc9d19= 4fafb0cec0423 Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- v3: - Fixed __has_builtin check. --- tests/tcg/ppc64le/bcdsub.c | 71 ++++++++++++++++++++++---------------- 1 file changed, 41 insertions(+), 30 deletions(-) diff --git a/tests/tcg/ppc64le/bcdsub.c b/tests/tcg/ppc64le/bcdsub.c index 12da19b78e..87c8c44a44 100644 --- a/tests/tcg/ppc64le/bcdsub.c +++ b/tests/tcg/ppc64le/bcdsub.c @@ -9,37 +9,48 @@ #define CRF_SO (1 << 0) #define UNDEF 0 =20 -/* - * Use GPR pairs to load the VSR values and place the resulting VSR and CR= 6 in - * th, tl, and cr. Note that we avoid newer instructions (e.g., mtvsrdd/mf= vsrld) - * so we can run this test on POWER8 machines. - */ -#define BCDSUB(AH, AL, BH, BL, PS) \ - asm ("mtvsrd 32, %3\n\t" \ - "mtvsrd 33, %4\n\t" \ - "xxmrghd 32, 32, 33\n\t" \ - "mtvsrd 33, %5\n\t" \ - "mtvsrd 34, %6\n\t" \ - "xxmrghd 33, 33, 34\n\t" \ - "bcdsub. 0, 0, 1, %7\n\t" \ - "mfocrf %0, 0b10\n\t" \ - "mfvsrd %1, 32\n\t" \ - "xxswapd 32, 32\n\t" \ - "mfvsrd %2, 32\n\t" \ - : "=3Dr" (cr), "=3Dr" (th), "=3Dr" (tl) \ - : "r" (AH), "r" (AL), "r" (BH), "r" (BL), "i" (PS) \ - : "v0", "v1", "v2"); +#ifdef __has_builtin +#if !__has_builtin(__builtin_bcdsub) +#define NO_BUILTIN_BCDSUB +#endif +#endif =20 -#define TEST(AH, AL, BH, BL, PS, TH, TL, CR6) \ - do { \ - int cr =3D 0; \ - uint64_t th, tl; \ - BCDSUB(AH, AL, BH, BL, PS); \ - if (TH !=3D UNDEF || TL !=3D UNDEF) { \ - assert(tl =3D=3D TL); \ - assert(th =3D=3D TH); \ - } \ - assert((cr >> 4) =3D=3D CR6); \ +#ifdef NO_BUILTIN_BCDSUB +#define BCDSUB(T, A, B, PS) \ + ".long 4 << 26 | (" #T ") << 21 | (" #A ") << 16 | (" #B ") << 11" \ + " | 1 << 10 | (" #PS ") << 9 | 65\n\t" +#else +#define BCDSUB(T, A, B, PS) "bcdsub. " #T ", " #A ", " #B ", " #PS "\n\t" +#endif + +#define TEST(AH, AL, BH, BL, PS, TH, TL, CR6) = \ + do { = \ + int cr =3D 0; = \ + uint64_t th, tl; = \ + /* = \ + * Use GPR pairs to load the VSR values and place the resulting VS= R and\ + * CR6 in th, tl, and cr. Note that we avoid newer instructions (e= .g., \ + * mtvsrdd/mfvsrld) so we can run this test on POWER8 machines. = \ + */ = \ + asm ("mtvsrd 32, %3\n\t" = \ + "mtvsrd 33, %4\n\t" = \ + "xxmrghd 32, 32, 33\n\t" = \ + "mtvsrd 33, %5\n\t" = \ + "mtvsrd 34, %6\n\t" = \ + "xxmrghd 33, 33, 34\n\t" = \ + BCDSUB(0, 0, 1, PS) = \ + "mfocrf %0, 0b10\n\t" = \ + "mfvsrd %1, 32\n\t" = \ + "xxswapd 32, 32\n\t" = \ + "mfvsrd %2, 32\n\t" = \ + : "=3Dr" (cr), "=3Dr" (th), "=3Dr" (tl) = \ + : "r" (AH), "r" (AL), "r" (BH), "r" (BL) = \ + : "v0", "v1", "v2"); = \ + if (TH !=3D UNDEF || TL !=3D UNDEF) { = \ + assert(tl =3D=3D TL); = \ + assert(th =3D=3D TH); = \ + } = \ + assert((cr >> 4) =3D=3D CR6); = \ } while (0) =20 /* --=20 2.25.1 From nobody Sun May 19 00:17:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646415631144559.8164834725737; Fri, 4 Mar 2022 09:40:31 -0800 (PST) Received: from localhost ([::1]:43684 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nQBun-0003rr-FH for importer@patchew.org; Fri, 04 Mar 2022 12:40:29 -0500 Received: from eggs.gnu.org ([209.51.188.92]:54436) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nQBCY-0000Vu-DI; Fri, 04 Mar 2022 11:54:46 -0500 Received: from [187.72.171.209] (port=61123 helo=outlook.eldorado.org.br) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nQBCW-0004rt-TE; Fri, 04 Mar 2022 11:54:46 -0500 Received: from p9ibm ([10.10.71.235]) by outlook.eldorado.org.br over TLS secured channel with Microsoft SMTPSVC(8.5.9600.16384); Fri, 4 Mar 2022 13:54:27 -0300 Received: from eldorado.org.br (unknown [10.10.70.45]) by p9ibm (Postfix) with ESMTP id 52E81800502; Fri, 4 Mar 2022 13:54:27 -0300 (-03) From: matheus.ferst@eldorado.org.br To: qemu-devel@nongnu.org, qemu-ppc@nongnu.org Subject: [PATCH v3 5/5] tests/tcg/ppc64le: Use Altivec register names in clobber list Date: Fri, 4 Mar 2022 13:54:17 -0300 Message-Id: <20220304165417.1981159-6-matheus.ferst@eldorado.org.br> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220304165417.1981159-1-matheus.ferst@eldorado.org.br> References: <20220304165417.1981159-1-matheus.ferst@eldorado.org.br> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-OriginalArrivalTime: 04 Mar 2022 16:54:27.0711 (UTC) FILETIME=[829460F0:01D82FE8] X-Host-Lookup-Failed: Reverse DNS lookup failed for 187.72.171.209 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=187.72.171.209; envelope-from=matheus.ferst@eldorado.org.br; helo=outlook.eldorado.org.br X-Spam_score_int: -4 X-Spam_score: -0.5 X-Spam_bar: / X-Spam_report: (-0.5 / 5.0 requ) BAYES_00=-1.9, PDS_HP_HELO_NORDNS=0.659, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: thuth@redhat.com, Matheus Ferst , danielhb413@gmail.com, richard.henderson@linaro.org, groug@kaod.org, philippe.mathieu.daude@gmail.com, clg@kaod.org, mrezanin@redhat.com, alex.bennee@linaro.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1646415632154100001 Content-Type: text/plain; charset="utf-8" From: Matheus Ferst LLVM/Clang doesn't know the VSX registers when compiling with -mabi=3Delfv1. Use only registers >=3D 32 and list them with their Altivec name. Reviewed-by: Richard Henderson Signed-off-by: Matheus Ferst --- tests/tcg/ppc64le/non_signalling_xscv.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/tests/tcg/ppc64le/non_signalling_xscv.c b/tests/tcg/ppc64le/no= n_signalling_xscv.c index 91e25cad46..836df71ef0 100644 --- a/tests/tcg/ppc64le/non_signalling_xscv.c +++ b/tests/tcg/ppc64le/non_signalling_xscv.c @@ -6,16 +6,16 @@ #define TEST(INSN, B_HI, B_LO, T_HI, T_LO) \ do { \ uint64_t th, tl, bh =3D B_HI, bl =3D B_LO; = \ - asm("mtvsrd 0, %2\n\t" \ - "mtvsrd 1, %3\n\t" \ - "xxmrghd 0, 0, 1\n\t" \ - INSN " 0, 0\n\t" \ - "mfvsrd %0, 0\n\t" \ - "xxswapd 0, 0\n\t" \ - "mfvsrd %1, 0\n\t" \ + asm("mtvsrd 32, %2\n\t" \ + "mtvsrd 33, %3\n\t" \ + "xxmrghd 32, 32, 33\n\t" \ + INSN " 32, 32\n\t" \ + "mfvsrd %0, 32\n\t" \ + "xxswapd 32, 32\n\t" \ + "mfvsrd %1, 32\n\t" \ : "=3Dr" (th), "=3Dr" (tl) = \ : "r" (bh), "r" (bl) \ - : "vs0", "vs1"); \ + : "v0", "v1"); \ printf(INSN "(0x%016" PRIx64 "%016" PRIx64 ") =3D 0x%016" PRIx64 \ "%016" PRIx64 "\n", bh, bl, th, tl); \ assert(th =3D=3D T_HI && tl =3D=3D T_LO); = \ --=20 2.25.1