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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id t5-20020adff045000000b001f0684c3404sm517060wro.11.2022.03.03.12.23.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 12:23:46 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=BwQur4NZBGGWfHrVPMLWwKCyDvLwx3c9PUY0EKxgx9k=; b=dnTyXeu1Yaiit8GnHMv0BTLnhMuUWGKjNnwyZ6lmKiSXTrd+TuVV72sNBvqSS0Ag2A FpRdeJ8+7KgV5TH1M+5jE3/WhiWhRkN6Z0eS5SMiq7U7HC6uI7qA0Tnia6vZjdYYD/ug m2o+ls1iCbirTUg2um/VeaHHHRsySaA0pjQLLgXpWLtO/lAYbHKpq1dbt9hi1mtHSXRW vwm2Xy32mAsNEY92jj66Op34Ml06WTblylElZNSXPYGwQ8q8Rkom21gNc30fTkt/sdBV QKViKUiamVLpiHg5ViTa3hY7QYuTho/Esctg/cDBGPZBYu4FdDK4FwEFV/QjApQw4n1c RERw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BwQur4NZBGGWfHrVPMLWwKCyDvLwx3c9PUY0EKxgx9k=; b=MMbYm85Jp5FMKtGKLxsg+1naAPtxcyt7k476+mkyx3MQeQ2+pYGHA+uHmKf5af7OPD 5mh4PgrAneBmpPZI6orqEm2FR5/UDxzyUWvP3qaa6lmNzFXDNsgoyRdRJMRzc624qfsY 9exoPoNL2mmZo0Tx+iFMd2i2vZQvQ1yj+y4Tx4XALGhT77X2Mi07g/tO/gc7fRYosJvC lpsP/bcx/Ca9jxzTPpTYFubbmFpstzUrpBZdadMbYfEtxAe79afybJzoULMWPn3YUJN1 H3mIfxqJKi/rBRxtwZ8VIGM9nztFcX/8NJJrmLNxrnCgJmjnn5+a9X93wiylWJKgBa4z YqHQ== X-Gm-Message-State: AOAM533Vrx8SfFAznoTblvpX60S77EGAugPZP6cQP/j4eh8eQ3IUJ5zd GWkk+0IQ5sbw9s7Cd9BOXxYTyA== X-Google-Smtp-Source: ABdhPJyIFJEbFCXFrAXAG1V1cE8DNT7nazsjswnKzudAkRbKp1jRdK2zDTzw8dyoRDzIgjoihXVvbg== X-Received: by 2002:a05:600c:3d0b:b0:382:aa17:8f16 with SMTP id bh11-20020a05600c3d0b00b00382aa178f16mr5025218wmb.82.1646339027128; Thu, 03 Mar 2022 12:23:47 -0800 (PST) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 3/5] hw/intc/arm_gicv3: Specify valid and impl in MemoryRegionOps Date: Thu, 3 Mar 2022 20:23:39 +0000 Message-Id: <20220303202341.2232284-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303202341.2232284-1-peter.maydell@linaro.org> References: <20220303202341.2232284-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32e (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1646339143396100001 Content-Type: text/plain; charset="utf-8" The GICv3 has some registers that support byte accesses, and some that support 8-byte accesses. Our TCG implementation implements all of this, switching on the 'size' argument and handling the registers that must support reads of that size while logging an error for attempted accesses to registers that do not support that size access. However we forgot to tell the core memory subsystem about this by specifying the .impl and .valid fields in the MemoryRegionOps struct, so the core was happily simulating 8 byte accesses by combining two 4 byte accesses. This doesn't have much guest-visible effect, since there aren't many 8 byte registers and they all support being written in two 4 byte parts. Set the .impl and .valid fields to say that all sizes from 1 to 8 bytes are both valid and implemented by the device. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3.c | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c index 6d3c8ee231c..0b8f79a1227 100644 --- a/hw/intc/arm_gicv3.c +++ b/hw/intc/arm_gicv3.c @@ -369,11 +369,19 @@ static const MemoryRegionOps gic_ops[] =3D { .read_with_attrs =3D gicv3_dist_read, .write_with_attrs =3D gicv3_dist_write, .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 8, + .impl.min_access_size =3D 1, + .impl.max_access_size =3D 8, }, { .read_with_attrs =3D gicv3_redist_read, .write_with_attrs =3D gicv3_redist_write, .endianness =3D DEVICE_NATIVE_ENDIAN, + .valid.min_access_size =3D 1, + .valid.max_access_size =3D 8, + .impl.min_access_size =3D 1, + .impl.max_access_size =3D 8, } }; =20 --=20 2.25.1