From nobody Mon May 13 20:50:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646335280499613.7672470003725; Thu, 3 Mar 2022 11:21:20 -0800 (PST) Received: from localhost ([::1]:37882 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nPr0p-000780-Fl for importer@patchew.org; Thu, 03 Mar 2022 14:21:19 -0500 Received: from eggs.gnu.org ([209.51.188.92]:59986) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nPqvo-0001qk-DK for qemu-devel@nongnu.org; Thu, 03 Mar 2022 14:16:08 -0500 Received: from [2607:f8b0:4864:20::533] (port=39737 helo=mail-pg1-x533.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nPqvk-0007SM-0E for qemu-devel@nongnu.org; Thu, 03 Mar 2022 14:16:07 -0500 Received: by mail-pg1-x533.google.com with SMTP id 195so5461867pgc.6 for ; Thu, 03 Mar 2022 11:15:56 -0800 (PST) Received: from localhost.localdomain (2603-800c-1201-c600-119c-490c-a4ee-08e8.res6.spectrum.com. [2603:800c:1201:c600:119c:490c:a4ee:8e8]) by smtp.gmail.com with ESMTPSA id u25-20020a62ed19000000b004f140515d56sm3318043pfh.46.2022.03.03.11.15.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 11:15:54 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eYMPBK8uImUtEf60mqBA0vpSt2l5oNERr0mQgdkY/9s=; b=kqh4zXoSucppFDZzorR9VmtyuwDk+wZFTR46pccKn45uGw9xbCvRD7lktc5gtRNEwx w3moOjeWVxlx1l1g41iP1cC1QyCulXhXfK4Y07D7J3/CbZWadAWARHNAFr+Q1yuYkXXV HOmFxtrv178UrXvrG5O4M621iAm8tqYy9Onau5lTJIYSY8f3TWVmTYuhuoBpvJDiKZ7D 1fvfcxbNO4qwvgZCBBiPxc6C9DFhgPs30QxuRL1Z44O/7cySVstCwQrx5RHrzkGnYW2g mEl9AxVgKDovxDfwn5N111IFhZtdNsUHe6ZB9YuDixlGfEIeRYdl/emxVNETbISjJ0eT RksA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eYMPBK8uImUtEf60mqBA0vpSt2l5oNERr0mQgdkY/9s=; b=jjPQIjV0ysssuZBPuSyOoI4L5Mxu1G2KsYUUrs7IVe0c0eGZYLjWkO6RDwtcWhQMrj W0d7dz8fJYbnT0ToS0CBfBkd3P3lLEF6oOTzt3YNo/43ilzn+k4vuvRLDLJXBybdeAQy UJGX03lVdnqoY59oiiiIuVXDzS4Rv2lcagEsOHPseyOdDQfuvnEaNF6m032tPT7KhS0P iBTb5RPNcQny1pmH3yfigq7NNCcoYksOyo90bdEbsBqjFtH/mSU2UjqPipNHLQGwEp3b mWuhvasVTQtoyoCl4ikD/CI/swhqmNJnjKICZqJMgetDfm9SHy55MpH0gOXWI/xuswq0 Rlug== X-Gm-Message-State: AOAM532Fzd9tuO+ki8x4jU3T8+T9+J6YwmZHNxcnrGE+updpUlEOCOLG aAPKoEj8d/CEORxs3aHXnLo3f6WXyRWa/g== X-Google-Smtp-Source: ABdhPJyymSb0EzkuwTvuX4+V1MolgevWKTMYohohrHXP6mVtPoB2CZ5GwsppHzQNMxi8OOg3lTq/bA== X-Received: by 2002:a05:6a00:1a07:b0:4f3:eba5:42ae with SMTP id g7-20020a056a001a0700b004f3eba542aemr28207748pfv.53.1646334955438; Thu, 03 Mar 2022 11:15:55 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 1/9] tcg: Add TCG_TARGET_SIGNED_ADDR32 Date: Thu, 3 Mar 2022 09:15:43 -1000 Message-Id: <20220303191551.466631-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303191551.466631-1-richard.henderson@linaro.org> References: <20220303191551.466631-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::533 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::533; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x533.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui , Alistair Francis , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646335281756100001 Define as 0 for all tcg hosts. Put this in a separate header, because we'll want this in places that do not ordinarily have access to all of tcg/tcg.h. Reviewed-by: WANG Xuerui Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target-sa32.h | 1 + tcg/arm/tcg-target-sa32.h | 1 + tcg/i386/tcg-target-sa32.h | 1 + tcg/loongarch64/tcg-target-sa32.h | 1 + tcg/mips/tcg-target-sa32.h | 1 + tcg/ppc/tcg-target-sa32.h | 1 + tcg/riscv/tcg-target-sa32.h | 1 + tcg/s390x/tcg-target-sa32.h | 1 + tcg/sparc/tcg-target-sa32.h | 1 + tcg/tci/tcg-target-sa32.h | 1 + tcg/tcg.c | 4 ++++ 11 files changed, 14 insertions(+) create mode 100644 tcg/aarch64/tcg-target-sa32.h create mode 100644 tcg/arm/tcg-target-sa32.h create mode 100644 tcg/i386/tcg-target-sa32.h create mode 100644 tcg/loongarch64/tcg-target-sa32.h create mode 100644 tcg/mips/tcg-target-sa32.h create mode 100644 tcg/ppc/tcg-target-sa32.h create mode 100644 tcg/riscv/tcg-target-sa32.h create mode 100644 tcg/s390x/tcg-target-sa32.h create mode 100644 tcg/sparc/tcg-target-sa32.h create mode 100644 tcg/tci/tcg-target-sa32.h diff --git a/tcg/aarch64/tcg-target-sa32.h b/tcg/aarch64/tcg-target-sa32.h new file mode 100644 index 0000000000..cb185b1526 --- /dev/null +++ b/tcg/aarch64/tcg-target-sa32.h @@ -0,0 +1 @@ +#define TCG_TARGET_SIGNED_ADDR32 0 diff --git a/tcg/arm/tcg-target-sa32.h b/tcg/arm/tcg-target-sa32.h new file mode 100644 index 0000000000..cb185b1526 --- /dev/null +++ b/tcg/arm/tcg-target-sa32.h @@ -0,0 +1 @@ +#define TCG_TARGET_SIGNED_ADDR32 0 diff --git a/tcg/i386/tcg-target-sa32.h b/tcg/i386/tcg-target-sa32.h new file mode 100644 index 0000000000..cb185b1526 --- /dev/null +++ b/tcg/i386/tcg-target-sa32.h @@ -0,0 +1 @@ +#define TCG_TARGET_SIGNED_ADDR32 0 diff --git a/tcg/loongarch64/tcg-target-sa32.h b/tcg/loongarch64/tcg-target= -sa32.h new file mode 100644 index 0000000000..cb185b1526 --- /dev/null +++ b/tcg/loongarch64/tcg-target-sa32.h @@ -0,0 +1 @@ +#define TCG_TARGET_SIGNED_ADDR32 0 diff --git a/tcg/mips/tcg-target-sa32.h b/tcg/mips/tcg-target-sa32.h new file mode 100644 index 0000000000..cb185b1526 --- /dev/null +++ b/tcg/mips/tcg-target-sa32.h @@ -0,0 +1 @@ +#define TCG_TARGET_SIGNED_ADDR32 0 diff --git a/tcg/ppc/tcg-target-sa32.h b/tcg/ppc/tcg-target-sa32.h new file mode 100644 index 0000000000..cb185b1526 --- /dev/null +++ b/tcg/ppc/tcg-target-sa32.h @@ -0,0 +1 @@ +#define TCG_TARGET_SIGNED_ADDR32 0 diff --git a/tcg/riscv/tcg-target-sa32.h b/tcg/riscv/tcg-target-sa32.h new file mode 100644 index 0000000000..cb185b1526 --- /dev/null +++ b/tcg/riscv/tcg-target-sa32.h @@ -0,0 +1 @@ +#define TCG_TARGET_SIGNED_ADDR32 0 diff --git a/tcg/s390x/tcg-target-sa32.h b/tcg/s390x/tcg-target-sa32.h new file mode 100644 index 0000000000..cb185b1526 --- /dev/null +++ b/tcg/s390x/tcg-target-sa32.h @@ -0,0 +1 @@ +#define TCG_TARGET_SIGNED_ADDR32 0 diff --git a/tcg/sparc/tcg-target-sa32.h b/tcg/sparc/tcg-target-sa32.h new file mode 100644 index 0000000000..cb185b1526 --- /dev/null +++ b/tcg/sparc/tcg-target-sa32.h @@ -0,0 +1 @@ +#define TCG_TARGET_SIGNED_ADDR32 0 diff --git a/tcg/tci/tcg-target-sa32.h b/tcg/tci/tcg-target-sa32.h new file mode 100644 index 0000000000..cb185b1526 --- /dev/null +++ b/tcg/tci/tcg-target-sa32.h @@ -0,0 +1 @@ +#define TCG_TARGET_SIGNED_ADDR32 0 diff --git a/tcg/tcg.c b/tcg/tcg.c index 33a97eabdb..8c131293fe 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -61,6 +61,10 @@ #include "exec/log.h" #include "tcg/tcg-ldst.h" #include "tcg-internal.h" +#include "tcg-target-sa32.h" + +/* Sanity check for TCG_TARGET_SIGNED_ADDR32. */ +QEMU_BUILD_BUG_ON(TCG_TARGET_REG_BITS =3D=3D 32 && TCG_TARGET_SIGNED_ADDR3= 2); =20 #ifdef CONFIG_TCG_INTERPRETER #include --=20 2.25.1 From nobody Mon May 13 20:50:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646335237976474.71563971968544; Thu, 3 Mar 2022 11:20:37 -0800 (PST) Received: from localhost ([::1]:35956 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nPr08-0005kq-U7 for importer@patchew.org; Thu, 03 Mar 2022 14:20:36 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60008) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nPqvo-0001sN-La for qemu-devel@nongnu.org; Thu, 03 Mar 2022 14:16:08 -0500 Received: from [2607:f8b0:4864:20::52b] (port=41813 helo=mail-pg1-x52b.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nPqvk-0007SQ-0B for qemu-devel@nongnu.org; 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[2603:800c:1201:c600:119c:490c:a4ee:8e8]) by smtp.gmail.com with ESMTPSA id u25-20020a62ed19000000b004f140515d56sm3318043pfh.46.2022.03.03.11.15.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 11:15:56 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=f5NF1Xhw+Erdj+thQwPRUzILFmSAD0uMaYQuiNMvI6I=; b=CTTYz6SRD4maCA0i70BHCznp+kU+4cuT7ar01WLuhcim92aPZHQaT5xcbtU7I1UEsn lxrlEgM05kKu4BX34Bnal8cfTXBwzh6spoDoMhBnFRybL64izNK/GKvRudfN+DtG7lCH hA1IwV2hRl5KRL/Pe0ht7p5oxrxWmrXn0ZHuoYFgz9eYKSsoeWLHyHvnzg1vL99pz5mK q8pP4HG3Bffm+yYMZjB0WKcY/ekDq4GPud49aPFYtwRW0Lj72Hegbj0Q3wtx9l3qbPZC Sw6ot4j7f/vwVsavaYHRNSoU6wp/6ucqGyHxYPII9428SA62pbCetMPcJ7e5vSB6EmIg lClw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=f5NF1Xhw+Erdj+thQwPRUzILFmSAD0uMaYQuiNMvI6I=; b=qwATwJjeN6I6pCzHgFs2YjKqMfwr8I+ckhz8/NHNdI5O1LMk3Vq6IRoPOC95eyoeY7 dWsaENOCK9BwR4fhhM1n7FX7BGWh4jhJe7564iIzA2VT8O1xDkJ8BlhAFW2hHQfNILhe BQkWhF7od+xpKCmCaIsv6MqJJs03hirL09JbfIGTtSqlsv/IswEtPVzTCV4d/sxrDag4 6R41OHjWkmkOO97GWBFMeiT2HvfnRkb5uJqTBByGOTWtffwnEAtkRxa52fLgePLDzJoW uvVBzvo6wL/QggLyUwriiNge8wmGbg1LxSplfcUXAQZuCfD1XHBdrHZfY3Ax1+pWD158 9Y3Q== X-Gm-Message-State: AOAM532Iu51fC82Bk8PSdnr4fQySlQ/87R0bxl/aiKjLzBRhoeyLkK2D EMzv4oUvw+5Rim2ZgRgIlKDBRIBQ8IbNsw== X-Google-Smtp-Source: ABdhPJxKmA2HQNTNxWCVgOioqII/Ou6aIh2R9erfQIjw0yVqUNNJqqZLxU2E3svFaxKGJjY1d8JaBA== X-Received: by 2002:a05:6a00:24c7:b0:4e1:cb76:32d1 with SMTP id d7-20020a056a0024c700b004e1cb7632d1mr39486434pfv.36.1646334956978; Thu, 03 Mar 2022 11:15:56 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 2/9] accel/tcg: Split out g2h_tlbe Date: Thu, 3 Mar 2022 09:15:44 -1000 Message-Id: <20220303191551.466631-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303191551.466631-1-richard.henderson@linaro.org> References: <20220303191551.466631-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::52b (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui , Alistair Francis , =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646335239225100001 Create a new function to combine a CPUTLBEntry addend with the guest address to form a host address. Reviewed-by: WANG Xuerui Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 24 ++++++++++++++---------- 1 file changed, 14 insertions(+), 10 deletions(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 3b918fe018..0e62aa5d7c 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -91,6 +91,11 @@ static inline size_t sizeof_tlb(CPUTLBDescFast *fast) return fast->mask + (1 << CPU_TLB_ENTRY_BITS); } =20 +static inline uintptr_t g2h_tlbe(const CPUTLBEntry *tlb, target_ulong gadd= r) +{ + return tlb->addend + (uintptr_t)gaddr; +} + static void tlb_window_reset(CPUTLBDesc *desc, int64_t ns, size_t max_entries) { @@ -986,8 +991,7 @@ static void tlb_reset_dirty_range_locked(CPUTLBEntry *t= lb_entry, =20 if ((addr & (TLB_INVALID_MASK | TLB_MMIO | TLB_DISCARD_WRITE | TLB_NOTDIRTY)) =3D=3D 0) { - addr &=3D TARGET_PAGE_MASK; - addr +=3D tlb_entry->addend; + addr =3D g2h_tlbe(tlb_entry, addr & TARGET_PAGE_MASK); if ((addr - start) < length) { #if TCG_OVERSIZED_GUEST tlb_entry->addr_write |=3D TLB_NOTDIRTY; @@ -1537,7 +1541,7 @@ tb_page_addr_t get_page_addr_code_hostp(CPUArchState = *env, target_ulong addr, return -1; } =20 - p =3D (void *)((uintptr_t)addr + entry->addend); + p =3D (void *)g2h_tlbe(entry, addr); if (hostp) { *hostp =3D p; } @@ -1629,7 +1633,7 @@ static int probe_access_internal(CPUArchState *env, t= arget_ulong addr, } =20 /* Everything else is RAM. */ - *phost =3D (void *)((uintptr_t)addr + entry->addend); + *phost =3D (void *)g2h_tlbe(entry, addr); return flags; } =20 @@ -1737,7 +1741,7 @@ bool tlb_plugin_lookup(CPUState *cpu, target_ulong ad= dr, int mmu_idx, data->v.io.offset =3D (iotlbentry->addr & TARGET_PAGE_MASK) + = addr; } else { data->is_io =3D false; - data->v.ram.hostaddr =3D (void *)((uintptr_t)addr + tlbe->adde= nd); + data->v.ram.hostaddr =3D (void *)g2h_tlbe(tlbe, addr); } return true; } else { @@ -1836,7 +1840,7 @@ static void *atomic_mmu_lookup(CPUArchState *env, tar= get_ulong addr, goto stop_the_world; } =20 - hostaddr =3D (void *)((uintptr_t)addr + tlbe->addend); + hostaddr =3D (void *)g2h_tlbe(tlbe, addr); =20 if (unlikely(tlb_addr & TLB_NOTDIRTY)) { notdirty_write(env_cpu(env), addr, size, @@ -1967,7 +1971,7 @@ load_helper(CPUArchState *env, target_ulong addr, Mem= OpIdx oi, access_type, op ^ (need_swap * MO_BSWAP)); } =20 - haddr =3D (void *)((uintptr_t)addr + entry->addend); + haddr =3D (void *)g2h_tlbe(entry, addr); =20 /* * Keep these two load_memop separate to ensure that the compiler @@ -2004,7 +2008,7 @@ load_helper(CPUArchState *env, target_ulong addr, Mem= OpIdx oi, return res & MAKE_64BIT_MASK(0, size * 8); } =20 - haddr =3D (void *)((uintptr_t)addr + entry->addend); + haddr =3D (void *)g2h_tlbe(entry, addr); return load_memop(haddr, op); } =20 @@ -2375,7 +2379,7 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, notdirty_write(env_cpu(env), addr, size, iotlbentry, retaddr); } =20 - haddr =3D (void *)((uintptr_t)addr + entry->addend); + haddr =3D (void *)g2h_tlbe(entry, addr); =20 /* * Keep these two store_memop separate to ensure that the compiler @@ -2400,7 +2404,7 @@ store_helper(CPUArchState *env, target_ulong addr, ui= nt64_t val, return; } =20 - haddr =3D (void *)((uintptr_t)addr + entry->addend); + haddr =3D (void *)g2h_tlbe(entry, addr); store_memop(haddr, val, op); } =20 --=20 2.25.1 From nobody Mon May 13 20:50:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1646335619; cv=none; d=zohomail.com; s=zohoarc; b=kDo/JxihQPTXM27rESbrTbZuiWqPpxDnkU2/9RyKHdm4BqRPSK+DgvgNEQD4ri6xswDOJ+D5J9hJDKN9HdcS7/kihSBj/NRpQ3a0REvn/p3YDUMBCMer1PTFyxnT6kieCMSJDu5iZBrijwCMj3JcGhkVsdQWn9wZuikxinZCNc4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1646335619; 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[2603:800c:1201:c600:119c:490c:a4ee:8e8]) by smtp.gmail.com with ESMTPSA id u25-20020a62ed19000000b004f140515d56sm3318043pfh.46.2022.03.03.11.15.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 11:15:58 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=1XkfzGvn+ZlmZZNrl7Dk1RW038tolY/tjYs6706uD7c=; b=KZghr0Rv2uDZt/caCMlAE/o4Apx1JJYT5WjYz+YUxBOkCq1LMBirKiFg1h6ADGFjsp t1UW6xUXP/Hq7rCA+p3i3rQT6TF9oPKp22zjCJvUtwMk2+un9lc1k8n0pqUqVrZVF95h d/8eLUUm06199tDvi/Gc+q+Ik72M5skCn2MARHrkS/hhh+cc0cILPZ9vaEWofx+uicJ2 kMrxN1ZGiap4iKr7VshnixBDZ6Fxlso3Uw0pvn/ajfxOE+oPYSNoHmG11u/ZT8fWeghC S56RZZ+muPlwg/+ZwjJg1KIyUwg4r/Q06CjdIY0TijIi3bFFcLGl2LcdCJCIUxh/CCrJ pa6g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1XkfzGvn+ZlmZZNrl7Dk1RW038tolY/tjYs6706uD7c=; b=bZ6vuxRhMZNc2avCseCV48WGvCmK+2Bar/nCEungvonX65WkiB7u8y33UkF25UQfE1 x2cKMiQ06gu+tjN5ZaGg5c/agSJi1+7z46459WdrGO6Q8skSxjw1Do4SAqDZFmD/VpDj RqG80nVh55wXmm5TdbgIULLNBxCcjITp5Wl2AcbbKok5ReczoGh14rrEFzom4rt/lpZG 6fjI/OKhZZpSbh9Q4BnVkzrCuqmVtln9k2URgYUXJfFbF2Fkbto6SHdgXKi8E3v4y/5h ehkEZbaVv0BnGgehrO0nlDVFXc/gPvbl9k4e/coBrebr9MfFeBdRLoXD6x2RxwaDgwUr uHow== X-Gm-Message-State: AOAM530JOMItsGI8wGUPVPOx2Oc+uQz+cAuBj5au8bnx1+2+GAxrUhRa KoZi08TCKz6GmupEEmThwYquuNHbOWZ1oQ== X-Google-Smtp-Source: ABdhPJxv2FEtl46h0UGFHqaWmmZJKQv6RyKElTeQ0DuWNyRmcLdOaBbcPMakA15SYXSP0IlCP9l2LA== X-Received: by 2002:a62:586:0:b0:4e1:dc81:8543 with SMTP id 128-20020a620586000000b004e1dc818543mr39572150pff.0.1646334958440; Thu, 03 Mar 2022 11:15:58 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 3/9] accel/tcg: Support TCG_TARGET_SIGNED_ADDR32 for softmmu Date: Thu, 3 Mar 2022 09:15:45 -1000 Message-Id: <20220303191551.466631-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303191551.466631-1-richard.henderson@linaro.org> References: <20220303191551.466631-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::42b (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42b; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42b.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1646335623624100001 When TCG_TARGET_SIGNED_ADDR32 is set, adjust the tlb addend to allow the 32-bit guest address to be sign extended within the 64-bit host register instead of zero extended. This will simplify tcg hosts like MIPS, RISC-V, and LoongArch, which naturally sign-extend 32-bit values, in contrast to x86_64 and AArch64 which zero-extend them. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-) diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 0e62aa5d7c..0dbc3efbc7 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -40,6 +40,7 @@ #include "qemu/plugin-memory.h" #endif #include "tcg/tcg-ldst.h" +#include "tcg-target-sa32.h" =20 /* DEBUG defines, enable DEBUG_TLB_LOG to log to the CPU_LOG_MMU target */ /* #define DEBUG_TLB */ @@ -93,6 +94,9 @@ static inline size_t sizeof_tlb(CPUTLBDescFast *fast) =20 static inline uintptr_t g2h_tlbe(const CPUTLBEntry *tlb, target_ulong gadd= r) { + if (TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS =3D=3D 32) { + return tlb->addend + (int32_t)gaddr; + } return tlb->addend + (uintptr_t)gaddr; } =20 @@ -1244,7 +1248,13 @@ void tlb_set_page_with_attrs(CPUState *cpu, target_u= long vaddr, desc->iotlb[index].attrs =3D attrs; =20 /* Now calculate the new entry */ - tn.addend =3D addend - vaddr_page; + + if (TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS =3D=3D 32) { + tn.addend =3D addend - (int32_t)vaddr_page; + } else { + tn.addend =3D addend - vaddr_page; + } + if (prot & PAGE_READ) { tn.addr_read =3D address; if (wp_flags & BP_MEM_READ) { --=20 2.25.1 From nobody Mon May 13 20:50:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1646335418; cv=none; d=zohomail.com; s=zohoarc; b=PShA71fW3KzPDm3gnDG4kL2CVqunOjXbincL0ObuSdfs7WrhikmsMp7p4zXH+Qc6rhtiIpquKuAGRlJwP2kKxqG9I+WFA5wrshBPRQC9Gol/StWMv8e+VYN7cAyK4b7Jg0Uh++0KUMidnXRhBV+n4LO3JVvMopPUl6wHfSo06Vk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1646335418; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vyU1dEICQtRQByu98DNY2ApCIAVgpQWfK9xFqkqxnVc=; b=nBz3lUdnq9m08XREhNtkk/CRcoDKBrrTFxHjEkZefnmHqNqzknt3sxN4Quc1DdRJjRPM24eeIoGGtoO/rQt0xAfKlbrbGeXouN9LJOEvMX8Grm9kUefj9o/ooV7H+SehQeJWiYoLSJ2QjpY3jJTlgJc1U7cyfCmHLQbnkmXSQYM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646335418263604.14432044577; Thu, 3 Mar 2022 11:23:38 -0800 (PST) Received: from localhost ([::1]:43202 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nPr32-0002Wz-Pd for importer@patchew.org; Thu, 03 Mar 2022 14:23:36 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60050) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nPqvp-0001vP-IC for qemu-devel@nongnu.org; Thu, 03 Mar 2022 14:16:09 -0500 Received: from [2607:f8b0:4864:20::532] (port=46935 helo=mail-pg1-x532.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nPqvk-0007Sl-1B for qemu-devel@nongnu.org; Thu, 03 Mar 2022 14:16:09 -0500 Received: by mail-pg1-x532.google.com with SMTP id o23so5436298pgk.13 for ; Thu, 03 Mar 2022 11:16:02 -0800 (PST) Received: from localhost.localdomain (2603-800c-1201-c600-119c-490c-a4ee-08e8.res6.spectrum.com. [2603:800c:1201:c600:119c:490c:a4ee:8e8]) by smtp.gmail.com with ESMTPSA id u25-20020a62ed19000000b004f140515d56sm3318043pfh.46.2022.03.03.11.15.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 11:15:59 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vyU1dEICQtRQByu98DNY2ApCIAVgpQWfK9xFqkqxnVc=; b=DJ2qjQDsHDTiNusM6Hd9T1+kX8SPHKggll0QdchYA/lEjY8SGKn6LhhnZqzJpwdUtD Ay5+dJbC6+IHa9jQCnXMMvU+rFz1AFFwunHIrJ9DhEnYpRxzU47Q7x5FXhf9EtKjSSrS 1bpm4uTWJjq+ZLGH+1Uhvsey5CRrclCkHUVMdu3urVhvRnJY6lA76L4plRhKhDnhwp8C MEKK7B+9CjrWyifWpzveQkZA4HUTFk8+irgNzwovtUQphDqAKORxeuWrPEPgmy8pl3/4 Pc8BjvgZGlOdEbrPhHQC6ox/AYeTM2FGpNw3QRzvgF2wnuAEIlMwjNDeXDK0g18/bkhF y4Hg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vyU1dEICQtRQByu98DNY2ApCIAVgpQWfK9xFqkqxnVc=; b=3p7iHfZBfLCPlaOGHJGGKVbUhHr2b1TefZ3gb3kzSBW8gDd5SL525FqRvAMLgoPi7Z AdOstdJVJMItZArBXxD2tHhUhuZBFgDX7M32d0qNUpNZZfa0RXaAh2SbuiM2z7a/F9Oa GTfU5ZVkoz6o5gS6D0tdgdUiHbqIlKVzwzY8a9zQHPFQL2FKsCH4T1rGMikvT0C8EkU+ 1jGh0wkEw6upDPT+chsb9D21US7U+GD9oTFWOkqZNnYWFfjkH4lva8+Hs/aQHSP7EZzX JRNVPdPcmEZkD7b2rnyLSJxqyPWzmXHXVOywKgUC8w7r7LL8MeEhF2+v7oJ5KojeR4P/ aLeA== X-Gm-Message-State: AOAM5333+92Y9Zbkpfwjs9yFmi5462RCjOKRNmjkqnIGpTrh3gu8Cdb6 6tqW2gpGgKkYUcUYDaMfzZ8EjKg2GStDkg== X-Google-Smtp-Source: ABdhPJwxLT7/+MLgv4QMeGujjZh4JJ1y4cwpYwR8aDbr0ZFIMxoXbZv2qgklvl5kclcb/XIF4QTQGw== X-Received: by 2002:a62:dd03:0:b0:4f1:1bfa:134c with SMTP id w3-20020a62dd03000000b004f11bfa134cmr39820338pff.14.1646334959957; Thu, 03 Mar 2022 11:15:59 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 4/9] accel/tcg: Add guest_base_signed_addr32 for user-only Date: Thu, 3 Mar 2022 09:15:46 -1000 Message-Id: <20220303191551.466631-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303191551.466631-1-richard.henderson@linaro.org> References: <20220303191551.466631-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::532 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::532; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x532.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1646335421001100001 While the host may prefer to treat 32-bit addresses as signed, there are edge cases of guests that cannot be implemented with addresses 0x7fff_ffff and 0x8000_0000 being non-consecutive. Therefore, default to guest_base_signed_addr32 false, and allow probe_guest_base to determine whether it is possible to set it to true. A tcg backend which sets TCG_TARGET_SIGNED_ADDR32 will have to cope with either setting for user-only. Reviewed-by: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 16 ++++++++++++++++ include/exec/cpu_ldst.h | 3 ++- bsd-user/main.c | 4 ++++ linux-user/main.c | 3 +++ 4 files changed, 25 insertions(+), 1 deletion(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 84caf5c3d9..26ecd3c886 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -146,6 +146,7 @@ static inline void tswap64s(uint64_t *s) =20 #if defined(CONFIG_USER_ONLY) #include "exec/user/abitypes.h" +#include "tcg-target-sa32.h" =20 /* On some host systems the guest address space is reserved on the host. * This allows the guest address space to be offset to a convenient locati= on. @@ -154,6 +155,21 @@ extern uintptr_t guest_base; extern bool have_guest_base; extern unsigned long reserved_va; =20 +#if TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS =3D=3D 32 +extern bool guest_base_signed_addr32; +#else +#define guest_base_signed_addr32 false +#endif + +static inline void set_guest_base_signed_addr32(void) +{ +#ifdef guest_base_signed_addr32 + qemu_build_not_reached(); +#else + guest_base_signed_addr32 =3D true; +#endif +} + /* * Limit the guest addresses as best we can. * diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h index da987fe8ad..add45499ee 100644 --- a/include/exec/cpu_ldst.h +++ b/include/exec/cpu_ldst.h @@ -87,7 +87,8 @@ static inline abi_ptr cpu_untagged_addr(CPUState *cs, abi= _ptr x) /* All direct uses of g2h and h2g need to go away for usermode softmmu. */ static inline void *g2h_untagged(abi_ptr x) { - return (void *)((uintptr_t)(x) + guest_base); + uintptr_t hx =3D guest_base_signed_addr32 ? (int32_t)x : (uintptr_t)x; + return (void *)(guest_base + hx); } =20 static inline void *g2h(CPUState *cs, abi_ptr x) diff --git a/bsd-user/main.c b/bsd-user/main.c index 88d347d05e..c181e54495 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -54,6 +54,10 @@ int singlestep; uintptr_t guest_base; bool have_guest_base; +#ifndef guest_base_signed_addr32 +bool guest_base_signed_addr32; +#endif + /* * When running 32-on-64 we should make sure we can fit all of the possible * guest address space into a contiguous chunk of virtual host memory. diff --git a/linux-user/main.c b/linux-user/main.c index fbc9bcfd5f..5d963ddb64 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -72,6 +72,9 @@ static const char *seed_optarg; unsigned long mmap_min_addr; uintptr_t guest_base; bool have_guest_base; +#ifndef guest_base_signed_addr32 +bool guest_base_signed_addr32; +#endif =20 /* * Used to implement backwards-compatibility for the `-strace`, and --=20 2.25.1 From nobody Mon May 13 20:50:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646335703833761.9802789916868; Thu, 3 Mar 2022 11:28:23 -0800 (PST) Received: from localhost ([::1]:50980 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nPr7e-0008BQ-SN for importer@patchew.org; Thu, 03 Mar 2022 14:28:22 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60054) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nPqvp-0001wV-Ro for qemu-devel@nongnu.org; Thu, 03 Mar 2022 14:16:09 -0500 Received: from [2607:f8b0:4864:20::62b] (port=46911 helo=mail-pl1-x62b.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nPqvk-0007Sn-3U for qemu-devel@nongnu.org; Thu, 03 Mar 2022 14:16:09 -0500 Received: by mail-pl1-x62b.google.com with SMTP id bd1so5545557plb.13 for ; Thu, 03 Mar 2022 11:16:02 -0800 (PST) Received: from localhost.localdomain (2603-800c-1201-c600-119c-490c-a4ee-08e8.res6.spectrum.com. [2603:800c:1201:c600:119c:490c:a4ee:8e8]) by smtp.gmail.com with ESMTPSA id u25-20020a62ed19000000b004f140515d56sm3318043pfh.46.2022.03.03.11.16.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 11:16:01 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=F2bsGcziKKgWIATQyKoWzWtQMllrUtNMWOT4PiIDWxo=; b=La+UZkFGsKvGG3mpg7hSMQ4FthcocZ8kLEh2JGTOpFGcCbVk9Q0pOUFDYGsuMvM52/ t6uDWcCCZ42L9Io//OpzuiA+eE9qRyt13w0mmfaPnrnigk/tEbPqfLGls0rdrOrSNnfi 5XkIj/Fm3/FJfa3Y5T5W2NatvI9tMKAWudI9rX9gNdiE1yq9Re7+ol5fMXxKOGQvRUJ2 TraUNs8AVkqvAC8S2SqkrnI27f5+SIzd/Di2HQdF6sYlUvqWIPGuN4YfVbKril9tkr0z ldgBIjWYw0VqBDRXYkfmG/LJ+6DOg9ORmEYQP1uJOG84KrNaz+GBr/3F8qMJ8c+J1YZs HXww== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=F2bsGcziKKgWIATQyKoWzWtQMllrUtNMWOT4PiIDWxo=; b=hrkjPM2Lj/wvH3odxrrecv5A0VS6EK44ZPL6lSAqa75d6Prpf/dvqx34jlg3qZ5fk/ +l3UhdA2LUH9h0GZEcs27F+i4vYjJifwcArUW96gOtfR+brIaoBwwJcAi0JOXlDT8BTO MBMq6ZXeysJgO7QXr7NMLh3bSHMX9YO4TOurHyKs+XuS0PstSy77Fr2cfkSc0OslY2xQ yOZeh4J8vMZoj0dO0siERr/4yGzf8DIy5ijoxtXq5UjeRYMQToOiQPGZ1oPs5x1GPpBd 8iYbLl+R6fxGd6LZeY56ZuJtz6xsYynVzYvOyiuUTmdxL5vnzYc53npicLP3kgFLyHj6 vDHg== X-Gm-Message-State: AOAM532JAapDFmI0aGVv9VlpBgT1oLzN+BXvEhSn7zR6W9VW5gKd5tkV xYcCLTE0Vbt7V/NIbeW/95PHNUTmWRn1sw== X-Google-Smtp-Source: ABdhPJwT8Z3ziOY+Ruf2W+MGq4lgVPJSjjhaHO4M8xFxvEphtF+tVNYwRTuFrZEU+cI02hLX8DPmcA== X-Received: by 2002:a17:90b:1a81:b0:1bc:c3e5:27b2 with SMTP id ng1-20020a17090b1a8100b001bcc3e527b2mr6997483pjb.20.1646334961675; Thu, 03 Mar 2022 11:16:01 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 5/9] linux-user: Support TCG_TARGET_SIGNED_ADDR32 Date: Thu, 3 Mar 2022 09:15:47 -1000 Message-Id: <20220303191551.466631-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303191551.466631-1-richard.henderson@linaro.org> References: <20220303191551.466631-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62b (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Alex=20Benn=C3=A9e?= , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646335704631100001 When using reserved_va, which is the default for a 64-bit host and a 32-bit guest, set guest_base_signed_addr32 if requested by TCG_TARGET_SIGNED_ADDR32, and the executable layout allows. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alex Benn=C3=A9e Signed-off-by: Richard Henderson --- include/exec/cpu-all.h | 4 --- linux-user/elfload.c | 62 ++++++++++++++++++++++++++++++++++-------- 2 files changed, 50 insertions(+), 16 deletions(-) diff --git a/include/exec/cpu-all.h b/include/exec/cpu-all.h index 26ecd3c886..8bea0e069e 100644 --- a/include/exec/cpu-all.h +++ b/include/exec/cpu-all.h @@ -269,11 +269,7 @@ extern const TargetPageBits target_page; #define PAGE_RESET 0x0040 /* For linux-user, indicates that the page is MAP_ANON. */ #define PAGE_ANON 0x0080 - -#if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY) -/* FIXME: Code that sets/uses this is broken and needs to go away. */ #define PAGE_RESERVED 0x0100 -#endif /* Target-specific bits that will be used via page_get_flags(). */ #define PAGE_TARGET_1 0x0200 #define PAGE_TARGET_2 0x0400 diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 9628a38361..5522f9e721 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -2482,34 +2482,72 @@ static void pgb_dynamic(const char *image_name, lon= g align) static void pgb_reserved_va(const char *image_name, abi_ulong guest_loaddr, abi_ulong guest_hiaddr, long align) { - int flags =3D MAP_ANONYMOUS | MAP_PRIVATE | MAP_NORESERVE; + int flags =3D (MAP_ANONYMOUS | MAP_PRIVATE | + MAP_NORESERVE | MAP_FIXED_NOREPLACE); + unsigned long local_rva =3D reserved_va; + bool protect_wrap =3D false; void *addr, *test; =20 - if (guest_hiaddr > reserved_va) { + if (guest_hiaddr > local_rva) { error_report("%s: requires more than reserved virtual " "address space (0x%" PRIx64 " > 0x%lx)", - image_name, (uint64_t)guest_hiaddr, reserved_va); + image_name, (uint64_t)guest_hiaddr, local_rva); exit(EXIT_FAILURE); } =20 - /* Widen the "image" to the entire reserved address space. */ - pgb_static(image_name, 0, reserved_va, align); + if (TCG_TARGET_SIGNED_ADDR32 && TARGET_LONG_BITS =3D=3D 32) { + if (guest_loaddr < 0x80000000u && guest_hiaddr > 0x80000000u) { + /* + * The executable itself wraps on signed addresses. + * Without per-page translation, we must keep the + * guest address 0x7fff_ffff adjacent to 0x8000_0000 + * consecutive in host memory: unsigned addresses. + */ + } else { + set_guest_base_signed_addr32(); + if (local_rva <=3D 0x80000000u) { + /* No guest addresses are "negative": win! */ + } else { + /* Begin by allocating the entire address space. */ + local_rva =3D 0xfffffffful + 1; + protect_wrap =3D true; + } + } + } =20 - /* osdep.h defines this as 0 if it's missing */ - flags |=3D MAP_FIXED_NOREPLACE; + /* Widen the "image" to the entire reserved address space. */ + pgb_static(image_name, 0, local_rva, align); + assert(guest_base !=3D 0); =20 /* Reserve the memory on the host. */ - assert(guest_base !=3D 0); test =3D g2h_untagged(0); - addr =3D mmap(test, reserved_va, PROT_NONE, flags, -1, 0); + addr =3D mmap(test, local_rva, PROT_NONE, flags, -1, 0); if (addr =3D=3D MAP_FAILED || addr !=3D test) { + /* + * If protect_wrap, we could try again with the original reserved_= va + * setting, but the edge case of low ulimit vm setting on a 64-bit + * host is probably useless. + */ error_report("Unable to reserve 0x%lx bytes of virtual address " - "space at %p (%s) for use as guest address space (che= ck your" - "virtual memory ulimit setting, min_mmap_addr or rese= rve less " - "using -R option)", reserved_va, test, strerror(errno= )); + "space at %p (%s) for use as guest address space " + "(check your virtual memory ulimit setting, " + "min_mmap_addr or reserve less using -R option)", + local_rva, test, strerror(errno)); exit(EXIT_FAILURE); } =20 + if (protect_wrap) { + /* + * Prevent the page just before 0x80000000 from being allocated. + * This prevents a single guest object/allocation from crossing + * the signed wrap, and thus being discontiguous in host memory. + */ + page_set_flags(0x7fffffff & TARGET_PAGE_MASK, 0x80000000u, + PAGE_RESERVED); + /* Adjust guest_base so that 0 is in the middle of the reservation= . */ + guest_base +=3D 0x80000000ul; + } + qemu_log_mask(CPU_LOG_PAGE, "%s: base @ %p for %lu bytes\n", __func__, addr, reserved_va); } --=20 2.25.1 From nobody Mon May 13 20:50:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1646335701; cv=none; d=zohomail.com; s=zohoarc; b=VyVL/w7enOSqGXF/3hzn5/iM21Cxy1DgTJaIf0UL0MOU3RB4rH2zTR01cZbIidnqLqkBFVAiEjInNdtNIOhbabJBG7bgiEhNSBd17nY+wQ8WQbXQGd8EgjsuUXt06Z+I4QQk2YLdqpedmRl2jIGUE7KUud+kscIFrmsDhgGfY/E= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1646335701; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pw9Lr6A1xqwAKDrOkoPeST8MZRplOG8Yhjei+xoRZSc=; b=Cw6WSYfreUg687s/kTLZwEkeiHLWyLeOPoGDme6y/ghDEljVAREyaIhyLfEnTih6rELPWCyRBuLlctbRRLUvuq0SNi2CGIGhoFYRLWHe0AkjKY0ZG+Fl2BwcyzLlpA/RWmtqgy/1dGLrm8j26qgS1JBXPFoEDT66zKws+vydVbE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646335701950282.1703625347644; Thu, 3 Mar 2022 11:28:21 -0800 (PST) Received: from localhost ([::1]:50812 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nPr7c-000842-RM for importer@patchew.org; Thu, 03 Mar 2022 14:28:20 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60110) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nPqvr-00020i-6D for qemu-devel@nongnu.org; Thu, 03 Mar 2022 14:16:11 -0500 Received: from [2607:f8b0:4864:20::1035] (port=46951 helo=mail-pj1-x1035.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nPqvk-0007Sw-Av for qemu-devel@nongnu.org; Thu, 03 Mar 2022 14:16:10 -0500 Received: by mail-pj1-x1035.google.com with SMTP id 15-20020a17090a098f00b001bef0376d5cso5852133pjo.5 for ; Thu, 03 Mar 2022 11:16:03 -0800 (PST) Received: from localhost.localdomain (2603-800c-1201-c600-119c-490c-a4ee-08e8.res6.spectrum.com. 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Enabling this for AArch64 gives us testing of the feature in CI. Cc: Peter Maydell Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- tcg/aarch64/tcg-target-sa32.h | 8 +++- tcg/aarch64/tcg-target.c.inc | 81 ++++++++++++++++++++++++----------- 2 files changed, 64 insertions(+), 25 deletions(-) diff --git a/tcg/aarch64/tcg-target-sa32.h b/tcg/aarch64/tcg-target-sa32.h index cb185b1526..c99e502e4c 100644 --- a/tcg/aarch64/tcg-target-sa32.h +++ b/tcg/aarch64/tcg-target-sa32.h @@ -1 +1,7 @@ -#define TCG_TARGET_SIGNED_ADDR32 0 +/* + * AArch64 has both SXTW and UXTW addressing modes, which means that + * it is agnostic to how guest addresses should be represented. + * Because aarch64 is more common than the other hosts that will + * want to use this feature, enable it for continuous testing. + */ +#define TCG_TARGET_SIGNED_ADDR32 1 diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 077fc51401..4a3edd6963 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -361,6 +361,16 @@ typedef enum { LDST_LD_S_W =3D 3, /* load and sign-extend into Wt */ } AArch64LdstType; =20 +/* + * See aarch64/instrs/extendreg/DecodeRegExtend + * But note that option<1> =3D=3D 0 is UNDEFINED for LDR/STR. + */ +typedef enum { + LDST_EXT_UXTW =3D 2, /* zero-extend from uint32_t */ + LDST_EXT_UXTX =3D 3, /* zero-extend from uint64_t (i.e. no extension)= */ + LDST_EXT_SXTW =3D 6, /* sign-extend from int32_t */ +} AArch64LdstExt; + /* We encode the format of the insn into the beginning of the name, so that we can have the preprocessor help "typecheck" the insn vs the output function. Arm didn't provide us with nice names for the formats, so we @@ -806,12 +816,12 @@ static void tcg_out_insn_3617(TCGContext *s, AArch64I= nsn insn, bool q, } =20 static void tcg_out_insn_3310(TCGContext *s, AArch64Insn insn, - TCGReg rd, TCGReg base, TCGType ext, + TCGReg rd, TCGReg base, AArch64LdstExt optio= n, TCGReg regoff) { /* Note the AArch64Insn constants above are for C3.3.12. Adjust. */ tcg_out32(s, insn | I3312_TO_I3310 | regoff << 16 | - 0x4000 | ext << 13 | base << 5 | (rd & 0x1f)); + option << 13 | base << 5 | (rd & 0x1f)); } =20 static void tcg_out_insn_3312(TCGContext *s, AArch64Insn insn, @@ -1126,7 +1136,7 @@ static void tcg_out_ldst(TCGContext *s, AArch64Insn i= nsn, TCGReg rd, =20 /* Worst-case scenario, move offset to temp register, use reg offset. = */ tcg_out_movi(s, TCG_TYPE_I64, TCG_REG_TMP, offset); - tcg_out_ldst_r(s, insn, rd, rn, TCG_TYPE_I64, TCG_REG_TMP); + tcg_out_ldst_r(s, insn, rd, rn, LDST_EXT_UXTX, TCG_REG_TMP); } =20 static bool tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg ar= g) @@ -1765,31 +1775,31 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s= , TCGLabelQemuLdst *l) =20 static void tcg_out_qemu_ld_direct(TCGContext *s, MemOp memop, TCGType ext, TCGReg data_r, TCGReg addr_r, - TCGType otype, TCGReg off_r) + AArch64LdstExt option, TCGReg off_r) { switch (memop & MO_SSIZE) { case MO_UB: - tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_LDRB, data_r, addr_r, option, off_r); break; case MO_SB: tcg_out_ldst_r(s, ext ? I3312_LDRSBX : I3312_LDRSBW, - data_r, addr_r, otype, off_r); + data_r, addr_r, option, off_r); break; case MO_UW: - tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_LDRH, data_r, addr_r, option, off_r); break; case MO_SW: tcg_out_ldst_r(s, (ext ? I3312_LDRSHX : I3312_LDRSHW), - data_r, addr_r, otype, off_r); + data_r, addr_r, option, off_r); break; case MO_UL: - tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_LDRW, data_r, addr_r, option, off_r); break; case MO_SL: - tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_LDRSWX, data_r, addr_r, option, off_r); break; case MO_UQ: - tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_LDRX, data_r, addr_r, option, off_r); break; default: tcg_abort(); @@ -1798,31 +1808,52 @@ static void tcg_out_qemu_ld_direct(TCGContext *s, M= emOp memop, TCGType ext, =20 static void tcg_out_qemu_st_direct(TCGContext *s, MemOp memop, TCGReg data_r, TCGReg addr_r, - TCGType otype, TCGReg off_r) + AArch64LdstExt option, TCGReg off_r) { switch (memop & MO_SIZE) { case MO_8: - tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_STRB, data_r, addr_r, option, off_r); break; case MO_16: - tcg_out_ldst_r(s, I3312_STRH, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_STRH, data_r, addr_r, option, off_r); break; case MO_32: - tcg_out_ldst_r(s, I3312_STRW, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_STRW, data_r, addr_r, option, off_r); break; case MO_64: - tcg_out_ldst_r(s, I3312_STRX, data_r, addr_r, otype, off_r); + tcg_out_ldst_r(s, I3312_STRX, data_r, addr_r, option, off_r); break; default: tcg_abort(); } } =20 +/* + * Bits for the option field of LDR/STR (register), + * for application to a guest address. + */ +static AArch64LdstExt ldst_ext_option(void) +{ +#ifdef CONFIG_USER_ONLY + bool signed_addr32 =3D guest_base_signed_addr32; +#else + bool signed_addr32 =3D TCG_TARGET_SIGNED_ADDR32; +#endif + + if (TARGET_LONG_BITS =3D=3D 64) { + return LDST_EXT_UXTX; + } else if (signed_addr32) { + return LDST_EXT_SXTW; + } else { + return LDST_EXT_UXTW; + } +} + static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_re= g, MemOpIdx oi, TCGType ext) { MemOp memop =3D get_memop(oi); - const TCGType otype =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TC= G_TYPE_I32; + AArch64LdstExt option =3D ldst_ext_option(); =20 /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((memop & MO_BSWAP) =3D=3D 0); @@ -1833,7 +1864,7 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg dat= a_reg, TCGReg addr_reg, =20 tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 1); tcg_out_qemu_ld_direct(s, memop, ext, data_reg, - TCG_REG_X1, otype, addr_reg); + TCG_REG_X1, option, addr_reg); add_qemu_ldst_label(s, true, oi, ext, data_reg, addr_reg, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ @@ -1843,10 +1874,11 @@ static void tcg_out_qemu_ld(TCGContext *s, TCGReg d= ata_reg, TCGReg addr_reg, } if (USE_GUEST_BASE) { tcg_out_qemu_ld_direct(s, memop, ext, data_reg, - TCG_REG_GUEST_BASE, otype, addr_reg); + TCG_REG_GUEST_BASE, option, addr_reg); } else { + /* This case is always a 64-bit guest with no extension. */ tcg_out_qemu_ld_direct(s, memop, ext, data_reg, - addr_reg, TCG_TYPE_I64, TCG_REG_XZR); + addr_reg, LDST_EXT_UXTX, TCG_REG_XZR); } #endif /* CONFIG_SOFTMMU */ } @@ -1855,7 +1887,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg dat= a_reg, TCGReg addr_reg, MemOpIdx oi) { MemOp memop =3D get_memop(oi); - const TCGType otype =3D TARGET_LONG_BITS =3D=3D 64 ? TCG_TYPE_I64 : TC= G_TYPE_I32; + AArch64LdstExt option =3D ldst_ext_option(); =20 /* Byte swapping is left to middle-end expansion. */ tcg_debug_assert((memop & MO_BSWAP) =3D=3D 0); @@ -1866,7 +1898,7 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg dat= a_reg, TCGReg addr_reg, =20 tcg_out_tlb_read(s, addr_reg, memop, &label_ptr, mem_index, 0); tcg_out_qemu_st_direct(s, memop, data_reg, - TCG_REG_X1, otype, addr_reg); + TCG_REG_X1, option, addr_reg); add_qemu_ldst_label(s, false, oi, (memop & MO_SIZE)=3D=3D MO_64, data_reg, addr_reg, s->code_ptr, label_ptr); #else /* !CONFIG_SOFTMMU */ @@ -1876,10 +1908,11 @@ static void tcg_out_qemu_st(TCGContext *s, TCGReg d= ata_reg, TCGReg addr_reg, } if (USE_GUEST_BASE) { tcg_out_qemu_st_direct(s, memop, data_reg, - TCG_REG_GUEST_BASE, otype, addr_reg); + TCG_REG_GUEST_BASE, option, addr_reg); } else { + /* This case is always a 64-bit guest with no extension. */ tcg_out_qemu_st_direct(s, memop, data_reg, - addr_reg, TCG_TYPE_I64, TCG_REG_XZR); + addr_reg, LDST_EXT_UXTX, TCG_REG_XZR); } #endif /* CONFIG_SOFTMMU */ } --=20 2.25.1 From nobody Mon May 13 20:50:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1646335451; cv=none; d=zohomail.com; s=zohoarc; b=JXaKo7Crl/sObjoa0h6r6Ey9h1idn7fJgqeSgRLRvP/ldM9pDimgoW6tksYGsr88A1woT5yaXSHGmgpLiDk528WKK0oDLkC3J79EQSNfb7ag9GWRtBJS9QD4OWy+c83/yjjid7eUn+fRZzrkP0Kqdm2BrHDcmMxDYvJdwjw45sc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1646335451; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+BD96XfV2twTSXl72v5Agr1at/ZBm5w6SA0tYUmlFcg=; b=dNeWQr6j0gpwVtJe1fRGBvPhmkFQEaanIjsG9zcEX5Lj0c8QXcuIyaWRlAv60WkZJydJB1ni8tTzoGNP36Q9q/qsu1YY7Mdng1mFxS+g4ZR2yTNA71YOA1P5+YRq9CEPAX0EEDlSasqQL4RJj+OKbX9eoTGyL/rmBtq6aBx4IjE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646335451475302.3796544790721; Thu, 3 Mar 2022 11:24:11 -0800 (PST) Received: from localhost ([::1]:44528 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nPr3b-0003Qf-2a for importer@patchew.org; Thu, 03 Mar 2022 14:24:11 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60106) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nPqvr-00020Y-3T for qemu-devel@nongnu.org; Thu, 03 Mar 2022 14:16:11 -0500 Received: from [2607:f8b0:4864:20::62b] (port=36571 helo=mail-pl1-x62b.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nPqvl-0007TU-Gf for qemu-devel@nongnu.org; Thu, 03 Mar 2022 14:16:10 -0500 Received: by mail-pl1-x62b.google.com with SMTP id e13so5579567plh.3 for ; Thu, 03 Mar 2022 11:16:05 -0800 (PST) Received: from localhost.localdomain (2603-800c-1201-c600-119c-490c-a4ee-08e8.res6.spectrum.com. [2603:800c:1201:c600:119c:490c:a4ee:8e8]) by smtp.gmail.com with ESMTPSA id u25-20020a62ed19000000b004f140515d56sm3318043pfh.46.2022.03.03.11.16.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 11:16:03 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=+BD96XfV2twTSXl72v5Agr1at/ZBm5w6SA0tYUmlFcg=; b=OkqH6XdZCMAUqMXMoosmx8OP1jNJz9JOhlFOMxrRGnMlEjAh2Zycj/h1VcVCEu3GV2 1PL/zulSrvn1WAhjmoWfJw5X5bYEDI/adxdv+coPJfS1vNW6iPmSDWCGTR7SKa/41Ul9 LqwYtKFmYi2FbUEW4PYprJwsgNzn36XZIUs9gnFR5j+2uQlFxcjZF0eh7yQSSxL4CXd6 S9e5dBOv+7z2cLzaw7J3mMAXnE7cb+twe/wT2pucjIrhq74VMIwG9bRhdeldKj+8Ughf 59rsZDAPGN4EJHpiydbB+toPOysQOSnPC2x4joK9r5GMQfl1puwd43DZRshr6TrqacCc rORg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+BD96XfV2twTSXl72v5Agr1at/ZBm5w6SA0tYUmlFcg=; b=b2i/hqRR7aub2wzkvdlqQMXGXCM6tjRjZuAz9QD4Kq2u44+h9u5iuRBtkD2nEp63EM uzLbaYBxNp+J1GPEb7k20dyJU782D/G31p/pcln7hlCLP3KEM/K4RIOjprYa3xTeoLvn 1iod+8ovFRbOG13z2+fdddbIlXVhgI3Y9sExoE0Sy+wtnDuvACizEKugLqyzaFO8yjfL MrqCXQwR1btqHev6PIGFcORv23IdpMd7lDjTcgCvYQL68PgLOKvGRo/OJK3vSkdtpD9L /XjYl+RRx3Mbea/KrPE3cqucCcPy7ac62vdhLRi9bCAl45ejVYekCrTZuJN/j59n10bS VXig== X-Gm-Message-State: AOAM530uZy/ojOsn/pO4yVPwCfV5bZ2mXbK8nCLXiN6o1C1CkMmIbB2t tcU5PBgbeeRU8DdIVHCe0of+eLA8oYdi4g== X-Google-Smtp-Source: ABdhPJxg7gVHfuLDCfvpUKCNwD00UchB0xJa3u8r/olx6QhxVc8tBPfvChGW3LJPmE0Zirk+yTcJvg== X-Received: by 2002:a17:90a:ad88:b0:1be:ec99:a695 with SMTP id s8-20020a17090aad8800b001beec99a695mr6888331pjq.119.1646334964275; Thu, 03 Mar 2022 11:16:04 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 7/9] tcg/mips: Support TCG_TARGET_SIGNED_ADDR32 Date: Thu, 3 Mar 2022 09:15:49 -1000 Message-Id: <20220303191551.466631-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303191551.466631-1-richard.henderson@linaro.org> References: <20220303191551.466631-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::62b (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1646335452870100001 All 32-bit mips operations sign-extend the output, so we are easily able to keep TCG_TYPE_I32 values sign-extended in host registers. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/mips/tcg-target-sa32.h | 8 ++++++++ tcg/mips/tcg-target.c.inc | 10 ++-------- 2 files changed, 10 insertions(+), 8 deletions(-) diff --git a/tcg/mips/tcg-target-sa32.h b/tcg/mips/tcg-target-sa32.h index cb185b1526..51255e7cba 100644 --- a/tcg/mips/tcg-target-sa32.h +++ b/tcg/mips/tcg-target-sa32.h @@ -1 +1,9 @@ +/* + * Do not set TCG_TARGET_SIGNED_ADDR32 for mips32; + * TCG expects this to only be set for 64-bit hosts. + */ +#ifdef __mips64 +#define TCG_TARGET_SIGNED_ADDR32 1 +#else #define TCG_TARGET_SIGNED_ADDR32 0 +#endif diff --git a/tcg/mips/tcg-target.c.inc b/tcg/mips/tcg-target.c.inc index 993149d18a..b97c032ded 100644 --- a/tcg/mips/tcg-target.c.inc +++ b/tcg/mips/tcg-target.c.inc @@ -1168,12 +1168,6 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg b= ase, TCGReg addrl, TCG_TMP0, TCG_TMP3, cmp_off); } =20 - /* Zero extend a 32-bit guest address for a 64-bit host. */ - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, base, addrl); - addrl =3D base; - } - /* * Mask the page bits, keeping the alignment bits to compare against. * For unaligned accesses, compare against the end of the access to @@ -1679,7 +1673,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) data_regl, data_regh, addr_regl, addr_regh, s->code_ptr, label_ptr); #else - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr3= 2) { tcg_out_ext32u(s, base, addr_regl); addr_regl =3D base; } @@ -1878,7 +1872,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) data_regl, data_regh, addr_regl, addr_regh, s->code_ptr, label_ptr); #else - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr3= 2) { tcg_out_ext32u(s, base, addr_regl); addr_regl =3D base; } --=20 2.25.1 From nobody Mon May 13 20:50:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646335957505517.3876153077628; Thu, 3 Mar 2022 11:32:37 -0800 (PST) Received: from localhost ([::1]:58506 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nPrBk-0005Ki-Ht for importer@patchew.org; Thu, 03 Mar 2022 14:32:36 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60150) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nPqvs-00024v-E1 for qemu-devel@nongnu.org; Thu, 03 Mar 2022 14:16:12 -0500 Received: from [2607:f8b0:4864:20::434] (port=40778 helo=mail-pf1-x434.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nPqvm-0007U3-Qk for qemu-devel@nongnu.org; Thu, 03 Mar 2022 14:16:12 -0500 Received: by mail-pf1-x434.google.com with SMTP id z15so5545203pfe.7 for ; Thu, 03 Mar 2022 11:16:06 -0800 (PST) Received: from localhost.localdomain (2603-800c-1201-c600-119c-490c-a4ee-08e8.res6.spectrum.com. [2603:800c:1201:c600:119c:490c:a4ee:8e8]) by smtp.gmail.com with ESMTPSA id u25-20020a62ed19000000b004f140515d56sm3318043pfh.46.2022.03.03.11.16.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 11:16:05 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Ho2jnp9wAsj5SBP8tX6ESXDweHDs0USlRJ9dHfy8f/A=; b=CTNxQqXtZxYoa4O2xPlaWOr5/h3yNMD9m9fAzXA+HjI2ColhGP2jIE4AW+ZAIaTi11 MxbNRzEIegS+1jzkiIuEZENqLrysUTsvTv1ZtQDs4o0vrvy4S/bwtawfXRoCb7frUFD1 a5urOOnYjgQvZsW372g+JdzWHP/XIUCkoYTVPpDnD4gdZCrsO3hw3mnN+rNqhlWrizYC CYySVIJ3xkvOa+NUC8G2hqsIVlEcrTxC+0X3iNQ6xLYgH8THTuqcBflF8qmjDNnl3v0T kfn/VYJXpZQaQKTPqJ+DVEDH0SBmWUafE/cabL8lu0jFkygwvctHqlaxwiVQP89hgHxO KTEw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Ho2jnp9wAsj5SBP8tX6ESXDweHDs0USlRJ9dHfy8f/A=; b=4lCxZdxFwliQFjgTFLh+vHPbxoVCl33eUOiLMYeLRMabsDqmdIrTxAM8rsH3AMk7Ft N1jqK0VtCPHhG3YEA6NtfCEdYkbSyePbnEE2Uchp21+gMWCXiT0E4jjkvjiOpVw74NR2 tYAdycqAWvEYge5QdE8uLNgCBH5ipMUE6SxvTtA0sYu5nxCjuVc0DeosMpQfCAbksaLL rWu5sqgQ7YJJVxHvgZ7C/VvfIy37uoLHC4USKELW19+fYOrkhnOq8EXqNh7p2xTkFCBb rZv1DF+AZO7uUCzBEATq6sbOGA7eMIXS8dXTVerrM3Lso/D2UVdiy7YHJC5mRFO0OD8j vWJA== X-Gm-Message-State: AOAM531VrZ+dEglCE9IcrZiTEWYJ8+uQi3W3RsG0ppf9lysBbjHzVaQE ftIpthz/2YR7nil01gQDp8eDTkka+/oZaA== X-Google-Smtp-Source: ABdhPJxfdhZ720W3SuYvzW9VDMAL2+RY2hUTiUrfI3vqZI4XEcdrB7a16bchptiFeg85K/6SuAFlCg== X-Received: by 2002:a65:48c8:0:b0:375:9c2b:ad33 with SMTP id o8-20020a6548c8000000b003759c2bad33mr30638842pgs.232.1646334965563; Thu, 03 Mar 2022 11:16:05 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 8/9] tcg/riscv: Support TCG_TARGET_SIGNED_ADDR32 Date: Thu, 3 Mar 2022 09:15:50 -1000 Message-Id: <20220303191551.466631-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303191551.466631-1-richard.henderson@linaro.org> References: <20220303191551.466631-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::434 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alistair Francis , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646335958831100001 All RV64 32-bit operations sign-extend the output, so we are easily able to keep TCG_TYPE_I32 values sign-extended in host registers. Reviewed-by: Philippe Mathieu-Daud=C3=A9 Reviewed-by: Alistair Francis Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-sa32.h | 6 +++++- tcg/riscv/tcg-target.c.inc | 8 ++------ 2 files changed, 7 insertions(+), 7 deletions(-) diff --git a/tcg/riscv/tcg-target-sa32.h b/tcg/riscv/tcg-target-sa32.h index cb185b1526..703467b37a 100644 --- a/tcg/riscv/tcg-target-sa32.h +++ b/tcg/riscv/tcg-target-sa32.h @@ -1 +1,5 @@ -#define TCG_TARGET_SIGNED_ADDR32 0 +/* + * Do not set TCG_TARGET_SIGNED_ADDR32 for RV32; + * TCG expects this to only be set for 64-bit hosts. + */ +#define TCG_TARGET_SIGNED_ADDR32 (__riscv_xlen =3D=3D 64) diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc index 6409d9c3d5..c999711494 100644 --- a/tcg/riscv/tcg-target.c.inc +++ b/tcg/riscv/tcg-target.c.inc @@ -951,10 +951,6 @@ static void tcg_out_tlb_load(TCGContext *s, TCGReg add= rl, tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0); =20 /* TLB Hit - translate address using addend. */ - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { - tcg_out_ext32u(s, TCG_REG_TMP0, addrl); - addrl =3D TCG_REG_TMP0; - } tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl); } =20 @@ -1175,7 +1171,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGA= rg *args, bool is_64) data_regl, data_regh, addr_regl, addr_regh, s->code_ptr, label_ptr); #else - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr3= 2) { tcg_out_ext32u(s, base, addr_regl); addr_regl =3D base; } @@ -1247,7 +1243,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args, bool is_64) data_regl, data_regh, addr_regl, addr_regh, s->code_ptr, label_ptr); #else - if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS && !guest_base_signed_addr3= 2) { tcg_out_ext32u(s, base, addr_regl); addr_regl =3D base; } --=20 2.25.1 From nobody Mon May 13 20:50:02 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1646335168; cv=none; d=zohomail.com; s=zohoarc; b=fmcbGfZ+lxPJnhZ6g9xeAhNIMnG88AZPRHpKP7oBuRe6ry0DkYmaOYrBHocrpg11OK9upayz1tAcOJi8N2yS/y6P6yR1S6mgF2eKNhTBgnUf0XL+wPTXlMXKyQ+7oONOmf7BqjARGvjvXu40veRn2klKfyt24+wjalXboLufhG0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1646335168; h=Content-Type:Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=KnojlxdJvLZ10xztEz7NOsevcqMVQEVsVSU9aLxpzTg=; b=B/kxLO2U1EXZJUk79E5jfKfxGArSup6WnLwXn0B9WEzgvA4mbCg6p648h+PnjY0QkXcNoFdTHnBXcbmhz96OD1AFatbSeJY3fqt13MkyOb9Dt3zmDAyuk48374TlRsEcpy2VQ1Kt6rUEJQJMktvyz2ZIl/NQbx6+4MNf+uux0Jg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646335168167355.92484805380684; Thu, 3 Mar 2022 11:19:28 -0800 (PST) Received: from localhost ([::1]:34872 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nPqz0-0004wh-Ro for importer@patchew.org; Thu, 03 Mar 2022 14:19:26 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60162) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nPqvt-00027g-BJ for qemu-devel@nongnu.org; Thu, 03 Mar 2022 14:16:13 -0500 Received: from [2607:f8b0:4864:20::1035] (port=32911 helo=mail-pj1-x1035.google.com) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nPqvo-0007UN-Bd for qemu-devel@nongnu.org; Thu, 03 Mar 2022 14:16:12 -0500 Received: by mail-pj1-x1035.google.com with SMTP id m13-20020a17090aab0d00b001bbe267d4d1so6721437pjq.0 for ; Thu, 03 Mar 2022 11:16:07 -0800 (PST) Received: from localhost.localdomain (2603-800c-1201-c600-119c-490c-a4ee-08e8.res6.spectrum.com. [2603:800c:1201:c600:119c:490c:a4ee:8e8]) by smtp.gmail.com with ESMTPSA id u25-20020a62ed19000000b004f140515d56sm3318043pfh.46.2022.03.03.11.16.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 03 Mar 2022 11:16:06 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=KnojlxdJvLZ10xztEz7NOsevcqMVQEVsVSU9aLxpzTg=; b=qz6RvfJFMgigWzzM1vRT/5gb9lGxqkQWy6iTWqwlLwVxc4Di62FNOYwztB/Nf83cB5 2d633BfUoHMevCAR2acUejkqcTJQHOHT1wuDl61Nfz9kNJ9YsAjWGga2PC9aNYvf4P3F Dk9a111+jCaDg567I8EeUTjWHzuCGXtgfn51vzenakFOHBGIjXO/IbYVcQjywe0yGSmw keW3rxsMYgKz/3YUdYgb6X7aMGw0AuEs2V7lVH7FGnhrvkkhNym5bg39EYZnj/NZo8Bx fTVPQaG9JgW9coh+Z9Eu5M+jvMCQgMri8kBaxr/HRSnib+TWVagcHBE3UfxtKRofDGMT ZWyg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=KnojlxdJvLZ10xztEz7NOsevcqMVQEVsVSU9aLxpzTg=; b=hlywM21ej7xcX/32Uvnv8wI14YRYVy1I8hjxd75onT31VBuwH0N3bUEVT4pbg/pC8I i7ufybW5ScnFFgmQ24gwfpV7dxtS4YQhhWYyTUMaf1Wi4i5tFCv3UFpCPQtBOaiFcQVG HhWH0WPMVwAK+1r4eLgEGBCtW+AHprV+BDA3YYYHO4Tm1lOlyHEXbekfoSGmaTNFz2cp ONDAOpCjCqy7qtX0nqqGQda5Hx2GTYPmq5uWWXFR95fBtv9UbddhGQvaF6Bt9RD+RZ0W LDs8erf0c/LL73OesCLl324Sgrf2MebOJ8bst6CZGKVxlwfoXMKoJINui0ktSN45dqbL gIpQ== X-Gm-Message-State: AOAM530XIaUc1lDH7B13SXQvfSD9DVL7ddiXZKfnN0D8CAPyM7qe0gZB d3imlCv/J3HOC/R6k+TP1mCH8ugRfzaeWQ== X-Google-Smtp-Source: ABdhPJwD5tjnIeiyD16cT49Zxn0ZpH46vFyhdTyyA+O04FkB/VIQbhowFuuOfxd/L0zCnwkkQcw8XA== X-Received: by 2002:a17:902:9348:b0:14f:c715:2a94 with SMTP id g8-20020a170902934800b0014fc7152a94mr38082555plp.66.1646334967036; Thu, 03 Mar 2022 11:16:07 -0800 (PST) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v3 9/9] tcg/loongarch64: Support TCG_TARGET_SIGNED_ADDR32 Date: Thu, 3 Mar 2022 09:15:51 -1000 Message-Id: <20220303191551.466631-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220303191551.466631-1-richard.henderson@linaro.org> References: <20220303191551.466631-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::1035 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1035.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: WANG Xuerui , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1646335168965100001 All 32-bit LoongArch operations sign-extend the output, so we are easily able to keep TCG_TYPE_I32 values sign-extended in host registers. Cc: WANG Xuerui Reviewed-by: Philippe Mathieu-Daud=C3=A9 Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target-sa32.h | 2 +- tcg/loongarch64/tcg-target.c.inc | 15 ++++++--------- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/tcg/loongarch64/tcg-target-sa32.h b/tcg/loongarch64/tcg-target= -sa32.h index cb185b1526..aaffd777bf 100644 --- a/tcg/loongarch64/tcg-target-sa32.h +++ b/tcg/loongarch64/tcg-target-sa32.h @@ -1 +1 @@ -#define TCG_TARGET_SIGNED_ADDR32 0 +#define TCG_TARGET_SIGNED_ADDR32 1 diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.= c.inc index a3debf6da7..425f6629ca 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg/loongarch64/tcg-target.c.inc @@ -880,8 +880,6 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, TC= GLabelQemuLdst *l) return tcg_out_fail_alignment(s, l); } =20 -#endif /* CONFIG_SOFTMMU */ - /* * `ext32u` the address register into the temp register given, * if target is 32-bit, no-op otherwise. @@ -891,12 +889,13 @@ static bool tcg_out_qemu_st_slow_path(TCGContext *s, = TCGLabelQemuLdst *l) static TCGReg tcg_out_zext_addr_if_32_bit(TCGContext *s, TCGReg addr, TCGReg tmp) { - if (TARGET_LONG_BITS =3D=3D 32) { + if (TARGET_LONG_BITS =3D=3D 32 && !guest_base_signed_addr32) { tcg_out_ext32u(s, tmp, addr); return tmp; } return addr; } +#endif /* CONFIG_SOFTMMU */ =20 static void tcg_out_qemu_ld_indexed(TCGContext *s, TCGReg rd, TCGReg rj, TCGReg rk, MemOp opc, TCGType type) @@ -944,8 +943,8 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg= *args, TCGType type) tcg_insn_unit *label_ptr[1]; #else unsigned a_bits; -#endif TCGReg base; +#endif =20 data_regl =3D *args++; addr_regl =3D *args++; @@ -954,8 +953,7 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg= *args, TCGType type) =20 #if defined(CONFIG_SOFTMMU) tcg_out_tlb_load(s, addr_regl, oi, label_ptr, 1); - base =3D tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0); - tcg_out_qemu_ld_indexed(s, data_regl, base, TCG_REG_TMP2, opc, type); + tcg_out_qemu_ld_indexed(s, data_regl, addr_regl, TCG_REG_TMP2, opc, ty= pe); add_qemu_ldst_label(s, 1, oi, type, data_regl, addr_regl, s->code_ptr, label_ptr); @@ -1004,8 +1002,8 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args) tcg_insn_unit *label_ptr[1]; #else unsigned a_bits; -#endif TCGReg base; +#endif =20 data_regl =3D *args++; addr_regl =3D *args++; @@ -1014,8 +1012,7 @@ static void tcg_out_qemu_st(TCGContext *s, const TCGA= rg *args) =20 #if defined(CONFIG_SOFTMMU) tcg_out_tlb_load(s, addr_regl, oi, label_ptr, 0); - base =3D tcg_out_zext_addr_if_32_bit(s, addr_regl, TCG_REG_TMP0); - tcg_out_qemu_st_indexed(s, data_regl, base, TCG_REG_TMP2, opc); + tcg_out_qemu_st_indexed(s, data_regl, addr_regl, TCG_REG_TMP2, opc); add_qemu_ldst_label(s, 0, oi, 0, /* type param is unused for stores */ data_regl, addr_regl, --=20 2.25.1