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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=05403f1d5=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1646285983887100001 Content-Type: text/plain; charset="utf-8" From: Weiwei Li Co-authored-by: ardxwe Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20220211043920.28981-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 4 ++++ target/riscv/cpu.c | 12 ++++++++++++ 2 files changed, 16 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8183fb86d5..9ba05042ed 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -362,8 +362,12 @@ struct RISCVCPUConfig { bool ext_svinval; bool ext_svnapot; bool ext_svpbmt; + bool ext_zdinx; bool ext_zfh; bool ext_zfhmin; + bool ext_zfinx; + bool ext_zhinx; + bool ext_zhinxmin; bool ext_zve32f; bool ext_zve64f; =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b0a40b83e7..55371b1aa5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -587,6 +587,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) cpu->cfg.ext_d =3D true; } =20 + if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || + cpu->cfg.ext_zhinxmin) { + cpu->cfg.ext_zfinx =3D true; + } + /* Set the ISA extensions, checks should have happened above */ if (cpu->cfg.ext_i) { ext |=3D RVI; @@ -665,6 +670,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) if (cpu->cfg.ext_j) { ext |=3D RVJ; } + if (cpu->cfg.ext_zfinx && ((ext & (RVF | RVD)) || cpu->cfg.ext_zfh= || + cpu->cfg.ext_zfhmin)) { + error_setg(errp, + "'Zfinx' cannot be supported together with 'F', 'D', '= Zfh'," + " 'Zfhmin'"); + return; + } =20 set_misa(env, env->misa_mxl, ext); } --=20 2.35.1