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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=05403f1d5=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1646285652199100001 Content-Type: text/plain; charset="utf-8" From: Wilfred Mallawa This patch updates the SPI_DEVICE, SPI_HOST0, SPI_HOST1 base addresses. Also adds these as unimplemented devices. The address references can be found [1]. [1] https://github.com/lowRISC/opentitan/blob/6c317992fbd646818b34f2a2dbf44= bc850e461e4/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h#L107 Signed-off-by: Wilfred Mallawa Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Message-Id: <20220218063839.405082-1-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis --- include/hw/riscv/opentitan.h | 4 +++- hw/riscv/opentitan.c | 12 +++++++++--- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h index eac35ef590..00da9ded43 100644 --- a/include/hw/riscv/opentitan.h +++ b/include/hw/riscv/opentitan.h @@ -57,8 +57,10 @@ enum { IBEX_DEV_FLASH, IBEX_DEV_FLASH_VIRTUAL, IBEX_DEV_UART, + IBEX_DEV_SPI_DEVICE, + IBEX_DEV_SPI_HOST0, + IBEX_DEV_SPI_HOST1, IBEX_DEV_GPIO, - IBEX_DEV_SPI, IBEX_DEV_I2C, IBEX_DEV_PATTGEN, IBEX_DEV_TIMER, diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index aec7cfa33f..833624d66c 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -34,13 +34,15 @@ static const MemMapEntry ibex_memmap[] =3D { [IBEX_DEV_FLASH] =3D { 0x20000000, 0x80000 }, [IBEX_DEV_UART] =3D { 0x40000000, 0x1000 }, [IBEX_DEV_GPIO] =3D { 0x40040000, 0x1000 }, - [IBEX_DEV_SPI] =3D { 0x40050000, 0x1000 }, + [IBEX_DEV_SPI_DEVICE] =3D { 0x40050000, 0x1000 }, [IBEX_DEV_I2C] =3D { 0x40080000, 0x1000 }, [IBEX_DEV_PATTGEN] =3D { 0x400e0000, 0x1000 }, [IBEX_DEV_TIMER] =3D { 0x40100000, 0x1000 }, [IBEX_DEV_SENSOR_CTRL] =3D { 0x40110000, 0x1000 }, [IBEX_DEV_OTP_CTRL] =3D { 0x40130000, 0x4000 }, [IBEX_DEV_USBDEV] =3D { 0x40150000, 0x1000 }, + [IBEX_DEV_SPI_HOST0] =3D { 0x40300000, 0x1000 }, + [IBEX_DEV_SPI_HOST1] =3D { 0x40310000, 0x1000 }, [IBEX_DEV_PWRMGR] =3D { 0x40400000, 0x1000 }, [IBEX_DEV_RSTMGR] =3D { 0x40410000, 0x1000 }, [IBEX_DEV_CLKMGR] =3D { 0x40420000, 0x1000 }, @@ -209,8 +211,12 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_= soc, Error **errp) =20 create_unimplemented_device("riscv.lowrisc.ibex.gpio", memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size); - create_unimplemented_device("riscv.lowrisc.ibex.spi", - memmap[IBEX_DEV_SPI].base, memmap[IBEX_DEV_SPI].size); + create_unimplemented_device("riscv.lowrisc.ibex.spi_device", + memmap[IBEX_DEV_SPI_DEVICE].base, memmap[IBEX_DEV_SPI_DEVICE].size= ); + create_unimplemented_device("riscv.lowrisc.ibex.spi_host0", + memmap[IBEX_DEV_SPI_HOST0].base, memmap[IBEX_DEV_SPI_HOST0].size); + create_unimplemented_device("riscv.lowrisc.ibex.spi_host1", + memmap[IBEX_DEV_SPI_HOST1].base, memmap[IBEX_DEV_SPI_HOST1].size); create_unimplemented_device("riscv.lowrisc.ibex.i2c", memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size); create_unimplemented_device("riscv.lowrisc.ibex.pattgen", --=20 2.35.1