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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1646285304; x=1648877305; bh=MUZz+LwRynMTgIS3CJ SCWRQFEAgiKHT458bfHMZIv8k=; b=SrXsJDqoS+mwvbdqrFMedGNMA1d6KPpkXN /a5OzhwlCn+J4GwrYpvCszQytvseJN3J0wx+Iz0VhaPv3artTncOUlhrNTiI2jpu fol7TTmy82DE04LSO0FMMF+yT1mbZQ9OosDQesxGeQUjvrtwfPSCaHrnhIY0hZR2 rZdf1X8gyzRVxEW2ZEpZKeN2fV/rv/FE509QAXQ4Bieo1pZtCwxoS7t1d07dLCIv 7E9Xqa1Pc8dsUuJIGk9nJw6W+ckfXSP1Px5NODQ4m9hZejDSsTv5W9oyBwtY17yc eLhLqR5DKSxxN+ferOahcFZGwZISLFhBSyWt4YadNM3Tfqpm9JPw== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Philipp Tomsich , Alistair Francis Subject: [PULL 01/13] target/riscv: fix inverted checks for ext_zb[abcs] Date: Thu, 3 Mar 2022 15:27:52 +1000 Message-Id: <20220303052804.529967-2-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220303052804.529967-1-alistair.francis@opensource.wdc.com> References: <20220303052804.529967-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.154.45; envelope-from=prvs=05403f1d5=alistair.francis@opensource.wdc.com; helo=esa6.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1646285473432100001 Content-Type: text/plain; charset="utf-8" From: Philipp Tomsich While changing to the use of cfg_ptr, the conditions for REQUIRE_ZB[ABCS] inadvertently became inverted and slipped through the initial testing (which used RV64GC_XVentanaCondOps as a target). This fixes the regression. Tested against SPEC2017 w/ GCC 12 (prerelease) for RV64GC_zba_zbb_zbc_zbs. Fixes: f2a32bec8f0da99 ("target/riscv: access cfg structure through DisasCo= ntext") Signed-off-by: Philipp Tomsich Reviewed-by: Alistair Francis Message-Id: <20220203153946.2676353-1-philipp.tomsich@vrull.eu> Signed-off-by: Alistair Francis --- target/riscv/insn_trans/trans_rvb.c.inc | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/target/riscv/insn_trans/trans_rvb.c.inc b/target/riscv/insn_tr= ans/trans_rvb.c.inc index f9bd3b7ec4..e8519a6d69 100644 --- a/target/riscv/insn_trans/trans_rvb.c.inc +++ b/target/riscv/insn_trans/trans_rvb.c.inc @@ -19,25 +19,25 @@ */ =20 #define REQUIRE_ZBA(ctx) do { \ - if (ctx->cfg_ptr->ext_zba) { \ + if (!ctx->cfg_ptr->ext_zba) { \ return false; \ } \ } while (0) =20 #define REQUIRE_ZBB(ctx) do { \ - if (ctx->cfg_ptr->ext_zbb) { \ + if (!ctx->cfg_ptr->ext_zbb) { \ return false; \ } \ } while (0) =20 #define REQUIRE_ZBC(ctx) do { \ - if (ctx->cfg_ptr->ext_zbc) { \ + if (!ctx->cfg_ptr->ext_zbc) { \ return false; \ } \ } while (0) =20 #define REQUIRE_ZBS(ctx) do { \ - if (ctx->cfg_ptr->ext_zbs) { \ + if (!ctx->cfg_ptr->ext_zbs) { \ return false; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1646285309; x=1648877310; bh=vwfffb7uOAbcbFms73 B4qrF+Q5n2X60H9OXvkn4LzGs=; b=jz1d7eQGqrlKiwwxpkHrOXm7WG+8yHUGM3 VojMxNYgt1k6z/b5H0Nml4SIrmbAapouX/Zf29ajtmT4Gf+0zxyxzG/peUOvqhci 9kAUXYqjQdMi6um0VZnCD4knYyA2Fq/xXSzaPh9TxHF83XM3A2Rq4fbcAIaTQCdI rKn0SZfAjBg0CPHvnrE5B5k0PWwcHD8L92TcwMKmGHUjTx7HDYlk6TeMBhki0VF4 Ofp7pw/HRVo6r9V82QlVQ49KwDmZbDbRp1iN1qbdxNeE8tzGQbRqRcgK0rtVQEHg OioC0TtXqcZG0Jz3q/B5ZCkpE5y7WhD9nw4Qx3V08IwrVEIzu2nQ== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Anup Patel , Anup Patel , Alistair Francis Subject: [PULL 02/13] hw/riscv: virt: Add optional AIA APLIC support to virt machine Date: Thu, 3 Mar 2022 15:27:53 +1000 Message-Id: <20220303052804.529967-3-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220303052804.529967-1-alistair.francis@opensource.wdc.com> References: <20220303052804.529967-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=05403f1d5=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1646285483325100001 Content-Type: text/plain; charset="utf-8" From: Anup Patel We extend virt machine to emulate AIA APLIC devices only when "aia=3Daplic" parameter is passed along with machine name in QEMU command-line. When "aia=3Dnone" or not specified then we fallback to original PLIC device emulation. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Message-Id: <20220220085526.808674-2-anup@brainfault.org> Signed-off-by: Alistair Francis --- include/hw/riscv/virt.h | 26 +++- hw/riscv/virt.c | 291 ++++++++++++++++++++++++++++++++-------- hw/riscv/Kconfig | 1 + 3 files changed, 259 insertions(+), 59 deletions(-) diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 6e9f61ccd9..47706b456d 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -32,18 +32,24 @@ typedef struct RISCVVirtState RISCVVirtState; DECLARE_INSTANCE_CHECKER(RISCVVirtState, RISCV_VIRT_MACHINE, TYPE_RISCV_VIRT_MACHINE) =20 +typedef enum RISCVVirtAIAType { + VIRT_AIA_TYPE_NONE =3D 0, + VIRT_AIA_TYPE_APLIC, +} RISCVVirtAIAType; + struct RISCVVirtState { /*< private >*/ MachineState parent; =20 /*< public >*/ RISCVHartArrayState soc[VIRT_SOCKETS_MAX]; - DeviceState *plic[VIRT_SOCKETS_MAX]; + DeviceState *irqchip[VIRT_SOCKETS_MAX]; PFlashCFI01 *flash[2]; FWCfgState *fw_cfg; =20 int fdt_size; bool have_aclint; + RISCVVirtAIAType aia_type; }; =20 enum { @@ -54,6 +60,8 @@ enum { VIRT_CLINT, VIRT_ACLINT_SSWI, VIRT_PLIC, + VIRT_APLIC_M, + VIRT_APLIC_S, VIRT_UART0, VIRT_VIRTIO, VIRT_FW_CFG, @@ -73,8 +81,9 @@ enum { VIRTIO_NDEV =3D 0x35 /* Arbitrary maximum number of interrupts */ }; =20 -#define VIRT_PLIC_NUM_SOURCES 127 -#define VIRT_PLIC_NUM_PRIORITIES 7 +#define VIRT_IRQCHIP_NUM_SOURCES 127 +#define VIRT_IRQCHIP_NUM_PRIO_BITS 3 + #define VIRT_PLIC_PRIORITY_BASE 0x04 #define VIRT_PLIC_PENDING_BASE 0x1000 #define VIRT_PLIC_ENABLE_BASE 0x2000 @@ -86,9 +95,14 @@ enum { =20 #define FDT_PCI_ADDR_CELLS 3 #define FDT_PCI_INT_CELLS 1 -#define FDT_PLIC_ADDR_CELLS 0 #define FDT_PLIC_INT_CELLS 1 -#define FDT_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + 1 = + \ - FDT_PLIC_ADDR_CELLS + FDT_PLIC_INT_CELLS) +#define FDT_APLIC_INT_CELLS 2 +#define FDT_MAX_INT_CELLS 2 +#define FDT_MAX_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ + 1 + FDT_MAX_INT_CELLS) +#define FDT_PLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ + 1 + FDT_PLIC_INT_CELLS) +#define FDT_APLIC_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ + 1 + FDT_APLIC_INT_CELLS) =20 #endif diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index e3068d6126..6b06f79b46 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -33,6 +33,7 @@ #include "hw/riscv/boot.h" #include "hw/riscv/numa.h" #include "hw/intc/riscv_aclint.h" +#include "hw/intc/riscv_aplic.h" #include "hw/intc/sifive_plic.h" #include "hw/misc/sifive_test.h" #include "chardev/char.h" @@ -52,6 +53,8 @@ static const MemMapEntry virt_memmap[] =3D { [VIRT_ACLINT_SSWI] =3D { 0x2F00000, 0x4000 }, [VIRT_PCIE_PIO] =3D { 0x3000000, 0x10000 }, [VIRT_PLIC] =3D { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2)= }, + [VIRT_APLIC_M] =3D { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, + [VIRT_APLIC_S] =3D { 0xd000000, APLIC_SIZE(VIRT_CPUS_MAX) }, [VIRT_UART0] =3D { 0x10000000, 0x100 }, [VIRT_VIRTIO] =3D { 0x10001000, 0x1000 }, [VIRT_FW_CFG] =3D { 0x10100000, 0x18 }, @@ -133,12 +136,13 @@ static void virt_flash_map(RISCVVirtState *s, sysmem); } =20 -static void create_pcie_irq_map(void *fdt, char *nodename, - uint32_t plic_phandle) +static void create_pcie_irq_map(RISCVVirtState *s, void *fdt, char *nodena= me, + uint32_t irqchip_phandle) { int pin, dev; - uint32_t - full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = =3D {}; + uint32_t irq_map_stride =3D 0; + uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * + FDT_MAX_INT_MAP_WIDTH] =3D {}; uint32_t *irq_map =3D full_irq_map; =20 /* This code creates a standard swizzle of interrupts such that @@ -156,23 +160,31 @@ static void create_pcie_irq_map(void *fdt, char *node= name, int irq_nr =3D PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_= IRQS); int i =3D 0; =20 + /* Fill PCI address cells */ irq_map[i] =3D cpu_to_be32(devfn << 8); - i +=3D FDT_PCI_ADDR_CELLS; - irq_map[i] =3D cpu_to_be32(pin + 1); =20 + /* Fill PCI Interrupt cells */ + irq_map[i] =3D cpu_to_be32(pin + 1); i +=3D FDT_PCI_INT_CELLS; - irq_map[i++] =3D cpu_to_be32(plic_phandle); =20 - i +=3D FDT_PLIC_ADDR_CELLS; - irq_map[i] =3D cpu_to_be32(irq_nr); + /* Fill interrupt controller phandle and cells */ + irq_map[i++] =3D cpu_to_be32(irqchip_phandle); + irq_map[i++] =3D cpu_to_be32(irq_nr); + if (s->aia_type !=3D VIRT_AIA_TYPE_NONE) { + irq_map[i++] =3D cpu_to_be32(0x4); + } =20 - irq_map +=3D FDT_INT_MAP_WIDTH; + if (!irq_map_stride) { + irq_map_stride =3D i; + } + irq_map +=3D irq_map_stride; } } =20 - qemu_fdt_setprop(fdt, nodename, "interrupt-map", - full_irq_map, sizeof(full_irq_map)); + qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, + GPEX_NUM_IRQS * GPEX_NUM_IRQS * + irq_map_stride * sizeof(uint32_t)); =20 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 0x1800, 0, 0, 0x7); @@ -404,8 +416,6 @@ static void create_fdt_socket_plic(RISCVVirtState *s, plic_addr =3D memmap[VIRT_PLIC].base + (memmap[VIRT_PLIC].size * socke= t); plic_name =3D g_strdup_printf("/soc/plic@%lx", plic_addr); qemu_fdt_add_subnode(mc->fdt, plic_name); - qemu_fdt_setprop_cell(mc->fdt, plic_name, - "#address-cells", FDT_PLIC_ADDR_CELLS); qemu_fdt_setprop_cell(mc->fdt, plic_name, "#interrupt-cells", FDT_PLIC_INT_CELLS); qemu_fdt_setprop_string_array(mc->fdt, plic_name, "compatible", @@ -425,6 +435,76 @@ static void create_fdt_socket_plic(RISCVVirtState *s, g_free(plic_cells); } =20 +static void create_fdt_socket_aia(RISCVVirtState *s, + const MemMapEntry *memmap, int socket, + uint32_t *phandle, uint32_t *intc_phandl= es, + uint32_t *aplic_phandles) +{ + int cpu; + char *aplic_name; + uint32_t *aplic_cells; + unsigned long aplic_addr; + MachineState *mc =3D MACHINE(s); + uint32_t aplic_m_phandle, aplic_s_phandle; + + aplic_m_phandle =3D (*phandle)++; + aplic_s_phandle =3D (*phandle)++; + aplic_cells =3D g_new0(uint32_t, s->soc[socket].num_harts * 2); + + /* M-level APLIC node */ + for (cpu =3D 0; cpu < s->soc[socket].num_harts; cpu++) { + aplic_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); + aplic_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_M_EXT); + } + aplic_addr =3D memmap[VIRT_APLIC_M].base + + (memmap[VIRT_APLIC_M].size * socket); + aplic_name =3D g_strdup_printf("/soc/aplic@%lx", aplic_addr); + qemu_fdt_add_subnode(mc->fdt, aplic_name); + qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,apli= c"); + qemu_fdt_setprop_cell(mc->fdt, aplic_name, + "#interrupt-cells", FDT_APLIC_INT_CELLS); + qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", + aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); + qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", + 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size); + qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", + VIRT_IRQCHIP_NUM_SOURCES); + qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,children", + aplic_s_phandle); + qemu_fdt_setprop_cells(mc->fdt, aplic_name, "riscv,delegate", + aplic_s_phandle, 0x1, VIRT_IRQCHIP_NUM_SOURCES); + riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); + qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_m_phandle); + g_free(aplic_name); + + /* S-level APLIC node */ + for (cpu =3D 0; cpu < s->soc[socket].num_harts; cpu++) { + aplic_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); + aplic_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_S_EXT); + } + aplic_addr =3D memmap[VIRT_APLIC_S].base + + (memmap[VIRT_APLIC_S].size * socket); + aplic_name =3D g_strdup_printf("/soc/aplic@%lx", aplic_addr); + qemu_fdt_add_subnode(mc->fdt, aplic_name); + qemu_fdt_setprop_string(mc->fdt, aplic_name, "compatible", "riscv,apli= c"); + qemu_fdt_setprop_cell(mc->fdt, aplic_name, + "#interrupt-cells", FDT_APLIC_INT_CELLS); + qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", + aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); + qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", + 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size); + qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", + VIRT_IRQCHIP_NUM_SOURCES); + riscv_socket_fdt_write_id(mc, mc->fdt, aplic_name, socket); + qemu_fdt_setprop_cell(mc->fdt, aplic_name, "phandle", aplic_s_phandle); + g_free(aplic_name); + + g_free(aplic_cells); + aplic_phandles[socket] =3D aplic_s_phandle; +} + static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memma= p, bool is_32_bit, uint32_t *phandle, uint32_t *irq_mmio_phandle, @@ -463,8 +543,13 @@ static void create_fdt_sockets(RISCVVirtState *s, cons= t MemMapEntry *memmap, } } =20 - create_fdt_socket_plic(s, memmap, socket, phandle, - intc_phandles, xplic_phandles); + if (s->aia_type =3D=3D VIRT_AIA_TYPE_NONE) { + create_fdt_socket_plic(s, memmap, socket, phandle, + intc_phandles, xplic_phandles); + } else { + create_fdt_socket_aia(s, memmap, socket, phandle, + intc_phandles, xplic_phandles); + } =20 g_free(intc_phandles); g_free(clust_name); @@ -505,7 +590,13 @@ static void create_fdt_virtio(RISCVVirtState *s, const= MemMapEntry *memmap, 0x0, memmap[VIRT_VIRTIO].size); qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_virtio_phandle); - qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", VIRTIO_IRQ + i); + if (s->aia_type =3D=3D VIRT_AIA_TYPE_NONE) { + qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", + VIRTIO_IRQ + i); + } else { + qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", + VIRTIO_IRQ + i, 0x4); + } g_free(name); } } @@ -543,7 +634,7 @@ static void create_fdt_pcie(RISCVVirtState *s, const Me= mMapEntry *memmap, 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); =20 - create_pcie_irq_map(mc->fdt, name, irq_pcie_phandle); + create_pcie_irq_map(s, mc->fdt, name, irq_pcie_phandle); g_free(name); } =20 @@ -602,7 +693,11 @@ static void create_fdt_uart(RISCVVirtState *s, const M= emMapEntry *memmap, 0x0, memmap[VIRT_UART0].size); qemu_fdt_setprop_cell(mc->fdt, name, "clock-frequency", 3686400); qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phan= dle); - qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ); + if (s->aia_type =3D=3D VIRT_AIA_TYPE_NONE) { + qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", UART0_IRQ); + } else { + qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", UART0_IRQ, 0x4= ); + } =20 qemu_fdt_add_subnode(mc->fdt, "/chosen"); qemu_fdt_setprop_string(mc->fdt, "/chosen", "stdout-path", name); @@ -623,7 +718,11 @@ static void create_fdt_rtc(RISCVVirtState *s, const Me= mMapEntry *memmap, 0x0, memmap[VIRT_RTC].base, 0x0, memmap[VIRT_RTC].size); qemu_fdt_setprop_cell(mc->fdt, name, "interrupt-parent", irq_mmio_phandle); - qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ); + if (s->aia_type =3D=3D VIRT_AIA_TYPE_NONE) { + qemu_fdt_setprop_cell(mc->fdt, name, "interrupts", RTC_IRQ); + } else { + qemu_fdt_setprop_cells(mc->fdt, name, "interrupts", RTC_IRQ, 0x4); + } g_free(name); } =20 @@ -704,7 +803,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion = *sys_mem, hwaddr high_mmio_base, hwaddr high_mmio_size, hwaddr pio_base, - DeviceState *plic) + DeviceState *irqchip) { DeviceState *dev; MemoryRegion *ecam_alias, *ecam_reg; @@ -738,7 +837,7 @@ static inline DeviceState *gpex_pcie_init(MemoryRegion = *sys_mem, sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); =20 for (i =3D 0; i < GPEX_NUM_IRQS; i++) { - irq =3D qdev_get_gpio_in(plic, PCIE_IRQ + i); + irq =3D qdev_get_gpio_in(irqchip, PCIE_IRQ + i); =20 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); @@ -769,18 +868,75 @@ static FWCfgState *create_fw_cfg(const MachineState *= mc) return fw_cfg; } =20 +static DeviceState *virt_create_plic(const MemMapEntry *memmap, int socket, + int base_hartid, int hart_count) +{ + DeviceState *ret; + char *plic_hart_config; + + /* Per-socket PLIC hart topology configuration string */ + plic_hart_config =3D riscv_plic_hart_config_string(hart_count); + + /* Per-socket PLIC */ + ret =3D sifive_plic_create( + memmap[VIRT_PLIC].base + socket * memmap[VIRT_PLIC].size, + plic_hart_config, hart_count, base_hartid, + VIRT_IRQCHIP_NUM_SOURCES, + ((1U << VIRT_IRQCHIP_NUM_PRIO_BITS) - 1), + VIRT_PLIC_PRIORITY_BASE, + VIRT_PLIC_PENDING_BASE, + VIRT_PLIC_ENABLE_BASE, + VIRT_PLIC_ENABLE_STRIDE, + VIRT_PLIC_CONTEXT_BASE, + VIRT_PLIC_CONTEXT_STRIDE, + memmap[VIRT_PLIC].size); + + g_free(plic_hart_config); + + return ret; +} + +static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, + const MemMapEntry *memmap, int socket, + int base_hartid, int hart_count) +{ + DeviceState *aplic_m; + + /* Per-socket M-level APLIC */ + aplic_m =3D riscv_aplic_create( + memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].size, + memmap[VIRT_APLIC_M].size, + base_hartid, hart_count, + VIRT_IRQCHIP_NUM_SOURCES, + VIRT_IRQCHIP_NUM_PRIO_BITS, + false, true, NULL); + + if (aplic_m) { + /* Per-socket S-level APLIC */ + riscv_aplic_create( + memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size, + memmap[VIRT_APLIC_S].size, + base_hartid, hart_count, + VIRT_IRQCHIP_NUM_SOURCES, + VIRT_IRQCHIP_NUM_PRIO_BITS, + false, false, aplic_m); + } + + return aplic_m; +} + static void virt_machine_init(MachineState *machine) { const MemMapEntry *memmap =3D virt_memmap; RISCVVirtState *s =3D RISCV_VIRT_MACHINE(machine); MemoryRegion *system_memory =3D get_system_memory(); MemoryRegion *mask_rom =3D g_new(MemoryRegion, 1); - char *plic_hart_config, *soc_name; + char *soc_name; target_ulong start_addr =3D memmap[VIRT_DRAM].base; target_ulong firmware_end_addr, kernel_start_addr; uint32_t fdt_load_addr; uint64_t kernel_entry; - DeviceState *mmio_plic, *virtio_plic, *pcie_plic; + DeviceState *mmio_irqchip, *virtio_irqchip, *pcie_irqchip; int i, base_hartid, hart_count; =20 /* Check socket count limit */ @@ -791,7 +947,7 @@ static void virt_machine_init(MachineState *machine) } =20 /* Initialize sockets */ - mmio_plic =3D virtio_plic =3D pcie_plic =3D NULL; + mmio_irqchip =3D virtio_irqchip =3D pcie_irqchip =3D NULL; for (i =3D 0; i < riscv_socket_count(machine); i++) { if (!riscv_socket_check_hartids(machine, i)) { error_report("discontinuous hartids in socket%d", i); @@ -843,36 +999,27 @@ static void virt_machine_init(MachineState *machine) } } =20 - /* Per-socket PLIC hart topology configuration string */ - plic_hart_config =3D riscv_plic_hart_config_string(hart_count); - - /* Per-socket PLIC */ - s->plic[i] =3D sifive_plic_create( - memmap[VIRT_PLIC].base + i * memmap[VIRT_PLIC].size, - plic_hart_config, hart_count, base_hartid, - VIRT_PLIC_NUM_SOURCES, - VIRT_PLIC_NUM_PRIORITIES, - VIRT_PLIC_PRIORITY_BASE, - VIRT_PLIC_PENDING_BASE, - VIRT_PLIC_ENABLE_BASE, - VIRT_PLIC_ENABLE_STRIDE, - VIRT_PLIC_CONTEXT_BASE, - VIRT_PLIC_CONTEXT_STRIDE, - memmap[VIRT_PLIC].size); - g_free(plic_hart_config); + /* Per-socket interrupt controller */ + if (s->aia_type =3D=3D VIRT_AIA_TYPE_NONE) { + s->irqchip[i] =3D virt_create_plic(memmap, i, + base_hartid, hart_count); + } else { + s->irqchip[i] =3D virt_create_aia(s->aia_type, memmap, i, + base_hartid, hart_count); + } =20 - /* Try to use different PLIC instance based device type */ + /* Try to use different IRQCHIP instance based device type */ if (i =3D=3D 0) { - mmio_plic =3D s->plic[i]; - virtio_plic =3D s->plic[i]; - pcie_plic =3D s->plic[i]; + mmio_irqchip =3D s->irqchip[i]; + virtio_irqchip =3D s->irqchip[i]; + pcie_irqchip =3D s->irqchip[i]; } if (i =3D=3D 1) { - virtio_plic =3D s->plic[i]; - pcie_plic =3D s->plic[i]; + virtio_irqchip =3D s->irqchip[i]; + pcie_irqchip =3D s->irqchip[i]; } if (i =3D=3D 2) { - pcie_plic =3D s->plic[i]; + pcie_irqchip =3D s->irqchip[i]; } } =20 @@ -990,7 +1137,7 @@ static void virt_machine_init(MachineState *machine) for (i =3D 0; i < VIRTIO_COUNT; i++) { sysbus_create_simple("virtio-mmio", memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, - qdev_get_gpio_in(DEVICE(virtio_plic), VIRTIO_IRQ + i)); + qdev_get_gpio_in(DEVICE(virtio_irqchip), VIRTIO_IRQ + i)); } =20 gpex_pcie_init(system_memory, @@ -1001,14 +1148,14 @@ static void virt_machine_init(MachineState *machine) virt_high_pcie_memmap.base, virt_high_pcie_memmap.size, memmap[VIRT_PCIE_PIO].base, - DEVICE(pcie_plic)); + DEVICE(pcie_irqchip)); =20 serial_mm_init(system_memory, memmap[VIRT_UART0].base, - 0, qdev_get_gpio_in(DEVICE(mmio_plic), UART0_IRQ), 399193, + 0, qdev_get_gpio_in(DEVICE(mmio_irqchip), UART0_IRQ), 399193, serial_hd(0), DEVICE_LITTLE_ENDIAN); =20 sysbus_create_simple("goldfish_rtc", memmap[VIRT_RTC].base, - qdev_get_gpio_in(DEVICE(mmio_plic), RTC_IRQ)); + qdev_get_gpio_in(DEVICE(mmio_irqchip), RTC_IRQ)); =20 virt_flash_create(s); =20 @@ -1024,6 +1171,37 @@ static void virt_machine_instance_init(Object *obj) { } =20 +static char *virt_get_aia(Object *obj, Error **errp) +{ + RISCVVirtState *s =3D RISCV_VIRT_MACHINE(obj); + const char *val; + + switch (s->aia_type) { + case VIRT_AIA_TYPE_APLIC: + val =3D "aplic"; + break; + default: + val =3D "none"; + break; + }; + + return g_strdup(val); +} + +static void virt_set_aia(Object *obj, const char *val, Error **errp) +{ + RISCVVirtState *s =3D RISCV_VIRT_MACHINE(obj); + + if (!strcmp(val, "none")) { + s->aia_type =3D VIRT_AIA_TYPE_NONE; + } else if (!strcmp(val, "aplic")) { + s->aia_type =3D VIRT_AIA_TYPE_APLIC; + } else { + error_setg(errp, "Invalid AIA interrupt controller type"); + error_append_hint(errp, "Valid values are none, and aplic.\n"); + } +} + static bool virt_get_aclint(Object *obj, Error **errp) { MachineState *ms =3D MACHINE(obj); @@ -1062,6 +1240,13 @@ static void virt_machine_class_init(ObjectClass *oc,= void *data) object_class_property_set_description(oc, "aclint", "Set on/off to enable/disable " "emulating ACLINT devices"); + + object_class_property_add_str(oc, "aia", virt_get_aia, + virt_set_aia); + object_class_property_set_description(oc, "aia", + "Set type of AIA interrupt " + "conttoller. Valid values are " + "none, and aplic."); } =20 static const TypeInfo virt_machine_typeinfo =3D { diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index d2d869aaad..c30bb7cb6c 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -42,6 +42,7 @@ config RISCV_VIRT select PFLASH_CFI01 select SERIAL select RISCV_ACLINT + select RISCV_APLIC select SIFIVE_PLIC select SIFIVE_TEST select VIRTIO_MMIO --=20 2.35.1 From nobody Tue May 14 20:20:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646285647828225.37845576497693; Wed, 2 Mar 2022 21:34:07 -0800 (PST) Received: from localhost ([::1]:52276 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nPe6J-00027h-7z for importer@patchew.org; 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s=dkim; t=1646285314; x=1648877315; bh=ChAc2z794yrRBoihVQ 4DAFFBNDmIVUhwv9znXDutxeg=; b=sGxlU56kjTlV0ZJ3C5EWmrVAIdiqmx4JGh iW4SDpWX8di84xlgzXohkrdmnqa74iodKbsObz12wwukZ3eWe7yIriJu6z0iUCV2 5eaw+JEvKrpdgVBV3qkx5VjT9aNtckUXHUtgGUysSdPl/u3LyUh2pMi4IT6mfs4l 81z2DQgCuuUxZChyxmfyy/nUdfsCNSwHc3DneJ1tbrlkbGEgmpoejhBMKTEmTpi1 gJxdHaR3IHWwbqvIRCGcqIfbIb17fVSiMDNLG5klFhgBh1TMuf5u0X0NmzcyCXBC O6LEaPula9uJTo4jLIkQ5UN2cfFLGFvnF6BXaA65mjEqu2b6XNMw== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Anup Patel , Anup Patel , Frank Chang , Alistair Francis Subject: [PULL 03/13] hw/intc: Add RISC-V AIA IMSIC device emulation Date: Thu, 3 Mar 2022 15:27:54 +1000 Message-Id: <20220303052804.529967-4-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220303052804.529967-1-alistair.francis@opensource.wdc.com> References: <20220303052804.529967-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=05403f1d5=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1646285662961100003 Content-Type: text/plain; charset="utf-8" From: Anup Patel The RISC-V AIA (Advanced Interrupt Architecture) defines a new interrupt controller for MSIs (message signal interrupts) called IMSIC (Incoming Message Signal Interrupt Controller). The IMSIC is per-HART device and also suppport virtualizaiton of MSIs using dedicated VS-level guest interrupt files. This patch adds device emulation for RISC-V AIA IMSIC which supports M-level, S-level, and VS-level MSIs. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Frank Chang Message-Id: <20220220085526.808674-3-anup@brainfault.org> Signed-off-by: Alistair Francis --- include/hw/intc/riscv_imsic.h | 68 ++++++ hw/intc/riscv_imsic.c | 448 ++++++++++++++++++++++++++++++++++ hw/intc/Kconfig | 3 + hw/intc/meson.build | 1 + 4 files changed, 520 insertions(+) create mode 100644 include/hw/intc/riscv_imsic.h create mode 100644 hw/intc/riscv_imsic.c diff --git a/include/hw/intc/riscv_imsic.h b/include/hw/intc/riscv_imsic.h new file mode 100644 index 0000000000..58c2aaa8dc --- /dev/null +++ b/include/hw/intc/riscv_imsic.h @@ -0,0 +1,68 @@ +/* + * RISC-V IMSIC (Incoming Message Signal Interrupt Controller) interface + * + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#ifndef HW_RISCV_IMSIC_H +#define HW_RISCV_IMSIC_H + +#include "hw/sysbus.h" +#include "qom/object.h" + +#define TYPE_RISCV_IMSIC "riscv.imsic" + +typedef struct RISCVIMSICState RISCVIMSICState; +DECLARE_INSTANCE_CHECKER(RISCVIMSICState, RISCV_IMSIC, TYPE_RISCV_IMSIC) + +#define IMSIC_MMIO_PAGE_SHIFT 12 +#define IMSIC_MMIO_PAGE_SZ (1UL << IMSIC_MMIO_PAGE_SHIFT) +#define IMSIC_MMIO_SIZE(__num_pages) ((__num_pages) * IMSIC_MMIO_PAGE_SZ) + +#define IMSIC_MMIO_HART_GUEST_MAX_BTIS 6 +#define IMSIC_MMIO_GROUP_MIN_SHIFT 24 + +#define IMSIC_HART_NUM_GUESTS(__guest_bits) \ + (1U << (__guest_bits)) +#define IMSIC_HART_SIZE(__guest_bits) \ + (IMSIC_HART_NUM_GUESTS(__guest_bits) * IMSIC_MMIO_PAGE_SZ) +#define IMSIC_GROUP_NUM_HARTS(__hart_bits) \ + (1U << (__hart_bits)) +#define IMSIC_GROUP_SIZE(__hart_bits, __guest_bits) \ + (IMSIC_GROUP_NUM_HARTS(__hart_bits) * IMSIC_HART_SIZE(__guest_bits)) + +struct RISCVIMSICState { + /*< private >*/ + SysBusDevice parent_obj; + qemu_irq *external_irqs; + + /*< public >*/ + MemoryRegion mmio; + uint32_t num_eistate; + uint32_t *eidelivery; + uint32_t *eithreshold; + uint32_t *eistate; + + /* config */ + bool mmode; + uint32_t hartid; + uint32_t num_pages; + uint32_t num_irqs; +}; + +DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode, + uint32_t num_pages, uint32_t num_ids); + +#endif diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c new file mode 100644 index 0000000000..8615e4cc1d --- /dev/null +++ b/hw/intc/riscv_imsic.c @@ -0,0 +1,448 @@ +/* + * RISC-V IMSIC (Incoming Message Signaled Interrupt Controller) + * + * Copyright (c) 2021 Western Digital Corporation or its affiliates. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License f= or + * more details. + * + * You should have received a copy of the GNU General Public License along= with + * this program. If not, see . + */ + +#include "qemu/osdep.h" +#include "qapi/error.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "qemu/error-report.h" +#include "qemu/bswap.h" +#include "exec/address-spaces.h" +#include "hw/sysbus.h" +#include "hw/pci/msi.h" +#include "hw/boards.h" +#include "hw/qdev-properties.h" +#include "hw/intc/riscv_imsic.h" +#include "hw/irq.h" +#include "target/riscv/cpu.h" +#include "target/riscv/cpu_bits.h" +#include "sysemu/sysemu.h" +#include "migration/vmstate.h" + +#define IMSIC_MMIO_PAGE_LE 0x00 +#define IMSIC_MMIO_PAGE_BE 0x04 + +#define IMSIC_MIN_ID ((IMSIC_EIPx_BITS * 2) - 1) +#define IMSIC_MAX_ID (IMSIC_TOPEI_IID_MASK) + +#define IMSIC_EISTATE_PENDING (1U << 0) +#define IMSIC_EISTATE_ENABLED (1U << 1) +#define IMSIC_EISTATE_ENPEND (IMSIC_EISTATE_ENABLED | \ + IMSIC_EISTATE_PENDING) + +static uint32_t riscv_imsic_topei(RISCVIMSICState *imsic, uint32_t page) +{ + uint32_t i, max_irq, base; + + base =3D page * imsic->num_irqs; + max_irq =3D (imsic->eithreshold[page] && + (imsic->eithreshold[page] <=3D imsic->num_irqs)) ? + imsic->eithreshold[page] : imsic->num_irqs; + for (i =3D 1; i < max_irq; i++) { + if ((imsic->eistate[base + i] & IMSIC_EISTATE_ENPEND) =3D=3D + IMSIC_EISTATE_ENPEND) { + return (i << IMSIC_TOPEI_IID_SHIFT) | i; + } + } + + return 0; +} + +static void riscv_imsic_update(RISCVIMSICState *imsic, uint32_t page) +{ + if (imsic->eidelivery[page] && riscv_imsic_topei(imsic, page)) { + qemu_irq_raise(imsic->external_irqs[page]); + } else { + qemu_irq_lower(imsic->external_irqs[page]); + } +} + +static int riscv_imsic_eidelivery_rmw(RISCVIMSICState *imsic, uint32_t pag= e, + target_ulong *val, + target_ulong new_val, + target_ulong wr_mask) +{ + target_ulong old_val =3D imsic->eidelivery[page]; + + if (val) { + *val =3D old_val; + } + + wr_mask &=3D 0x1; + imsic->eidelivery[page] =3D (old_val & ~wr_mask) | (new_val & wr_mask); + + riscv_imsic_update(imsic, page); + return 0; +} + +static int riscv_imsic_eithreshold_rmw(RISCVIMSICState *imsic, uint32_t pa= ge, + target_ulong *val, + target_ulong new_val, + target_ulong wr_mask) +{ + target_ulong old_val =3D imsic->eithreshold[page]; + + if (val) { + *val =3D old_val; + } + + wr_mask &=3D IMSIC_MAX_ID; + imsic->eithreshold[page] =3D (old_val & ~wr_mask) | (new_val & wr_mask= ); + + riscv_imsic_update(imsic, page); + return 0; +} + +static int riscv_imsic_topei_rmw(RISCVIMSICState *imsic, uint32_t page, + target_ulong *val, target_ulong new_val, + target_ulong wr_mask) +{ + uint32_t base, topei =3D riscv_imsic_topei(imsic, page); + + /* Read pending and enabled interrupt with highest priority */ + if (val) { + *val =3D topei; + } + + /* Writes ignore value and clear top pending interrupt */ + if (topei && wr_mask) { + topei >>=3D IMSIC_TOPEI_IID_SHIFT; + base =3D page * imsic->num_irqs; + if (topei) { + imsic->eistate[base + topei] &=3D ~IMSIC_EISTATE_PENDING; + } + + riscv_imsic_update(imsic, page); + } + + return 0; +} + +static int riscv_imsic_eix_rmw(RISCVIMSICState *imsic, + uint32_t xlen, uint32_t page, + uint32_t num, bool pend, target_ulong *val, + target_ulong new_val, target_ulong wr_mask) +{ + uint32_t i, base; + target_ulong mask; + uint32_t state =3D (pend) ? IMSIC_EISTATE_PENDING : IMSIC_EISTATE_ENAB= LED; + + if (xlen !=3D 32) { + if (num & 0x1) { + return -EINVAL; + } + num >>=3D 1; + } + if (num >=3D (imsic->num_irqs / xlen)) { + return -EINVAL; + } + + base =3D (page * imsic->num_irqs) + (num * xlen); + + if (val) { + *val =3D 0; + for (i =3D 0; i < xlen; i++) { + mask =3D (target_ulong)1 << i; + *val |=3D (imsic->eistate[base + i] & state) ? mask : 0; + } + } + + for (i =3D 0; i < xlen; i++) { + /* Bit0 of eip0 and eie0 are read-only zero */ + if (!num && !i) { + continue; + } + + mask =3D (target_ulong)1 << i; + if (wr_mask & mask) { + if (new_val & mask) { + imsic->eistate[base + i] |=3D state; + } else { + imsic->eistate[base + i] &=3D ~state; + } + } + } + + riscv_imsic_update(imsic, page); + return 0; +} + +static int riscv_imsic_rmw(void *arg, target_ulong reg, target_ulong *val, + target_ulong new_val, target_ulong wr_mask) +{ + RISCVIMSICState *imsic =3D arg; + uint32_t isel, priv, virt, vgein, xlen, page; + + priv =3D AIA_IREG_PRIV(reg); + virt =3D AIA_IREG_VIRT(reg); + isel =3D AIA_IREG_ISEL(reg); + vgein =3D AIA_IREG_VGEIN(reg); + xlen =3D AIA_IREG_XLEN(reg); + + if (imsic->mmode) { + if (priv =3D=3D PRV_M && !virt) { + page =3D 0; + } else { + goto err; + } + } else { + if (priv =3D=3D PRV_S) { + if (virt) { + if (vgein && vgein < imsic->num_pages) { + page =3D vgein; + } else { + goto err; + } + } else { + page =3D 0; + } + } else { + goto err; + } + } + + switch (isel) { + case ISELECT_IMSIC_EIDELIVERY: + return riscv_imsic_eidelivery_rmw(imsic, page, val, + new_val, wr_mask); + case ISELECT_IMSIC_EITHRESHOLD: + return riscv_imsic_eithreshold_rmw(imsic, page, val, + new_val, wr_mask); + case ISELECT_IMSIC_TOPEI: + return riscv_imsic_topei_rmw(imsic, page, val, new_val, wr_mask); + case ISELECT_IMSIC_EIP0 ... ISELECT_IMSIC_EIP63: + return riscv_imsic_eix_rmw(imsic, xlen, page, + isel - ISELECT_IMSIC_EIP0, + true, val, new_val, wr_mask); + case ISELECT_IMSIC_EIE0 ... ISELECT_IMSIC_EIE63: + return riscv_imsic_eix_rmw(imsic, xlen, page, + isel - ISELECT_IMSIC_EIE0, + false, val, new_val, wr_mask); + default: + break; + }; + +err: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid register priv=3D%d virt=3D%d isel=3D%d vgei= n=3D%d\n", + __func__, priv, virt, isel, vgein); + return -EINVAL; +} + +static uint64_t riscv_imsic_read(void *opaque, hwaddr addr, unsigned size) +{ + RISCVIMSICState *imsic =3D opaque; + + /* Reads must be 4 byte words */ + if ((addr & 0x3) !=3D 0) { + goto err; + } + + /* Reads cannot be out of range */ + if (addr > IMSIC_MMIO_SIZE(imsic->num_pages)) { + goto err; + } + + return 0; + +err: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid register read 0x%" HWADDR_PRIx "\n", + __func__, addr); + return 0; +} + +static void riscv_imsic_write(void *opaque, hwaddr addr, uint64_t value, + unsigned size) +{ + RISCVIMSICState *imsic =3D opaque; + uint32_t page; + + /* Writes must be 4 byte words */ + if ((addr & 0x3) !=3D 0) { + goto err; + } + + /* Writes cannot be out of range */ + if (addr > IMSIC_MMIO_SIZE(imsic->num_pages)) { + goto err; + } + + /* Writes only supported for MSI little-endian registers */ + page =3D addr >> IMSIC_MMIO_PAGE_SHIFT; + if ((addr & (IMSIC_MMIO_PAGE_SZ - 1)) =3D=3D IMSIC_MMIO_PAGE_LE) { + if (value && (value < imsic->num_irqs)) { + imsic->eistate[(page * imsic->num_irqs) + value] |=3D + IMSIC_EISTATE_PENDING; + } + } + + /* Update CPU external interrupt status */ + riscv_imsic_update(imsic, page); + + return; + +err: + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid register write 0x%" HWADDR_PRIx "\n", + __func__, addr); +} + +static const MemoryRegionOps riscv_imsic_ops =3D { + .read =3D riscv_imsic_read, + .write =3D riscv_imsic_write, + .endianness =3D DEVICE_LITTLE_ENDIAN, + .valid =3D { + .min_access_size =3D 4, + .max_access_size =3D 4 + } +}; + +static void riscv_imsic_realize(DeviceState *dev, Error **errp) +{ + RISCVIMSICState *imsic =3D RISCV_IMSIC(dev); + RISCVCPU *rcpu =3D RISCV_CPU(qemu_get_cpu(imsic->hartid)); + CPUState *cpu =3D qemu_get_cpu(imsic->hartid); + CPURISCVState *env =3D cpu ? cpu->env_ptr : NULL; + + imsic->num_eistate =3D imsic->num_pages * imsic->num_irqs; + imsic->eidelivery =3D g_new0(uint32_t, imsic->num_pages); + imsic->eithreshold =3D g_new0(uint32_t, imsic->num_pages); + imsic->eistate =3D g_new0(uint32_t, imsic->num_eistate); + + memory_region_init_io(&imsic->mmio, OBJECT(dev), &riscv_imsic_ops, + imsic, TYPE_RISCV_IMSIC, + IMSIC_MMIO_SIZE(imsic->num_pages)); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &imsic->mmio); + + /* Claim the CPU interrupt to be triggered by this IMSIC */ + if (riscv_cpu_claim_interrupts(rcpu, + (imsic->mmode) ? MIP_MEIP : MIP_SEIP) < 0) { + error_setg(errp, "%s already claimed", + (imsic->mmode) ? "MEIP" : "SEIP"); + return; + } + + /* Create output IRQ lines */ + imsic->external_irqs =3D g_malloc(sizeof(qemu_irq) * imsic->num_pages); + qdev_init_gpio_out(dev, imsic->external_irqs, imsic->num_pages); + + /* Force select AIA feature and setup CSR read-modify-write callback */ + if (env) { + riscv_set_feature(env, RISCV_FEATURE_AIA); + if (!imsic->mmode) { + riscv_cpu_set_geilen(env, imsic->num_pages - 1); + } + riscv_cpu_set_aia_ireg_rmw_fn(env, (imsic->mmode) ? PRV_M : PRV_S, + riscv_imsic_rmw, imsic); + } + + msi_nonbroken =3D true; +} + +static Property riscv_imsic_properties[] =3D { + DEFINE_PROP_BOOL("mmode", RISCVIMSICState, mmode, 0), + DEFINE_PROP_UINT32("hartid", RISCVIMSICState, hartid, 0), + DEFINE_PROP_UINT32("num-pages", RISCVIMSICState, num_pages, 0), + DEFINE_PROP_UINT32("num-irqs", RISCVIMSICState, num_irqs, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static const VMStateDescription vmstate_riscv_imsic =3D { + .name =3D "riscv_imsic", + .version_id =3D 1, + .minimum_version_id =3D 1, + .fields =3D (VMStateField[]) { + VMSTATE_VARRAY_UINT32(eidelivery, RISCVIMSICState, + num_pages, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(eithreshold, RISCVIMSICState, + num_pages, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_VARRAY_UINT32(eistate, RISCVIMSICState, + num_eistate, 0, + vmstate_info_uint32, uint32_t), + VMSTATE_END_OF_LIST() + } +}; + +static void riscv_imsic_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc =3D DEVICE_CLASS(klass); + + device_class_set_props(dc, riscv_imsic_properties); + dc->realize =3D riscv_imsic_realize; + dc->vmsd =3D &vmstate_riscv_imsic; +} + +static const TypeInfo riscv_imsic_info =3D { + .name =3D TYPE_RISCV_IMSIC, + .parent =3D TYPE_SYS_BUS_DEVICE, + .instance_size =3D sizeof(RISCVIMSICState), + .class_init =3D riscv_imsic_class_init, +}; + +static void riscv_imsic_register_types(void) +{ + type_register_static(&riscv_imsic_info); +} + +type_init(riscv_imsic_register_types) + +/* + * Create IMSIC device. + */ +DeviceState *riscv_imsic_create(hwaddr addr, uint32_t hartid, bool mmode, + uint32_t num_pages, uint32_t num_ids) +{ + DeviceState *dev =3D qdev_new(TYPE_RISCV_IMSIC); + CPUState *cpu =3D qemu_get_cpu(hartid); + uint32_t i; + + assert(!(addr & (IMSIC_MMIO_PAGE_SZ - 1))); + if (mmode) { + assert(num_pages =3D=3D 1); + } else { + assert(num_pages >=3D 1 && num_pages <=3D (IRQ_LOCAL_GUEST_MAX + 1= )); + } + assert(IMSIC_MIN_ID <=3D num_ids); + assert(num_ids <=3D IMSIC_MAX_ID); + assert((num_ids & IMSIC_MIN_ID) =3D=3D IMSIC_MIN_ID); + + qdev_prop_set_bit(dev, "mmode", mmode); + qdev_prop_set_uint32(dev, "hartid", hartid); + qdev_prop_set_uint32(dev, "num-pages", num_pages); + qdev_prop_set_uint32(dev, "num-irqs", num_ids + 1); + + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + + for (i =3D 0; i < num_pages; i++) { + if (!i) { + qdev_connect_gpio_out_named(dev, NULL, i, + qdev_get_gpio_in(DEVICE(cpu), + (mmode) ? IRQ_M_EXT : IRQ_S_EX= T)); + } else { + qdev_connect_gpio_out_named(dev, NULL, i, + qdev_get_gpio_in(DEVICE(cpu), + IRQ_LOCAL_MAX + i - 1)); + } + } + + return dev; +} diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index 528e77b4a6..ec8d4cec29 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -73,6 +73,9 @@ config RISCV_ACLINT config RISCV_APLIC bool =20 +config RISCV_IMSIC + bool + config SIFIVE_PLIC bool =20 diff --git a/hw/intc/meson.build b/hw/intc/meson.build index d953197413..81ccdb0d78 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -51,6 +51,7 @@ specific_ss.add(when: 'CONFIG_S390_FLIC_KVM', if_true: fi= les('s390_flic_kvm.c')) specific_ss.add(when: 'CONFIG_SH_INTC', if_true: files('sh_intc.c')) specific_ss.add(when: 'CONFIG_RISCV_ACLINT', if_true: files('riscv_aclint.= c')) specific_ss.add(when: 'CONFIG_RISCV_APLIC', if_true: files('riscv_aplic.c'= )) +specific_ss.add(when: 'CONFIG_RISCV_IMSIC', if_true: files('riscv_imsic.c'= )) specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c'= )) specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c', 'xive2.c')) specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XICS'], --=20 2.35.1 From nobody Tue May 14 20:20:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1646285319; x=1648877320; bh=Dudh/U3ccYgAh4noMd cDR133FxkJfDJh2p7v0sKoEhY=; b=bsQGtSKlRHaE44rJWLQaw52xuJgcuOsypE jpJo5EyeJVAG5yXAWTUtQawIKvNodYkzfwMzh0x6vARQZhe427d5Gy4wsL6xFeut KsDExL3sHAeNKhAS4k/n6JLsZ+jBYNn+ReAQayab+xBOeAVV4wQBwN1npYJeCPzh 4ra7wO5nGr59KSY/LEIs0b46SMpwr6Cak+WfwcmdC2iFaSvUnrrxo74exTa/7H0o KmV3UJG8fHnzyt5WXYjXMSkC+jpuzO0A8OPnO1uhJZNwyTc3HxFpKuc9h/u9MZzX /vwSJNr61Wn1G5PAbeAg7/YUvAnCyvfGSSAM2xgHmurFWD2lAC3w== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Anup Patel , Anup Patel , Alistair Francis Subject: [PULL 04/13] hw/riscv: virt: Add optional AIA IMSIC support to virt machine Date: Thu, 3 Mar 2022 15:27:55 +1000 Message-Id: <20220303052804.529967-5-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220303052804.529967-1-alistair.francis@opensource.wdc.com> References: <20220303052804.529967-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=05403f1d5=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1646285487030100001 Content-Type: text/plain; charset="utf-8" From: Anup Patel We extend virt machine to emulate both AIA IMSIC and AIA APLIC devices only when "aia=3Daplic-imsic" parameter is passed along with machine name in the QEMU command-line. The AIA IMSIC is only a per-HART MSI controller so we use AIA APLIC in MSI-mode to forward all wired interrupts as MSIs to the AIA IMSIC. We also provide "aia-guests=3D" parameter which can be used to specify number of VS-level AIA IMSIC Guests MMIO pages for each HART. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Acked-by: Alistair Francis Message-Id: <20220220085526.808674-4-anup@brainfault.org> Signed-off-by: Alistair Francis --- include/hw/riscv/virt.h | 17 +- hw/riscv/virt.c | 439 ++++++++++++++++++++++++++++++++-------- hw/riscv/Kconfig | 1 + 3 files changed, 373 insertions(+), 84 deletions(-) diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 47706b456d..d248d0dfa0 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -24,8 +24,10 @@ #include "hw/block/flash.h" #include "qom/object.h" =20 -#define VIRT_CPUS_MAX 32 -#define VIRT_SOCKETS_MAX 8 +#define VIRT_CPUS_MAX_BITS 3 +#define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS) +#define VIRT_SOCKETS_MAX_BITS 2 +#define VIRT_SOCKETS_MAX (1 << VIRT_SOCKETS_MAX_BITS) =20 #define TYPE_RISCV_VIRT_MACHINE MACHINE_TYPE_NAME("virt") typedef struct RISCVVirtState RISCVVirtState; @@ -35,6 +37,7 @@ DECLARE_INSTANCE_CHECKER(RISCVVirtState, RISCV_VIRT_MACHI= NE, typedef enum RISCVVirtAIAType { VIRT_AIA_TYPE_NONE =3D 0, VIRT_AIA_TYPE_APLIC, + VIRT_AIA_TYPE_APLIC_IMSIC, } RISCVVirtAIAType; =20 struct RISCVVirtState { @@ -50,6 +53,7 @@ struct RISCVVirtState { int fdt_size; bool have_aclint; RISCVVirtAIAType aia_type; + int aia_guests; }; =20 enum { @@ -65,6 +69,8 @@ enum { VIRT_UART0, VIRT_VIRTIO, VIRT_FW_CFG, + VIRT_IMSIC_M, + VIRT_IMSIC_S, VIRT_FLASH, VIRT_DRAM, VIRT_PCIE_MMIO, @@ -81,8 +87,12 @@ enum { VIRTIO_NDEV =3D 0x35 /* Arbitrary maximum number of interrupts */ }; =20 -#define VIRT_IRQCHIP_NUM_SOURCES 127 +#define VIRT_IRQCHIP_IPI_MSI 1 +#define VIRT_IRQCHIP_NUM_MSIS 255 +#define VIRT_IRQCHIP_NUM_SOURCES VIRTIO_NDEV #define VIRT_IRQCHIP_NUM_PRIO_BITS 3 +#define VIRT_IRQCHIP_MAX_GUESTS_BITS 3 +#define VIRT_IRQCHIP_MAX_GUESTS ((1U << VIRT_IRQCHIP_MAX_GUESTS_BITS) - 1U) =20 #define VIRT_PLIC_PRIORITY_BASE 0x04 #define VIRT_PLIC_PENDING_BASE 0x1000 @@ -97,6 +107,7 @@ enum { #define FDT_PCI_INT_CELLS 1 #define FDT_PLIC_INT_CELLS 1 #define FDT_APLIC_INT_CELLS 2 +#define FDT_IMSIC_INT_CELLS 0 #define FDT_MAX_INT_CELLS 2 #define FDT_MAX_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + \ 1 + FDT_MAX_INT_CELLS) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 6b06f79b46..94fbf63ec8 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -34,6 +34,7 @@ #include "hw/riscv/numa.h" #include "hw/intc/riscv_aclint.h" #include "hw/intc/riscv_aplic.h" +#include "hw/intc/riscv_imsic.h" #include "hw/intc/sifive_plic.h" #include "hw/misc/sifive_test.h" #include "chardev/char.h" @@ -44,6 +45,18 @@ #include "hw/pci-host/gpex.h" #include "hw/display/ramfb.h" =20 +#define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT) +#if VIRT_IMSIC_GROUP_MAX_SIZE < \ + IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS) +#error "Can't accomodate single IMSIC group in address space" +#endif + +#define VIRT_IMSIC_MAX_SIZE (VIRT_SOCKETS_MAX * \ + VIRT_IMSIC_GROUP_MAX_SIZE) +#if 0x4000000 < VIRT_IMSIC_MAX_SIZE +#error "Can't accomodate all IMSIC groups in address space" +#endif + static const MemMapEntry virt_memmap[] =3D { [VIRT_DEBUG] =3D { 0x0, 0x100 }, [VIRT_MROM] =3D { 0x1000, 0xf000 }, @@ -59,6 +72,8 @@ static const MemMapEntry virt_memmap[] =3D { [VIRT_VIRTIO] =3D { 0x10001000, 0x1000 }, [VIRT_FW_CFG] =3D { 0x10100000, 0x18 }, [VIRT_FLASH] =3D { 0x20000000, 0x4000000 }, + [VIRT_IMSIC_M] =3D { 0x24000000, VIRT_IMSIC_MAX_SIZE }, + [VIRT_IMSIC_S] =3D { 0x28000000, VIRT_IMSIC_MAX_SIZE }, [VIRT_PCIE_ECAM] =3D { 0x30000000, 0x10000000 }, [VIRT_PCIE_MMIO] =3D { 0x40000000, 0x40000000 }, [VIRT_DRAM] =3D { 0x80000000, 0x0 }, @@ -310,7 +325,7 @@ static void create_fdt_socket_aclint(RISCVVirtState *s, { int cpu; char *name; - unsigned long addr; + unsigned long addr, size; uint32_t aclint_cells_size; uint32_t *aclint_mswi_cells; uint32_t *aclint_sswi_cells; @@ -331,29 +346,38 @@ static void create_fdt_socket_aclint(RISCVVirtState *= s, } aclint_cells_size =3D s->soc[socket].num_harts * sizeof(uint32_t) * 2; =20 - addr =3D memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * socket); - name =3D g_strdup_printf("/soc/mswi@%lx", addr); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "riscv,aclint-msw= i"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", - 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); - qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", - aclint_mswi_cells, aclint_cells_size); - qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); - riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); - g_free(name); + if (s->aia_type !=3D VIRT_AIA_TYPE_APLIC_IMSIC) { + addr =3D memmap[VIRT_CLINT].base + (memmap[VIRT_CLINT].size * sock= et); + name =3D g_strdup_printf("/soc/mswi@%lx", addr); + qemu_fdt_add_subnode(mc->fdt, name); + qemu_fdt_setprop_string(mc->fdt, name, "compatible", + "riscv,aclint-mswi"); + qemu_fdt_setprop_cells(mc->fdt, name, "reg", + 0x0, addr, 0x0, RISCV_ACLINT_SWI_SIZE); + qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", + aclint_mswi_cells, aclint_cells_size); + qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); + riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); + g_free(name); + } =20 - addr =3D memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + - (memmap[VIRT_CLINT].size * socket); + if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC_IMSIC) { + addr =3D memmap[VIRT_CLINT].base + + (RISCV_ACLINT_DEFAULT_MTIMER_SIZE * socket); + size =3D RISCV_ACLINT_DEFAULT_MTIMER_SIZE; + } else { + addr =3D memmap[VIRT_CLINT].base + RISCV_ACLINT_SWI_SIZE + + (memmap[VIRT_CLINT].size * socket); + size =3D memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE; + } name =3D g_strdup_printf("/soc/mtimer@%lx", addr); qemu_fdt_add_subnode(mc->fdt, name); qemu_fdt_setprop_string(mc->fdt, name, "compatible", "riscv,aclint-mtimer"); qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0x0, addr + RISCV_ACLINT_DEFAULT_MTIME, - 0x0, memmap[VIRT_CLINT].size - RISCV_ACLINT_SWI_SIZE - - RISCV_ACLINT_DEFAULT_MTIME, + 0x0, size - RISCV_ACLINT_DEFAULT_MTIME, 0x0, addr + RISCV_ACLINT_DEFAULT_MTIMECMP, 0x0, RISCV_ACLINT_DEFAULT_MTIME); qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", @@ -361,19 +385,22 @@ static void create_fdt_socket_aclint(RISCVVirtState *= s, riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); g_free(name); =20 - addr =3D memmap[VIRT_ACLINT_SSWI].base + - (memmap[VIRT_ACLINT_SSWI].size * socket); - name =3D g_strdup_printf("/soc/sswi@%lx", addr); - qemu_fdt_add_subnode(mc->fdt, name); - qemu_fdt_setprop_string(mc->fdt, name, "compatible", "riscv,aclint-ssw= i"); - qemu_fdt_setprop_cells(mc->fdt, name, "reg", - 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); - qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", - aclint_sswi_cells, aclint_cells_size); - qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); - riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); - g_free(name); + if (s->aia_type !=3D VIRT_AIA_TYPE_APLIC_IMSIC) { + addr =3D memmap[VIRT_ACLINT_SSWI].base + + (memmap[VIRT_ACLINT_SSWI].size * socket); + name =3D g_strdup_printf("/soc/sswi@%lx", addr); + qemu_fdt_add_subnode(mc->fdt, name); + qemu_fdt_setprop_string(mc->fdt, name, "compatible", + "riscv,aclint-sswi"); + qemu_fdt_setprop_cells(mc->fdt, name, "reg", + 0x0, addr, 0x0, memmap[VIRT_ACLINT_SSWI].size); + qemu_fdt_setprop(mc->fdt, name, "interrupts-extended", + aclint_sswi_cells, aclint_cells_size); + qemu_fdt_setprop(mc->fdt, name, "interrupt-controller", NULL, 0); + qemu_fdt_setprop_cell(mc->fdt, name, "#interrupt-cells", 0); + riscv_socket_fdt_write_id(mc, mc->fdt, name, socket); + g_free(name); + } =20 g_free(aclint_mswi_cells); g_free(aclint_mtimer_cells); @@ -435,10 +462,145 @@ static void create_fdt_socket_plic(RISCVVirtState *s, g_free(plic_cells); } =20 -static void create_fdt_socket_aia(RISCVVirtState *s, - const MemMapEntry *memmap, int socket, - uint32_t *phandle, uint32_t *intc_phandl= es, - uint32_t *aplic_phandles) +static uint32_t imsic_num_bits(uint32_t count) +{ + uint32_t ret =3D 0; + + while (BIT(ret) < count) { + ret++; + } + + return ret; +} + +static void create_fdt_imsic(RISCVVirtState *s, const MemMapEntry *memmap, + uint32_t *phandle, uint32_t *intc_phandles, + uint32_t *msi_m_phandle, uint32_t *msi_s_phan= dle) +{ + int cpu, socket; + char *imsic_name; + MachineState *mc =3D MACHINE(s); + uint32_t imsic_max_hart_per_socket, imsic_guest_bits; + uint32_t *imsic_cells, *imsic_regs, imsic_addr, imsic_size; + + *msi_m_phandle =3D (*phandle)++; + *msi_s_phandle =3D (*phandle)++; + imsic_cells =3D g_new0(uint32_t, mc->smp.cpus * 2); + imsic_regs =3D g_new0(uint32_t, riscv_socket_count(mc) * 4); + + /* M-level IMSIC node */ + for (cpu =3D 0; cpu < mc->smp.cpus; cpu++) { + imsic_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); + imsic_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_M_EXT); + } + imsic_max_hart_per_socket =3D 0; + for (socket =3D 0; socket < riscv_socket_count(mc); socket++) { + imsic_addr =3D memmap[VIRT_IMSIC_M].base + + socket * VIRT_IMSIC_GROUP_MAX_SIZE; + imsic_size =3D IMSIC_HART_SIZE(0) * s->soc[socket].num_harts; + imsic_regs[socket * 4 + 0] =3D 0; + imsic_regs[socket * 4 + 1] =3D cpu_to_be32(imsic_addr); + imsic_regs[socket * 4 + 2] =3D 0; + imsic_regs[socket * 4 + 3] =3D cpu_to_be32(imsic_size); + if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { + imsic_max_hart_per_socket =3D s->soc[socket].num_harts; + } + } + imsic_name =3D g_strdup_printf("/soc/imsics@%lx", + (unsigned long)memmap[VIRT_IMSIC_M].base); + qemu_fdt_add_subnode(mc->fdt, imsic_name); + qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", + "riscv,imsics"); + qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", + FDT_IMSIC_INT_CELLS); + qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", + NULL, 0); + qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", + NULL, 0); + qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", + imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); + qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, + riscv_socket_count(mc) * sizeof(uint32_t) * 4); + qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", + VIRT_IRQCHIP_NUM_MSIS); + qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id", + VIRT_IRQCHIP_IPI_MSI); + if (riscv_socket_count(mc) > 1) { + qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", + imsic_num_bits(imsic_max_hart_per_socket)); + qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits= ", + imsic_num_bits(riscv_socket_count(mc))); + qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shif= t", + IMSIC_MMIO_GROUP_MIN_SHIFT); + } + qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_m_phandle); + g_free(imsic_name); + + /* S-level IMSIC node */ + for (cpu =3D 0; cpu < mc->smp.cpus; cpu++) { + imsic_cells[cpu * 2 + 0] =3D cpu_to_be32(intc_phandles[cpu]); + imsic_cells[cpu * 2 + 1] =3D cpu_to_be32(IRQ_S_EXT); + } + imsic_guest_bits =3D imsic_num_bits(s->aia_guests + 1); + imsic_max_hart_per_socket =3D 0; + for (socket =3D 0; socket < riscv_socket_count(mc); socket++) { + imsic_addr =3D memmap[VIRT_IMSIC_S].base + + socket * VIRT_IMSIC_GROUP_MAX_SIZE; + imsic_size =3D IMSIC_HART_SIZE(imsic_guest_bits) * + s->soc[socket].num_harts; + imsic_regs[socket * 4 + 0] =3D 0; + imsic_regs[socket * 4 + 1] =3D cpu_to_be32(imsic_addr); + imsic_regs[socket * 4 + 2] =3D 0; + imsic_regs[socket * 4 + 3] =3D cpu_to_be32(imsic_size); + if (imsic_max_hart_per_socket < s->soc[socket].num_harts) { + imsic_max_hart_per_socket =3D s->soc[socket].num_harts; + } + } + imsic_name =3D g_strdup_printf("/soc/imsics@%lx", + (unsigned long)memmap[VIRT_IMSIC_S].base); + qemu_fdt_add_subnode(mc->fdt, imsic_name); + qemu_fdt_setprop_string(mc->fdt, imsic_name, "compatible", + "riscv,imsics"); + qemu_fdt_setprop_cell(mc->fdt, imsic_name, "#interrupt-cells", + FDT_IMSIC_INT_CELLS); + qemu_fdt_setprop(mc->fdt, imsic_name, "interrupt-controller", + NULL, 0); + qemu_fdt_setprop(mc->fdt, imsic_name, "msi-controller", + NULL, 0); + qemu_fdt_setprop(mc->fdt, imsic_name, "interrupts-extended", + imsic_cells, mc->smp.cpus * sizeof(uint32_t) * 2); + qemu_fdt_setprop(mc->fdt, imsic_name, "reg", imsic_regs, + riscv_socket_count(mc) * sizeof(uint32_t) * 4); + qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,num-ids", + VIRT_IRQCHIP_NUM_MSIS); + qemu_fdt_setprop_cells(mc->fdt, imsic_name, "riscv,ipi-id", + VIRT_IRQCHIP_IPI_MSI); + if (imsic_guest_bits) { + qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,guest-index-bits= ", + imsic_guest_bits); + } + if (riscv_socket_count(mc) > 1) { + qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,hart-index-bits", + imsic_num_bits(imsic_max_hart_per_socket)); + qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-bits= ", + imsic_num_bits(riscv_socket_count(mc))); + qemu_fdt_setprop_cell(mc->fdt, imsic_name, "riscv,group-index-shif= t", + IMSIC_MMIO_GROUP_MIN_SHIFT); + } + qemu_fdt_setprop_cell(mc->fdt, imsic_name, "phandle", *msi_s_phandle); + g_free(imsic_name); + + g_free(imsic_regs); + g_free(imsic_cells); +} + +static void create_fdt_socket_aplic(RISCVVirtState *s, + const MemMapEntry *memmap, int socket, + uint32_t msi_m_phandle, + uint32_t msi_s_phandle, + uint32_t *phandle, + uint32_t *intc_phandles, + uint32_t *aplic_phandles) { int cpu; char *aplic_name; @@ -464,8 +626,13 @@ static void create_fdt_socket_aia(RISCVVirtState *s, qemu_fdt_setprop_cell(mc->fdt, aplic_name, "#interrupt-cells", FDT_APLIC_INT_CELLS); qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", - aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); + if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC) { + qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", + aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); + } else { + qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", + msi_m_phandle); + } qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_M].size); qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", @@ -491,8 +658,13 @@ static void create_fdt_socket_aia(RISCVVirtState *s, qemu_fdt_setprop_cell(mc->fdt, aplic_name, "#interrupt-cells", FDT_APLIC_INT_CELLS); qemu_fdt_setprop(mc->fdt, aplic_name, "interrupt-controller", NULL, 0); - qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", - aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); + if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC) { + qemu_fdt_setprop(mc->fdt, aplic_name, "interrupts-extended", + aplic_cells, s->soc[socket].num_harts * sizeof(uint32_t) * 2); + } else { + qemu_fdt_setprop_cell(mc->fdt, aplic_name, "msi-parent", + msi_s_phandle); + } qemu_fdt_setprop_cells(mc->fdt, aplic_name, "reg", 0x0, aplic_addr, 0x0, memmap[VIRT_APLIC_S].size); qemu_fdt_setprop_cell(mc->fdt, aplic_name, "riscv,num-sources", @@ -509,13 +681,14 @@ static void create_fdt_sockets(RISCVVirtState *s, con= st MemMapEntry *memmap, bool is_32_bit, uint32_t *phandle, uint32_t *irq_mmio_phandle, uint32_t *irq_pcie_phandle, - uint32_t *irq_virtio_phandle) + uint32_t *irq_virtio_phandle, + uint32_t *msi_pcie_phandle) { - int socket; char *clust_name; - uint32_t *intc_phandles; + int socket, phandle_pos; MachineState *mc =3D MACHINE(s); - uint32_t xplic_phandles[MAX_NODES]; + uint32_t msi_m_phandle =3D 0, msi_s_phandle =3D 0; + uint32_t *intc_phandles, xplic_phandles[MAX_NODES]; =20 qemu_fdt_add_subnode(mc->fdt, "/cpus"); qemu_fdt_setprop_cell(mc->fdt, "/cpus", "timebase-frequency", @@ -524,37 +697,55 @@ static void create_fdt_sockets(RISCVVirtState *s, con= st MemMapEntry *memmap, qemu_fdt_setprop_cell(mc->fdt, "/cpus", "#address-cells", 0x1); qemu_fdt_add_subnode(mc->fdt, "/cpus/cpu-map"); =20 + intc_phandles =3D g_new0(uint32_t, mc->smp.cpus); + + phandle_pos =3D mc->smp.cpus; for (socket =3D (riscv_socket_count(mc) - 1); socket >=3D 0; socket--)= { + phandle_pos -=3D s->soc[socket].num_harts; + clust_name =3D g_strdup_printf("/cpus/cpu-map/cluster%d", socket); qemu_fdt_add_subnode(mc->fdt, clust_name); =20 - intc_phandles =3D g_new0(uint32_t, s->soc[socket].num_harts); - create_fdt_socket_cpus(s, socket, clust_name, phandle, - is_32_bit, intc_phandles); + is_32_bit, &intc_phandles[phandle_pos]); =20 create_fdt_socket_memory(s, memmap, socket); =20 + g_free(clust_name); + if (!kvm_enabled()) { if (s->have_aclint) { - create_fdt_socket_aclint(s, memmap, socket, intc_phandles); + create_fdt_socket_aclint(s, memmap, socket, + &intc_phandles[phandle_pos]); } else { - create_fdt_socket_clint(s, memmap, socket, intc_phandles); + create_fdt_socket_clint(s, memmap, socket, + &intc_phandles[phandle_pos]); } } + } + + if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC_IMSIC) { + create_fdt_imsic(s, memmap, phandle, intc_phandles, + &msi_m_phandle, &msi_s_phandle); + *msi_pcie_phandle =3D msi_s_phandle; + } + + phandle_pos =3D mc->smp.cpus; + for (socket =3D (riscv_socket_count(mc) - 1); socket >=3D 0; socket--)= { + phandle_pos -=3D s->soc[socket].num_harts; =20 if (s->aia_type =3D=3D VIRT_AIA_TYPE_NONE) { create_fdt_socket_plic(s, memmap, socket, phandle, - intc_phandles, xplic_phandles); + &intc_phandles[phandle_pos], xplic_phandles); } else { - create_fdt_socket_aia(s, memmap, socket, phandle, - intc_phandles, xplic_phandles); + create_fdt_socket_aplic(s, memmap, socket, + msi_m_phandle, msi_s_phandle, phandle, + &intc_phandles[phandle_pos], xplic_phandles); } - - g_free(intc_phandles); - g_free(clust_name); } =20 + g_free(intc_phandles); + for (socket =3D 0; socket < riscv_socket_count(mc); socket++) { if (socket =3D=3D 0) { *irq_mmio_phandle =3D xplic_phandles[socket]; @@ -602,7 +793,8 @@ static void create_fdt_virtio(RISCVVirtState *s, const = MemMapEntry *memmap, } =20 static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, - uint32_t irq_pcie_phandle) + uint32_t irq_pcie_phandle, + uint32_t msi_pcie_phandle) { char *name; MachineState *mc =3D MACHINE(s); @@ -622,6 +814,9 @@ static void create_fdt_pcie(RISCVVirtState *s, const Me= mMapEntry *memmap, qemu_fdt_setprop_cells(mc->fdt, name, "bus-range", 0, memmap[VIRT_PCIE_ECAM].size / PCIE_MMCFG_SIZE_MIN - 1); qemu_fdt_setprop(mc->fdt, name, "dma-coherent", NULL, 0); + if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC_IMSIC) { + qemu_fdt_setprop_cell(mc->fdt, name, "msi-parent", msi_pcie_phandl= e); + } qemu_fdt_setprop_cells(mc->fdt, name, "reg", 0, memmap[VIRT_PCIE_ECAM].base, 0, memmap[VIRT_PCIE_ECAM].size); qemu_fdt_setprop_sized_cells(mc->fdt, name, "ranges", @@ -747,7 +942,7 @@ static void create_fdt(RISCVVirtState *s, const MemMapE= ntry *memmap, uint64_t mem_size, const char *cmdline, bool is_32_= bit) { MachineState *mc =3D MACHINE(s); - uint32_t phandle =3D 1, irq_mmio_phandle =3D 1; + uint32_t phandle =3D 1, irq_mmio_phandle =3D 1, msi_pcie_phandle =3D 1; uint32_t irq_pcie_phandle =3D 1, irq_virtio_phandle =3D 1; =20 if (mc->dtb) { @@ -777,11 +972,12 @@ static void create_fdt(RISCVVirtState *s, const MemMa= pEntry *memmap, qemu_fdt_setprop_cell(mc->fdt, "/soc", "#address-cells", 0x2); =20 create_fdt_sockets(s, memmap, is_32_bit, &phandle, - &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle); + &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle, + &msi_pcie_phandle); =20 create_fdt_virtio(s, memmap, irq_virtio_phandle); =20 - create_fdt_pcie(s, memmap, irq_pcie_phandle); + create_fdt_pcie(s, memmap, irq_pcie_phandle, msi_pcie_phandle); =20 create_fdt_reset(s, memmap, &phandle); =20 @@ -896,30 +1092,55 @@ static DeviceState *virt_create_plic(const MemMapEnt= ry *memmap, int socket, return ret; } =20 -static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, +static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_gue= sts, const MemMapEntry *memmap, int socket, int base_hartid, int hart_count) { + int i; + hwaddr addr; + uint32_t guest_bits; DeviceState *aplic_m; + bool msimode =3D (aia_type =3D=3D VIRT_AIA_TYPE_APLIC_IMSIC) ? true : = false; + + if (msimode) { + /* Per-socket M-level IMSICs */ + addr =3D memmap[VIRT_IMSIC_M].base + socket * VIRT_IMSIC_GROUP_MAX= _SIZE; + for (i =3D 0; i < hart_count; i++) { + riscv_imsic_create(addr + i * IMSIC_HART_SIZE(0), + base_hartid + i, true, 1, + VIRT_IRQCHIP_NUM_MSIS); + } + + /* Per-socket S-level IMSICs */ + guest_bits =3D imsic_num_bits(aia_guests + 1); + addr =3D memmap[VIRT_IMSIC_S].base + socket * VIRT_IMSIC_GROUP_MAX= _SIZE; + for (i =3D 0; i < hart_count; i++) { + riscv_imsic_create(addr + i * IMSIC_HART_SIZE(guest_bits), + base_hartid + i, false, 1 + aia_guests, + VIRT_IRQCHIP_NUM_MSIS); + } + } =20 /* Per-socket M-level APLIC */ aplic_m =3D riscv_aplic_create( memmap[VIRT_APLIC_M].base + socket * memmap[VIRT_APLIC_M].size, memmap[VIRT_APLIC_M].size, - base_hartid, hart_count, + (msimode) ? 0 : base_hartid, + (msimode) ? 0 : hart_count, VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_PRIO_BITS, - false, true, NULL); + msimode, true, NULL); =20 if (aplic_m) { /* Per-socket S-level APLIC */ riscv_aplic_create( memmap[VIRT_APLIC_S].base + socket * memmap[VIRT_APLIC_S].size, memmap[VIRT_APLIC_S].size, - base_hartid, hart_count, + (msimode) ? 0 : base_hartid, + (msimode) ? 0 : hart_count, VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_PRIO_BITS, - false, false, aplic_m); + msimode, false, aplic_m); } =20 return aplic_m; @@ -979,23 +1200,43 @@ static void virt_machine_init(MachineState *machine) sysbus_realize(SYS_BUS_DEVICE(&s->soc[i]), &error_abort); =20 if (!kvm_enabled()) { - /* Per-socket CLINT */ - riscv_aclint_swi_create( - memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, - base_hartid, hart_count, false); - riscv_aclint_mtimer_create( - memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size + - RISCV_ACLINT_SWI_SIZE, - RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_count, - RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MTIME, - RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); - - /* Per-socket ACLINT SSWI */ if (s->have_aclint) { + if (s->aia_type =3D=3D VIRT_AIA_TYPE_APLIC_IMSIC) { + /* Per-socket ACLINT MTIMER */ + riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + + i * RISCV_ACLINT_DEFAULT_MTIMER_SIZE, + RISCV_ACLINT_DEFAULT_MTIMER_SIZE, + base_hartid, hart_count, + RISCV_ACLINT_DEFAULT_MTIMECMP, + RISCV_ACLINT_DEFAULT_MTIME, + RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); + } else { + /* Per-socket ACLINT MSWI, MTIMER, and SSWI */ + riscv_aclint_swi_create(memmap[VIRT_CLINT].base + + i * memmap[VIRT_CLINT].size, + base_hartid, hart_count, false); + riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + + i * memmap[VIRT_CLINT].size + + RISCV_ACLINT_SWI_SIZE, + RISCV_ACLINT_DEFAULT_MTIMER_SIZE, + base_hartid, hart_count, + RISCV_ACLINT_DEFAULT_MTIMECMP, + RISCV_ACLINT_DEFAULT_MTIME, + RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); + riscv_aclint_swi_create(memmap[VIRT_ACLINT_SSWI].base + + i * memmap[VIRT_ACLINT_SSWI].size, + base_hartid, hart_count, true); + } + } else { + /* Per-socket SiFive CLINT */ riscv_aclint_swi_create( - memmap[VIRT_ACLINT_SSWI].base + - i * memmap[VIRT_ACLINT_SSWI].size, - base_hartid, hart_count, true); + memmap[VIRT_CLINT].base + i * memmap[VIRT_CLINT].size, + base_hartid, hart_count, false); + riscv_aclint_mtimer_create(memmap[VIRT_CLINT].base + + i * memmap[VIRT_CLINT].size + RISCV_ACLINT_SWI_SIZ= E, + RISCV_ACLINT_DEFAULT_MTIMER_SIZE, base_hartid, hart_co= unt, + RISCV_ACLINT_DEFAULT_MTIMECMP, RISCV_ACLINT_DEFAULT_MT= IME, + RISCV_ACLINT_DEFAULT_TIMEBASE_FREQ, true); } } =20 @@ -1004,8 +1245,9 @@ static void virt_machine_init(MachineState *machine) s->irqchip[i] =3D virt_create_plic(memmap, i, base_hartid, hart_count); } else { - s->irqchip[i] =3D virt_create_aia(s->aia_type, memmap, i, - base_hartid, hart_count); + s->irqchip[i] =3D virt_create_aia(s->aia_type, s->aia_guests, + memmap, i, base_hartid, + hart_count); } =20 /* Try to use different IRQCHIP instance based device type */ @@ -1171,6 +1413,27 @@ static void virt_machine_instance_init(Object *obj) { } =20 +static char *virt_get_aia_guests(Object *obj, Error **errp) +{ + RISCVVirtState *s =3D RISCV_VIRT_MACHINE(obj); + char val[32]; + + sprintf(val, "%d", s->aia_guests); + return g_strdup(val); +} + +static void virt_set_aia_guests(Object *obj, const char *val, Error **errp) +{ + RISCVVirtState *s =3D RISCV_VIRT_MACHINE(obj); + + s->aia_guests =3D atoi(val); + if (s->aia_guests < 0 || s->aia_guests > VIRT_IRQCHIP_MAX_GUESTS) { + error_setg(errp, "Invalid number of AIA IMSIC guests"); + error_append_hint(errp, "Valid values be between 0 and %d.\n", + VIRT_IRQCHIP_MAX_GUESTS); + } +} + static char *virt_get_aia(Object *obj, Error **errp) { RISCVVirtState *s =3D RISCV_VIRT_MACHINE(obj); @@ -1180,6 +1443,9 @@ static char *virt_get_aia(Object *obj, Error **errp) case VIRT_AIA_TYPE_APLIC: val =3D "aplic"; break; + case VIRT_AIA_TYPE_APLIC_IMSIC: + val =3D "aplic-imsic"; + break; default: val =3D "none"; break; @@ -1196,9 +1462,12 @@ static void virt_set_aia(Object *obj, const char *va= l, Error **errp) s->aia_type =3D VIRT_AIA_TYPE_NONE; } else if (!strcmp(val, "aplic")) { s->aia_type =3D VIRT_AIA_TYPE_APLIC; + } else if (!strcmp(val, "aplic-imsic")) { + s->aia_type =3D VIRT_AIA_TYPE_APLIC_IMSIC; } else { error_setg(errp, "Invalid AIA interrupt controller type"); - error_append_hint(errp, "Valid values are none, and aplic.\n"); + error_append_hint(errp, "Valid values are none, aplic, and " + "aplic-imsic.\n"); } } =20 @@ -1220,6 +1489,7 @@ static void virt_set_aclint(Object *obj, bool value, = Error **errp) =20 static void virt_machine_class_init(ObjectClass *oc, void *data) { + char str[128]; MachineClass *mc =3D MACHINE_CLASS(oc); =20 mc->desc =3D "RISC-V VirtIO board"; @@ -1246,7 +1516,14 @@ static void virt_machine_class_init(ObjectClass *oc,= void *data) object_class_property_set_description(oc, "aia", "Set type of AIA interrupt " "conttoller. Valid values are " - "none, and aplic."); + "none, aplic, and aplic-imsic."); + + object_class_property_add_str(oc, "aia-guests", + virt_get_aia_guests, + virt_set_aia_guests); + sprintf(str, "Set number of guest MMIO pages for AIA IMSIC. Valid valu= e " + "should be between 0 and %d.", VIRT_IRQCHIP_MAX_GUESTS); + object_class_property_set_description(oc, "aia-guests", str); } =20 static const TypeInfo virt_machine_typeinfo =3D { diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index c30bb7cb6c..91bb9d21c4 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -43,6 +43,7 @@ config RISCV_VIRT select SERIAL select RISCV_ACLINT select RISCV_APLIC + select RISCV_IMSIC select SIFIVE_PLIC select SIFIVE_TEST select VIRTIO_MMIO --=20 2.35.1 From nobody Tue May 14 20:20:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646285645689631.6674507419629; Wed, 2 Mar 2022 21:34:05 -0800 (PST) Received: from localhost ([::1]:52018 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nPe6G-0001wh-KA for importer@patchew.org; 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s=dkim; t=1646285323; x=1648877324; bh=t1GoyBNEEoH1/4EjkN 226ZZt19ZRWA/EXrkabE2mpbo=; b=pR2h4qk/JZwzB+21hNiKkgsVc1sfg08Zn9 L/wVclOkjE3VwIqLsU0IN4veaU4d0RyX8QdO09U/rQSTyqlKQcnpeH4m/MlZdVyp 8OzWOhZAFED/gjOy/tdDvks/K/pRHWDaV6COiMTM9khpaLHkPXB25RosCrmBJabd 2ySbLn5fwU76ZYkUPXv7aFYtsgvs4zpj4+uVMQhFoFl6p91Kpk9LpCVI0rl+umXe GcSsqVuezc1HDKoVtTAvG97c5103Lk4VcM4gl8B3plwlxrT4cqLM7GcfWW5deGoF 21/IGNIVFDCjw7B/yBJ7lXgphOtLYdxjRHy7NTn2q0BWat7w4/9g== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Anup Patel , Anup Patel , Alistair Francis , Frank Chang Subject: [PULL 05/13] docs/system: riscv: Document AIA options for virt machine Date: Thu, 3 Mar 2022 15:27:56 +1000 Message-Id: <20220303052804.529967-6-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220303052804.529967-1-alistair.francis@opensource.wdc.com> References: <20220303052804.529967-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=05403f1d5=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1646285646226100001 Content-Type: text/plain; charset="utf-8" From: Anup Patel We have two new machine options "aia" and "aia-guests" available for the RISC-V virt machine so let's document these options. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Message-Id: <20220220085526.808674-5-anup@brainfault.org> Signed-off-by: Alistair Francis --- docs/system/riscv/virt.rst | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst index 08ce3c4177..1272b6659e 100644 --- a/docs/system/riscv/virt.rst +++ b/docs/system/riscv/virt.rst @@ -63,6 +63,22 @@ The following machine-specific options are supported: When this option is "on", ACLINT devices will be emulated instead of SiFive CLINT. When not specified, this option is assumed to be "off". =20 +- aia=3D[none|aplic|aplic-imsic] + + This option allows selecting interrupt controller defined by the AIA + (advanced interrupt architecture) specification. The "aia=3Daplic" selec= ts + APLIC (advanced platform level interrupt controller) to handle wired + interrupts whereas the "aia=3Daplic-imsic" selects APLIC and IMSIC (inco= ming + message signaled interrupt controller) to handle both wired interrupts a= nd + MSIs. When not specified, this option is assumed to be "none" which sele= cts + SiFive PLIC to handle wired interrupts. + +- aia-guests=3Dnnn + + The number of per-HART VS-level AIA IMSIC pages to be emulated for a gue= st + having AIA IMSIC (i.e. "aia=3Daplic-imsic" selected). When not specified, + the default number of per-HART VS-level AIA IMSIC pages is 0. + Running Linux kernel -------------------- =20 --=20 2.35.1 From nobody Tue May 14 20:20:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646285860802938.4131722797605; Wed, 2 Mar 2022 21:37:40 -0800 (PST) Received: from localhost ([::1]:60812 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nPe9j-0007zN-F2 for importer@patchew.org; Thu, 03 Mar 2022 00:37:39 -0500 Received: from eggs.gnu.org ([209.51.188.92]:39808) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nPe1E-0001m8-JM for qemu-devel@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1646285328; x=1648877329; bh=lhTxYmg91JpfH29IdC PqqOgWEV/DYvR1IbtewiR2zo0=; b=potzfNse3gcPliWYQVSg3tXr3vNY9+qsJs 5fm35zTdD3n4svNANVOndYPj3B/t5wHyAd8nZpc6GjH12qKOsY3rMMb3210h8fqE QIpgIewEZMuqj8STx+O2iqy2B8p2/geoHbjmPZ59biGXQwiOKLz6BpMqIfRJT5DT yr6Mmc7OHhut9mchp+aPk2AUaP54JV8SnquHq+orbcXx4LAKZjzSQS2+EgLOaMdh HdS6CUXmsB+VEoM+pJuJcvSNuLf7TU9y09vwIsqiN/HrZ30k1q1ETbXEtNJNv4/G uOExbqtmxLoAIkecnGB5X/bnEcM9gj+PV7DLmtq7y5QoI6ugajhA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Anup Patel , Anup Patel , Alistair Francis , Frank Chang Subject: [PULL 06/13] hw/riscv: virt: Increase maximum number of allowed CPUs Date: Thu, 3 Mar 2022 15:27:57 +1000 Message-Id: <20220303052804.529967-7-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220303052804.529967-1-alistair.francis@opensource.wdc.com> References: <20220303052804.529967-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=05403f1d5=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1646285861980100001 Content-Type: text/plain; charset="utf-8" From: Anup Patel To facilitate software development of RISC-V systems with large number of HARTs, we increase the maximum number of allowed CPUs to 512 (2^9). We also add a detailed source level comments about limit defines which impact the physical address space utilization. Signed-off-by: Anup Patel Signed-off-by: Anup Patel Reviewed-by: Alistair Francis Reviewed-by: Frank Chang Message-Id: <20220220085526.808674-6-anup@brainfault.org> Signed-off-by: Alistair Francis --- include/hw/riscv/virt.h | 2 +- hw/riscv/virt.c | 10 ++++++++++ 2 files changed, 11 insertions(+), 1 deletion(-) diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index d248d0dfa0..78b058ec86 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -24,7 +24,7 @@ #include "hw/block/flash.h" #include "qom/object.h" =20 -#define VIRT_CPUS_MAX_BITS 3 +#define VIRT_CPUS_MAX_BITS 9 #define VIRT_CPUS_MAX (1 << VIRT_CPUS_MAX_BITS) #define VIRT_SOCKETS_MAX_BITS 2 #define VIRT_SOCKETS_MAX (1 << VIRT_SOCKETS_MAX_BITS) diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 94fbf63ec8..da50cbed43 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -45,6 +45,16 @@ #include "hw/pci-host/gpex.h" #include "hw/display/ramfb.h" =20 +/* + * The virt machine physical address space used by some of the devices + * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets, + * number of CPUs, and number of IMSIC guest files. + * + * Various limits defined by VIRT_SOCKETS_MAX_BITS, VIRT_CPUS_MAX_BITS, + * and VIRT_IRQCHIP_MAX_GUESTS_BITS are tuned for maximum utilization + * of virt machine physical address space. + */ + #define VIRT_IMSIC_GROUP_MAX_SIZE (1U << IMSIC_MMIO_GROUP_MIN_SHIFT) #if VIRT_IMSIC_GROUP_MAX_SIZE < \ IMSIC_GROUP_SIZE(VIRT_CPUS_MAX_BITS, VIRT_IRQCHIP_MAX_GUESTS_BITS) --=20 2.35.1 From nobody Tue May 14 20:20:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1646285332; x=1648877333; bh=1zBpqLWvYbZXszGRoR QcV0k4yc8Y5i/zbSdC126j/28=; b=pWgZXuh6ECTzvWS21u2FlIaTuBE2pmH2/g 1PrzlVP6aWHnsbiDgbRCJ8rr90zaysE6LtBnDIRJ9IN9qtbzmisHZv2Snbs/oiPt tPwIhprvWDn/xUHu/VSTgYlRcJhcYs+QH3BGdqIoUj++dsmX1Wem9rNzGRcuaynP qwt/0U00rqZlFuhB5xrW8gX1MhE4OFXiK6khVuCgDTcca6JsWv5DEf37/HNjnScM 2zWM3OVQd0wGgwqOU9yhM7Sf6aYAdQmuV5j5IlOzYKkITD7Qc3tclp14zAPdOdkH E2b3Bz6KFnuq9QFuHBsTYWhyNUw4tPit3k0ZPk2ZuFpnccbKIh5w== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Wilfred Mallawa , Alistair Francis , Bin Meng Subject: [PULL 07/13] hw: riscv: opentitan: fixup SPI addresses Date: Thu, 3 Mar 2022 15:27:58 +1000 Message-Id: <20220303052804.529967-8-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220303052804.529967-1-alistair.francis@opensource.wdc.com> References: <20220303052804.529967-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=05403f1d5=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1646285652199100001 Content-Type: text/plain; charset="utf-8" From: Wilfred Mallawa This patch updates the SPI_DEVICE, SPI_HOST0, SPI_HOST1 base addresses. Also adds these as unimplemented devices. The address references can be found [1]. [1] https://github.com/lowRISC/opentitan/blob/6c317992fbd646818b34f2a2dbf44= bc850e461e4/hw/top_earlgrey/sw/autogen/top_earlgrey_memory.h#L107 Signed-off-by: Wilfred Mallawa Reviewed-by: Alistair Francis Reviewed-by: Bin Meng Message-Id: <20220218063839.405082-1-alistair.francis@opensource.wdc.com> Signed-off-by: Alistair Francis --- include/hw/riscv/opentitan.h | 4 +++- hw/riscv/opentitan.c | 12 +++++++++--- 2 files changed, 12 insertions(+), 4 deletions(-) diff --git a/include/hw/riscv/opentitan.h b/include/hw/riscv/opentitan.h index eac35ef590..00da9ded43 100644 --- a/include/hw/riscv/opentitan.h +++ b/include/hw/riscv/opentitan.h @@ -57,8 +57,10 @@ enum { IBEX_DEV_FLASH, IBEX_DEV_FLASH_VIRTUAL, IBEX_DEV_UART, + IBEX_DEV_SPI_DEVICE, + IBEX_DEV_SPI_HOST0, + IBEX_DEV_SPI_HOST1, IBEX_DEV_GPIO, - IBEX_DEV_SPI, IBEX_DEV_I2C, IBEX_DEV_PATTGEN, IBEX_DEV_TIMER, diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index aec7cfa33f..833624d66c 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -34,13 +34,15 @@ static const MemMapEntry ibex_memmap[] =3D { [IBEX_DEV_FLASH] =3D { 0x20000000, 0x80000 }, [IBEX_DEV_UART] =3D { 0x40000000, 0x1000 }, [IBEX_DEV_GPIO] =3D { 0x40040000, 0x1000 }, - [IBEX_DEV_SPI] =3D { 0x40050000, 0x1000 }, + [IBEX_DEV_SPI_DEVICE] =3D { 0x40050000, 0x1000 }, [IBEX_DEV_I2C] =3D { 0x40080000, 0x1000 }, [IBEX_DEV_PATTGEN] =3D { 0x400e0000, 0x1000 }, [IBEX_DEV_TIMER] =3D { 0x40100000, 0x1000 }, [IBEX_DEV_SENSOR_CTRL] =3D { 0x40110000, 0x1000 }, [IBEX_DEV_OTP_CTRL] =3D { 0x40130000, 0x4000 }, [IBEX_DEV_USBDEV] =3D { 0x40150000, 0x1000 }, + [IBEX_DEV_SPI_HOST0] =3D { 0x40300000, 0x1000 }, + [IBEX_DEV_SPI_HOST1] =3D { 0x40310000, 0x1000 }, [IBEX_DEV_PWRMGR] =3D { 0x40400000, 0x1000 }, [IBEX_DEV_RSTMGR] =3D { 0x40410000, 0x1000 }, [IBEX_DEV_CLKMGR] =3D { 0x40420000, 0x1000 }, @@ -209,8 +211,12 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_= soc, Error **errp) =20 create_unimplemented_device("riscv.lowrisc.ibex.gpio", memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size); - create_unimplemented_device("riscv.lowrisc.ibex.spi", - memmap[IBEX_DEV_SPI].base, memmap[IBEX_DEV_SPI].size); + create_unimplemented_device("riscv.lowrisc.ibex.spi_device", + memmap[IBEX_DEV_SPI_DEVICE].base, memmap[IBEX_DEV_SPI_DEVICE].size= ); + create_unimplemented_device("riscv.lowrisc.ibex.spi_host0", + memmap[IBEX_DEV_SPI_HOST0].base, memmap[IBEX_DEV_SPI_HOST0].size); + create_unimplemented_device("riscv.lowrisc.ibex.spi_host1", + memmap[IBEX_DEV_SPI_HOST1].base, memmap[IBEX_DEV_SPI_HOST1].size); create_unimplemented_device("riscv.lowrisc.ibex.i2c", memmap[IBEX_DEV_I2C].base, memmap[IBEX_DEV_I2C].size); create_unimplemented_device("riscv.lowrisc.ibex.pattgen", --=20 2.35.1 From nobody Tue May 14 20:20:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646285981602264.6357309903444; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=05403f1d5=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1646285983887100001 Content-Type: text/plain; charset="utf-8" From: Weiwei Li Co-authored-by: ardxwe Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20220211043920.28981-2-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu.h | 4 ++++ target/riscv/cpu.c | 12 ++++++++++++ 2 files changed, 16 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 8183fb86d5..9ba05042ed 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -362,8 +362,12 @@ struct RISCVCPUConfig { bool ext_svinval; bool ext_svnapot; bool ext_svpbmt; + bool ext_zdinx; bool ext_zfh; bool ext_zfhmin; + bool ext_zfinx; + bool ext_zhinx; + bool ext_zhinxmin; bool ext_zve32f; bool ext_zve64f; =20 diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b0a40b83e7..55371b1aa5 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -587,6 +587,11 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) cpu->cfg.ext_d =3D true; } =20 + if (cpu->cfg.ext_zdinx || cpu->cfg.ext_zhinx || + cpu->cfg.ext_zhinxmin) { + cpu->cfg.ext_zfinx =3D true; + } + /* Set the ISA extensions, checks should have happened above */ if (cpu->cfg.ext_i) { ext |=3D RVI; @@ -665,6 +670,13 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) if (cpu->cfg.ext_j) { ext |=3D RVJ; } + if (cpu->cfg.ext_zfinx && ((ext & (RVF | RVD)) || cpu->cfg.ext_zfh= || + cpu->cfg.ext_zfhmin)) { + error_setg(errp, + "'Zfinx' cannot be supported together with 'F', 'D', '= Zfh'," + " 'Zfhmin'"); + return; + } =20 set_misa(env, env->misa_mxl, ext); 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=216.71.153.144; envelope-from=prvs=05403f1d5=alistair.francis@opensource.wdc.com; helo=esa5.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H2=-0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1646285872102100001 Content-Type: text/plain; charset="utf-8" From: Weiwei Li Co-authored-by: ardxwe Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis Message-Id: <20220211043920.28981-3-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu_helper.c | 6 +++++- target/riscv/csr.c | 25 ++++++++++++++++++++----- target/riscv/translate.c | 4 ++++ 3 files changed, 29 insertions(+), 6 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 746335bfd6..1c60fb2e80 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -466,9 +466,13 @@ bool riscv_cpu_vector_enabled(CPURISCVState *env) =20 void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env) { - uint64_t mstatus_mask =3D MSTATUS_MXR | MSTATUS_SUM | MSTATUS_FS | + uint64_t mstatus_mask =3D MSTATUS_MXR | MSTATUS_SUM | MSTATUS_SPP | MSTATUS_SPIE | MSTATUS_SIE | MSTATUS64_UXL | MSTATUS_VS; + + if (riscv_has_ext(env, RVF)) { + mstatus_mask |=3D MSTATUS_FS; + } bool current_virt =3D riscv_cpu_virt_enabled(env); =20 g_assert(riscv_has_ext(env, RVH)); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index a938760a3f..aea82dff4a 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -39,7 +39,8 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *o= ps) static RISCVException fs(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !riscv_cpu_fp_enabled(env)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env) && + !RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { return RISCV_EXCP_ILLEGAL_INST; } #endif @@ -302,7 +303,9 @@ static RISCVException write_fflags(CPURISCVState *env, = int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - env->mstatus |=3D MSTATUS_FS; + if (riscv_has_ext(env, RVF)) { + env->mstatus |=3D MSTATUS_FS; + } #endif riscv_cpu_set_fflags(env, val & (FSR_AEXC >> FSR_AEXC_SHIFT)); return RISCV_EXCP_NONE; @@ -319,7 +322,9 @@ static RISCVException write_frm(CPURISCVState *env, int= csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - env->mstatus |=3D MSTATUS_FS; + if (riscv_has_ext(env, RVF)) { + env->mstatus |=3D MSTATUS_FS; + } #endif env->frm =3D val & (FSR_RD >> FSR_RD_SHIFT); return RISCV_EXCP_NONE; @@ -337,7 +342,9 @@ static RISCVException write_fcsr(CPURISCVState *env, in= t csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - env->mstatus |=3D MSTATUS_FS; + if (riscv_has_ext(env, RVF)) { + env->mstatus |=3D MSTATUS_FS; + } #endif env->frm =3D (val & FSR_RD) >> FSR_RD_SHIFT; riscv_cpu_set_fflags(env, (val & FSR_AEXC) >> FSR_AEXC_SHIFT); @@ -653,10 +660,14 @@ static RISCVException write_mstatus(CPURISCVState *en= v, int csrno, tlb_flush(env_cpu(env)); } mask =3D MSTATUS_SIE | MSTATUS_SPIE | MSTATUS_MIE | MSTATUS_MPIE | - MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM | + MSTATUS_SPP | MSTATUS_MPRV | MSTATUS_SUM | MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR | MSTATUS_TW | MSTATUS_VS; =20 + if (riscv_has_ext(env, RVF)) { + mask |=3D MSTATUS_FS; + } + if (xl !=3D MXL_RV32 || env->debugger) { /* * RV32: MPV and GVA are not in mstatus. The current plan is to @@ -788,6 +799,10 @@ static RISCVException write_misa(CPURISCVState *env, i= nt csrno, return RISCV_EXCP_NONE; } =20 + if (!(val & RVF)) { + env->mstatus &=3D ~MSTATUS_FS; + } + /* flush translation cache */ tb_flush(env_cpu(env)); env->misa_ext =3D val; diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 84dbfa6340..c7232de326 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -426,6 +426,10 @@ static void mark_fs_dirty(DisasContext *ctx) { TCGv tmp; =20 + if (!has_ext(ctx, RVF)) { + return; + } + if (ctx->mstatus_fs !=3D MSTATUS_FS) { /* Remember the state change for the rest of the TB. */ ctx->mstatus_fs =3D MSTATUS_FS; --=20 2.35.1 From nobody Tue May 14 20:20:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646286094243234.05657570975495; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=05403f1d5=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1646286096504100001 Content-Type: text/plain; charset="utf-8" From: Weiwei Li - update extension check REQUIRE_ZFINX_OR_F - update single float point register read/write - disable nanbox_s check Co-authored-by: ardxwe Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Acked-by: Alistair Francis Message-Id: <20220211043920.28981-4-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 2 +- target/riscv/internals.h | 16 +- target/riscv/fpu_helper.c | 89 +++---- target/riscv/translate.c | 93 ++++++- target/riscv/insn_trans/trans_rvf.c.inc | 314 ++++++++++++++++-------- 5 files changed, 369 insertions(+), 145 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 72cc2582f4..89195aad9d 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -38,7 +38,7 @@ DEF_HELPER_FLAGS_2(fcvt_s_w, TCG_CALL_NO_RWG, i64, env, t= l) DEF_HELPER_FLAGS_2(fcvt_s_wu, TCG_CALL_NO_RWG, i64, env, tl) DEF_HELPER_FLAGS_2(fcvt_s_l, TCG_CALL_NO_RWG, i64, env, tl) DEF_HELPER_FLAGS_2(fcvt_s_lu, TCG_CALL_NO_RWG, i64, env, tl) -DEF_HELPER_FLAGS_1(fclass_s, TCG_CALL_NO_RWG_SE, tl, i64) +DEF_HELPER_FLAGS_2(fclass_s, TCG_CALL_NO_RWG_SE, tl, env, i64) =20 /* Floating Point - Double Precision */ DEF_HELPER_FLAGS_3(fadd_d, TCG_CALL_NO_RWG, i64, env, i64, i64) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 065e8162a2..6237bb3115 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -46,13 +46,23 @@ enum { RISCV_FRM_ROD =3D 8, /* Round to Odd */ }; =20 -static inline uint64_t nanbox_s(float32 f) +static inline uint64_t nanbox_s(CPURISCVState *env, float32 f) { - return f | MAKE_64BIT_MASK(32, 32); + /* the value is sign-extended instead of NaN-boxing for zfinx */ + if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { + return (int32_t)f; + } else { + return f | MAKE_64BIT_MASK(32, 32); + } } =20 -static inline float32 check_nanbox_s(uint64_t f) +static inline float32 check_nanbox_s(CPURISCVState *env, uint64_t f) { + /* Disable NaN-boxing check when enable zfinx */ + if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { + return (uint32_t)f; + } + uint64_t mask =3D MAKE_64BIT_MASK(32, 32); =20 if (likely((f & mask) =3D=3D mask)) { diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index 4a5982d594..63ca703459 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -98,10 +98,11 @@ static uint64_t do_fmadd_h(CPURISCVState *env, uint64_t= rs1, uint64_t rs2, static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2, uint64_t rs3, int flags) { - float32 frs1 =3D check_nanbox_s(rs1); - float32 frs2 =3D check_nanbox_s(rs2); - float32 frs3 =3D check_nanbox_s(rs3); - return nanbox_s(float32_muladd(frs1, frs2, frs3, flags, &env->fp_statu= s)); + float32 frs1 =3D check_nanbox_s(env, rs1); + float32 frs2 =3D check_nanbox_s(env, rs2); + float32 frs3 =3D check_nanbox_s(env, rs3); + return nanbox_s(env, float32_muladd(frs1, frs2, frs3, flags, + &env->fp_status)); } =20 uint64_t helper_fmadd_s(CPURISCVState *env, uint64_t frs1, uint64_t frs2, @@ -183,124 +184,124 @@ uint64_t helper_fnmadd_h(CPURISCVState *env, uint64= _t frs1, uint64_t frs2, =20 uint64_t helper_fadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { - float32 frs1 =3D check_nanbox_s(rs1); - float32 frs2 =3D check_nanbox_s(rs2); - return nanbox_s(float32_add(frs1, frs2, &env->fp_status)); + float32 frs1 =3D check_nanbox_s(env, rs1); + float32 frs2 =3D check_nanbox_s(env, rs2); + return nanbox_s(env, float32_add(frs1, frs2, &env->fp_status)); } =20 uint64_t helper_fsub_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { - float32 frs1 =3D check_nanbox_s(rs1); - float32 frs2 =3D check_nanbox_s(rs2); - return nanbox_s(float32_sub(frs1, frs2, &env->fp_status)); + float32 frs1 =3D check_nanbox_s(env, rs1); + float32 frs2 =3D check_nanbox_s(env, rs2); + return nanbox_s(env, float32_sub(frs1, frs2, &env->fp_status)); } =20 uint64_t helper_fmul_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { - float32 frs1 =3D check_nanbox_s(rs1); - float32 frs2 =3D check_nanbox_s(rs2); - return nanbox_s(float32_mul(frs1, frs2, &env->fp_status)); + float32 frs1 =3D check_nanbox_s(env, rs1); + float32 frs2 =3D check_nanbox_s(env, rs2); + return nanbox_s(env, float32_mul(frs1, frs2, &env->fp_status)); } =20 uint64_t helper_fdiv_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { - float32 frs1 =3D check_nanbox_s(rs1); - float32 frs2 =3D check_nanbox_s(rs2); - return nanbox_s(float32_div(frs1, frs2, &env->fp_status)); + float32 frs1 =3D check_nanbox_s(env, rs1); + float32 frs2 =3D check_nanbox_s(env, rs2); + return nanbox_s(env, float32_div(frs1, frs2, &env->fp_status)); } =20 uint64_t helper_fmin_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { - float32 frs1 =3D check_nanbox_s(rs1); - float32 frs2 =3D check_nanbox_s(rs2); - return nanbox_s(env->priv_ver < PRIV_VERSION_1_11_0 ? + float32 frs1 =3D check_nanbox_s(env, rs1); + float32 frs2 =3D check_nanbox_s(env, rs2); + return nanbox_s(env, env->priv_ver < PRIV_VERSION_1_11_0 ? float32_minnum(frs1, frs2, &env->fp_status) : float32_minimum_number(frs1, frs2, &env->fp_status)); } =20 uint64_t helper_fmax_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { - float32 frs1 =3D check_nanbox_s(rs1); - float32 frs2 =3D check_nanbox_s(rs2); - return nanbox_s(env->priv_ver < PRIV_VERSION_1_11_0 ? + float32 frs1 =3D check_nanbox_s(env, rs1); + float32 frs2 =3D check_nanbox_s(env, rs2); + return nanbox_s(env, env->priv_ver < PRIV_VERSION_1_11_0 ? float32_maxnum(frs1, frs2, &env->fp_status) : float32_maximum_number(frs1, frs2, &env->fp_status)); } =20 uint64_t helper_fsqrt_s(CPURISCVState *env, uint64_t rs1) { - float32 frs1 =3D check_nanbox_s(rs1); - return nanbox_s(float32_sqrt(frs1, &env->fp_status)); + float32 frs1 =3D check_nanbox_s(env, rs1); + return nanbox_s(env, float32_sqrt(frs1, &env->fp_status)); } =20 target_ulong helper_fle_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { - float32 frs1 =3D check_nanbox_s(rs1); - float32 frs2 =3D check_nanbox_s(rs2); + float32 frs1 =3D check_nanbox_s(env, rs1); + float32 frs2 =3D check_nanbox_s(env, rs2); return float32_le(frs1, frs2, &env->fp_status); } =20 target_ulong helper_flt_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { - float32 frs1 =3D check_nanbox_s(rs1); - float32 frs2 =3D check_nanbox_s(rs2); + float32 frs1 =3D check_nanbox_s(env, rs1); + float32 frs2 =3D check_nanbox_s(env, rs2); return float32_lt(frs1, frs2, &env->fp_status); } =20 target_ulong helper_feq_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { - float32 frs1 =3D check_nanbox_s(rs1); - float32 frs2 =3D check_nanbox_s(rs2); + float32 frs1 =3D check_nanbox_s(env, rs1); + float32 frs2 =3D check_nanbox_s(env, rs2); return float32_eq_quiet(frs1, frs2, &env->fp_status); } =20 target_ulong helper_fcvt_w_s(CPURISCVState *env, uint64_t rs1) { - float32 frs1 =3D check_nanbox_s(rs1); + float32 frs1 =3D check_nanbox_s(env, rs1); return float32_to_int32(frs1, &env->fp_status); } =20 target_ulong helper_fcvt_wu_s(CPURISCVState *env, uint64_t rs1) { - float32 frs1 =3D check_nanbox_s(rs1); + float32 frs1 =3D check_nanbox_s(env, rs1); return (int32_t)float32_to_uint32(frs1, &env->fp_status); } =20 target_ulong helper_fcvt_l_s(CPURISCVState *env, uint64_t rs1) { - float32 frs1 =3D check_nanbox_s(rs1); + float32 frs1 =3D check_nanbox_s(env, rs1); return float32_to_int64(frs1, &env->fp_status); } =20 target_ulong helper_fcvt_lu_s(CPURISCVState *env, uint64_t rs1) { - float32 frs1 =3D check_nanbox_s(rs1); + float32 frs1 =3D check_nanbox_s(env, rs1); return float32_to_uint64(frs1, &env->fp_status); } =20 uint64_t helper_fcvt_s_w(CPURISCVState *env, target_ulong rs1) { - return nanbox_s(int32_to_float32((int32_t)rs1, &env->fp_status)); + return nanbox_s(env, int32_to_float32((int32_t)rs1, &env->fp_status)); } =20 uint64_t helper_fcvt_s_wu(CPURISCVState *env, target_ulong rs1) { - return nanbox_s(uint32_to_float32((uint32_t)rs1, &env->fp_status)); + return nanbox_s(env, uint32_to_float32((uint32_t)rs1, &env->fp_status)= ); } =20 uint64_t helper_fcvt_s_l(CPURISCVState *env, target_ulong rs1) { - return nanbox_s(int64_to_float32(rs1, &env->fp_status)); + return nanbox_s(env, int64_to_float32(rs1, &env->fp_status)); } =20 uint64_t helper_fcvt_s_lu(CPURISCVState *env, target_ulong rs1) { - return nanbox_s(uint64_to_float32(rs1, &env->fp_status)); + return nanbox_s(env, uint64_to_float32(rs1, &env->fp_status)); } =20 -target_ulong helper_fclass_s(uint64_t rs1) +target_ulong helper_fclass_s(CPURISCVState *env, uint64_t rs1) { - float32 frs1 =3D check_nanbox_s(rs1); + float32 frs1 =3D check_nanbox_s(env, rs1); return fclass_s(frs1); } =20 @@ -340,12 +341,12 @@ uint64_t helper_fmax_d(CPURISCVState *env, uint64_t f= rs1, uint64_t frs2) =20 uint64_t helper_fcvt_s_d(CPURISCVState *env, uint64_t rs1) { - return nanbox_s(float64_to_float32(rs1, &env->fp_status)); + return nanbox_s(env, float64_to_float32(rs1, &env->fp_status)); } =20 uint64_t helper_fcvt_d_s(CPURISCVState *env, uint64_t rs1) { - float32 frs1 =3D check_nanbox_s(rs1); + float32 frs1 =3D check_nanbox_s(env, rs1); return float32_to_float64(frs1, &env->fp_status); } =20 @@ -539,14 +540,14 @@ uint64_t helper_fcvt_h_lu(CPURISCVState *env, target_= ulong rs1) =20 uint64_t helper_fcvt_h_s(CPURISCVState *env, uint64_t rs1) { - float32 frs1 =3D check_nanbox_s(rs1); + float32 frs1 =3D check_nanbox_s(env, rs1); return nanbox_h(float32_to_float16(frs1, true, &env->fp_status)); } =20 uint64_t helper_fcvt_s_h(CPURISCVState *env, uint64_t rs1) { float16 frs1 =3D check_nanbox_h(rs1); - return nanbox_s(float16_to_float32(frs1, true, &env->fp_status)); + return nanbox_s(env, float16_to_float32(frs1, true, &env->fp_status)); } =20 uint64_t helper_fcvt_h_d(CPURISCVState *env, uint64_t rs1) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index c7232de326..10cf37be41 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -101,6 +101,9 @@ typedef struct DisasContext { TCGv zero; /* Space for 3 operands plus 1 extra for address computation. */ TCGv temp[4]; + /* Space for 4 operands(1 dest and <=3D3 src) for float point computat= ion */ + TCGv_i64 ftemp[4]; + uint8_t nftemp; /* PointerMasking extension */ bool pm_mask_enabled; bool pm_base_enabled; @@ -380,6 +383,86 @@ static void gen_set_gpr128(DisasContext *ctx, int reg_= num, TCGv rl, TCGv rh) } } =20 +static TCGv_i64 ftemp_new(DisasContext *ctx) +{ + assert(ctx->nftemp < ARRAY_SIZE(ctx->ftemp)); + return ctx->ftemp[ctx->nftemp++] =3D tcg_temp_new_i64(); +} + +static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_num) +{ + if (!ctx->cfg_ptr->ext_zfinx) { + return cpu_fpr[reg_num]; + } + + if (reg_num =3D=3D 0) { + return tcg_constant_i64(0); + } + switch (get_xl(ctx)) { + case MXL_RV32: +#ifdef TARGET_RISCV32 + { + TCGv_i64 t =3D ftemp_new(ctx); + tcg_gen_ext_i32_i64(t, cpu_gpr[reg_num]); + return t; + } +#else + /* fall through */ + case MXL_RV64: + return cpu_gpr[reg_num]; +#endif + default: + g_assert_not_reached(); + } +} + +static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) +{ + if (!ctx->cfg_ptr->ext_zfinx) { + return cpu_fpr[reg_num]; + } + + if (reg_num =3D=3D 0) { + return ftemp_new(ctx); + } + + switch (get_xl(ctx)) { + case MXL_RV32: + return ftemp_new(ctx); +#ifdef TARGET_RISCV64 + case MXL_RV64: + return cpu_gpr[reg_num]; +#endif + default: + g_assert_not_reached(); + } +} + +/* assume t is nanboxing (for normal) or sign-extended (for zfinx) */ +static void gen_set_fpr_hs(DisasContext *ctx, int reg_num, TCGv_i64 t) +{ + if (!ctx->cfg_ptr->ext_zfinx) { + tcg_gen_mov_i64(cpu_fpr[reg_num], t); + return; + } + if (reg_num !=3D 0) { + switch (get_xl(ctx)) { + case MXL_RV32: +#ifdef TARGET_RISCV32 + tcg_gen_extrl_i64_i32(cpu_gpr[reg_num], t); + break; +#else + /* fall through */ + case MXL_RV64: + tcg_gen_mov_i64(cpu_gpr[reg_num], t); + break; +#endif + default: + g_assert_not_reached(); + } + } +} + static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) { target_ulong next_pc; @@ -955,6 +1038,8 @@ static void riscv_tr_init_disas_context(DisasContextBa= se *dcbase, CPUState *cs) ctx->cs =3D cs; ctx->ntemp =3D 0; memset(ctx->temp, 0, sizeof(ctx->temp)); + ctx->nftemp =3D 0; + memset(ctx->ftemp, 0, sizeof(ctx->ftemp)); ctx->pm_mask_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_MASK_ENABLE= D); ctx->pm_base_enabled =3D FIELD_EX32(tb_flags, TB_FLAGS, PM_BASE_ENABLE= D); ctx->zero =3D tcg_constant_tl(0); @@ -976,16 +1061,22 @@ static void riscv_tr_translate_insn(DisasContextBase= *dcbase, CPUState *cpu) DisasContext *ctx =3D container_of(dcbase, DisasContext, base); CPURISCVState *env =3D cpu->env_ptr; uint16_t opcode16 =3D translator_lduw(env, &ctx->base, ctx->base.pc_ne= xt); + int i; =20 ctx->ol =3D ctx->xl; decode_opc(env, ctx, opcode16); ctx->base.pc_next =3D ctx->pc_succ_insn; =20 - for (int i =3D ctx->ntemp - 1; i >=3D 0; --i) { + for (i =3D ctx->ntemp - 1; i >=3D 0; --i) { tcg_temp_free(ctx->temp[i]); ctx->temp[i] =3D NULL; } ctx->ntemp =3D 0; + for (i =3D ctx->nftemp - 1; i >=3D 0; --i) { + tcg_temp_free_i64(ctx->ftemp[i]); + ctx->ftemp[i] =3D NULL; + } + ctx->nftemp =3D 0; =20 if (ctx->base.is_jmp =3D=3D DISAS_NEXT) { target_ulong page_start; diff --git a/target/riscv/insn_trans/trans_rvf.c.inc b/target/riscv/insn_tr= ans/trans_rvf.c.inc index 0aac87f7db..a1d3eb52ad 100644 --- a/target/riscv/insn_trans/trans_rvf.c.inc +++ b/target/riscv/insn_trans/trans_rvf.c.inc @@ -20,7 +20,14 @@ =20 #define REQUIRE_FPU do {\ if (ctx->mstatus_fs =3D=3D 0) \ - return false; \ + if (!ctx->cfg_ptr->ext_zfinx) \ + return false; \ +} while (0) + +#define REQUIRE_ZFINX_OR_F(ctx) do {\ + if (!ctx->cfg_ptr->ext_zfinx) { \ + REQUIRE_EXT(ctx, RVF); \ + } \ } while (0) =20 static bool trans_flw(DisasContext *ctx, arg_flw *a) @@ -55,10 +62,16 @@ static bool trans_fsw(DisasContext *ctx, arg_fsw *a) static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_s *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); + REQUIRE_ZFINX_OR_F(ctx); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); + TCGv_i64 src3 =3D get_fpr_hs(ctx, a->rs3); + gen_set_rm(ctx, a->rm); - gen_helper_fmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + gen_helper_fmadd_s(dest, cpu_env, src1, src2, src3); + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -66,10 +79,16 @@ static bool trans_fmadd_s(DisasContext *ctx, arg_fmadd_= s *a) static bool trans_fmsub_s(DisasContext *ctx, arg_fmsub_s *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); + REQUIRE_ZFINX_OR_F(ctx); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); + TCGv_i64 src3 =3D get_fpr_hs(ctx, a->rs3); + gen_set_rm(ctx, a->rm); - gen_helper_fmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + gen_helper_fmsub_s(dest, cpu_env, src1, src2, src3); + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -77,10 +96,16 @@ static bool trans_fmsub_s(DisasContext *ctx, arg_fmsub_= s *a) static bool trans_fnmsub_s(DisasContext *ctx, arg_fnmsub_s *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); + REQUIRE_ZFINX_OR_F(ctx); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); + TCGv_i64 src3 =3D get_fpr_hs(ctx, a->rs3); + gen_set_rm(ctx, a->rm); - gen_helper_fnmsub_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + gen_helper_fnmsub_s(dest, cpu_env, src1, src2, src3); + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -88,10 +113,16 @@ static bool trans_fnmsub_s(DisasContext *ctx, arg_fnms= ub_s *a) static bool trans_fnmadd_s(DisasContext *ctx, arg_fnmadd_s *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); + REQUIRE_ZFINX_OR_F(ctx); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); + TCGv_i64 src3 =3D get_fpr_hs(ctx, a->rs3); + gen_set_rm(ctx, a->rm); - gen_helper_fnmadd_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + gen_helper_fnmadd_s(dest, cpu_env, src1, src2, src3); + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -99,11 +130,15 @@ static bool trans_fnmadd_s(DisasContext *ctx, arg_fnma= dd_s *a) static bool trans_fadd_s(DisasContext *ctx, arg_fadd_s *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); + REQUIRE_ZFINX_OR_F(ctx); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fadd_s(cpu_fpr[a->rd], cpu_env, - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_helper_fadd_s(dest, cpu_env, src1, src2); + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -111,11 +146,15 @@ static bool trans_fadd_s(DisasContext *ctx, arg_fadd_= s *a) static bool trans_fsub_s(DisasContext *ctx, arg_fsub_s *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); + REQUIRE_ZFINX_OR_F(ctx); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fsub_s(cpu_fpr[a->rd], cpu_env, - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_helper_fsub_s(dest, cpu_env, src1, src2); + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -123,11 +162,15 @@ static bool trans_fsub_s(DisasContext *ctx, arg_fsub_= s *a) static bool trans_fmul_s(DisasContext *ctx, arg_fmul_s *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); + REQUIRE_ZFINX_OR_F(ctx); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fmul_s(cpu_fpr[a->rd], cpu_env, - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_helper_fmul_s(dest, cpu_env, src1, src2); + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -135,11 +178,15 @@ static bool trans_fmul_s(DisasContext *ctx, arg_fmul_= s *a) static bool trans_fdiv_s(DisasContext *ctx, arg_fdiv_s *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); + REQUIRE_ZFINX_OR_F(ctx); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fdiv_s(cpu_fpr[a->rd], cpu_env, - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_helper_fdiv_s(dest, cpu_env, src1, src2); + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -147,10 +194,14 @@ static bool trans_fdiv_s(DisasContext *ctx, arg_fdiv_= s *a) static bool trans_fsqrt_s(DisasContext *ctx, arg_fsqrt_s *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); + REQUIRE_ZFINX_OR_F(ctx); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fsqrt_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + gen_helper_fsqrt_s(dest, cpu_env, src1); + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -158,22 +209,37 @@ static bool trans_fsqrt_s(DisasContext *ctx, arg_fsqr= t_s *a) static bool trans_fsgnj_s(DisasContext *ctx, arg_fsgnj_s *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); + REQUIRE_ZFINX_OR_F(ctx); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 if (a->rs1 =3D=3D a->rs2) { /* FMOV */ - gen_check_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rs1]); + if (!ctx->cfg_ptr->ext_zfinx) { + gen_check_nanbox_s(dest, src1); + } else { + tcg_gen_ext32s_i64(dest, src1); + } } else { /* FSGNJ */ - TCGv_i64 rs1 =3D tcg_temp_new_i64(); - TCGv_i64 rs2 =3D tcg_temp_new_i64(); - - gen_check_nanbox_s(rs1, cpu_fpr[a->rs1]); - gen_check_nanbox_s(rs2, cpu_fpr[a->rs2]); - - /* This formulation retains the nanboxing of rs2. */ - tcg_gen_deposit_i64(cpu_fpr[a->rd], rs2, rs1, 0, 31); - tcg_temp_free_i64(rs1); - tcg_temp_free_i64(rs2); + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); + + if (!ctx->cfg_ptr->ext_zfinx) { + TCGv_i64 rs1 =3D tcg_temp_new_i64(); + TCGv_i64 rs2 =3D tcg_temp_new_i64(); + gen_check_nanbox_s(rs1, src1); + gen_check_nanbox_s(rs2, src2); + + /* This formulation retains the nanboxing of rs2 in normal 'F'= . */ + tcg_gen_deposit_i64(dest, rs2, rs1, 0, 31); + + tcg_temp_free_i64(rs1); + tcg_temp_free_i64(rs2); + } else { + tcg_gen_deposit_i64(dest, src2, src1, 0, 31); + tcg_gen_ext32s_i64(dest, dest); + } } + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -183,16 +249,27 @@ static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsg= njn_s *a) TCGv_i64 rs1, rs2, mask; =20 REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); + REQUIRE_ZFINX_OR_F(ctx); =20 - rs1 =3D tcg_temp_new_i64(); - gen_check_nanbox_s(rs1, cpu_fpr[a->rs1]); + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 + rs1 =3D tcg_temp_new_i64(); + if (!ctx->cfg_ptr->ext_zfinx) { + gen_check_nanbox_s(rs1, src1); + } else { + tcg_gen_mov_i64(rs1, src1); + } if (a->rs1 =3D=3D a->rs2) { /* FNEG */ - tcg_gen_xori_i64(cpu_fpr[a->rd], rs1, MAKE_64BIT_MASK(31, 1)); + tcg_gen_xori_i64(dest, rs1, MAKE_64BIT_MASK(31, 1)); } else { + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); rs2 =3D tcg_temp_new_i64(); - gen_check_nanbox_s(rs2, cpu_fpr[a->rs2]); + if (!ctx->cfg_ptr->ext_zfinx) { + gen_check_nanbox_s(rs2, src2); + } else { + tcg_gen_mov_i64(rs2, src2); + } =20 /* * Replace bit 31 in rs1 with inverse in rs2. @@ -200,13 +277,17 @@ static bool trans_fsgnjn_s(DisasContext *ctx, arg_fsg= njn_s *a) */ mask =3D tcg_constant_i64(~MAKE_64BIT_MASK(31, 1)); tcg_gen_nor_i64(rs2, rs2, mask); - tcg_gen_and_i64(rs1, mask, rs1); - tcg_gen_or_i64(cpu_fpr[a->rd], rs1, rs2); + tcg_gen_and_i64(dest, mask, rs1); + tcg_gen_or_i64(dest, dest, rs2); =20 tcg_temp_free_i64(rs2); } + /* signed-extended intead of nanboxing for result if enable zfinx */ + if (ctx->cfg_ptr->ext_zfinx) { + tcg_gen_ext32s_i64(dest, dest); + } + gen_set_fpr_hs(ctx, a->rd, dest); tcg_temp_free_i64(rs1); - mark_fs_dirty(ctx); return true; } @@ -216,28 +297,45 @@ static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsg= njx_s *a) TCGv_i64 rs1, rs2; =20 REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); + REQUIRE_ZFINX_OR_F(ctx); =20 + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); rs1 =3D tcg_temp_new_i64(); - gen_check_nanbox_s(rs1, cpu_fpr[a->rs1]); + + if (!ctx->cfg_ptr->ext_zfinx) { + gen_check_nanbox_s(rs1, src1); + } else { + tcg_gen_mov_i64(rs1, src1); + } =20 if (a->rs1 =3D=3D a->rs2) { /* FABS */ - tcg_gen_andi_i64(cpu_fpr[a->rd], rs1, ~MAKE_64BIT_MASK(31, 1)); + tcg_gen_andi_i64(dest, rs1, ~MAKE_64BIT_MASK(31, 1)); } else { + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); rs2 =3D tcg_temp_new_i64(); - gen_check_nanbox_s(rs2, cpu_fpr[a->rs2]); + + if (!ctx->cfg_ptr->ext_zfinx) { + gen_check_nanbox_s(rs2, src2); + } else { + tcg_gen_mov_i64(rs2, src2); + } =20 /* * Xor bit 31 in rs1 with that in rs2. * This formulation retains the nanboxing of rs1. */ - tcg_gen_andi_i64(rs2, rs2, MAKE_64BIT_MASK(31, 1)); - tcg_gen_xor_i64(cpu_fpr[a->rd], rs1, rs2); + tcg_gen_andi_i64(dest, rs2, MAKE_64BIT_MASK(31, 1)); + tcg_gen_xor_i64(dest, rs1, dest); =20 tcg_temp_free_i64(rs2); } + /* signed-extended intead of nanboxing for result if enable zfinx */ + if (ctx->cfg_ptr->ext_zfinx) { + tcg_gen_ext32s_i64(dest, dest); + } tcg_temp_free_i64(rs1); - + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -245,10 +343,14 @@ static bool trans_fsgnjx_s(DisasContext *ctx, arg_fsg= njx_s *a) static bool trans_fmin_s(DisasContext *ctx, arg_fmin_s *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); + REQUIRE_ZFINX_OR_F(ctx); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 - gen_helper_fmin_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2]); + gen_helper_fmin_s(dest, cpu_env, src1, src2); + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -256,10 +358,14 @@ static bool trans_fmin_s(DisasContext *ctx, arg_fmin_= s *a) static bool trans_fmax_s(DisasContext *ctx, arg_fmax_s *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); + REQUIRE_ZFINX_OR_F(ctx); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 - gen_helper_fmax_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2]); + gen_helper_fmax_s(dest, cpu_env, src1, src2); + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -267,12 +373,13 @@ static bool trans_fmax_s(DisasContext *ctx, arg_fmax_= s *a) static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcvt_w_s *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); + REQUIRE_ZFINX_OR_F(ctx); =20 TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_w_s(dest, cpu_env, cpu_fpr[a->rs1]); + gen_helper_fcvt_w_s(dest, cpu_env, src1); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -280,12 +387,13 @@ static bool trans_fcvt_w_s(DisasContext *ctx, arg_fcv= t_w_s *a) static bool trans_fcvt_wu_s(DisasContext *ctx, arg_fcvt_wu_s *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); + REQUIRE_ZFINX_OR_F(ctx); =20 TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_wu_s(dest, cpu_env, cpu_fpr[a->rs1]); + gen_helper_fcvt_wu_s(dest, cpu_env, src1); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -294,14 +402,14 @@ static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_= x_w *a) { /* NOTE: This was FMV.X.S in an earlier version of the ISA spec! */ REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); + REQUIRE_ZFINX_OR_F(ctx); =20 TCGv dest =3D dest_gpr(ctx, a->rd); - + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); #if defined(TARGET_RISCV64) - tcg_gen_ext32s_tl(dest, cpu_fpr[a->rs1]); + tcg_gen_ext32s_tl(dest, src1); #else - tcg_gen_extrl_i64_i32(dest, cpu_fpr[a->rs1]); + tcg_gen_extrl_i64_i32(dest, src1); #endif =20 gen_set_gpr(ctx, a->rd, dest); @@ -311,11 +419,13 @@ static bool trans_fmv_x_w(DisasContext *ctx, arg_fmv_= x_w *a) static bool trans_feq_s(DisasContext *ctx, arg_feq_s *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); + REQUIRE_ZFINX_OR_F(ctx); =20 TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 - gen_helper_feq_s(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_helper_feq_s(dest, cpu_env, src1, src2); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -323,11 +433,13 @@ static bool trans_feq_s(DisasContext *ctx, arg_feq_s = *a) static bool trans_flt_s(DisasContext *ctx, arg_flt_s *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); + REQUIRE_ZFINX_OR_F(ctx); =20 TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 - gen_helper_flt_s(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_helper_flt_s(dest, cpu_env, src1, src2); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -335,11 +447,13 @@ static bool trans_flt_s(DisasContext *ctx, arg_flt_s = *a) static bool trans_fle_s(DisasContext *ctx, arg_fle_s *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); + REQUIRE_ZFINX_OR_F(ctx); =20 TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 - gen_helper_fle_s(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_helper_fle_s(dest, cpu_env, src1, src2); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -347,11 +461,12 @@ static bool trans_fle_s(DisasContext *ctx, arg_fle_s = *a) static bool trans_fclass_s(DisasContext *ctx, arg_fclass_s *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); + REQUIRE_ZFINX_OR_F(ctx); =20 TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 - gen_helper_fclass_s(dest, cpu_fpr[a->rs1]); + gen_helper_fclass_s(dest, cpu_env, src1); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -359,13 +474,14 @@ static bool trans_fclass_s(DisasContext *ctx, arg_fcl= ass_s *a) static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcvt_s_w *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); + REQUIRE_ZFINX_OR_F(ctx); =20 + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); TCGv src =3D get_gpr(ctx, a->rs1, EXT_SIGN); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_s_w(cpu_fpr[a->rd], cpu_env, src); - + gen_helper_fcvt_s_w(dest, cpu_env, src); + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -373,13 +489,14 @@ static bool trans_fcvt_s_w(DisasContext *ctx, arg_fcv= t_s_w *a) static bool trans_fcvt_s_wu(DisasContext *ctx, arg_fcvt_s_wu *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); + REQUIRE_ZFINX_OR_F(ctx); =20 + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); TCGv src =3D get_gpr(ctx, a->rs1, EXT_ZERO); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_s_wu(cpu_fpr[a->rd], cpu_env, src); - + gen_helper_fcvt_s_wu(dest, cpu_env, src); + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -388,13 +505,14 @@ static bool trans_fmv_w_x(DisasContext *ctx, arg_fmv_= w_x *a) { /* NOTE: This was FMV.S.X in an earlier version of the ISA spec! */ REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); + REQUIRE_ZFINX_OR_F(ctx); =20 + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); TCGv src =3D get_gpr(ctx, a->rs1, EXT_ZERO); =20 - tcg_gen_extu_tl_i64(cpu_fpr[a->rd], src); - gen_nanbox_s(cpu_fpr[a->rd], cpu_fpr[a->rd]); - + tcg_gen_extu_tl_i64(dest, src); + gen_nanbox_s(dest, dest); + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -403,12 +521,13 @@ static bool trans_fcvt_l_s(DisasContext *ctx, arg_fcv= t_l_s *a) { REQUIRE_64BIT(ctx); REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); + REQUIRE_ZFINX_OR_F(ctx); =20 TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_l_s(dest, cpu_env, cpu_fpr[a->rs1]); + gen_helper_fcvt_l_s(dest, cpu_env, src1); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -417,12 +536,13 @@ static bool trans_fcvt_lu_s(DisasContext *ctx, arg_fc= vt_lu_s *a) { REQUIRE_64BIT(ctx); REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); + REQUIRE_ZFINX_OR_F(ctx); =20 TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_lu_s(dest, cpu_env, cpu_fpr[a->rs1]); + gen_helper_fcvt_lu_s(dest, cpu_env, src1); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -431,13 +551,14 @@ static bool trans_fcvt_s_l(DisasContext *ctx, arg_fcv= t_s_l *a) { REQUIRE_64BIT(ctx); REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); + REQUIRE_ZFINX_OR_F(ctx); =20 + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); TCGv src =3D get_gpr(ctx, a->rs1, EXT_SIGN); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_s_l(cpu_fpr[a->rd], cpu_env, src); - + gen_helper_fcvt_s_l(dest, cpu_env, src); + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -446,13 +567,14 @@ static bool trans_fcvt_s_lu(DisasContext *ctx, arg_fc= vt_s_lu *a) { REQUIRE_64BIT(ctx); REQUIRE_FPU; - REQUIRE_EXT(ctx, RVF); + REQUIRE_ZFINX_OR_F(ctx); =20 + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); TCGv src =3D get_gpr(ctx, a->rs1, EXT_ZERO); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_s_lu(cpu_fpr[a->rd], cpu_env, src); - + gen_helper_fcvt_s_lu(dest, cpu_env, src); + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } --=20 2.35.1 From nobody Tue May 14 20:20:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1646285353; x=1648877354; bh=2t0vsEldS300M3Equf nFYimaYfcDKd82uIpaHgjF9fQ=; b=jd0noyfYtYQnXn3czEs0PA/KFREGuZrzgV cQdFiL/5pNUrzPgn/IKsKtwagGDZPnBxv/70YT7lvuvsdmXeRyVvw2O5EAiyEiH8 VepLRaMNq27J+0XgcmeNZj4X096aalkQZ5qYfnWao99sxpne9kNmVd26s06qG2xe kQaiImIjJG13UJjNYFhXAKQH/TnO5QYKY4nWVO3Gm9Is+fY28XpFZ+7rLBWJyUrE mek4RpIBifLbJf7vB+UCzDUMX9INljGm+1CyiFh4PRvwVyLp7SpGAq9GL3rR/jMr PGJ5kHInV8ZDXhW7g+Hvh53FryTttV7OIcDGwmMnPYd1EwPjyYtg== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , ardxwe , Junqiang Wang , Richard Henderson , Alistair Francis Subject: [PULL 11/13] target/riscv: add support for zdinx Date: Thu, 3 Mar 2022 15:28:02 +1000 Message-Id: <20220303052804.529967-12-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220303052804.529967-1-alistair.francis@opensource.wdc.com> References: <20220303052804.529967-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.143.124; envelope-from=prvs=05403f1d5=alistair.francis@opensource.wdc.com; helo=esa2.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1646285737311100001 Content-Type: text/plain; charset="utf-8" From: Weiwei Li -- update extension check REQUIRE_ZDINX_OR_D -- update double float point register read/write Co-authored-by: ardxwe Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20220211043920.28981-5-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/translate.c | 52 +++++ target/riscv/insn_trans/trans_rvd.c.inc | 285 +++++++++++++++++------- 2 files changed, 259 insertions(+), 78 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 10cf37be41..fac998a6b5 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -416,6 +416,31 @@ static TCGv_i64 get_fpr_hs(DisasContext *ctx, int reg_= num) } } =20 +static TCGv_i64 get_fpr_d(DisasContext *ctx, int reg_num) +{ + if (!ctx->cfg_ptr->ext_zfinx) { + return cpu_fpr[reg_num]; + } + + if (reg_num =3D=3D 0) { + return tcg_constant_i64(0); + } + switch (get_xl(ctx)) { + case MXL_RV32: + { + TCGv_i64 t =3D ftemp_new(ctx); + tcg_gen_concat_tl_i64(t, cpu_gpr[reg_num], cpu_gpr[reg_num + 1]); + return t; + } +#ifdef TARGET_RISCV64 + case MXL_RV64: + return cpu_gpr[reg_num]; +#endif + default: + g_assert_not_reached(); + } +} + static TCGv_i64 dest_fpr(DisasContext *ctx, int reg_num) { if (!ctx->cfg_ptr->ext_zfinx) { @@ -463,6 +488,33 @@ static void gen_set_fpr_hs(DisasContext *ctx, int reg_= num, TCGv_i64 t) } } =20 +static void gen_set_fpr_d(DisasContext *ctx, int reg_num, TCGv_i64 t) +{ + if (!ctx->cfg_ptr->ext_zfinx) { + tcg_gen_mov_i64(cpu_fpr[reg_num], t); + return; + } + + if (reg_num !=3D 0) { + switch (get_xl(ctx)) { + case MXL_RV32: +#ifdef TARGET_RISCV32 + tcg_gen_extr_i64_i32(cpu_gpr[reg_num], cpu_gpr[reg_num + 1], t= ); + break; +#else + tcg_gen_ext32s_i64(cpu_gpr[reg_num], t); + tcg_gen_sari_i64(cpu_gpr[reg_num + 1], t, 32); + break; + case MXL_RV64: + tcg_gen_mov_i64(cpu_gpr[reg_num], t); + break; +#endif + default: + g_assert_not_reached(); + } + } +} + static void gen_jal(DisasContext *ctx, int rd, target_ulong imm) { target_ulong next_pc; diff --git a/target/riscv/insn_trans/trans_rvd.c.inc b/target/riscv/insn_tr= ans/trans_rvd.c.inc index 091ed3a8ad..1397c1ce1c 100644 --- a/target/riscv/insn_trans/trans_rvd.c.inc +++ b/target/riscv/insn_trans/trans_rvd.c.inc @@ -18,6 +18,19 @@ * this program. If not, see . */ =20 +#define REQUIRE_ZDINX_OR_D(ctx) do { \ + if (!ctx->cfg_ptr->ext_zdinx) { \ + REQUIRE_EXT(ctx, RVD); \ + } \ +} while (0) + +#define REQUIRE_EVEN(ctx, reg) do { \ + if (ctx->cfg_ptr->ext_zdinx && (get_xl(ctx) =3D=3D MXL_RV32) && \ + ((reg) & 0x1)) { \ + return false; \ + } \ +} while (0) + static bool trans_fld(DisasContext *ctx, arg_fld *a) { TCGv addr; @@ -47,10 +60,17 @@ static bool trans_fsd(DisasContext *ctx, arg_fsd *a) static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_d *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); + REQUIRE_ZDINX_OR_D(ctx); + REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); + TCGv_i64 src3 =3D get_fpr_d(ctx, a->rs3); + gen_set_rm(ctx, a->rm); - gen_helper_fmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + gen_helper_fmadd_d(dest, cpu_env, src1, src2, src3); + gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -58,10 +78,17 @@ static bool trans_fmadd_d(DisasContext *ctx, arg_fmadd_= d *a) static bool trans_fmsub_d(DisasContext *ctx, arg_fmsub_d *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); + REQUIRE_ZDINX_OR_D(ctx); + REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); + TCGv_i64 src3 =3D get_fpr_d(ctx, a->rs3); + gen_set_rm(ctx, a->rm); - gen_helper_fmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + gen_helper_fmsub_d(dest, cpu_env, src1, src2, src3); + gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -69,10 +96,17 @@ static bool trans_fmsub_d(DisasContext *ctx, arg_fmsub_= d *a) static bool trans_fnmsub_d(DisasContext *ctx, arg_fnmsub_d *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); + REQUIRE_ZDINX_OR_D(ctx); + REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); + TCGv_i64 src3 =3D get_fpr_d(ctx, a->rs3); + gen_set_rm(ctx, a->rm); - gen_helper_fnmsub_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + gen_helper_fnmsub_d(dest, cpu_env, src1, src2, src3); + gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -80,10 +114,17 @@ static bool trans_fnmsub_d(DisasContext *ctx, arg_fnms= ub_d *a) static bool trans_fnmadd_d(DisasContext *ctx, arg_fnmadd_d *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); + REQUIRE_ZDINX_OR_D(ctx); + REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2 | a->rs3); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); + TCGv_i64 src3 =3D get_fpr_d(ctx, a->rs3); + gen_set_rm(ctx, a->rm); - gen_helper_fnmadd_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + gen_helper_fnmadd_d(dest, cpu_env, src1, src2, src3); + gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -91,12 +132,16 @@ static bool trans_fnmadd_d(DisasContext *ctx, arg_fnma= dd_d *a) static bool trans_fadd_d(DisasContext *ctx, arg_fadd_d *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); + REQUIRE_ZDINX_OR_D(ctx); + REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2); =20 - gen_set_rm(ctx, a->rm); - gen_helper_fadd_d(cpu_fpr[a->rd], cpu_env, - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); =20 + gen_set_rm(ctx, a->rm); + gen_helper_fadd_d(dest, cpu_env, src1, src2); + gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -104,12 +149,16 @@ static bool trans_fadd_d(DisasContext *ctx, arg_fadd_= d *a) static bool trans_fsub_d(DisasContext *ctx, arg_fsub_d *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); + REQUIRE_ZDINX_OR_D(ctx); + REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2); =20 - gen_set_rm(ctx, a->rm); - gen_helper_fsub_d(cpu_fpr[a->rd], cpu_env, - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); =20 + gen_set_rm(ctx, a->rm); + gen_helper_fsub_d(dest, cpu_env, src1, src2); + gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -117,12 +166,16 @@ static bool trans_fsub_d(DisasContext *ctx, arg_fsub_= d *a) static bool trans_fmul_d(DisasContext *ctx, arg_fmul_d *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); + REQUIRE_ZDINX_OR_D(ctx); + REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2); =20 - gen_set_rm(ctx, a->rm); - gen_helper_fmul_d(cpu_fpr[a->rd], cpu_env, - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); =20 + gen_set_rm(ctx, a->rm); + gen_helper_fmul_d(dest, cpu_env, src1, src2); + gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -130,12 +183,16 @@ static bool trans_fmul_d(DisasContext *ctx, arg_fmul_= d *a) static bool trans_fdiv_d(DisasContext *ctx, arg_fdiv_d *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); + REQUIRE_ZDINX_OR_D(ctx); + REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2); =20 - gen_set_rm(ctx, a->rm); - gen_helper_fdiv_d(cpu_fpr[a->rd], cpu_env, - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); =20 + gen_set_rm(ctx, a->rm); + gen_helper_fdiv_d(dest, cpu_env, src1, src2); + gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -143,23 +200,34 @@ static bool trans_fdiv_d(DisasContext *ctx, arg_fdiv_= d *a) static bool trans_fsqrt_d(DisasContext *ctx, arg_fsqrt_d *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); + REQUIRE_ZDINX_OR_D(ctx); + REQUIRE_EVEN(ctx, a->rd | a->rs1); =20 - gen_set_rm(ctx, a->rm); - gen_helper_fsqrt_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); =20 + gen_set_rm(ctx, a->rm); + gen_helper_fsqrt_d(dest, cpu_env, src1); + gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } =20 static bool trans_fsgnj_d(DisasContext *ctx, arg_fsgnj_d *a) { + REQUIRE_FPU; + REQUIRE_ZDINX_OR_D(ctx); + REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); if (a->rs1 =3D=3D a->rs2) { /* FMOV */ - tcg_gen_mov_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1]); + dest =3D get_fpr_d(ctx, a->rs1); } else { - tcg_gen_deposit_i64(cpu_fpr[a->rd], cpu_fpr[a->rs2], - cpu_fpr[a->rs1], 0, 63); + TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); + tcg_gen_deposit_i64(dest, src2, src1, 0, 63); } + gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -167,15 +235,22 @@ static bool trans_fsgnj_d(DisasContext *ctx, arg_fsgn= j_d *a) static bool trans_fsgnjn_d(DisasContext *ctx, arg_fsgnjn_d *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); + REQUIRE_ZDINX_OR_D(ctx); + REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); + if (a->rs1 =3D=3D a->rs2) { /* FNEG */ - tcg_gen_xori_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], INT64_MIN); + tcg_gen_xori_i64(dest, src1, INT64_MIN); } else { + TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); TCGv_i64 t0 =3D tcg_temp_new_i64(); - tcg_gen_not_i64(t0, cpu_fpr[a->rs2]); - tcg_gen_deposit_i64(cpu_fpr[a->rd], t0, cpu_fpr[a->rs1], 0, 63); + tcg_gen_not_i64(t0, src2); + tcg_gen_deposit_i64(dest, t0, src1, 0, 63); tcg_temp_free_i64(t0); } + gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -183,15 +258,22 @@ static bool trans_fsgnjn_d(DisasContext *ctx, arg_fsg= njn_d *a) static bool trans_fsgnjx_d(DisasContext *ctx, arg_fsgnjx_d *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); + REQUIRE_ZDINX_OR_D(ctx); + REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); + if (a->rs1 =3D=3D a->rs2) { /* FABS */ - tcg_gen_andi_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], ~INT64_MIN); + tcg_gen_andi_i64(dest, src1, ~INT64_MIN); } else { + TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); TCGv_i64 t0 =3D tcg_temp_new_i64(); - tcg_gen_andi_i64(t0, cpu_fpr[a->rs2], INT64_MIN); - tcg_gen_xor_i64(cpu_fpr[a->rd], cpu_fpr[a->rs1], t0); + tcg_gen_andi_i64(t0, src2, INT64_MIN); + tcg_gen_xor_i64(dest, src1, t0); tcg_temp_free_i64(t0); } + gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -199,11 +281,15 @@ static bool trans_fsgnjx_d(DisasContext *ctx, arg_fsg= njx_d *a) static bool trans_fmin_d(DisasContext *ctx, arg_fmin_d *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); + REQUIRE_ZDINX_OR_D(ctx); + REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2); =20 - gen_helper_fmin_d(cpu_fpr[a->rd], cpu_env, - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); =20 + gen_helper_fmin_d(dest, cpu_env, src1, src2); + gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -211,11 +297,15 @@ static bool trans_fmin_d(DisasContext *ctx, arg_fmin_= d *a) static bool trans_fmax_d(DisasContext *ctx, arg_fmax_d *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); + REQUIRE_ZDINX_OR_D(ctx); + REQUIRE_EVEN(ctx, a->rd | a->rs1 | a->rs2); =20 - gen_helper_fmax_d(cpu_fpr[a->rd], cpu_env, - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); =20 + gen_helper_fmax_d(dest, cpu_env, src1, src2); + gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -223,11 +313,15 @@ static bool trans_fmax_d(DisasContext *ctx, arg_fmax_= d *a) static bool trans_fcvt_s_d(DisasContext *ctx, arg_fcvt_s_d *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); + REQUIRE_ZDINX_OR_D(ctx); + REQUIRE_EVEN(ctx, a->rs1); =20 - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_s_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); =20 + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_s_d(dest, cpu_env, src1); + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -235,11 +329,15 @@ static bool trans_fcvt_s_d(DisasContext *ctx, arg_fcv= t_s_d *a) static bool trans_fcvt_d_s(DisasContext *ctx, arg_fcvt_d_s *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); + REQUIRE_ZDINX_OR_D(ctx); + REQUIRE_EVEN(ctx, a->rd); =20 - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_d_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_d_s(dest, cpu_env, src1); + gen_set_fpr_d(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -247,11 +345,14 @@ static bool trans_fcvt_d_s(DisasContext *ctx, arg_fcv= t_d_s *a) static bool trans_feq_d(DisasContext *ctx, arg_feq_d *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); + REQUIRE_ZDINX_OR_D(ctx); + REQUIRE_EVEN(ctx, a->rs1 | a->rs2); =20 TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); =20 - gen_helper_feq_d(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_helper_feq_d(dest, cpu_env, src1, src2); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -259,11 +360,14 @@ static bool trans_feq_d(DisasContext *ctx, arg_feq_d = *a) static bool trans_flt_d(DisasContext *ctx, arg_flt_d *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); + REQUIRE_ZDINX_OR_D(ctx); + REQUIRE_EVEN(ctx, a->rs1 | a->rs2); =20 TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); =20 - gen_helper_flt_d(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_helper_flt_d(dest, cpu_env, src1, src2); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -271,11 +375,14 @@ static bool trans_flt_d(DisasContext *ctx, arg_flt_d = *a) static bool trans_fle_d(DisasContext *ctx, arg_fle_d *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); + REQUIRE_ZDINX_OR_D(ctx); + REQUIRE_EVEN(ctx, a->rs1 | a->rs2); =20 TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_d(ctx, a->rs2); =20 - gen_helper_fle_d(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_helper_fle_d(dest, cpu_env, src1, src2); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -283,11 +390,13 @@ static bool trans_fle_d(DisasContext *ctx, arg_fle_d = *a) static bool trans_fclass_d(DisasContext *ctx, arg_fclass_d *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); + REQUIRE_ZDINX_OR_D(ctx); + REQUIRE_EVEN(ctx, a->rs1); =20 TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); =20 - gen_helper_fclass_d(dest, cpu_fpr[a->rs1]); + gen_helper_fclass_d(dest, src1); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -295,12 +404,14 @@ static bool trans_fclass_d(DisasContext *ctx, arg_fcl= ass_d *a) static bool trans_fcvt_w_d(DisasContext *ctx, arg_fcvt_w_d *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); + REQUIRE_ZDINX_OR_D(ctx); + REQUIRE_EVEN(ctx, a->rs1); =20 TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_w_d(dest, cpu_env, cpu_fpr[a->rs1]); + gen_helper_fcvt_w_d(dest, cpu_env, src1); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -308,12 +419,14 @@ static bool trans_fcvt_w_d(DisasContext *ctx, arg_fcv= t_w_d *a) static bool trans_fcvt_wu_d(DisasContext *ctx, arg_fcvt_wu_d *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); + REQUIRE_ZDINX_OR_D(ctx); + REQUIRE_EVEN(ctx, a->rs1); =20 TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_wu_d(dest, cpu_env, cpu_fpr[a->rs1]); + gen_helper_fcvt_wu_d(dest, cpu_env, src1); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -321,12 +434,15 @@ static bool trans_fcvt_wu_d(DisasContext *ctx, arg_fc= vt_wu_d *a) static bool trans_fcvt_d_w(DisasContext *ctx, arg_fcvt_d_w *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); + REQUIRE_ZDINX_OR_D(ctx); + REQUIRE_EVEN(ctx, a->rd); =20 + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); TCGv src =3D get_gpr(ctx, a->rs1, EXT_SIGN); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_d_w(cpu_fpr[a->rd], cpu_env, src); + gen_helper_fcvt_d_w(dest, cpu_env, src); + gen_set_fpr_d(ctx, a->rd, dest); =20 mark_fs_dirty(ctx); return true; @@ -335,12 +451,15 @@ static bool trans_fcvt_d_w(DisasContext *ctx, arg_fcv= t_d_w *a) static bool trans_fcvt_d_wu(DisasContext *ctx, arg_fcvt_d_wu *a) { REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); + REQUIRE_ZDINX_OR_D(ctx); + REQUIRE_EVEN(ctx, a->rd); =20 + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); TCGv src =3D get_gpr(ctx, a->rs1, EXT_ZERO); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_d_wu(cpu_fpr[a->rd], cpu_env, src); + gen_helper_fcvt_d_wu(dest, cpu_env, src); + gen_set_fpr_d(ctx, a->rd, dest); =20 mark_fs_dirty(ctx); return true; @@ -350,12 +469,14 @@ static bool trans_fcvt_l_d(DisasContext *ctx, arg_fcv= t_l_d *a) { REQUIRE_64BIT(ctx); REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); + REQUIRE_ZDINX_OR_D(ctx); + REQUIRE_EVEN(ctx, a->rs1); =20 TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_l_d(dest, cpu_env, cpu_fpr[a->rs1]); + gen_helper_fcvt_l_d(dest, cpu_env, src1); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -364,12 +485,14 @@ static bool trans_fcvt_lu_d(DisasContext *ctx, arg_fc= vt_lu_d *a) { REQUIRE_64BIT(ctx); REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); + REQUIRE_ZDINX_OR_D(ctx); + REQUIRE_EVEN(ctx, a->rs1); =20 TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_lu_d(dest, cpu_env, cpu_fpr[a->rs1]); + gen_helper_fcvt_lu_d(dest, cpu_env, src1); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -392,12 +515,15 @@ static bool trans_fcvt_d_l(DisasContext *ctx, arg_fcv= t_d_l *a) { REQUIRE_64BIT(ctx); REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); + REQUIRE_ZDINX_OR_D(ctx); + REQUIRE_EVEN(ctx, a->rd); =20 + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); TCGv src =3D get_gpr(ctx, a->rs1, EXT_SIGN); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_d_l(cpu_fpr[a->rd], cpu_env, src); + gen_helper_fcvt_d_l(dest, cpu_env, src); + gen_set_fpr_d(ctx, a->rd, dest); =20 mark_fs_dirty(ctx); return true; @@ -407,12 +533,15 @@ static bool trans_fcvt_d_lu(DisasContext *ctx, arg_fc= vt_d_lu *a) { REQUIRE_64BIT(ctx); REQUIRE_FPU; - REQUIRE_EXT(ctx, RVD); + REQUIRE_ZDINX_OR_D(ctx); + REQUIRE_EVEN(ctx, a->rd); =20 + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); TCGv src =3D get_gpr(ctx, a->rs1, EXT_ZERO); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_d_lu(cpu_fpr[a->rd], cpu_env, src); + gen_helper_fcvt_d_lu(dest, cpu_env, src); + gen_set_fpr_d(ctx, a->rd, dest); =20 mark_fs_dirty(ctx); return true; --=20 2.35.1 From nobody Tue May 14 20:20:37 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=quarantine dis=quarantine) header.from=opensource.wdc.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646285849677570.3547407351581; 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s=dkim; t=1646285358; x=1648877359; bh=/5tCj7ol249FUH1Ksh jRPA7xPDrsV4lcg6F8IggF7hM=; b=ETyMjjEo60HOMqleOeYFEaaksi0uj+6o/H ClquxBJPCpOFKHAuX2b6gN9S5D53NhhisSs4o0K7yxo++NlmFo9vPSo2D+WrpGdI ULaXE0kuMFJgCvbSd96QGwLgDc9o+LE3DSy2xt3iwIaISdKW79o1N+IWJYatlUB+ 38Qez6t9e44XrY/2QGsIi9q/Sz9J34NH7OpnC4kTX+su620ry+20zmeTUtIZVXiT S6ssXm8J3SfTTn6Widfy4WGsLkQ089T/WtyTgAGmZrEKLX1WKxaJApzdqjOqPRe5 B0VIJP8YvvFPX71/H/2CxsoMWPNmddynRY8B4pXv+QuSMODjfQNA== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , Junqiang Wang , Richard Henderson , Alistair Francis Subject: [PULL 12/13] target/riscv: add support for zhinx/zhinxmin Date: Thu, 3 Mar 2022 15:28:03 +1000 Message-Id: <20220303052804.529967-13-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220303052804.529967-1-alistair.francis@opensource.wdc.com> References: <20220303052804.529967-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=05403f1d5=alistair.francis@opensource.wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1646285852794100001 Content-Type: text/plain; charset="utf-8" From: Weiwei Li - update extension check REQUIRE_ZHINX_OR_ZFH and REQUIRE_ZFH_OR_ZFHMIN_O= R_ZHINX_OR_ZHINXMIN - update half float point register read/write - disable nanbox_h check Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Acked-by: Alistair Francis Message-Id: <20220211043920.28981-6-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/helper.h | 2 +- target/riscv/internals.h | 16 +- target/riscv/fpu_helper.c | 89 +++--- target/riscv/insn_trans/trans_rvzfh.c.inc | 332 +++++++++++++++------- 4 files changed, 296 insertions(+), 143 deletions(-) diff --git a/target/riscv/helper.h b/target/riscv/helper.h index 89195aad9d..26bbab2fab 100644 --- a/target/riscv/helper.h +++ b/target/riscv/helper.h @@ -90,7 +90,7 @@ DEF_HELPER_FLAGS_2(fcvt_h_w, TCG_CALL_NO_RWG, i64, env, t= l) DEF_HELPER_FLAGS_2(fcvt_h_wu, TCG_CALL_NO_RWG, i64, env, tl) DEF_HELPER_FLAGS_2(fcvt_h_l, TCG_CALL_NO_RWG, i64, env, tl) DEF_HELPER_FLAGS_2(fcvt_h_lu, TCG_CALL_NO_RWG, i64, env, tl) -DEF_HELPER_FLAGS_1(fclass_h, TCG_CALL_NO_RWG_SE, tl, i64) +DEF_HELPER_FLAGS_2(fclass_h, TCG_CALL_NO_RWG_SE, tl, env, i64) =20 /* Special functions */ DEF_HELPER_2(csrr, tl, env, int) diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 6237bb3115..dbb322bfa7 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -72,13 +72,23 @@ static inline float32 check_nanbox_s(CPURISCVState *env= , uint64_t f) } } =20 -static inline uint64_t nanbox_h(float16 f) +static inline uint64_t nanbox_h(CPURISCVState *env, float16 f) { - return f | MAKE_64BIT_MASK(16, 48); + /* the value is sign-extended instead of NaN-boxing for zfinx */ + if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { + return (int16_t)f; + } else { + return f | MAKE_64BIT_MASK(16, 48); + } } =20 -static inline float16 check_nanbox_h(uint64_t f) +static inline float16 check_nanbox_h(CPURISCVState *env, uint64_t f) { + /* Disable nanbox check when enable zfinx */ + if (RISCV_CPU(env_cpu(env))->cfg.ext_zfinx) { + return (uint16_t)f; + } + uint64_t mask =3D MAKE_64BIT_MASK(16, 48); =20 if (likely((f & mask) =3D=3D mask)) { diff --git a/target/riscv/fpu_helper.c b/target/riscv/fpu_helper.c index 63ca703459..5699c9517f 100644 --- a/target/riscv/fpu_helper.c +++ b/target/riscv/fpu_helper.c @@ -89,10 +89,11 @@ void helper_set_rod_rounding_mode(CPURISCVState *env) static uint64_t do_fmadd_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2, uint64_t rs3, int flags) { - float16 frs1 =3D check_nanbox_h(rs1); - float16 frs2 =3D check_nanbox_h(rs2); - float16 frs3 =3D check_nanbox_h(rs3); - return nanbox_h(float16_muladd(frs1, frs2, frs3, flags, &env->fp_statu= s)); + float16 frs1 =3D check_nanbox_h(env, rs1); + float16 frs2 =3D check_nanbox_h(env, rs2); + float16 frs3 =3D check_nanbox_h(env, rs3); + return nanbox_h(env, float16_muladd(frs1, frs2, frs3, flags, + &env->fp_status)); } =20 static uint64_t do_fmadd_s(CPURISCVState *env, uint64_t rs1, uint64_t rs2, @@ -417,146 +418,146 @@ target_ulong helper_fclass_d(uint64_t frs1) =20 uint64_t helper_fadd_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { - float16 frs1 =3D check_nanbox_h(rs1); - float16 frs2 =3D check_nanbox_h(rs2); - return nanbox_h(float16_add(frs1, frs2, &env->fp_status)); + float16 frs1 =3D check_nanbox_h(env, rs1); + float16 frs2 =3D check_nanbox_h(env, rs2); + return nanbox_h(env, float16_add(frs1, frs2, &env->fp_status)); } =20 uint64_t helper_fsub_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { - float16 frs1 =3D check_nanbox_h(rs1); - float16 frs2 =3D check_nanbox_h(rs2); - return nanbox_h(float16_sub(frs1, frs2, &env->fp_status)); + float16 frs1 =3D check_nanbox_h(env, rs1); + float16 frs2 =3D check_nanbox_h(env, rs2); + return nanbox_h(env, float16_sub(frs1, frs2, &env->fp_status)); } =20 uint64_t helper_fmul_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { - float16 frs1 =3D check_nanbox_h(rs1); - float16 frs2 =3D check_nanbox_h(rs2); - return nanbox_h(float16_mul(frs1, frs2, &env->fp_status)); + float16 frs1 =3D check_nanbox_h(env, rs1); + float16 frs2 =3D check_nanbox_h(env, rs2); + return nanbox_h(env, float16_mul(frs1, frs2, &env->fp_status)); } =20 uint64_t helper_fdiv_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { - float16 frs1 =3D check_nanbox_h(rs1); - float16 frs2 =3D check_nanbox_h(rs2); - return nanbox_h(float16_div(frs1, frs2, &env->fp_status)); + float16 frs1 =3D check_nanbox_h(env, rs1); + float16 frs2 =3D check_nanbox_h(env, rs2); + return nanbox_h(env, float16_div(frs1, frs2, &env->fp_status)); } =20 uint64_t helper_fmin_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { - float16 frs1 =3D check_nanbox_h(rs1); - float16 frs2 =3D check_nanbox_h(rs2); - return nanbox_h(env->priv_ver < PRIV_VERSION_1_11_0 ? + float16 frs1 =3D check_nanbox_h(env, rs1); + float16 frs2 =3D check_nanbox_h(env, rs2); + return nanbox_h(env, env->priv_ver < PRIV_VERSION_1_11_0 ? float16_minnum(frs1, frs2, &env->fp_status) : float16_minimum_number(frs1, frs2, &env->fp_status)); } =20 uint64_t helper_fmax_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { - float16 frs1 =3D check_nanbox_h(rs1); - float16 frs2 =3D check_nanbox_h(rs2); - return nanbox_h(env->priv_ver < PRIV_VERSION_1_11_0 ? + float16 frs1 =3D check_nanbox_h(env, rs1); + float16 frs2 =3D check_nanbox_h(env, rs2); + return nanbox_h(env, env->priv_ver < PRIV_VERSION_1_11_0 ? float16_maxnum(frs1, frs2, &env->fp_status) : float16_maximum_number(frs1, frs2, &env->fp_status)); } =20 uint64_t helper_fsqrt_h(CPURISCVState *env, uint64_t rs1) { - float16 frs1 =3D check_nanbox_h(rs1); - return nanbox_h(float16_sqrt(frs1, &env->fp_status)); + float16 frs1 =3D check_nanbox_h(env, rs1); + return nanbox_h(env, float16_sqrt(frs1, &env->fp_status)); } =20 target_ulong helper_fle_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { - float16 frs1 =3D check_nanbox_h(rs1); - float16 frs2 =3D check_nanbox_h(rs2); + float16 frs1 =3D check_nanbox_h(env, rs1); + float16 frs2 =3D check_nanbox_h(env, rs2); return float16_le(frs1, frs2, &env->fp_status); } =20 target_ulong helper_flt_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { - float16 frs1 =3D check_nanbox_h(rs1); - float16 frs2 =3D check_nanbox_h(rs2); + float16 frs1 =3D check_nanbox_h(env, rs1); + float16 frs2 =3D check_nanbox_h(env, rs2); return float16_lt(frs1, frs2, &env->fp_status); } =20 target_ulong helper_feq_h(CPURISCVState *env, uint64_t rs1, uint64_t rs2) { - float16 frs1 =3D check_nanbox_h(rs1); - float16 frs2 =3D check_nanbox_h(rs2); + float16 frs1 =3D check_nanbox_h(env, rs1); + float16 frs2 =3D check_nanbox_h(env, rs2); return float16_eq_quiet(frs1, frs2, &env->fp_status); } =20 -target_ulong helper_fclass_h(uint64_t rs1) +target_ulong helper_fclass_h(CPURISCVState *env, uint64_t rs1) { - float16 frs1 =3D check_nanbox_h(rs1); + float16 frs1 =3D check_nanbox_h(env, rs1); return fclass_h(frs1); } =20 target_ulong helper_fcvt_w_h(CPURISCVState *env, uint64_t rs1) { - float16 frs1 =3D check_nanbox_h(rs1); + float16 frs1 =3D check_nanbox_h(env, rs1); return float16_to_int32(frs1, &env->fp_status); } =20 target_ulong helper_fcvt_wu_h(CPURISCVState *env, uint64_t rs1) { - float16 frs1 =3D check_nanbox_h(rs1); + float16 frs1 =3D check_nanbox_h(env, rs1); return (int32_t)float16_to_uint32(frs1, &env->fp_status); } =20 target_ulong helper_fcvt_l_h(CPURISCVState *env, uint64_t rs1) { - float16 frs1 =3D check_nanbox_h(rs1); + float16 frs1 =3D check_nanbox_h(env, rs1); return float16_to_int64(frs1, &env->fp_status); } =20 target_ulong helper_fcvt_lu_h(CPURISCVState *env, uint64_t rs1) { - float16 frs1 =3D check_nanbox_h(rs1); + float16 frs1 =3D check_nanbox_h(env, rs1); return float16_to_uint64(frs1, &env->fp_status); } =20 uint64_t helper_fcvt_h_w(CPURISCVState *env, target_ulong rs1) { - return nanbox_h(int32_to_float16((int32_t)rs1, &env->fp_status)); + return nanbox_h(env, int32_to_float16((int32_t)rs1, &env->fp_status)); } =20 uint64_t helper_fcvt_h_wu(CPURISCVState *env, target_ulong rs1) { - return nanbox_h(uint32_to_float16((uint32_t)rs1, &env->fp_status)); + return nanbox_h(env, uint32_to_float16((uint32_t)rs1, &env->fp_status)= ); } =20 uint64_t helper_fcvt_h_l(CPURISCVState *env, target_ulong rs1) { - return nanbox_h(int64_to_float16(rs1, &env->fp_status)); + return nanbox_h(env, int64_to_float16(rs1, &env->fp_status)); } =20 uint64_t helper_fcvt_h_lu(CPURISCVState *env, target_ulong rs1) { - return nanbox_h(uint64_to_float16(rs1, &env->fp_status)); + return nanbox_h(env, uint64_to_float16(rs1, &env->fp_status)); } =20 uint64_t helper_fcvt_h_s(CPURISCVState *env, uint64_t rs1) { float32 frs1 =3D check_nanbox_s(env, rs1); - return nanbox_h(float32_to_float16(frs1, true, &env->fp_status)); + return nanbox_h(env, float32_to_float16(frs1, true, &env->fp_status)); } =20 uint64_t helper_fcvt_s_h(CPURISCVState *env, uint64_t rs1) { - float16 frs1 =3D check_nanbox_h(rs1); + float16 frs1 =3D check_nanbox_h(env, rs1); return nanbox_s(env, float16_to_float32(frs1, true, &env->fp_status)); } =20 uint64_t helper_fcvt_h_d(CPURISCVState *env, uint64_t rs1) { - return nanbox_h(float64_to_float16(rs1, true, &env->fp_status)); + return nanbox_h(env, float64_to_float16(rs1, true, &env->fp_status)); } =20 uint64_t helper_fcvt_d_h(CPURISCVState *env, uint64_t rs1) { - float16 frs1 =3D check_nanbox_h(rs1); + float16 frs1 =3D check_nanbox_h(env, rs1); return float16_to_float64(frs1, true, &env->fp_status); } diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_= trans/trans_rvzfh.c.inc index 608c51da2c..5d07150cd0 100644 --- a/target/riscv/insn_trans/trans_rvzfh.c.inc +++ b/target/riscv/insn_trans/trans_rvzfh.c.inc @@ -22,12 +22,25 @@ } \ } while (0) =20 +#define REQUIRE_ZHINX_OR_ZFH(ctx) do { \ + if (!ctx->cfg_ptr->ext_zhinx && !ctx->cfg_ptr->ext_zfh) { \ + return false; \ + } \ +} while (0) + #define REQUIRE_ZFH_OR_ZFHMIN(ctx) do { \ if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin)) { \ return false; \ } \ } while (0) =20 +#define REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx) do { \ + if (!(ctx->cfg_ptr->ext_zfh || ctx->cfg_ptr->ext_zfhmin || \ + ctx->cfg_ptr->ext_zhinx || ctx->cfg_ptr->ext_zhinxmin)) { \ + return false; \ + } \ +} while (0) + static bool trans_flh(DisasContext *ctx, arg_flh *a) { TCGv_i64 dest; @@ -73,11 +86,16 @@ static bool trans_fsh(DisasContext *ctx, arg_fsh *a) static bool trans_fmadd_h(DisasContext *ctx, arg_fmadd_h *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZHINX_OR_ZFH(ctx); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); + TCGv_i64 src3 =3D get_fpr_hs(ctx, a->rs3); =20 gen_set_rm(ctx, a->rm); - gen_helper_fmadd_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + gen_helper_fmadd_h(dest, cpu_env, src1, src2, src3); + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -85,11 +103,16 @@ static bool trans_fmadd_h(DisasContext *ctx, arg_fmadd= _h *a) static bool trans_fmsub_h(DisasContext *ctx, arg_fmsub_h *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZHINX_OR_ZFH(ctx); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); + TCGv_i64 src3 =3D get_fpr_hs(ctx, a->rs3); =20 gen_set_rm(ctx, a->rm); - gen_helper_fmsub_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + gen_helper_fmsub_h(dest, cpu_env, src1, src2, src3); + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -97,11 +120,16 @@ static bool trans_fmsub_h(DisasContext *ctx, arg_fmsub= _h *a) static bool trans_fnmsub_h(DisasContext *ctx, arg_fnmsub_h *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZHINX_OR_ZFH(ctx); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); + TCGv_i64 src3 =3D get_fpr_hs(ctx, a->rs3); =20 gen_set_rm(ctx, a->rm); - gen_helper_fnmsub_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + gen_helper_fnmsub_h(dest, cpu_env, src1, src2, src3); + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -109,11 +137,16 @@ static bool trans_fnmsub_h(DisasContext *ctx, arg_fnm= sub_h *a) static bool trans_fnmadd_h(DisasContext *ctx, arg_fnmadd_h *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZHINX_OR_ZFH(ctx); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); + TCGv_i64 src3 =3D get_fpr_hs(ctx, a->rs3); =20 gen_set_rm(ctx, a->rm); - gen_helper_fnmadd_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2], cpu_fpr[a->rs3]); + gen_helper_fnmadd_h(dest, cpu_env, src1, src2, src3); + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -121,11 +154,15 @@ static bool trans_fnmadd_h(DisasContext *ctx, arg_fnm= add_h *a) static bool trans_fadd_h(DisasContext *ctx, arg_fadd_h *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZHINX_OR_ZFH(ctx); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fadd_h(cpu_fpr[a->rd], cpu_env, - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_helper_fadd_h(dest, cpu_env, src1, src2); + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -133,11 +170,15 @@ static bool trans_fadd_h(DisasContext *ctx, arg_fadd_= h *a) static bool trans_fsub_h(DisasContext *ctx, arg_fsub_h *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZHINX_OR_ZFH(ctx); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fsub_h(cpu_fpr[a->rd], cpu_env, - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_helper_fsub_h(dest, cpu_env, src1, src2); + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -145,11 +186,15 @@ static bool trans_fsub_h(DisasContext *ctx, arg_fsub_= h *a) static bool trans_fmul_h(DisasContext *ctx, arg_fmul_h *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZHINX_OR_ZFH(ctx); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fmul_h(cpu_fpr[a->rd], cpu_env, - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_helper_fmul_h(dest, cpu_env, src1, src2); + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -157,11 +202,15 @@ static bool trans_fmul_h(DisasContext *ctx, arg_fmul_= h *a) static bool trans_fdiv_h(DisasContext *ctx, arg_fdiv_h *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZHINX_OR_ZFH(ctx); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 gen_set_rm(ctx, a->rm); - gen_helper_fdiv_h(cpu_fpr[a->rd], cpu_env, - cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_helper_fdiv_h(dest, cpu_env, src1, src2); + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -169,10 +218,14 @@ static bool trans_fdiv_h(DisasContext *ctx, arg_fdiv_= h *a) static bool trans_fsqrt_h(DisasContext *ctx, arg_fsqrt_h *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZHINX_OR_ZFH(ctx); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fsqrt_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + gen_helper_fsqrt_h(dest, cpu_env, src1); + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -180,23 +233,37 @@ static bool trans_fsqrt_h(DisasContext *ctx, arg_fsqr= t_h *a) static bool trans_fsgnj_h(DisasContext *ctx, arg_fsgnj_h *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZHINX_OR_ZFH(ctx); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 if (a->rs1 =3D=3D a->rs2) { /* FMOV */ - gen_check_nanbox_h(cpu_fpr[a->rd], cpu_fpr[a->rs1]); + if (!ctx->cfg_ptr->ext_zfinx) { + gen_check_nanbox_h(dest, src1); + } else { + tcg_gen_ext16s_i64(dest, src1); + } } else { - TCGv_i64 rs1 =3D tcg_temp_new_i64(); - TCGv_i64 rs2 =3D tcg_temp_new_i64(); - - gen_check_nanbox_h(rs1, cpu_fpr[a->rs1]); - gen_check_nanbox_h(rs2, cpu_fpr[a->rs2]); - - /* This formulation retains the nanboxing of rs2. */ - tcg_gen_deposit_i64(cpu_fpr[a->rd], rs2, rs1, 0, 15); - tcg_temp_free_i64(rs1); - tcg_temp_free_i64(rs2); + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); + + if (!ctx->cfg_ptr->ext_zfinx) { + TCGv_i64 rs1 =3D tcg_temp_new_i64(); + TCGv_i64 rs2 =3D tcg_temp_new_i64(); + gen_check_nanbox_h(rs1, src1); + gen_check_nanbox_h(rs2, src2); + + /* This formulation retains the nanboxing of rs2 in normal 'Zf= h'. */ + tcg_gen_deposit_i64(dest, rs2, rs1, 0, 15); + + tcg_temp_free_i64(rs1); + tcg_temp_free_i64(rs2); + } else { + tcg_gen_deposit_i64(dest, src2, src1, 0, 15); + tcg_gen_ext16s_i64(dest, dest); + } } - + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -206,16 +273,29 @@ static bool trans_fsgnjn_h(DisasContext *ctx, arg_fsg= njn_h *a) TCGv_i64 rs1, rs2, mask; =20 REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZHINX_OR_ZFH(ctx); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 rs1 =3D tcg_temp_new_i64(); - gen_check_nanbox_h(rs1, cpu_fpr[a->rs1]); + if (!ctx->cfg_ptr->ext_zfinx) { + gen_check_nanbox_h(rs1, src1); + } else { + tcg_gen_mov_i64(rs1, src1); + } =20 if (a->rs1 =3D=3D a->rs2) { /* FNEG */ - tcg_gen_xori_i64(cpu_fpr[a->rd], rs1, MAKE_64BIT_MASK(15, 1)); + tcg_gen_xori_i64(dest, rs1, MAKE_64BIT_MASK(15, 1)); } else { + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); rs2 =3D tcg_temp_new_i64(); - gen_check_nanbox_h(rs2, cpu_fpr[a->rs2]); + + if (!ctx->cfg_ptr->ext_zfinx) { + gen_check_nanbox_h(rs2, src2); + } else { + tcg_gen_mov_i64(rs2, src2); + } =20 /* * Replace bit 15 in rs1 with inverse in rs2. @@ -224,12 +304,17 @@ static bool trans_fsgnjn_h(DisasContext *ctx, arg_fsg= njn_h *a) mask =3D tcg_const_i64(~MAKE_64BIT_MASK(15, 1)); tcg_gen_not_i64(rs2, rs2); tcg_gen_andc_i64(rs2, rs2, mask); - tcg_gen_and_i64(rs1, mask, rs1); - tcg_gen_or_i64(cpu_fpr[a->rd], rs1, rs2); + tcg_gen_and_i64(dest, mask, rs1); + tcg_gen_or_i64(dest, dest, rs2); =20 tcg_temp_free_i64(mask); tcg_temp_free_i64(rs2); } + /* signed-extended intead of nanboxing for result if enable zfinx */ + if (ctx->cfg_ptr->ext_zfinx) { + tcg_gen_ext16s_i64(dest, dest); + } + tcg_temp_free_i64(rs1); mark_fs_dirty(ctx); return true; } @@ -239,27 +324,44 @@ static bool trans_fsgnjx_h(DisasContext *ctx, arg_fsg= njx_h *a) TCGv_i64 rs1, rs2; =20 REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZHINX_OR_ZFH(ctx); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 rs1 =3D tcg_temp_new_i64(); - gen_check_nanbox_s(rs1, cpu_fpr[a->rs1]); + if (!ctx->cfg_ptr->ext_zfinx) { + gen_check_nanbox_h(rs1, src1); + } else { + tcg_gen_mov_i64(rs1, src1); + } =20 if (a->rs1 =3D=3D a->rs2) { /* FABS */ - tcg_gen_andi_i64(cpu_fpr[a->rd], rs1, ~MAKE_64BIT_MASK(15, 1)); + tcg_gen_andi_i64(dest, rs1, ~MAKE_64BIT_MASK(15, 1)); } else { + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); rs2 =3D tcg_temp_new_i64(); - gen_check_nanbox_s(rs2, cpu_fpr[a->rs2]); + + if (!ctx->cfg_ptr->ext_zfinx) { + gen_check_nanbox_h(rs2, src2); + } else { + tcg_gen_mov_i64(rs2, src2); + } =20 /* * Xor bit 15 in rs1 with that in rs2. * This formulation retains the nanboxing of rs1. */ - tcg_gen_andi_i64(rs2, rs2, MAKE_64BIT_MASK(15, 1)); - tcg_gen_xor_i64(cpu_fpr[a->rd], rs1, rs2); + tcg_gen_andi_i64(dest, rs2, MAKE_64BIT_MASK(15, 1)); + tcg_gen_xor_i64(dest, rs1, dest); =20 tcg_temp_free_i64(rs2); } - + /* signed-extended intead of nanboxing for result if enable zfinx */ + if (ctx->cfg_ptr->ext_zfinx) { + tcg_gen_ext16s_i64(dest, dest); + } + tcg_temp_free_i64(rs1); mark_fs_dirty(ctx); return true; } @@ -267,10 +369,14 @@ static bool trans_fsgnjx_h(DisasContext *ctx, arg_fsg= njx_h *a) static bool trans_fmin_h(DisasContext *ctx, arg_fmin_h *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZHINX_OR_ZFH(ctx); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 - gen_helper_fmin_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2]); + gen_helper_fmin_h(dest, cpu_env, src1, src2); + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -278,10 +384,14 @@ static bool trans_fmin_h(DisasContext *ctx, arg_fmin_= h *a) static bool trans_fmax_h(DisasContext *ctx, arg_fmax_h *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZHINX_OR_ZFH(ctx); =20 - gen_helper_fmax_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1], - cpu_fpr[a->rs2]); + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); + + gen_helper_fmax_h(dest, cpu_env, src1, src2); + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); return true; } @@ -289,10 +399,14 @@ static bool trans_fmax_h(DisasContext *ctx, arg_fmax_= h *a) static bool trans_fcvt_s_h(DisasContext *ctx, arg_fcvt_s_h *a) { REQUIRE_FPU; - REQUIRE_ZFH_OR_ZFHMIN(ctx); + REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_s_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + gen_helper_fcvt_s_h(dest, cpu_env, src1); + gen_set_fpr_hs(ctx, a->rd, dest); =20 mark_fs_dirty(ctx); =20 @@ -302,26 +416,32 @@ static bool trans_fcvt_s_h(DisasContext *ctx, arg_fcv= t_s_h *a) static bool trans_fcvt_d_h(DisasContext *ctx, arg_fcvt_d_h *a) { REQUIRE_FPU; - REQUIRE_ZFH_OR_ZFHMIN(ctx); - REQUIRE_EXT(ctx, RVD); + REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx); + REQUIRE_ZDINX_OR_D(ctx); + + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_d_h(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + gen_helper_fcvt_d_h(dest, cpu_env, src1); + gen_set_fpr_d(ctx, a->rd, dest); =20 mark_fs_dirty(ctx); =20 - return true; } =20 static bool trans_fcvt_h_s(DisasContext *ctx, arg_fcvt_h_s *a) { REQUIRE_FPU; - REQUIRE_ZFH_OR_ZFHMIN(ctx); + REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx); =20 - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_h_s(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_h_s(dest, cpu_env, src1); + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); =20 return true; @@ -330,12 +450,15 @@ static bool trans_fcvt_h_s(DisasContext *ctx, arg_fcv= t_h_s *a) static bool trans_fcvt_h_d(DisasContext *ctx, arg_fcvt_h_d *a) { REQUIRE_FPU; - REQUIRE_ZFH_OR_ZFHMIN(ctx); - REQUIRE_EXT(ctx, RVD); + REQUIRE_ZFH_OR_ZFHMIN_OR_ZHINX_OR_ZHINXMIN(ctx); + REQUIRE_ZDINX_OR_D(ctx); =20 - gen_set_rm(ctx, a->rm); - gen_helper_fcvt_h_d(cpu_fpr[a->rd], cpu_env, cpu_fpr[a->rs1]); + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_d(ctx, a->rs1); =20 + gen_set_rm(ctx, a->rm); + gen_helper_fcvt_h_d(dest, cpu_env, src1); + gen_set_fpr_hs(ctx, a->rd, dest); mark_fs_dirty(ctx); =20 return true; @@ -344,11 +467,13 @@ static bool trans_fcvt_h_d(DisasContext *ctx, arg_fcv= t_h_d *a) static bool trans_feq_h(DisasContext *ctx, arg_feq_h *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZHINX_OR_ZFH(ctx); =20 TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 - gen_helper_feq_h(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_helper_feq_h(dest, cpu_env, src1, src2); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -356,11 +481,13 @@ static bool trans_feq_h(DisasContext *ctx, arg_feq_h = *a) static bool trans_flt_h(DisasContext *ctx, arg_flt_h *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZHINX_OR_ZFH(ctx); =20 TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 - gen_helper_flt_h(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_helper_flt_h(dest, cpu_env, src1, src2); gen_set_gpr(ctx, a->rd, dest); =20 return true; @@ -369,11 +496,13 @@ static bool trans_flt_h(DisasContext *ctx, arg_flt_h = *a) static bool trans_fle_h(DisasContext *ctx, arg_fle_h *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZHINX_OR_ZFH(ctx); =20 TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); + TCGv_i64 src2 =3D get_fpr_hs(ctx, a->rs2); =20 - gen_helper_fle_h(dest, cpu_env, cpu_fpr[a->rs1], cpu_fpr[a->rs2]); + gen_helper_fle_h(dest, cpu_env, src1, src2); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -381,11 +510,12 @@ static bool trans_fle_h(DisasContext *ctx, arg_fle_h = *a) static bool trans_fclass_h(DisasContext *ctx, arg_fclass_h *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZHINX_OR_ZFH(ctx); =20 TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 - gen_helper_fclass_h(dest, cpu_fpr[a->rs1]); + gen_helper_fclass_h(dest, cpu_env, src1); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -393,12 +523,13 @@ static bool trans_fclass_h(DisasContext *ctx, arg_fcl= ass_h *a) static bool trans_fcvt_w_h(DisasContext *ctx, arg_fcvt_w_h *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZHINX_OR_ZFH(ctx); =20 TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_w_h(dest, cpu_env, cpu_fpr[a->rs1]); + gen_helper_fcvt_w_h(dest, cpu_env, src1); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -406,12 +537,13 @@ static bool trans_fcvt_w_h(DisasContext *ctx, arg_fcv= t_w_h *a) static bool trans_fcvt_wu_h(DisasContext *ctx, arg_fcvt_wu_h *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZHINX_OR_ZFH(ctx); =20 TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_wu_h(dest, cpu_env, cpu_fpr[a->rs1]); + gen_helper_fcvt_wu_h(dest, cpu_env, src1); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -419,12 +551,14 @@ static bool trans_fcvt_wu_h(DisasContext *ctx, arg_fc= vt_wu_h *a) static bool trans_fcvt_h_w(DisasContext *ctx, arg_fcvt_h_w *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZHINX_OR_ZFH(ctx); =20 + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); TCGv t0 =3D get_gpr(ctx, a->rs1, EXT_SIGN); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_h_w(cpu_fpr[a->rd], cpu_env, t0); + gen_helper_fcvt_h_w(dest, cpu_env, t0); + gen_set_fpr_hs(ctx, a->rd, dest); =20 mark_fs_dirty(ctx); return true; @@ -433,12 +567,14 @@ static bool trans_fcvt_h_w(DisasContext *ctx, arg_fcv= t_h_w *a) static bool trans_fcvt_h_wu(DisasContext *ctx, arg_fcvt_h_wu *a) { REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZHINX_OR_ZFH(ctx); =20 + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); TCGv t0 =3D get_gpr(ctx, a->rs1, EXT_SIGN); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_h_wu(cpu_fpr[a->rd], cpu_env, t0); + gen_helper_fcvt_h_wu(dest, cpu_env, t0); + gen_set_fpr_hs(ctx, a->rd, dest); =20 mark_fs_dirty(ctx); return true; @@ -482,12 +618,13 @@ static bool trans_fcvt_l_h(DisasContext *ctx, arg_fcv= t_l_h *a) { REQUIRE_64BIT(ctx); REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZHINX_OR_ZFH(ctx); =20 TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_l_h(dest, cpu_env, cpu_fpr[a->rs1]); + gen_helper_fcvt_l_h(dest, cpu_env, src1); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -496,12 +633,13 @@ static bool trans_fcvt_lu_h(DisasContext *ctx, arg_fc= vt_lu_h *a) { REQUIRE_64BIT(ctx); REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZHINX_OR_ZFH(ctx); =20 TCGv dest =3D dest_gpr(ctx, a->rd); + TCGv_i64 src1 =3D get_fpr_hs(ctx, a->rs1); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_lu_h(dest, cpu_env, cpu_fpr[a->rs1]); + gen_helper_fcvt_lu_h(dest, cpu_env, src1); gen_set_gpr(ctx, a->rd, dest); return true; } @@ -510,12 +648,14 @@ static bool trans_fcvt_h_l(DisasContext *ctx, arg_fcv= t_h_l *a) { REQUIRE_64BIT(ctx); REQUIRE_FPU; - REQUIRE_ZFH(ctx); + REQUIRE_ZHINX_OR_ZFH(ctx); =20 + TCGv_i64 dest =3D dest_fpr(ctx, a->rd); TCGv t0 =3D get_gpr(ctx, a->rs1, EXT_SIGN); =20 gen_set_rm(ctx, a->rm); - gen_helper_fcvt_h_l(cpu_fpr[a->rd], cpu_env, t0); + gen_helper_fcvt_h_l(dest, cpu_env, t0); + gen_set_fpr_hs(ctx, a->rd, dest); =20 mark_fs_dirty(ctx); return true; @@ -525,12 +665,14 @@ static bool trans_fcvt_h_lu(DisasContext *ctx, arg_fc= vt_h_lu *a) { REQUIRE_64BIT(ctx); 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s=dkim; t=1646285363; x=1648877364; bh=6EoaoUI0VWVi9h01XL Thoe0gu1dQk9RbAjEAt92Xfig=; b=YxVY22jvI5/6ZbF1Sp2mH0TqfmUzuB/VbF 2nPx2n+KvZFfVKb8f6XJslktId59j8pMVfXOO8YNjRok4SwLvW5pT9Zj5vDLoji+ e+/bijAWmkdHopd+QLCI8kFiVVcMi+d+dibtl3jpYIZymMMbNx7kH4T0fZfgy0nO oaGYOxpYtXdE0OTWVUATFykNHoHwpNiDv5RsPBkvaSLrzCdcBBbLgNcsjRwOGJTa Ql4kabjj49fOiCLECOQ/0QxPJsDhkc/Cyv0PuWauwdaQJd4186beZ0jTM3OfnmZ1 JcKOKIJMRs68dxTjo5in2YxTiTdptlF8blyCecoDAJf0vjDD42Ag== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Weiwei Li , ardxwe , Junqiang Wang , Richard Henderson , Alistair Francis Subject: [PULL 13/13] target/riscv: expose zfinx, zdinx, zhinx{min} properties Date: Thu, 3 Mar 2022 15:28:04 +1000 Message-Id: <20220303052804.529967-14-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220303052804.529967-1-alistair.francis@opensource.wdc.com> References: <20220303052804.529967-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=05403f1d5=alistair.francis@opensource.wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1646285983894100002 Content-Type: text/plain; charset="utf-8" From: Weiwei Li Co-authored-by: ardxwe Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis Message-Id: <20220211043920.28981-7-liweiwei@iscas.ac.cn> Signed-off-by: Alistair Francis --- target/riscv/cpu.c | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 55371b1aa5..ddda4906ff 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -795,6 +795,11 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("zbc", RISCVCPU, cfg.ext_zbc, true), DEFINE_PROP_BOOL("zbs", RISCVCPU, cfg.ext_zbs, true), =20 + DEFINE_PROP_BOOL("zdinx", RISCVCPU, cfg.ext_zdinx, false), + DEFINE_PROP_BOOL("zfinx", RISCVCPU, cfg.ext_zfinx, false), + DEFINE_PROP_BOOL("zhinx", RISCVCPU, cfg.ext_zhinx, false), + DEFINE_PROP_BOOL("zhinxmin", RISCVCPU, cfg.ext_zhinxmin, false), + /* Vendor-specific custom extensions */ DEFINE_PROP_BOOL("xventanacondops", RISCVCPU, cfg.ext_XVentanaCondOps,= false), =20 --=20 2.35.1