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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id x13-20020adfec0d000000b001e31279cc38sm90801wrn.11.2022.03.02.12.52.48 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Mar 2022 12:52:48 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=i7la0k2eorJda0aIicEx+aLSW513Xo/ZYfhT/cVR5VI=; b=aO7EcNo1yNZb5ngWn+Fxlogzknw88bfn8E7A9sK7f4qmGt0aJNv6T6TPeATt8VVFqX wLuLSvvtpMC7er6lL0/RP7q5d1K7MVX+o6KiG8nP5ObuueM9dIjFJKe93dXYqr9I1x4l eI0THJLqy7SoVM9Hfwutm1zHKdE7RDRYCX7rXPor6qhxv0/VsPxKOksUzAomNAdkdZsb z4R95V2PthnVOp+w5zxUqQ9boPhhHR1XdpTolb8+2Nr+BmgENlS9/GyXMcHNCmN0DEuq KHVMh/hnpspRge83alZbR5n5wH4D//nv/oo3Sm4c/5VbYqzrSp8A6wlKaCGXrl014URv BOSg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=i7la0k2eorJda0aIicEx+aLSW513Xo/ZYfhT/cVR5VI=; b=Jh32GMDpQLbcAouKTCbb9ND9sIAZ6HyOtdUinDtIHB0GEHNPd4wDqOgKf6Sz193kyG ytZ0O21SzlfaTT1Qah8QxXUPoTgYqBc/52kzfGOH+EtxXgJi86hFevjuMhRbM6EJ27Nt cDvIIO3S+jaYk/YtUOV7Fu2BePDbMvIWyoY+Xt7ruQJTFlaTim8NeKqo1Y50AQnXWLtT FyjmLJ1vz2xRjAtEFpnlfntHaBnbgh307G9K4q92Ogq1bIeNJuzOLSy4Omy4oDTRIZbN t3vYn7Q00wpk33KzPQbVXR1Ku4TqV7KkuNZ6Q98STotdlbOmh+tZKNWT3M2YRvCl/qxc NwZQ== X-Gm-Message-State: AOAM530auuX/80TcCwPA13GuHTxt6VQ9YYHdsgv7sGU4xtCzgiwqpP7n COIEX4t8Yx7w/cAxY1Nc+M0KNSdtksiOWw== X-Google-Smtp-Source: ABdhPJwhTPM0OcEX6wZ5Xdx1p9sd9dqnS1UvNKUkdA0sx/K5SBXueqN5inWwVM3WV/j2MHfW8jqzlQ== X-Received: by 2002:adf:816c:0:b0:1e6:88a9:eb6c with SMTP id 99-20020adf816c000000b001e688a9eb6cmr23915795wrm.645.1646254369435; Wed, 02 Mar 2022 12:52:49 -0800 (PST) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/26] target/arm: Introduce tlbi_aa64_get_range Date: Wed, 2 Mar 2022 20:52:23 +0000 Message-Id: <20220302205230.2122390-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220302205230.2122390-1-peter.maydell@linaro.org> References: <20220302205230.2122390-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::432 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -6 X-Spam_score: -0.7 X-Spam_bar: / X-Spam_report: (-0.7 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1646255231929100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Merge tlbi_aa64_range_get_length and tlbi_aa64_range_get_base, returning a structure containing both results. Pass in the ARMMMUIdx, rather than the digested two_ranges boolean. This is in preparation for FEAT_LPA2, where the interpretation of 'value' depends on the effective value of DS for the regime. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220301215958.157011-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 58 +++++++++++++++++++-------------------------- 1 file changed, 24 insertions(+), 34 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 950f56599e2..31c2a716f2a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -4511,70 +4511,60 @@ static void tlbi_aa64_vae3is_write(CPUARMState *env= , const ARMCPRegInfo *ri, } =20 #ifdef TARGET_AARCH64 -static uint64_t tlbi_aa64_range_get_length(CPUARMState *env, - uint64_t value) -{ - unsigned int page_shift; - unsigned int page_size_granule; - uint64_t num; - uint64_t scale; - uint64_t exponent; +typedef struct { + uint64_t base; uint64_t length; +} TLBIRange; + +static TLBIRange tlbi_aa64_get_range(CPUARMState *env, ARMMMUIdx mmuidx, + uint64_t value) +{ + unsigned int page_size_granule, page_shift, num, scale, exponent; + TLBIRange ret =3D { }; =20 - num =3D extract64(value, 39, 5); - scale =3D extract64(value, 44, 2); page_size_granule =3D extract64(value, 46, 2); =20 if (page_size_granule =3D=3D 0) { qemu_log_mask(LOG_GUEST_ERROR, "Invalid page size granule %d\n", page_size_granule); - return 0; + return ret; } =20 page_shift =3D (page_size_granule - 1) * 2 + 12; - + num =3D extract64(value, 39, 5); + scale =3D extract64(value, 44, 2); exponent =3D (5 * scale) + 1; - length =3D (num + 1) << (exponent + page_shift); =20 - return length; -} + ret.length =3D (num + 1) << (exponent + page_shift); =20 -static uint64_t tlbi_aa64_range_get_base(CPUARMState *env, uint64_t value, - bool two_ranges) -{ - /* TODO: ARMv8.7 FEAT_LPA2 */ - uint64_t pageaddr; - - if (two_ranges) { - pageaddr =3D sextract64(value, 0, 37) << TARGET_PAGE_BITS; + if (regime_has_2_ranges(mmuidx)) { + ret.base =3D sextract64(value, 0, 37) << TARGET_PAGE_BITS; } else { - pageaddr =3D extract64(value, 0, 37) << TARGET_PAGE_BITS; + ret.base =3D extract64(value, 0, 37) << TARGET_PAGE_BITS; } =20 - return pageaddr; + return ret; } =20 static void do_rvae_write(CPUARMState *env, uint64_t value, int idxmap, bool synced) { ARMMMUIdx one_idx =3D ARM_MMU_IDX_A | ctz32(idxmap); - bool two_ranges =3D regime_has_2_ranges(one_idx); - uint64_t baseaddr, length; + TLBIRange range; int bits; =20 - baseaddr =3D tlbi_aa64_range_get_base(env, value, two_ranges); - length =3D tlbi_aa64_range_get_length(env, value); - bits =3D tlbbits_for_regime(env, one_idx, baseaddr); + range =3D tlbi_aa64_get_range(env, one_idx, value); + bits =3D tlbbits_for_regime(env, one_idx, range.base); =20 if (synced) { tlb_flush_range_by_mmuidx_all_cpus_synced(env_cpu(env), - baseaddr, - length, + range.base, + range.length, idxmap, bits); } else { - tlb_flush_range_by_mmuidx(env_cpu(env), baseaddr, - length, idxmap, bits); + tlb_flush_range_by_mmuidx(env_cpu(env), range.base, + range.length, idxmap, bits); } } =20 --=20 2.25.1