From nobody Thu May 16 15:51:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646036147285967.3272472213689; Mon, 28 Feb 2022 00:15:47 -0800 (PST) Received: from localhost ([::1]:46302 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nObC6-0003Cb-5c for importer@patchew.org; Mon, 28 Feb 2022 03:15:46 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60442) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nOb27-0008IP-8U for qemu-devel@nongnu.org; Mon, 28 Feb 2022 03:05:32 -0500 Received: from mga14.intel.com ([192.55.52.115]:50056) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nOb23-0005ZR-TR for qemu-devel@nongnu.org; Mon, 28 Feb 2022 03:05:25 -0500 Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2022 00:05:16 -0800 Received: from 984fee00bf64.jf.intel.com ([10.165.54.77]) by fmsmga006.fm.intel.com with ESMTP; 28 Feb 2022 00:05:16 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646035523; x=1677571523; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=woOXInjx7C9bpUjllseY5xkUSYyCoviromYNYlMJyOU=; b=YGOtfpewC3UB4xURdnYp4AL+pnQw+sdpIOV+1W3Vi+8Bd5i6yJ9vuIh0 SjQqKpkWhP5EkT1pxqFsMUr4qHS6ast0u2Np2ZCoEuPqW+Ejxk5Fk9G2b ScRPeY25BC28BpRw8nNaH52uMWNyl87UGJrliYkctn+a5RxA5eiTLximt QAahtZA0X4nZnv75VY2lFD1x9JoK9oi6v1/NU7gC7aIN+6TaUeoRbaCj1 RZPkGMT29LsyHQvY33NA0JZDI7zQimYWfwzQIO1CC9cgPxJXH3k2M72mz hvrx2dvuMFeJbvdVQiVo1b8svkInVtIvljpVCmDGwpTF2X0igyjDIfj3f Q==; X-IronPort-AV: E=McAfee;i="6200,9189,10271"; a="253021629" X-IronPort-AV: E=Sophos;i="5.90,142,1643702400"; d="scan'208";a="253021629" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,142,1643702400"; d="scan'208";a="778014574" From: Yang Zhong To: qemu-devel@nongnu.org Subject: [PATCH v3 1/8] x86: Fix the 64-byte boundary enumeration for extended state Date: Mon, 28 Feb 2022 00:05:08 -0800 Message-Id: <20220228080515.42357-2-yang.zhong@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220228080515.42357-1-yang.zhong@intel.com> References: <20220228080515.42357-1-yang.zhong@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.115; envelope-from=yang.zhong@intel.com; helo=mga14.intel.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: yang.zhong@intel.com, kevin.tian@intel.com, seanjc@google.com, jing2.liu@linux.intel.com, wei.w.wang@intel.com, guang.zeng@intel.com, pbonzini@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646036148999100001 Content-Type: text/plain; charset="utf-8" From: Jing Liu The extended state subleaves (EAX=3D0Dh, ECX=3Dn, n>1).ECX[1] indicate whether the extended state component locates on the next 64-byte boundary following the preceding state component when the compacted format of an XSAVE area is used. Right now, they are all zero because no supported component needed the bit to be set, but the upcoming AMX feature will use it. Fix the subleaves value according to KVM's supported cpuid. Signed-off-by: Jing Liu Signed-off-by: Yang Zhong Reviewed-by: David Edmondson --- target/i386/cpu.h | 6 ++++++ target/i386/cpu.c | 1 + target/i386/kvm/kvm-cpu.c | 1 + 3 files changed, 8 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index e69ab5dd78..7bd9d58505 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -550,6 +550,11 @@ typedef enum X86Seg { #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) =20 +#define ESA_FEATURE_ALIGN64_BIT 1 + +#define ESA_FEATURE_ALIGN64_MASK (1U << ESA_FEATURE_ALIGN64_BIT) + + /* CPUID feature words */ typedef enum FeatureWord { FEAT_1_EDX, /* CPUID[1].EDX */ @@ -1356,6 +1361,7 @@ QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) !=3D 0x8); typedef struct ExtSaveArea { uint32_t feature, bits; uint32_t offset, size; + uint32_t ecx; } ExtSaveArea; =20 #define XSAVE_STATE_AREA_COUNT (XSTATE_PKRU_BIT + 1) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 6c7ef1099b..0f3c477dfc 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5488,6 +5488,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, const ExtSaveArea *esa =3D &x86_ext_save_areas[count]; *eax =3D esa->size; *ebx =3D esa->offset; + *ecx =3D esa->ecx & ESA_FEATURE_ALIGN64_MASK; } } break; diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c index d95028018e..ce27d3b1df 100644 --- a/target/i386/kvm/kvm-cpu.c +++ b/target/i386/kvm/kvm-cpu.c @@ -104,6 +104,7 @@ static void kvm_cpu_xsave_init(void) if (sz !=3D 0) { assert(esa->size =3D=3D sz); esa->offset =3D kvm_arch_get_supported_cpuid(s, 0xd, i, R_= EBX); + esa->ecx =3D kvm_arch_get_supported_cpuid(s, 0xd, i, R_ECX= ); } } } From nobody Thu May 16 15:51:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164603648210994.49966823029354; Mon, 28 Feb 2022 00:21:22 -0800 (PST) Received: from localhost ([::1]:54566 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nObHU-0000be-Lu for importer@patchew.org; Mon, 28 Feb 2022 03:21:20 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60440) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nOb26-0008IO-Mo for qemu-devel@nongnu.org; Mon, 28 Feb 2022 03:05:32 -0500 Received: from mga14.intel.com ([192.55.52.115]:50059) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nOb22-0005a2-25 for qemu-devel@nongnu.org; Mon, 28 Feb 2022 03:05:25 -0500 Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2022 00:05:16 -0800 Received: from 984fee00bf64.jf.intel.com ([10.165.54.77]) by fmsmga006.fm.intel.com with ESMTP; 28 Feb 2022 00:05:16 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646035522; x=1677571522; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=DTJ+vMaBzHwM/ZCQY9fZMzXsYDGvbaLyZANyo1b35/0=; b=kJjnNpBB69k4d7QMOS6sl/d8qkO5Laxgy7LN1VZHT/q2kO8iJHf62lAM kSvMH1nzwh0XS0tBE37bPZSU9qHryvi52sRhkdYPXFUsYHZXQR6V+Ph0w ZY3auRhDdnAOugosS95ShO4g1QDeqf5w4Pqr+wI3RBdamiZSEtGMJS8rI WYR/Z1WqiZLNrQ9/d8lLqOXo6tYeXd1lIB9un6JDaV8p2FVIbutY0Fw7r hVjqCxP1nrTAVGcyh5AK/9Y/Lso6Gbrkt5FOElTZSTHkOIoj87YLl3zuU vL0mlswLTF+hPeiTo0xwaytVm1sH6rAstykZduaGUUBaoJNKOA0v0FqR+ w==; X-IronPort-AV: E=McAfee;i="6200,9189,10271"; a="253021633" X-IronPort-AV: E=Sophos;i="5.90,142,1643702400"; d="scan'208";a="253021633" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,142,1643702400"; d="scan'208";a="778014577" From: Yang Zhong To: qemu-devel@nongnu.org Subject: [PATCH v3 2/8] x86: Add AMX XTILECFG and XTILEDATA components Date: Mon, 28 Feb 2022 00:05:09 -0800 Message-Id: <20220228080515.42357-3-yang.zhong@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220228080515.42357-1-yang.zhong@intel.com> References: <20220228080515.42357-1-yang.zhong@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.115; envelope-from=yang.zhong@intel.com; helo=mga14.intel.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: yang.zhong@intel.com, kevin.tian@intel.com, seanjc@google.com, jing2.liu@linux.intel.com, wei.w.wang@intel.com, guang.zeng@intel.com, pbonzini@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646036483944100001 Content-Type: text/plain; charset="utf-8" From: Jing Liu The AMX TILECFG register and the TMMx tile data registers are saved/restored via XSAVE, respectively in state component 17 (64 bytes) and state component 18 (8192 bytes). Add AMX feature bits to x86_ext_save_areas array to set up AMX components. Add structs that define the layout of AMX XSAVE areas and use QEMU_BUILD_BUG_ON to validate the structs sizes. Signed-off-by: Jing Liu Signed-off-by: Yang Zhong Reviewed-by: David Edmondson --- target/i386/cpu.h | 18 +++++++++++++++++- target/i386/cpu.c | 8 ++++++++ 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 7bd9d58505..3ff1b49d29 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -539,6 +539,8 @@ typedef enum X86Seg { #define XSTATE_ZMM_Hi256_BIT 6 #define XSTATE_Hi16_ZMM_BIT 7 #define XSTATE_PKRU_BIT 9 +#define XSTATE_XTILE_CFG_BIT 17 +#define XSTATE_XTILE_DATA_BIT 18 =20 #define XSTATE_FP_MASK (1ULL << XSTATE_FP_BIT) #define XSTATE_SSE_MASK (1ULL << XSTATE_SSE_BIT) @@ -847,6 +849,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_0_EDX_TSX_LDTRK (1U << 16) /* AVX512_FP16 instruction */ #define CPUID_7_0_EDX_AVX512_FP16 (1U << 23) +/* AMX tile (two-dimensional register) */ +#define CPUID_7_0_EDX_AMX_TILE (1U << 24) /* Speculation Control */ #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) /* Single Thread Indirect Branch Predictors */ @@ -1350,6 +1354,16 @@ typedef struct XSavePKRU { uint32_t padding; } XSavePKRU; =20 +/* Ext. save area 17: AMX XTILECFG state */ +typedef struct XSaveXTILECFG { + uint8_t xtilecfg[64]; +} XSaveXTILECFG; + +/* Ext. save area 18: AMX XTILEDATA state */ +typedef struct XSaveXTILEDATA { + uint8_t xtiledata[8][1024]; +} XSaveXTILEDATA; + QEMU_BUILD_BUG_ON(sizeof(XSaveAVX) !=3D 0x100); QEMU_BUILD_BUG_ON(sizeof(XSaveBNDREG) !=3D 0x40); QEMU_BUILD_BUG_ON(sizeof(XSaveBNDCSR) !=3D 0x40); @@ -1357,6 +1371,8 @@ QEMU_BUILD_BUG_ON(sizeof(XSaveOpmask) !=3D 0x40); QEMU_BUILD_BUG_ON(sizeof(XSaveZMM_Hi256) !=3D 0x200); QEMU_BUILD_BUG_ON(sizeof(XSaveHi16_ZMM) !=3D 0x400); QEMU_BUILD_BUG_ON(sizeof(XSavePKRU) !=3D 0x8); +QEMU_BUILD_BUG_ON(sizeof(XSaveXTILECFG) !=3D 0x40); +QEMU_BUILD_BUG_ON(sizeof(XSaveXTILEDATA) !=3D 0x2000); =20 typedef struct ExtSaveArea { uint32_t feature, bits; @@ -1364,7 +1380,7 @@ typedef struct ExtSaveArea { uint32_t ecx; } ExtSaveArea; =20 -#define XSAVE_STATE_AREA_COUNT (XSTATE_PKRU_BIT + 1) +#define XSAVE_STATE_AREA_COUNT (XSTATE_XTILE_DATA_BIT + 1) =20 extern ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUNT]; =20 diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 0f3c477dfc..ec35dd1717 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1402,6 +1402,14 @@ ExtSaveArea x86_ext_save_areas[XSAVE_STATE_AREA_COUN= T] =3D { [XSTATE_PKRU_BIT] =3D { .feature =3D FEAT_7_0_ECX, .bits =3D CPUID_7_0_ECX_PKU, .size =3D sizeof(XSavePKRU) }, + [XSTATE_XTILE_CFG_BIT] =3D { + .feature =3D FEAT_7_0_EDX, .bits =3D CPUID_7_0_EDX_AMX_TILE, + .size =3D sizeof(XSaveXTILECFG), + }, + [XSTATE_XTILE_DATA_BIT] =3D { + .feature =3D FEAT_7_0_EDX, .bits =3D CPUID_7_0_EDX_AMX_TILE, + .size =3D sizeof(XSaveXTILEDATA) + }, }; =20 static uint32_t xsave_area_size(uint64_t mask) From nobody Thu May 16 15:51:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646036190192853.6263762382293; Mon, 28 Feb 2022 00:16:30 -0800 (PST) Received: from localhost ([::1]:46682 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nObCm-0003Ty-Mm for importer@patchew.org; Mon, 28 Feb 2022 03:16:28 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60472) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nOb2B-0008IW-0X for qemu-devel@nongnu.org; Mon, 28 Feb 2022 03:05:33 -0500 Received: from mga14.intel.com ([192.55.52.115]:50047) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nOb26-0005Ys-CB for qemu-devel@nongnu.org; Mon, 28 Feb 2022 03:05:28 -0500 Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2022 00:05:17 -0800 Received: from 984fee00bf64.jf.intel.com ([10.165.54.77]) by fmsmga006.fm.intel.com with ESMTP; 28 Feb 2022 00:05:16 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646035526; x=1677571526; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=3OQjh7ARD/M4Uovx3W7j4YOwC+/p7z5IRQZ4IkDQ6QU=; b=Uix21Ek2pXH7N1mQuQjVox4t4RnnkGF7lp36Lia3MjGbmo68O6h4B6cH Nt6u6UTXpj9SwWFQ3eOVqO86CdhNZmm0dPAf1xmfExo/de+4rk4cLhLwv hV0WqGk8BC2HOSA25lbX+jERdOkNC4Pl+3YIdIoifO4AfsPxF7i6UNy4f fMz7n/nSW9o38aMA0r94/k6MnEAxOCMtDZoGMXKTT0L9JHL+uLMQS2wN3 ZCrHCpcAoc97wcxzlPxpyiWPB6pX1AFNW4ZDvvSDFjC6j+I339QdU6B6l 2W478KgS54Uv/qSbL6l/Tz2IwwEJcpfkpNBgHrWyN0bWQhyhlEhSwAShc g==; X-IronPort-AV: E=McAfee;i="6200,9189,10271"; a="253021638" X-IronPort-AV: E=Sophos;i="5.90,142,1643702400"; d="scan'208";a="253021638" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,142,1643702400"; d="scan'208";a="778014581" From: Yang Zhong To: qemu-devel@nongnu.org Subject: [PATCH v3 3/8] x86: Grant AMX permission for guest Date: Mon, 28 Feb 2022 00:05:10 -0800 Message-Id: <20220228080515.42357-4-yang.zhong@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220228080515.42357-1-yang.zhong@intel.com> References: <20220228080515.42357-1-yang.zhong@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.115; envelope-from=yang.zhong@intel.com; helo=mga14.intel.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: yang.zhong@intel.com, kevin.tian@intel.com, seanjc@google.com, jing2.liu@linux.intel.com, wei.w.wang@intel.com, guang.zeng@intel.com, pbonzini@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646036191468100001 Content-Type: text/plain; charset="utf-8" Kernel allocates 4K xstate buffer by default. For XSAVE features which require large state component (e.g. AMX), Linux kernel dynamically expands the xstate buffer only after the process has acquired the necessary permissions. Those are called dynamically- enabled XSAVE features (or dynamic xfeatures). There are separate permissions for native tasks and guests. Qemu should request the guest permissions for dynamic xfeatures which will be exposed to the guest. This only needs to be done once before the first vcpu is created. KVM implemented one new ARCH_GET_XCOMP_SUPP system attribute API to get host side supported_xcr0 and Qemu can decide if it can request dynamically enabled XSAVE features permission. https://lore.kernel.org/all/20220126152210.3044876-1-pbonzini@redhat.com/ Suggested-by: Paolo Bonzini Signed-off-by: Yang Zhong Signed-off-by: Jing Liu --- target/i386/cpu.h | 4 +++ target/i386/kvm/kvm_i386.h | 1 + target/i386/cpu.c | 7 +++++ target/i386/kvm/kvm-cpu.c | 12 ++++---- target/i386/kvm/kvm.c | 57 ++++++++++++++++++++++++++++++++++++++ 5 files changed, 75 insertions(+), 6 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 3ff1b49d29..9630f4712a 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -551,6 +551,10 @@ typedef enum X86Seg { #define XSTATE_ZMM_Hi256_MASK (1ULL << XSTATE_ZMM_Hi256_BIT) #define XSTATE_Hi16_ZMM_MASK (1ULL << XSTATE_Hi16_ZMM_BIT) #define XSTATE_PKRU_MASK (1ULL << XSTATE_PKRU_BIT) +#define XSTATE_XTILE_CFG_MASK (1ULL << XSTATE_XTILE_CFG_BIT) +#define XSTATE_XTILE_DATA_MASK (1ULL << XSTATE_XTILE_DATA_BIT) + +#define XSTATE_DYNAMIC_MASK (XSTATE_XTILE_DATA_MASK) =20 #define ESA_FEATURE_ALIGN64_BIT 1 =20 diff --git a/target/i386/kvm/kvm_i386.h b/target/i386/kvm/kvm_i386.h index a978509d50..4124912c20 100644 --- a/target/i386/kvm/kvm_i386.h +++ b/target/i386/kvm/kvm_i386.h @@ -52,5 +52,6 @@ bool kvm_hyperv_expand_features(X86CPU *cpu, Error **errp= ); uint64_t kvm_swizzle_msi_ext_dest_id(uint64_t address); =20 bool kvm_enable_sgx_provisioning(KVMState *s); +void kvm_request_xsave_components(X86CPU *cpu, uint64_t mask); =20 #endif diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ec35dd1717..505ee289bc 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -6007,6 +6007,7 @@ static void x86_cpu_enable_xsave_components(X86CPU *c= pu) CPUX86State *env =3D &cpu->env; int i; uint64_t mask; + static bool request_perm; =20 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE)) { env->features[FEAT_XSAVE_COMP_LO] =3D 0; @@ -6022,6 +6023,12 @@ static void x86_cpu_enable_xsave_components(X86CPU *= cpu) } } =20 + /* Only request permission for first vcpu */ + if (kvm_enabled() && !request_perm) { + kvm_request_xsave_components(cpu, mask); + request_perm =3D true; + } + env->features[FEAT_XSAVE_COMP_LO] =3D mask; env->features[FEAT_XSAVE_COMP_HI] =3D mask >> 32; } diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c index ce27d3b1df..a35a1bf9fe 100644 --- a/target/i386/kvm/kvm-cpu.c +++ b/target/i386/kvm/kvm-cpu.c @@ -84,7 +84,7 @@ static void kvm_cpu_max_instance_init(X86CPU *cpu) static void kvm_cpu_xsave_init(void) { static bool first =3D true; - KVMState *s =3D kvm_state; + uint32_t eax, ebx, ecx, edx; int i; =20 if (!first) { @@ -100,11 +100,11 @@ static void kvm_cpu_xsave_init(void) ExtSaveArea *esa =3D &x86_ext_save_areas[i]; =20 if (esa->size) { - int sz =3D kvm_arch_get_supported_cpuid(s, 0xd, i, R_EAX); - if (sz !=3D 0) { - assert(esa->size =3D=3D sz); - esa->offset =3D kvm_arch_get_supported_cpuid(s, 0xd, i, R_= EBX); - esa->ecx =3D kvm_arch_get_supported_cpuid(s, 0xd, i, R_ECX= ); + host_cpuid(0xd, i, &eax, &ebx, &ecx, &edx); + if (eax !=3D 0) { + assert(esa->size =3D=3D eax); + esa->offset =3D ebx; + esa->ecx =3D ecx; } } } diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 2c8feb4a6f..742f0eac4a 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -17,6 +17,7 @@ #include "qapi/error.h" #include #include +#include =20 #include #include "standard-headers/asm-x86/kvm_para.h" @@ -348,6 +349,7 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uint= 32_t function, struct kvm_cpuid2 *cpuid; uint32_t ret =3D 0; uint32_t cpuid_1_edx; + uint64_t bitmask; =20 cpuid =3D get_supported_cpuid(s); =20 @@ -405,6 +407,25 @@ uint32_t kvm_arch_get_supported_cpuid(KVMState *s, uin= t32_t function, if (!has_msr_arch_capabs) { ret &=3D ~CPUID_7_0_EDX_ARCH_CAPABILITIES; } + } else if (function =3D=3D 0xd && index =3D=3D 0 && + (reg =3D=3D R_EAX || reg =3D=3D R_EDX)) { + struct kvm_device_attr attr =3D { + .group =3D 0, + .attr =3D KVM_X86_XCOMP_GUEST_SUPP, + .addr =3D (unsigned long) &bitmask + }; + + bool sys_attr =3D kvm_check_extension(s, KVM_CAP_SYS_ATTRIBUTES); + if (!sys_attr) { + warn_report("cannot get sys attribute capabilities %d", sys_at= tr); + } + + int rc =3D kvm_ioctl(s, KVM_GET_DEVICE_ATTR, &attr); + if (rc =3D=3D -1 && (errno =3D=3D ENXIO || errno =3D=3D EINVAL)) { + warn_report("KVM_GET_DEVICE_ATTR(0, KVM_X86_XCOMP_GUEST_SUPP) " + "error: %d", rc); + } + ret =3D (reg =3D=3D R_EAX) ? bitmask : bitmask >> 32; } else if (function =3D=3D 0x80000001 && reg =3D=3D R_ECX) { /* * It's safe to enable TOPOEXT even if it's not returned by @@ -5148,3 +5169,39 @@ bool kvm_arch_cpu_check_are_resettable(void) { return !sev_es_enabled(); } + +#define ARCH_REQ_XCOMP_GUEST_PERM 0x1025 + +void kvm_request_xsave_components(X86CPU *cpu, uint64_t mask) +{ + KVMState *s =3D kvm_state; + uint64_t supported; + + mask &=3D XSTATE_DYNAMIC_MASK; + if (!mask) { + return; + } + /* + * Just ignore bits that are not in CPUID[EAX=3D0xD,ECX=3D0]. + * ARCH_REQ_XCOMP_GUEST_PERM would fail, and QEMU has warned + * about them already because they are not supported features. + */ + supported =3D kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX); + supported |=3D (uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX= ) << 32; + mask &=3D supported; + + while (mask) { + int bit =3D ctz64(mask); + int rc =3D syscall(SYS_arch_prctl, ARCH_REQ_XCOMP_GUEST_PERM, bit); + if (rc) { + /* + * Older kernel version (<5.17) do not support + * ARCH_REQ_XCOMP_GUEST_PERM, but also do not return + * any dynamic feature from kvm_arch_get_supported_cpuid. + */ + warn_report("prctl(ARCH_REQ_XCOMP_GUEST_PERM) failure " + "for feature bit %d", bit); + } + mask &=3D ~BIT_ULL(bit); + } +} From nobody Thu May 16 15:51:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646036143526902.5781875111055; Mon, 28 Feb 2022 00:15:43 -0800 (PST) Received: from localhost ([::1]:46094 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nObC1-00032t-Ev for importer@patchew.org; Mon, 28 Feb 2022 03:15:41 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60512) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nOb2C-0008IZ-S1 for qemu-devel@nongnu.org; Mon, 28 Feb 2022 03:05:33 -0500 Received: from mga14.intel.com ([192.55.52.115]:50059) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nOb28-0005a2-5p for qemu-devel@nongnu.org; Mon, 28 Feb 2022 03:05:31 -0500 Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2022 00:05:17 -0800 Received: from 984fee00bf64.jf.intel.com ([10.165.54.77]) by fmsmga006.fm.intel.com with ESMTP; 28 Feb 2022 00:05:17 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646035528; x=1677571528; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=hRD+yjUUUZjvfyx59uh+M/o6AEXqfzg9f9pmaQvETkw=; b=JBo1k/qGSwmuSZmqPyb5kHbjb0FEBNNnqSJSl+/V1wOxv1R7fwbQoCu+ KwW9QF04xDuvGsnE0cDGnHUNcankGcr0t01q2SOjGcKvdje/e3fzE8i3H 61iW6BnlHlDnA+Y31lFVT/wDwRl4ZeLK4+NXmBb5RUqxDg42mdvl4JPnh HKIfrRhjW2oqvvT1D6GyzQeAZ0AuITA+BojgBdA0XCGSUFEsCZUPDbKjE KCKGeYuLIUcdn9hgFSH8e7YzrSF1UK5ihbVdhFfjfupIYxKB644fECGl7 Fn5WwwO88GQ1rOvqPNCkHqQxfvzczP0HIgKOi8VczSR8hLW2FMFnRdlMv A==; X-IronPort-AV: E=McAfee;i="6200,9189,10271"; a="253021643" X-IronPort-AV: E=Sophos;i="5.90,142,1643702400"; d="scan'208";a="253021643" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,142,1643702400"; d="scan'208";a="778014585" From: Yang Zhong To: qemu-devel@nongnu.org Subject: [PATCH v3 4/8] x86: Add XFD faulting bit for state components Date: Mon, 28 Feb 2022 00:05:11 -0800 Message-Id: <20220228080515.42357-5-yang.zhong@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220228080515.42357-1-yang.zhong@intel.com> References: <20220228080515.42357-1-yang.zhong@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.115; envelope-from=yang.zhong@intel.com; helo=mga14.intel.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: yang.zhong@intel.com, kevin.tian@intel.com, seanjc@google.com, jing2.liu@linux.intel.com, wei.w.wang@intel.com, guang.zeng@intel.com, pbonzini@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646036145596100005 Content-Type: text/plain; charset="utf-8" From: Jing Liu Intel introduces XFD faulting mechanism for extended XSAVE features to dynamically enable the features in runtime. If CPUID (EAX=3D0Dh, ECX=3Dn, n>1).ECX[2] is set as 1, it indicates support for XFD faulting of this state component. Signed-off-by: Jing Liu Signed-off-by: Yang Zhong Reviewed-by: David Edmondson --- target/i386/cpu.h | 2 ++ target/i386/cpu.c | 3 ++- 2 files changed, 4 insertions(+), 1 deletion(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 9630f4712a..925d0129e2 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -557,8 +557,10 @@ typedef enum X86Seg { #define XSTATE_DYNAMIC_MASK (XSTATE_XTILE_DATA_MASK) =20 #define ESA_FEATURE_ALIGN64_BIT 1 +#define ESA_FEATURE_XFD_BIT 2 =20 #define ESA_FEATURE_ALIGN64_MASK (1U << ESA_FEATURE_ALIGN64_BIT) +#define ESA_FEATURE_XFD_MASK (1U << ESA_FEATURE_XFD_BIT) =20 =20 /* CPUID feature words */ diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 505ee289bc..79e24bb23f 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5496,7 +5496,8 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, = uint32_t count, const ExtSaveArea *esa =3D &x86_ext_save_areas[count]; *eax =3D esa->size; *ebx =3D esa->offset; - *ecx =3D esa->ecx & ESA_FEATURE_ALIGN64_MASK; + *ecx =3D esa->ecx & + (ESA_FEATURE_ALIGN64_MASK | ESA_FEATURE_XFD_MASK); } } break; From nobody Thu May 16 15:51:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164603652022397.36345179030275; Mon, 28 Feb 2022 00:22:00 -0800 (PST) Received: from localhost ([::1]:55698 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nObI6-0001NS-TL for importer@patchew.org; Mon, 28 Feb 2022 03:21:58 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60474) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nOb2B-0008IX-0Y for qemu-devel@nongnu.org; Mon, 28 Feb 2022 03:05:33 -0500 Received: from mga14.intel.com ([192.55.52.115]:50056) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nOb28-0005ZR-3I for qemu-devel@nongnu.org; Mon, 28 Feb 2022 03:05:30 -0500 Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2022 00:05:18 -0800 Received: from 984fee00bf64.jf.intel.com ([10.165.54.77]) by fmsmga006.fm.intel.com with ESMTP; 28 Feb 2022 00:05:17 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646035528; x=1677571528; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BAAvwZdr13iEb9qbADEFk6OPtOwkPxXkS9CUFa5jGlM=; b=TpwkvJsTei1S5ECFF+6WNBJmHjI/gX7nTQktL/UpXWa6t7lS3uf7Dxi6 +2xrxFbMkJ0QJRqv//uDW+XN8tj/dwsUmsU6SUu3tZgxFTx6c/srSoNuh CeEymhnzPOsFcF1CUBRsRwtVCuchcLQxMUP+qrfPz5zzFoVJmmmluXEky ZGQNWncRHV9MR25SmmQJj6/QHoJW8MlWHj6xYK/bQ3i+zwzzX8zDOj2uq lUyhCGN1kKzNkk2rqeYqNz2XgnFOhMIKLWnCCsCx6OY0jKnLnP5JBr81V fXrDnPdy6hj6Jdbf1szXut3C5Ycwlwppuuq8H8tJ/M3QEkuHVY7Rl7EsT w==; X-IronPort-AV: E=McAfee;i="6200,9189,10271"; a="253021645" X-IronPort-AV: E=Sophos;i="5.90,142,1643702400"; d="scan'208";a="253021645" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,142,1643702400"; d="scan'208";a="778014590" From: Yang Zhong To: qemu-devel@nongnu.org Subject: [PATCH v3 5/8] x86: Add AMX CPUIDs enumeration Date: Mon, 28 Feb 2022 00:05:12 -0800 Message-Id: <20220228080515.42357-6-yang.zhong@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220228080515.42357-1-yang.zhong@intel.com> References: <20220228080515.42357-1-yang.zhong@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.115; envelope-from=yang.zhong@intel.com; helo=mga14.intel.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: yang.zhong@intel.com, kevin.tian@intel.com, seanjc@google.com, jing2.liu@linux.intel.com, wei.w.wang@intel.com, guang.zeng@intel.com, pbonzini@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646036521929100001 Content-Type: text/plain; charset="utf-8" From: Jing Liu Add AMX primary feature bits XFD and AMX_TILE to enumerate the CPU's AMX capability. Meanwhile, add AMX TILE and TMUL CPUID leaf and subleaves which exist when AMX TILE is present to provide the maximum capability of TILE and TMUL. Signed-off-by: Jing Liu Signed-off-by: Yang Zhong Reviewed-by: David Edmondson --- target/i386/cpu.c | 55 ++++++++++++++++++++++++++++++++++++++++--- target/i386/kvm/kvm.c | 4 +++- 2 files changed, 55 insertions(+), 4 deletions(-) diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 79e24bb23f..351a1e4f2a 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -575,6 +575,18 @@ static CPUCacheInfo legacy_l3_cache =3D { #define INTEL_PT_CYCLE_BITMAP 0x1fff /* Support 0,2^(0~11) */ #define INTEL_PT_PSB_BITMAP (0x003f << 16) /* Support 2K,4K,8K,16K,32= K,64K */ =20 +/* CPUID Leaf 0x1D constants: */ +#define INTEL_AMX_TILE_MAX_SUBLEAF 0x1 +#define INTEL_AMX_TOTAL_TILE_BYTES 0x2000 +#define INTEL_AMX_BYTES_PER_TILE 0x400 +#define INTEL_AMX_BYTES_PER_ROW 0x40 +#define INTEL_AMX_TILE_MAX_NAMES 0x8 +#define INTEL_AMX_TILE_MAX_ROWS 0x10 + +/* CPUID Leaf 0x1E constants: */ +#define INTEL_AMX_TMUL_MAX_K 0x10 +#define INTEL_AMX_TMUL_MAX_N 0x40 + void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1, uint32_t vendor2, uint32_t vendor3) { @@ -844,8 +856,8 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { "avx512-vp2intersect", NULL, "md-clear", NULL, NULL, NULL, "serialize", NULL, "tsx-ldtrk", NULL, NULL /* pconfig */, NULL, - NULL, NULL, NULL, "avx512-fp16", - NULL, NULL, "spec-ctrl", "stibp", + NULL, NULL, "amx-bf16", "avx512-fp16", + "amx-tile", "amx-int8", "spec-ctrl", "stibp", NULL, "arch-capabilities", "core-capability", "ssbd", }, .cpuid =3D { @@ -910,7 +922,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] =3D { .type =3D CPUID_FEATURE_WORD, .feat_names =3D { "xsaveopt", "xsavec", "xgetbv1", "xsaves", - NULL, NULL, NULL, NULL, + "xfd", NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, @@ -5586,6 +5598,43 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index,= uint32_t count, } break; } + case 0x1D: { + /* AMX TILE */ + *eax =3D 0; + *ebx =3D 0; + *ecx =3D 0; + *edx =3D 0; + if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { + break; + } + + if (count =3D=3D 0) { + /* Highest numbered palette subleaf */ + *eax =3D INTEL_AMX_TILE_MAX_SUBLEAF; + } else if (count =3D=3D 1) { + *eax =3D INTEL_AMX_TOTAL_TILE_BYTES | + (INTEL_AMX_BYTES_PER_TILE << 16); + *ebx =3D INTEL_AMX_BYTES_PER_ROW | (INTEL_AMX_TILE_MAX_NAMES <= < 16); + *ecx =3D INTEL_AMX_TILE_MAX_ROWS; + } + break; + } + case 0x1E: { + /* AMX TMUL */ + *eax =3D 0; + *ebx =3D 0; + *ecx =3D 0; + *edx =3D 0; + if (!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE)) { + break; + } + + if (count =3D=3D 0) { + /* Highest numbered palette subleaf */ + *ebx =3D INTEL_AMX_TMUL_MAX_K | (INTEL_AMX_TMUL_MAX_N << 8); + } + break; + } case 0x40000000: /* * CPUID code in kvm_arch_init_vcpu() ignores stuff diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 742f0eac4a..b786d6da96 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -1780,7 +1780,9 @@ int kvm_arch_init_vcpu(CPUState *cs) c =3D &cpuid_data.entries[cpuid_i++]; } break; - case 0x14: { + case 0x14: + case 0x1d: + case 0x1e: { uint32_t times; =20 c->function =3D i; From nobody Thu May 16 15:51:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646036485184144.0528138834885; Mon, 28 Feb 2022 00:21:25 -0800 (PST) Received: from localhost ([::1]:54818 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nObHY-0000nX-3T for importer@patchew.org; Mon, 28 Feb 2022 03:21:24 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60542) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nOb2E-0008J4-Qd for qemu-devel@nongnu.org; Mon, 28 Feb 2022 03:05:39 -0500 Received: from mga14.intel.com ([192.55.52.115]:50047) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nOb2C-0005Ys-HL for qemu-devel@nongnu.org; Mon, 28 Feb 2022 03:05:34 -0500 Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2022 00:05:18 -0800 Received: from 984fee00bf64.jf.intel.com ([10.165.54.77]) by fmsmga006.fm.intel.com with ESMTP; 28 Feb 2022 00:05:18 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646035532; x=1677571532; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=BILWfpgxBFc/XZYvl0Hta8UqRo/VrmPpnYbpvNPD+LM=; b=Zhi7Hkw+RZi9VMm6iUJVmado/IhqSUDFRNVGe+py5D6QmliEnbAp2fBi rf5jJsE2RjrRpCYQW5x5FZMwRqMhIIpe9D4UkKv2crwhGyV/4ZLxIrKj8 D7Ct2LYJ0hj577l+0B1K+9Jnih/h2A5fI5SDrMoIfyoaO520tX1w+/Ii3 4IrweanWx3+jomETE3SnnatpQ3NgXUS1Slrh8VKbtmNRHyqb71wtkhsRd Pgzz3fXhcywOjR6unhOmYwaJhT58e26YbtMmuarLZchFELkpjqYOF/ck5 FT016ag79HM8M4ZF+/wttw9Q2aIKYfONupHXsoIscTszPQQa2OXYv98qV g==; X-IronPort-AV: E=McAfee;i="6200,9189,10271"; a="253021647" X-IronPort-AV: E=Sophos;i="5.90,142,1643702400"; d="scan'208";a="253021647" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,142,1643702400"; d="scan'208";a="778014594" From: Yang Zhong To: qemu-devel@nongnu.org Subject: [PATCH v3 6/8] x86: Add support for KVM_CAP_XSAVE2 and AMX state migration Date: Mon, 28 Feb 2022 00:05:13 -0800 Message-Id: <20220228080515.42357-7-yang.zhong@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220228080515.42357-1-yang.zhong@intel.com> References: <20220228080515.42357-1-yang.zhong@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.115; envelope-from=yang.zhong@intel.com; helo=mga14.intel.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: yang.zhong@intel.com, kevin.tian@intel.com, seanjc@google.com, jing2.liu@linux.intel.com, wei.w.wang@intel.com, guang.zeng@intel.com, pbonzini@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646036485611100003 Content-Type: text/plain; charset="utf-8" From: Jing Liu When dynamic xfeatures (e.g. AMX) are used by the guest, the xsave area would be larger than 4KB. KVM_GET_XSAVE2 and KVM_SET_XSAVE under KVM_CAP_XSAVE2 works with a xsave buffer larger than 4KB. Always use the new ioctls under KVM_CAP_XSAVE2 when KVM supports it. Signed-off-by: Jing Liu Signed-off-by: Zeng Guang Signed-off-by: Wei Wang Signed-off-by: Yang Zhong --- target/i386/cpu.h | 4 ++++ target/i386/kvm/kvm.c | 42 ++++++++++++++++++++++++-------------- target/i386/xsave_helper.c | 33 ++++++++++++++++++++++++++++++ 3 files changed, 64 insertions(+), 15 deletions(-) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 925d0129e2..8c850e74b8 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1527,6 +1527,10 @@ typedef struct CPUX86State { uint64_t opmask_regs[NB_OPMASK_REGS]; YMMReg zmmh_regs[CPU_NB_REGS]; ZMMReg hi16_zmm_regs[CPU_NB_REGS]; +#ifdef TARGET_X86_64 + uint8_t xtilecfg[64]; + uint8_t xtiledata[8192]; +#endif =20 /* sysenter registers */ uint32_t sysenter_cs; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index b786d6da96..e64c06d358 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -123,6 +123,7 @@ static uint32_t num_architectural_pmu_gp_counters; static uint32_t num_architectural_pmu_fixed_counters; =20 static int has_xsave; +static int has_xsave2; static int has_xcrs; static int has_pit_state2; static int has_sregs2; @@ -1586,6 +1587,26 @@ static Error *invtsc_mig_blocker; =20 #define KVM_MAX_CPUID_ENTRIES 100 =20 +static void kvm_init_xsave(CPUX86State *env) +{ + if (has_xsave2) { + env->xsave_buf_len =3D QEMU_ALIGN_UP(has_xsave2, 4096); + } else if (has_xsave) { + env->xsave_buf_len =3D sizeof(struct kvm_xsave); + } else { + return; + } + + env->xsave_buf =3D qemu_memalign(4096, env->xsave_buf_len); + memset(env->xsave_buf, 0, env->xsave_buf_len); + /* + * The allocated storage must be large enough for all of the + * possible XSAVE state components. + */ + assert(kvm_arch_get_supported_cpuid(kvm_state, 0xd, 0, R_ECX) <=3D + env->xsave_buf_len); +} + int kvm_arch_init_vcpu(CPUState *cs) { struct { @@ -1615,6 +1636,8 @@ int kvm_arch_init_vcpu(CPUState *cs) =20 cpuid_i =3D 0; =20 + has_xsave2 =3D kvm_check_extension(cs->kvm_state, KVM_CAP_XSAVE2); + r =3D kvm_arch_set_tsc_khz(cs); if (r < 0) { return r; @@ -2004,19 +2027,7 @@ int kvm_arch_init_vcpu(CPUState *cs) if (r) { goto fail; } - - if (has_xsave) { - env->xsave_buf_len =3D sizeof(struct kvm_xsave); - env->xsave_buf =3D qemu_memalign(4096, env->xsave_buf_len); - memset(env->xsave_buf, 0, env->xsave_buf_len); - - /* - * The allocated storage must be large enough for all of the - * possible XSAVE state components. - */ - assert(kvm_arch_get_supported_cpuid(kvm_state, 0xd, 0, R_ECX) - <=3D env->xsave_buf_len); - } + kvm_init_xsave(env); =20 max_nested_state_len =3D kvm_max_nested_state_length(); if (max_nested_state_len > 0) { @@ -3320,13 +3331,14 @@ static int kvm_get_xsave(X86CPU *cpu) { CPUX86State *env =3D &cpu->env; void *xsave =3D env->xsave_buf; - int ret; + int type, ret; =20 if (!has_xsave) { return kvm_get_fpu(cpu); } =20 - ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_XSAVE, xsave); + type =3D has_xsave2 ? KVM_GET_XSAVE2 : KVM_GET_XSAVE; + ret =3D kvm_vcpu_ioctl(CPU(cpu), type, xsave); if (ret < 0) { return ret; } diff --git a/target/i386/xsave_helper.c b/target/i386/xsave_helper.c index ac61a96344..b6a004505f 100644 --- a/target/i386/xsave_helper.c +++ b/target/i386/xsave_helper.c @@ -5,6 +5,7 @@ #include "qemu/osdep.h" =20 #include "cpu.h" +#include =20 void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, uint32_t buflen) { @@ -126,6 +127,22 @@ void x86_cpu_xsave_all_areas(X86CPU *cpu, void *buf, u= int32_t buflen) =20 memcpy(pkru, &env->pkru, sizeof(env->pkru)); } + + e =3D &x86_ext_save_areas[XSTATE_XTILE_CFG_BIT]; + if (e->size && e->offset) { + XSaveXTILECFG *tilecfg =3D buf + e->offset; + + memcpy(tilecfg, &env->xtilecfg, sizeof(env->xtilecfg)); + } + + if (buflen > sizeof(struct kvm_xsave)) { + e =3D &x86_ext_save_areas[XSTATE_XTILE_DATA_BIT]; + if (e->size && e->offset && buflen >=3D e->size + e->offset) { + XSaveXTILEDATA *tiledata =3D buf + e->offset; + + memcpy(tiledata, &env->xtiledata, sizeof(env->xtiledata)); + } + } #endif } =20 @@ -247,5 +264,21 @@ void x86_cpu_xrstor_all_areas(X86CPU *cpu, const void = *buf, uint32_t buflen) pkru =3D buf + e->offset; memcpy(&env->pkru, pkru, sizeof(env->pkru)); } + + e =3D &x86_ext_save_areas[XSTATE_XTILE_CFG_BIT]; + if (e->size && e->offset) { + const XSaveXTILECFG *tilecfg =3D buf + e->offset; + + memcpy(&env->xtilecfg, tilecfg, sizeof(env->xtilecfg)); + } + + if (buflen > sizeof(struct kvm_xsave)) { + e =3D &x86_ext_save_areas[XSTATE_XTILE_DATA_BIT]; + if (e->size && e->offset && buflen >=3D e->size + e->offset) { + const XSaveXTILEDATA *tiledata =3D buf + e->offset; + + memcpy(&env->xtiledata, tiledata, sizeof(env->xtiledata)); + } + } #endif } From nobody Thu May 16 15:51:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646036864199162.608575612879; Mon, 28 Feb 2022 00:27:44 -0800 (PST) Received: from localhost ([::1]:34578 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nObNf-0006Z5-06 for importer@patchew.org; Mon, 28 Feb 2022 03:27:43 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60540) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nOb2E-0008J3-Qf for qemu-devel@nongnu.org; Mon, 28 Feb 2022 03:05:39 -0500 Received: from mga14.intel.com ([192.55.52.115]:50056) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nOb2C-0005ZR-Mh for qemu-devel@nongnu.org; Mon, 28 Feb 2022 03:05:34 -0500 Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2022 00:05:18 -0800 Received: from 984fee00bf64.jf.intel.com ([10.165.54.77]) by fmsmga006.fm.intel.com with ESMTP; 28 Feb 2022 00:05:18 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646035532; x=1677571532; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=5UX6bc6F75Y+jyQEf0pgvwOcIDrka3TrwKDsfRKtcvk=; b=ZvOEqqhlKPPeosS25iDhU2sLwAsZx706hJHIJdDR2XJpd/IBR9PNQOID 62pzgyxTv5LaVwYC+fH6hImlxbp7xJXJQZFGdxpP/McrFP69v1Dt3qEQX Wo/y0edlRJho78P3cxYLAHhXS/3HuRKfaJMWCQMxW8BwIJhkCdfH6byNS N+UhGKJrq5c6Adgh4XJEKrA1JaPuDKZmjh8t9cuuISD7tK2r2FEw2+dwV G/trkdfg/KU3fyFNx4pw6o/X+GqsD9qqh38a1JpXUrDVBdqGdVOXPIgRP zy+F6t7eBeDAjETtKRA/C3aXqrCWWibcsi2LlXIL8NLLFN3RSn45VSEzg g==; X-IronPort-AV: E=McAfee;i="6200,9189,10271"; a="253021650" X-IronPort-AV: E=Sophos;i="5.90,142,1643702400"; d="scan'208";a="253021650" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,142,1643702400"; d="scan'208";a="778014599" From: Yang Zhong To: qemu-devel@nongnu.org Subject: [PATCH v3 7/8] x86: Support XFD and AMX xsave data migration Date: Mon, 28 Feb 2022 00:05:14 -0800 Message-Id: <20220228080515.42357-8-yang.zhong@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220228080515.42357-1-yang.zhong@intel.com> References: <20220228080515.42357-1-yang.zhong@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.115; envelope-from=yang.zhong@intel.com; helo=mga14.intel.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: yang.zhong@intel.com, kevin.tian@intel.com, seanjc@google.com, jing2.liu@linux.intel.com, wei.w.wang@intel.com, guang.zeng@intel.com, pbonzini@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646036865699100001 Content-Type: text/plain; charset="utf-8" From: Zeng Guang XFD(eXtended Feature Disable) allows to enable a feature on xsave state while preventing specific user threads from using the feature. Support save and restore XFD MSRs if CPUID.D.1.EAX[4] enumerate to be valid. Likewise migrate the MSRs and related xsave state necessarily. Signed-off-by: Zeng Guang Signed-off-by: Wei Wang Signed-off-by: Yang Zhong Reviewed-by: David Edmondson --- target/i386/cpu.h | 9 +++++++++ target/i386/kvm/kvm.c | 18 ++++++++++++++++++ target/i386/machine.c | 42 ++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 69 insertions(+) diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 8c850e74b8..efea2c78ec 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -507,6 +507,9 @@ typedef enum X86Seg { =20 #define MSR_VM_HSAVE_PA 0xc0010117 =20 +#define MSR_IA32_XFD 0x000001c4 +#define MSR_IA32_XFD_ERR 0x000001c5 + #define MSR_IA32_BNDCFGS 0x00000d90 #define MSR_IA32_XSS 0x00000da0 #define MSR_IA32_UMWAIT_CONTROL 0xe1 @@ -872,6 +875,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS]; #define CPUID_7_1_EAX_AVX_VNNI (1U << 4) /* AVX512 BFloat16 Instruction */ #define CPUID_7_1_EAX_AVX512_BF16 (1U << 5) +/* XFD Extend Feature Disabled */ +#define CPUID_D_1_EAX_XFD (1U << 4) =20 /* Packets which contain IP payload have LIP values */ #define CPUID_14_0_ECX_LIP (1U << 31) @@ -1616,6 +1621,10 @@ typedef struct CPUX86State { uint64_t msr_rtit_cr3_match; uint64_t msr_rtit_addrs[MAX_RTIT_ADDRS]; =20 + /* Per-VCPU XFD MSRs */ + uint64_t msr_xfd; + uint64_t msr_xfd_err; + /* exception/interrupt handling */ int error_code; int exception_is_int; diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index e64c06d358..fe8e924846 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -3276,6 +3276,13 @@ static int kvm_put_msrs(X86CPU *cpu, int level) env->msr_ia32_sgxlepubkeyhash[3]); } =20 + if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) { + kvm_msr_entry_add(cpu, MSR_IA32_XFD, + env->msr_xfd); + kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR, + env->msr_xfd_err); + } + /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see * kvm_put_msr_feature_control. */ } @@ -3668,6 +3675,11 @@ static int kvm_get_msrs(X86CPU *cpu) kvm_msr_entry_add(cpu, MSR_IA32_SGXLEPUBKEYHASH3, 0); } =20 + if (env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD) { + kvm_msr_entry_add(cpu, MSR_IA32_XFD, 0); + kvm_msr_entry_add(cpu, MSR_IA32_XFD_ERR, 0); + } + ret =3D kvm_vcpu_ioctl(CPU(cpu), KVM_GET_MSRS, cpu->kvm_msr_buf); if (ret < 0) { return ret; @@ -3964,6 +3976,12 @@ static int kvm_get_msrs(X86CPU *cpu) env->msr_ia32_sgxlepubkeyhash[index - MSR_IA32_SGXLEPUBKEYHASH= 0] =3D msrs[i].data; break; + case MSR_IA32_XFD: + env->msr_xfd =3D msrs[i].data; + break; + case MSR_IA32_XFD_ERR: + env->msr_xfd_err =3D msrs[i].data; + break; } } =20 diff --git a/target/i386/machine.c b/target/i386/machine.c index 6202f47793..1f9d0c46f1 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -1483,6 +1483,46 @@ static const VMStateDescription vmstate_pdptrs =3D { } }; =20 +static bool xfd_msrs_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return !!(env->features[FEAT_XSAVE] & CPUID_D_1_EAX_XFD); +} + +static const VMStateDescription vmstate_msr_xfd =3D { + .name =3D "cpu/msr_xfd", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D xfd_msrs_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT64(env.msr_xfd, X86CPU), + VMSTATE_UINT64(env.msr_xfd_err, X86CPU), + VMSTATE_END_OF_LIST() + } +}; + +static bool amx_xtile_needed(void *opaque) +{ + X86CPU *cpu =3D opaque; + CPUX86State *env =3D &cpu->env; + + return !!(env->features[FEAT_7_0_EDX] & CPUID_7_0_EDX_AMX_TILE); +} + +static const VMStateDescription vmstate_amx_xtile =3D { + .name =3D "cpu/intel_amx_xtile", + .version_id =3D 1, + .minimum_version_id =3D 1, + .needed =3D amx_xtile_needed, + .fields =3D (VMStateField[]) { + VMSTATE_UINT8_ARRAY(env.xtilecfg, X86CPU, 64), + VMSTATE_UINT8_ARRAY(env.xtiledata, X86CPU, 8192), + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_x86_cpu =3D { .name =3D "cpu", .version_id =3D 12, @@ -1622,6 +1662,8 @@ const VMStateDescription vmstate_x86_cpu =3D { &vmstate_msr_tsx_ctrl, &vmstate_msr_intel_sgx, &vmstate_pdptrs, + &vmstate_msr_xfd, + &vmstate_amx_xtile, NULL } }; From nobody Thu May 16 15:51:24 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=intel.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1646036814023728.8521920433994; Mon, 28 Feb 2022 00:26:54 -0800 (PST) Received: from localhost ([::1]:33090 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nObMp-0005Rz-Ui for importer@patchew.org; Mon, 28 Feb 2022 03:26:52 -0500 Received: from eggs.gnu.org ([209.51.188.92]:60572) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nOb2H-0008JK-9v for qemu-devel@nongnu.org; Mon, 28 Feb 2022 03:05:44 -0500 Received: from mga14.intel.com ([192.55.52.115]:50059) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nOb2E-0005a2-Ax for qemu-devel@nongnu.org; Mon, 28 Feb 2022 03:05:36 -0500 Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 28 Feb 2022 00:05:19 -0800 Received: from 984fee00bf64.jf.intel.com ([10.165.54.77]) by fmsmga006.fm.intel.com with ESMTP; 28 Feb 2022 00:05:18 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1646035534; x=1677571534; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=lygLHfFpKkNOpm8ULz7Ml4gu1/xM9RWbAxVPpfHcP1M=; b=Xgq4uPvLevh6NxdNyX13tABX3SVBIhcbLjoRk4aGKM9oqGaQLilzx8Qd KQ/minb9Pjo1Gawi6o0yZp6xJBF5041FOxLCelApDcnd0VG5bsx4sBPIC Cs6naRgAfsXUwqWLD4qU+TZDArHs8wHJRs14qFi4+qb4aYWnqirdexfui FMAmz9n7mjkO7yXKA0Thkt2RAxeecORzcUGN/yzWLWQcr9wOrC0D0Dcl/ uM8jdViVwJfVm6OvBODia20S7vvpVGfTfZMNfM3ZN0QQzV1ZxnErLYNHI kpfjpK6oM/ukPMh85YSspkbJRpZHFE5Pw1nASBC7ayAX4dmOVy7XXxMRJ w==; X-IronPort-AV: E=McAfee;i="6200,9189,10271"; a="253021654" X-IronPort-AV: E=Sophos;i="5.90,142,1643702400"; d="scan'208";a="253021654" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.90,142,1643702400"; d="scan'208";a="778014605" From: Yang Zhong To: qemu-devel@nongnu.org Subject: [PATCH v3 8/8] linux-header: Sync the linux headers Date: Mon, 28 Feb 2022 00:05:15 -0800 Message-Id: <20220228080515.42357-9-yang.zhong@intel.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220228080515.42357-1-yang.zhong@intel.com> References: <20220228080515.42357-1-yang.zhong@intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=192.55.52.115; envelope-from=yang.zhong@intel.com; helo=mga14.intel.com X-Spam_score_int: -71 X-Spam_score: -7.2 X-Spam_bar: ------- X-Spam_report: (-7.2 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: yang.zhong@intel.com, kevin.tian@intel.com, seanjc@google.com, jing2.liu@linux.intel.com, wei.w.wang@intel.com, guang.zeng@intel.com, pbonzini@redhat.com Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1646036815167100001 Content-Type: text/plain; charset="utf-8" This patch will be dropped once Qemu sync linux 5.17 header. Making all linux-headers changes here are only for maintainers to easily remove those changes once those patches are queued. Signed-off-by: Yang Zhong --- linux-headers/asm-x86/kvm.h | 3 +++ linux-headers/linux/kvm.h | 1 + 2 files changed, 4 insertions(+) diff --git a/linux-headers/asm-x86/kvm.h b/linux-headers/asm-x86/kvm.h index 2da3316bb5..8224d0dda2 100644 --- a/linux-headers/asm-x86/kvm.h +++ b/linux-headers/asm-x86/kvm.h @@ -452,6 +452,9 @@ struct kvm_sync_regs { =20 #define KVM_STATE_VMX_PREEMPTION_TIMER_DEADLINE 0x00000001 =20 +/* attributes for system fd (group 0) */ +#define KVM_X86_XCOMP_GUEST_SUPP 0 + struct kvm_vmx_nested_state_data { __u8 vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE]; __u8 shadow_vmcs12[KVM_STATE_NESTED_VMX_VMCS_SIZE]; diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index 00af3bc333..002503dc8b 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -1133,6 +1133,7 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_VM_MOVE_ENC_CONTEXT_FROM 206 #define KVM_CAP_VM_GPA_BITS 207 #define KVM_CAP_XSAVE2 208 +#define KVM_CAP_SYS_ATTRIBUTES 209 =20 #ifdef KVM_CAP_IRQ_ROUTING