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Gating it with CONFIG_TCG and changing meson.build accordingly will prevent problems --disable-tcg and --disable-linux-user later on. We're also changing the uses of !kvm_enabled() to tcg_enabled() to avoid adding "defined(CONFIG_TCG)" ifdefs, since tcg_enabled() will be defaulted to false with --disable-tcg and the block will always be skipped. Reviewed-by: Richard Henderson Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu_init.c | 16 +++++++--------- target/ppc/machine.c | 6 +++++- target/ppc/meson.build | 2 +- target/ppc/power8-pmu.h | 4 ++-- 4 files changed, 15 insertions(+), 13 deletions(-) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 61d36b11a0..544e052290 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -5698,12 +5698,10 @@ static void register_power9_mmu_sprs(CPUPPCState *e= nv) */ static void init_tcg_pmu_power8(CPUPPCState *env) { -#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) /* Init PMU overflow timers */ - if (!kvm_enabled()) { + if (tcg_enabled()) { cpu_ppc_pmu_init(env); } -#endif } =20 static void init_proc_book3s_common(CPUPPCState *env) @@ -7167,14 +7165,14 @@ static void ppc_cpu_reset(DeviceState *dev) =20 #if !defined(CONFIG_USER_ONLY) env->nip =3D env->hreset_vector | env->excp_prefix; -#if defined(CONFIG_TCG) - if (env->mmu_model !=3D POWERPC_MMU_REAL) { - ppc_tlb_invalidate_all(env); + + if (tcg_enabled()) { + if (env->mmu_model !=3D POWERPC_MMU_REAL) { + ppc_tlb_invalidate_all(env); + } + pmu_update_summaries(env); } -#endif /* CONFIG_TCG */ #endif - - pmu_update_summaries(env); hreg_compute_hflags(env); env->reserve_addr =3D (target_ulong)-1ULL; /* Be sure no exception or interrupt is pending */ diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 1b63146ed1..e673944597 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -2,6 +2,7 @@ #include "cpu.h" #include "exec/exec-all.h" #include "sysemu/kvm.h" +#include "sysemu/tcg.h" #include "helper_regs.h" #include "mmu-hash64.h" #include "migration/cpu.h" @@ -20,7 +21,10 @@ static void post_load_update_msr(CPUPPCState *env) */ env->msr ^=3D env->msr_mask & ~((1ULL << MSR_TGPR) | MSR_HVB); ppc_store_msr(env, msr); - pmu_update_summaries(env); + + if (tcg_enabled()) { + pmu_update_summaries(env); + } } =20 static int get_avr(QEMUFile *f, void *pv, size_t size, diff --git a/target/ppc/meson.build b/target/ppc/meson.build index a49a8911e0..79beaff147 100644 --- a/target/ppc/meson.build +++ b/target/ppc/meson.build @@ -16,6 +16,7 @@ ppc_ss.add(when: 'CONFIG_TCG', if_true: files( 'misc_helper.c', 'timebase_helper.c', 'translate.c', + 'power8-pmu.c', )) =20 ppc_ss.add(libdecnumber) @@ -51,7 +52,6 @@ ppc_softmmu_ss.add(when: 'TARGET_PPC64', if_true: files( 'mmu-book3s-v3.c', 'mmu-hash64.c', 'mmu-radix64.c', - 'power8-pmu.c', )) =20 target_arch +=3D {'ppc': ppc_ss} diff --git a/target/ppc/power8-pmu.h b/target/ppc/power8-pmu.h index a839199561..256d90f523 100644 --- a/target/ppc/power8-pmu.h +++ b/target/ppc/power8-pmu.h @@ -13,11 +13,11 @@ #ifndef POWER8_PMU #define POWER8_PMU =20 -void cpu_ppc_pmu_init(CPUPPCState *env); - #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) +void cpu_ppc_pmu_init(CPUPPCState *env); void pmu_update_summaries(CPUPPCState *env); #else +static inline void cpu_ppc_pmu_init(CPUPPCState *env) { } static inline void pmu_update_summaries(CPUPPCState *env) { } #endif =20 --=20 2.35.1 From nobody Sat May 11 21:14:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 164578417690442.1191999893216; Fri, 25 Feb 2022 02:16:16 -0800 (PST) Received: from localhost ([::1]:58668 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nNXe3-0002af-TF for importer@patchew.org; Fri, 25 Feb 2022 05:16:15 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46028) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nNXZx-0006ov-KV; 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charset="utf-8" There are still PMU exclusive bits to handle in fire_PMC_interrupt() before implementing the EBB support. Let's finalize it now to avoid dealing with PMU and EBB logic at the same time in the next patches. fire_PMC_interrupt() will fire an Performance Monitor alert depending on MMCR0_PMAE. If we are required to freeze the timers (MMCR0_FCECE) we'll also need to update summaries and delete the existing overflow timers. In all cases we're going to update the cycle counters. Signed-off-by: Daniel Henrique Barboza --- target/ppc/power8-pmu.c | 36 ++++++++++++++++++++++++++++++++++-- 1 file changed, 34 insertions(+), 2 deletions(-) diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index 236e8e66e9..d245663158 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -222,6 +222,20 @@ static void pmu_update_overflow_timers(CPUPPCState *en= v) } } =20 +static void pmu_delete_timers(CPUPPCState *env) +{ + QEMUTimer *pmc_overflow_timer; + int sprn; + + for (sprn =3D SPR_POWER_PMC1; sprn <=3D SPR_POWER_PMC6; sprn++) { + pmc_overflow_timer =3D get_cyc_overflow_timer(env, sprn); + + if (pmc_overflow_timer) { + timer_del(pmc_overflow_timer); + } + } +} + void helper_store_mmcr0(CPUPPCState *env, target_ulong value) { bool hflags_pmcc0 =3D (value & MMCR0_PMCC0) !=3D 0; @@ -271,8 +285,26 @@ static void fire_PMC_interrupt(PowerPCCPU *cpu) { CPUPPCState *env =3D &cpu->env; =20 - if (!(env->spr[SPR_POWER_MMCR0] & MMCR0_EBE)) { - return; + pmu_update_cycles(env); + + if (env->spr[SPR_POWER_MMCR0] & MMCR0_FCECE) { + env->spr[SPR_POWER_MMCR0] &=3D ~MMCR0_FCECE; + env->spr[SPR_POWER_MMCR0] |=3D MMCR0_FC; + + /* Changing MMCR0_FC requires a new HFLAGS_INSN_CNT calc */ + pmu_update_summaries(env); + + /* + * Delete all pending timers if we need to freeze + * the PMC. We'll restart them when the PMC starts + * running again. + */ + pmu_delete_timers(env); + } + + if (env->spr[SPR_POWER_MMCR0] & MMCR0_PMAE) { + env->spr[SPR_POWER_MMCR0] &=3D ~MMCR0_PMAE; + env->spr[SPR_POWER_MMCR0] |=3D MMCR0_PMAO; } =20 /* PMC interrupt not implemented yet */ --=20 2.35.1 From nobody Sat May 11 21:14:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=gmail.com Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1645784503619579.5293557037108; Fri, 25 Feb 2022 02:21:43 -0800 (PST) Received: from localhost ([::1]:39850 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nNXjK-0000m2-Dx for importer@patchew.org; Fri, 25 Feb 2022 05:21:42 -0500 Received: from eggs.gnu.org ([209.51.188.92]:46042) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nNXZz-0006py-G1; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::c36 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::c36; envelope-from=danielhb413@gmail.com; helo=mail-oo1-xc36.google.com X-Spam_score_int: -3 X-Spam_score: -0.4 X-Spam_bar: / X-Spam_report: (-0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1645784505490100001 PPC_INTERRUPT_EBB is a new interrupt that will be used to deliver EBB exceptions that had to be postponed because the thread wasn't in problem state at the time the event-based branch was supposed to occur. ISA 3.1 also defines two EBB exceptions: Performance Monitor EBB exception and External EBB exception. They are being added as POWERPC_EXCP_PERFM_EBB and POWERPC_EXCP_EXTERNAL_EBB. PPC_INTERRUPT_EBB will check BESCR bits to see the EBB type that occurred and trigger the appropriate exception. Both exceptions are doing the same thing in this first implementation: clear BESCR_GE and enter the branch with env->nip retrieved from SPR_EBBHR. The checks being done by the interrupt code are msr_pr and BESCR_GE states. All other checks (EBB facility check, BESCR_PME bit, specific bits related to the event type) must be done beforehand. Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 5 ++++- target/ppc/cpu_init.c | 4 ++++ target/ppc/excp_helper.c | 33 +++++++++++++++++++++++++++++++++ 3 files changed, 41 insertions(+), 1 deletion(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 5b01d409b3..79375e8df4 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -127,8 +127,10 @@ enum { /* ISA 3.00 additions */ POWERPC_EXCP_HVIRT =3D 101, POWERPC_EXCP_SYSCALL_VECTORED =3D 102, /* scv exception = */ + POWERPC_EXCP_PERFM_EBB =3D 103, /* Performance Monitor EBB Exceptio= n */ + POWERPC_EXCP_EXTERNAL_EBB =3D 104, /* External EBB Exception = */ /* EOL = */ - POWERPC_EXCP_NB =3D 103, + POWERPC_EXCP_NB =3D 105, /* QEMU exceptions: special cases we want to stop translation = */ POWERPC_EXCP_SYSCALL_USER =3D 0x203, /* System call in user mode only = */ }; @@ -2434,6 +2436,7 @@ enum { PPC_INTERRUPT_HMI, /* Hypervisor Maintenance interrupt */ PPC_INTERRUPT_HDOORBELL, /* Hypervisor Doorbell interrupt = */ PPC_INTERRUPT_HVIRT, /* Hypervisor virtualization interrupt = */ + PPC_INTERRUPT_EBB, /* Event-based Branch exception = */ }; =20 /* Processor Compatibility mask (PCR) */ diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 544e052290..073fd10168 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -2060,6 +2060,10 @@ static void init_excp_POWER8(CPUPPCState *env) env->excp_vectors[POWERPC_EXCP_FU] =3D 0x00000F60; env->excp_vectors[POWERPC_EXCP_HV_FU] =3D 0x00000F80; env->excp_vectors[POWERPC_EXCP_SDOOR_HV] =3D 0x00000E80; + + /* Userland exceptions without vector value in PowerISA v3.1 */ + env->excp_vectors[POWERPC_EXCP_PERFM_EBB] =3D 0x0; + env->excp_vectors[POWERPC_EXCP_EXTERNAL_EBB] =3D 0x0; #endif } =20 diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 6538c56ab0..5e7d29ae00 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1554,6 +1554,21 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int = excp) new_msr |=3D (target_ulong)MSR_HVB; new_msr |=3D env->msr & ((target_ulong)1 << MSR_RI); break; + case POWERPC_EXCP_PERFM_EBB: /* Performance Monitor EBB Excepti= on */ + case POWERPC_EXCP_EXTERNAL_EBB: /* External EBB Exception = */ + env->spr[SPR_BESCR] &=3D ~BESCR_GE; + + /* + * Save NIP for rfebb insn in SPR_EBBRR. Next nip is + * stored in the EBB Handler SPR_EBBHR. + */ + env->spr[SPR_EBBRR] =3D env->nip; + powerpc_set_excp_state(cpu, env->spr[SPR_EBBHR], env->msr); + + /* + * This exception is handled in userspace. No need to proceed. + */ + return; case POWERPC_EXCP_THERM: /* Thermal interrupt = */ case POWERPC_EXCP_PERFM: /* Embedded performance monitor interrupt= */ case POWERPC_EXCP_VPUA: /* Vector assist exception = */ @@ -1797,6 +1812,24 @@ static void ppc_hw_interrupt(CPUPPCState *env) powerpc_excp(cpu, POWERPC_EXCP_THERM); return; } + /* EBB exception */ + if (env->pending_interrupts & (1 << PPC_INTERRUPT_EBB)) { + /* + * EBB exception must be taken in problem state and + * with BESCR_GE set. + */ + if (msr_pr =3D=3D 1 && env->spr[SPR_BESCR] & BESCR_GE) { + env->pending_interrupts &=3D ~(1 << PPC_INTERRUPT_EBB); + + if (env->spr[SPR_BESCR] & BESCR_PMEO) { + powerpc_excp(cpu, POWERPC_EXCP_PERFM_EBB); + } else if (env->spr[SPR_BESCR] & BESCR_EEO) { + powerpc_excp(cpu, POWERPC_EXCP_EXTERNAL_EBB); + } + + return; + } + } } =20 if (env->resume_as_sreset) { --=20 2.35.1 From nobody Sat May 11 21:14:55 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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Fri, 25 Feb 2022 02:12:02 -0800 (PST) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Subject: [PATCH v14 4/4] target/ppc: trigger PERFM EBBs from power8-pmu.c Date: Fri, 25 Feb 2022 07:11:40 -0300 Message-Id: <20220225101140.1054160-5-danielhb413@gmail.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220225101140.1054160-1-danielhb413@gmail.com> References: <20220225101140.1054160-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Host-Lookup-Failed: Reverse DNS lookup failed for 2607:f8b0:4864:20::235 (failed) Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::235; envelope-from=danielhb413@gmail.com; helo=mail-oi1-x235.google.com X-Spam_score_int: -3 X-Spam_score: -0.4 X-Spam_bar: / X-Spam_report: (-0.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, PDS_HP_HELO_NORDNS=0.659, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Daniel Henrique Barboza , qemu-ppc@nongnu.org, clg@kaod.org, david@gibson.dropbear.id.au Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1645784440948100001 Content-Type: text/plain; charset="utf-8" This patch adds the EBB exception support that are triggered by Performance Monitor alerts. This happens when a Performance Monitor alert occurs and MMCR0_EBE, BESCR_PME and BESCR_GE are set. fire_PMC_interrupt() will execute the raise_ebb_perfm_exception() helper which will check for MMCR0_EBE, BESCR_PME and BESCR_GE bits. If all bits are set, do_ebb() will attempt to trigger a PERFM EBB event. If the EBB facility is enabled in both FSCR and HFSCR we consider that the EBB is valid and set BESCR_PMEO. After that, if we're running in problem state, fire a POWERPC_EXCP_PERM_EBB immediately. Otherwise we'll queue a PPC_INTERRUPT_EBB. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Richard Henderson --- target/ppc/cpu.h | 5 +++++ target/ppc/excp_helper.c | 48 ++++++++++++++++++++++++++++++++++++++++ target/ppc/power8-pmu.c | 3 +-- 3 files changed, 54 insertions(+), 2 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 79375e8df4..1b687521c7 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -2502,6 +2502,11 @@ void QEMU_NORETURN raise_exception_err(CPUPPCState *= env, uint32_t exception, void QEMU_NORETURN raise_exception_err_ra(CPUPPCState *env, uint32_t excep= tion, uint32_t error_code, uintptr_t r= addr); =20 +/* PERFM EBB helper*/ +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) +void raise_ebb_perfm_exception(CPUPPCState *env); +#endif + #if !defined(CONFIG_USER_ONLY) static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm) { diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 5e7d29ae00..d3e2cfcd71 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -2066,6 +2066,54 @@ void helper_rfebb(CPUPPCState *env, target_ulong s) env->spr[SPR_BESCR] &=3D ~BESCR_GE; } } + +/* + * Triggers or queues an 'ebb_excp' EBB exception. All checks + * but FSCR, HFSCR and msr_pr must be done beforehand. + * + * PowerISA v3.1 isn't clear about whether an EBB should be + * postponed or cancelled if the EBB facility is unavailable. + * Our assumption here is that the EBB is cancelled if both + * FSCR and HFSCR EBB facilities aren't available. + */ +static void do_ebb(CPUPPCState *env, int ebb_excp) +{ + PowerPCCPU *cpu =3D env_archcpu(env); + CPUState *cs =3D CPU(cpu); + + /* + * FSCR_EBB and FSCR_IC_EBB are the same bits used with + * HFSCR. + */ + helper_fscr_facility_check(env, FSCR_EBB, 0, FSCR_IC_EBB); + helper_hfscr_facility_check(env, FSCR_EBB, "EBB", FSCR_IC_EBB); + + if (ebb_excp =3D=3D POWERPC_EXCP_PERFM_EBB) { + env->spr[SPR_BESCR] |=3D BESCR_PMEO; + } else if (ebb_excp =3D=3D POWERPC_EXCP_EXTERNAL_EBB) { + env->spr[SPR_BESCR] |=3D BESCR_EEO; + } + + if (msr_pr =3D=3D 1) { + powerpc_excp(cpu, ebb_excp); + } else { + env->pending_interrupts |=3D 1 << PPC_INTERRUPT_EBB; + cpu_interrupt(cs, CPU_INTERRUPT_HARD); + } +} + +void raise_ebb_perfm_exception(CPUPPCState *env) +{ + bool perfm_ebb_enabled =3D env->spr[SPR_POWER_MMCR0] & MMCR0_EBE && + env->spr[SPR_BESCR] & BESCR_PME && + env->spr[SPR_BESCR] & BESCR_GE; + + if (!perfm_ebb_enabled) { + return; + } + + do_ebb(env, POWERPC_EXCP_PERFM_EBB); +} #endif =20 /*************************************************************************= ****/ diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index d245663158..beeab5c494 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -307,8 +307,7 @@ static void fire_PMC_interrupt(PowerPCCPU *cpu) env->spr[SPR_POWER_MMCR0] |=3D MMCR0_PMAO; } =20 - /* PMC interrupt not implemented yet */ - return; + raise_ebb_perfm_exception(env); } =20 /* This helper assumes that the PMC is running. */ --=20 2.35.1